1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/delay.h> 16 #include <linux/notifier.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/in.h> 20 #include <linux/ethtool.h> 21 #include <linux/topology.h> 22 #include <linux/gfp.h> 23 #include <linux/aer.h> 24 #include <linux/interrupt.h> 25 #include "net_driver.h" 26 #include <net/gre.h> 27 #include <net/udp_tunnel.h> 28 #include "efx.h" 29 #include "nic.h" 30 #include "selftest.h" 31 #include "sriov.h" 32 33 #include "mcdi.h" 34 #include "mcdi_pcol.h" 35 #include "workarounds.h" 36 37 /************************************************************************** 38 * 39 * Type name strings 40 * 41 ************************************************************************** 42 */ 43 44 /* Loopback mode names (see LOOPBACK_MODE()) */ 45 const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; 46 const char *const efx_loopback_mode_names[] = { 47 [LOOPBACK_NONE] = "NONE", 48 [LOOPBACK_DATA] = "DATAPATH", 49 [LOOPBACK_GMAC] = "GMAC", 50 [LOOPBACK_XGMII] = "XGMII", 51 [LOOPBACK_XGXS] = "XGXS", 52 [LOOPBACK_XAUI] = "XAUI", 53 [LOOPBACK_GMII] = "GMII", 54 [LOOPBACK_SGMII] = "SGMII", 55 [LOOPBACK_XGBR] = "XGBR", 56 [LOOPBACK_XFI] = "XFI", 57 [LOOPBACK_XAUI_FAR] = "XAUI_FAR", 58 [LOOPBACK_GMII_FAR] = "GMII_FAR", 59 [LOOPBACK_SGMII_FAR] = "SGMII_FAR", 60 [LOOPBACK_XFI_FAR] = "XFI_FAR", 61 [LOOPBACK_GPHY] = "GPHY", 62 [LOOPBACK_PHYXS] = "PHYXS", 63 [LOOPBACK_PCS] = "PCS", 64 [LOOPBACK_PMAPMD] = "PMA/PMD", 65 [LOOPBACK_XPORT] = "XPORT", 66 [LOOPBACK_XGMII_WS] = "XGMII_WS", 67 [LOOPBACK_XAUI_WS] = "XAUI_WS", 68 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", 69 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", 70 [LOOPBACK_GMII_WS] = "GMII_WS", 71 [LOOPBACK_XFI_WS] = "XFI_WS", 72 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", 73 [LOOPBACK_PHYXS_WS] = "PHYXS_WS", 74 }; 75 76 const unsigned int efx_reset_type_max = RESET_TYPE_MAX; 77 const char *const efx_reset_type_names[] = { 78 [RESET_TYPE_INVISIBLE] = "INVISIBLE", 79 [RESET_TYPE_ALL] = "ALL", 80 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", 81 [RESET_TYPE_WORLD] = "WORLD", 82 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", 83 [RESET_TYPE_DATAPATH] = "DATAPATH", 84 [RESET_TYPE_MC_BIST] = "MC_BIST", 85 [RESET_TYPE_DISABLE] = "DISABLE", 86 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", 87 [RESET_TYPE_INT_ERROR] = "INT_ERROR", 88 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", 89 [RESET_TYPE_TX_SKIP] = "TX_SKIP", 90 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", 91 [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)", 92 }; 93 94 /* UDP tunnel type names */ 95 static const char *const efx_udp_tunnel_type_names[] = { 96 [TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN] = "vxlan", 97 [TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE] = "geneve", 98 }; 99 100 void efx_get_udp_tunnel_type_name(u16 type, char *buf, size_t buflen) 101 { 102 if (type < ARRAY_SIZE(efx_udp_tunnel_type_names) && 103 efx_udp_tunnel_type_names[type] != NULL) 104 snprintf(buf, buflen, "%s", efx_udp_tunnel_type_names[type]); 105 else 106 snprintf(buf, buflen, "type %d", type); 107 } 108 109 /* Reset workqueue. If any NIC has a hardware failure then a reset will be 110 * queued onto this work queue. This is not a per-nic work queue, because 111 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. 112 */ 113 static struct workqueue_struct *reset_workqueue; 114 115 /* How often and how many times to poll for a reset while waiting for a 116 * BIST that another function started to complete. 117 */ 118 #define BIST_WAIT_DELAY_MS 100 119 #define BIST_WAIT_DELAY_COUNT 100 120 121 /************************************************************************** 122 * 123 * Configurable values 124 * 125 *************************************************************************/ 126 127 /* 128 * Use separate channels for TX and RX events 129 * 130 * Set this to 1 to use separate channels for TX and RX. It allows us 131 * to control interrupt affinity separately for TX and RX. 132 * 133 * This is only used in MSI-X interrupt mode 134 */ 135 bool efx_separate_tx_channels; 136 module_param(efx_separate_tx_channels, bool, 0444); 137 MODULE_PARM_DESC(efx_separate_tx_channels, 138 "Use separate channels for TX and RX"); 139 140 /* This is the weight assigned to each of the (per-channel) virtual 141 * NAPI devices. 142 */ 143 static int napi_weight = 64; 144 145 /* This is the time (in jiffies) between invocations of the hardware 146 * monitor. 147 * On Falcon-based NICs, this will: 148 * - Check the on-board hardware monitor; 149 * - Poll the link state and reconfigure the hardware as necessary. 150 * On Siena-based NICs for power systems with EEH support, this will give EEH a 151 * chance to start. 152 */ 153 static unsigned int efx_monitor_interval = 1 * HZ; 154 155 /* Initial interrupt moderation settings. They can be modified after 156 * module load with ethtool. 157 * 158 * The default for RX should strike a balance between increasing the 159 * round-trip latency and reducing overhead. 160 */ 161 static unsigned int rx_irq_mod_usec = 60; 162 163 /* Initial interrupt moderation settings. They can be modified after 164 * module load with ethtool. 165 * 166 * This default is chosen to ensure that a 10G link does not go idle 167 * while a TX queue is stopped after it has become full. A queue is 168 * restarted when it drops below half full. The time this takes (assuming 169 * worst case 3 descriptors per packet and 1024 descriptors) is 170 * 512 / 3 * 1.2 = 205 usec. 171 */ 172 static unsigned int tx_irq_mod_usec = 150; 173 174 /* This is the first interrupt mode to try out of: 175 * 0 => MSI-X 176 * 1 => MSI 177 * 2 => legacy 178 */ 179 static unsigned int interrupt_mode; 180 181 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 182 * i.e. the number of CPUs among which we may distribute simultaneous 183 * interrupt handling. 184 * 185 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 186 * The default (0) means to assign an interrupt to each core. 187 */ 188 static unsigned int rss_cpus; 189 module_param(rss_cpus, uint, 0444); 190 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 191 192 static bool phy_flash_cfg; 193 module_param(phy_flash_cfg, bool, 0644); 194 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); 195 196 static unsigned irq_adapt_low_thresh = 8000; 197 module_param(irq_adapt_low_thresh, uint, 0644); 198 MODULE_PARM_DESC(irq_adapt_low_thresh, 199 "Threshold score for reducing IRQ moderation"); 200 201 static unsigned irq_adapt_high_thresh = 16000; 202 module_param(irq_adapt_high_thresh, uint, 0644); 203 MODULE_PARM_DESC(irq_adapt_high_thresh, 204 "Threshold score for increasing IRQ moderation"); 205 206 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 207 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 208 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | 209 NETIF_MSG_TX_ERR | NETIF_MSG_HW); 210 module_param(debug, uint, 0); 211 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); 212 213 /************************************************************************** 214 * 215 * Utility functions and prototypes 216 * 217 *************************************************************************/ 218 219 static int efx_soft_enable_interrupts(struct efx_nic *efx); 220 static void efx_soft_disable_interrupts(struct efx_nic *efx); 221 static void efx_remove_channel(struct efx_channel *channel); 222 static void efx_remove_channels(struct efx_nic *efx); 223 static const struct efx_channel_type efx_default_channel_type; 224 static void efx_remove_port(struct efx_nic *efx); 225 static void efx_init_napi_channel(struct efx_channel *channel); 226 static void efx_fini_napi(struct efx_nic *efx); 227 static void efx_fini_napi_channel(struct efx_channel *channel); 228 static void efx_fini_struct(struct efx_nic *efx); 229 static void efx_start_all(struct efx_nic *efx); 230 static void efx_stop_all(struct efx_nic *efx); 231 232 #define EFX_ASSERT_RESET_SERIALISED(efx) \ 233 do { \ 234 if ((efx->state == STATE_READY) || \ 235 (efx->state == STATE_RECOVERY) || \ 236 (efx->state == STATE_DISABLED)) \ 237 ASSERT_RTNL(); \ 238 } while (0) 239 240 static int efx_check_disabled(struct efx_nic *efx) 241 { 242 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { 243 netif_err(efx, drv, efx->net_dev, 244 "device is disabled due to earlier errors\n"); 245 return -EIO; 246 } 247 return 0; 248 } 249 250 /************************************************************************** 251 * 252 * Event queue processing 253 * 254 *************************************************************************/ 255 256 /* Process channel's event queue 257 * 258 * This function is responsible for processing the event queue of a 259 * single channel. The caller must guarantee that this function will 260 * never be concurrently called more than once on the same channel, 261 * though different channels may be being processed concurrently. 262 */ 263 static int efx_process_channel(struct efx_channel *channel, int budget) 264 { 265 struct efx_tx_queue *tx_queue; 266 int spent; 267 268 if (unlikely(!channel->enabled)) 269 return 0; 270 271 efx_for_each_channel_tx_queue(tx_queue, channel) { 272 tx_queue->pkts_compl = 0; 273 tx_queue->bytes_compl = 0; 274 } 275 276 spent = efx_nic_process_eventq(channel, budget); 277 if (spent && efx_channel_has_rx_queue(channel)) { 278 struct efx_rx_queue *rx_queue = 279 efx_channel_get_rx_queue(channel); 280 281 efx_rx_flush_packet(channel); 282 efx_fast_push_rx_descriptors(rx_queue, true); 283 } 284 285 /* Update BQL */ 286 efx_for_each_channel_tx_queue(tx_queue, channel) { 287 if (tx_queue->bytes_compl) { 288 netdev_tx_completed_queue(tx_queue->core_txq, 289 tx_queue->pkts_compl, tx_queue->bytes_compl); 290 } 291 } 292 293 return spent; 294 } 295 296 /* NAPI poll handler 297 * 298 * NAPI guarantees serialisation of polls of the same device, which 299 * provides the guarantee required by efx_process_channel(). 300 */ 301 static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel) 302 { 303 int step = efx->irq_mod_step_us; 304 305 if (channel->irq_mod_score < irq_adapt_low_thresh) { 306 if (channel->irq_moderation_us > step) { 307 channel->irq_moderation_us -= step; 308 efx->type->push_irq_moderation(channel); 309 } 310 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { 311 if (channel->irq_moderation_us < 312 efx->irq_rx_moderation_us) { 313 channel->irq_moderation_us += step; 314 efx->type->push_irq_moderation(channel); 315 } 316 } 317 318 channel->irq_count = 0; 319 channel->irq_mod_score = 0; 320 } 321 322 static int efx_poll(struct napi_struct *napi, int budget) 323 { 324 struct efx_channel *channel = 325 container_of(napi, struct efx_channel, napi_str); 326 struct efx_nic *efx = channel->efx; 327 int spent; 328 329 netif_vdbg(efx, intr, efx->net_dev, 330 "channel %d NAPI poll executing on CPU %d\n", 331 channel->channel, raw_smp_processor_id()); 332 333 spent = efx_process_channel(channel, budget); 334 335 if (spent < budget) { 336 if (efx_channel_has_rx_queue(channel) && 337 efx->irq_rx_adaptive && 338 unlikely(++channel->irq_count == 1000)) { 339 efx_update_irq_mod(efx, channel); 340 } 341 342 efx_filter_rfs_expire(channel); 343 344 /* There is no race here; although napi_disable() will 345 * only wait for napi_complete(), this isn't a problem 346 * since efx_nic_eventq_read_ack() will have no effect if 347 * interrupts have already been disabled. 348 */ 349 if (napi_complete_done(napi, spent)) 350 efx_nic_eventq_read_ack(channel); 351 } 352 353 return spent; 354 } 355 356 /* Create event queue 357 * Event queue memory allocations are done only once. If the channel 358 * is reset, the memory buffer will be reused; this guards against 359 * errors during channel reset and also simplifies interrupt handling. 360 */ 361 static int efx_probe_eventq(struct efx_channel *channel) 362 { 363 struct efx_nic *efx = channel->efx; 364 unsigned long entries; 365 366 netif_dbg(efx, probe, efx->net_dev, 367 "chan %d create event queue\n", channel->channel); 368 369 /* Build an event queue with room for one event per tx and rx buffer, 370 * plus some extra for link state events and MCDI completions. */ 371 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 372 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 373 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 374 375 return efx_nic_probe_eventq(channel); 376 } 377 378 /* Prepare channel's event queue */ 379 static int efx_init_eventq(struct efx_channel *channel) 380 { 381 struct efx_nic *efx = channel->efx; 382 int rc; 383 384 EFX_WARN_ON_PARANOID(channel->eventq_init); 385 386 netif_dbg(efx, drv, efx->net_dev, 387 "chan %d init event queue\n", channel->channel); 388 389 rc = efx_nic_init_eventq(channel); 390 if (rc == 0) { 391 efx->type->push_irq_moderation(channel); 392 channel->eventq_read_ptr = 0; 393 channel->eventq_init = true; 394 } 395 return rc; 396 } 397 398 /* Enable event queue processing and NAPI */ 399 void efx_start_eventq(struct efx_channel *channel) 400 { 401 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 402 "chan %d start event queue\n", channel->channel); 403 404 /* Make sure the NAPI handler sees the enabled flag set */ 405 channel->enabled = true; 406 smp_wmb(); 407 408 napi_enable(&channel->napi_str); 409 efx_nic_eventq_read_ack(channel); 410 } 411 412 /* Disable event queue processing and NAPI */ 413 void efx_stop_eventq(struct efx_channel *channel) 414 { 415 if (!channel->enabled) 416 return; 417 418 napi_disable(&channel->napi_str); 419 channel->enabled = false; 420 } 421 422 static void efx_fini_eventq(struct efx_channel *channel) 423 { 424 if (!channel->eventq_init) 425 return; 426 427 netif_dbg(channel->efx, drv, channel->efx->net_dev, 428 "chan %d fini event queue\n", channel->channel); 429 430 efx_nic_fini_eventq(channel); 431 channel->eventq_init = false; 432 } 433 434 static void efx_remove_eventq(struct efx_channel *channel) 435 { 436 netif_dbg(channel->efx, drv, channel->efx->net_dev, 437 "chan %d remove event queue\n", channel->channel); 438 439 efx_nic_remove_eventq(channel); 440 } 441 442 /************************************************************************** 443 * 444 * Channel handling 445 * 446 *************************************************************************/ 447 448 /* Allocate and initialise a channel structure. */ 449 static struct efx_channel * 450 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) 451 { 452 struct efx_channel *channel; 453 struct efx_rx_queue *rx_queue; 454 struct efx_tx_queue *tx_queue; 455 int j; 456 457 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 458 if (!channel) 459 return NULL; 460 461 channel->efx = efx; 462 channel->channel = i; 463 channel->type = &efx_default_channel_type; 464 465 for (j = 0; j < EFX_TXQ_TYPES; j++) { 466 tx_queue = &channel->tx_queue[j]; 467 tx_queue->efx = efx; 468 tx_queue->queue = i * EFX_TXQ_TYPES + j; 469 tx_queue->channel = channel; 470 } 471 472 rx_queue = &channel->rx_queue; 473 rx_queue->efx = efx; 474 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 475 (unsigned long)rx_queue); 476 477 return channel; 478 } 479 480 /* Allocate and initialise a channel structure, copying parameters 481 * (but not resources) from an old channel structure. 482 */ 483 static struct efx_channel * 484 efx_copy_channel(const struct efx_channel *old_channel) 485 { 486 struct efx_channel *channel; 487 struct efx_rx_queue *rx_queue; 488 struct efx_tx_queue *tx_queue; 489 int j; 490 491 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 492 if (!channel) 493 return NULL; 494 495 *channel = *old_channel; 496 497 channel->napi_dev = NULL; 498 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); 499 channel->napi_str.napi_id = 0; 500 channel->napi_str.state = 0; 501 memset(&channel->eventq, 0, sizeof(channel->eventq)); 502 503 for (j = 0; j < EFX_TXQ_TYPES; j++) { 504 tx_queue = &channel->tx_queue[j]; 505 if (tx_queue->channel) 506 tx_queue->channel = channel; 507 tx_queue->buffer = NULL; 508 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 509 } 510 511 rx_queue = &channel->rx_queue; 512 rx_queue->buffer = NULL; 513 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 514 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 515 (unsigned long)rx_queue); 516 517 return channel; 518 } 519 520 static int efx_probe_channel(struct efx_channel *channel) 521 { 522 struct efx_tx_queue *tx_queue; 523 struct efx_rx_queue *rx_queue; 524 int rc; 525 526 netif_dbg(channel->efx, probe, channel->efx->net_dev, 527 "creating channel %d\n", channel->channel); 528 529 rc = channel->type->pre_probe(channel); 530 if (rc) 531 goto fail; 532 533 rc = efx_probe_eventq(channel); 534 if (rc) 535 goto fail; 536 537 efx_for_each_channel_tx_queue(tx_queue, channel) { 538 rc = efx_probe_tx_queue(tx_queue); 539 if (rc) 540 goto fail; 541 } 542 543 efx_for_each_channel_rx_queue(rx_queue, channel) { 544 rc = efx_probe_rx_queue(rx_queue); 545 if (rc) 546 goto fail; 547 } 548 549 return 0; 550 551 fail: 552 efx_remove_channel(channel); 553 return rc; 554 } 555 556 static void 557 efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 558 { 559 struct efx_nic *efx = channel->efx; 560 const char *type; 561 int number; 562 563 number = channel->channel; 564 if (efx->tx_channel_offset == 0) { 565 type = ""; 566 } else if (channel->channel < efx->tx_channel_offset) { 567 type = "-rx"; 568 } else { 569 type = "-tx"; 570 number -= efx->tx_channel_offset; 571 } 572 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 573 } 574 575 static void efx_set_channel_names(struct efx_nic *efx) 576 { 577 struct efx_channel *channel; 578 579 efx_for_each_channel(channel, efx) 580 channel->type->get_name(channel, 581 efx->msi_context[channel->channel].name, 582 sizeof(efx->msi_context[0].name)); 583 } 584 585 static int efx_probe_channels(struct efx_nic *efx) 586 { 587 struct efx_channel *channel; 588 int rc; 589 590 /* Restart special buffer allocation */ 591 efx->next_buffer_table = 0; 592 593 /* Probe channels in reverse, so that any 'extra' channels 594 * use the start of the buffer table. This allows the traffic 595 * channels to be resized without moving them or wasting the 596 * entries before them. 597 */ 598 efx_for_each_channel_rev(channel, efx) { 599 rc = efx_probe_channel(channel); 600 if (rc) { 601 netif_err(efx, probe, efx->net_dev, 602 "failed to create channel %d\n", 603 channel->channel); 604 goto fail; 605 } 606 } 607 efx_set_channel_names(efx); 608 609 return 0; 610 611 fail: 612 efx_remove_channels(efx); 613 return rc; 614 } 615 616 /* Channels are shutdown and reinitialised whilst the NIC is running 617 * to propagate configuration changes (mtu, checksum offload), or 618 * to clear hardware error conditions 619 */ 620 static void efx_start_datapath(struct efx_nic *efx) 621 { 622 netdev_features_t old_features = efx->net_dev->features; 623 bool old_rx_scatter = efx->rx_scatter; 624 struct efx_tx_queue *tx_queue; 625 struct efx_rx_queue *rx_queue; 626 struct efx_channel *channel; 627 size_t rx_buf_len; 628 629 /* Calculate the rx buffer allocation parameters required to 630 * support the current MTU, including padding for header 631 * alignment and overruns. 632 */ 633 efx->rx_dma_len = (efx->rx_prefix_size + 634 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + 635 efx->type->rx_buffer_padding); 636 rx_buf_len = (sizeof(struct efx_rx_page_state) + 637 efx->rx_ip_align + efx->rx_dma_len); 638 if (rx_buf_len <= PAGE_SIZE) { 639 efx->rx_scatter = efx->type->always_rx_scatter; 640 efx->rx_buffer_order = 0; 641 } else if (efx->type->can_rx_scatter) { 642 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); 643 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + 644 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, 645 EFX_RX_BUF_ALIGNMENT) > 646 PAGE_SIZE); 647 efx->rx_scatter = true; 648 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; 649 efx->rx_buffer_order = 0; 650 } else { 651 efx->rx_scatter = false; 652 efx->rx_buffer_order = get_order(rx_buf_len); 653 } 654 655 efx_rx_config_page_split(efx); 656 if (efx->rx_buffer_order) 657 netif_dbg(efx, drv, efx->net_dev, 658 "RX buf len=%u; page order=%u batch=%u\n", 659 efx->rx_dma_len, efx->rx_buffer_order, 660 efx->rx_pages_per_batch); 661 else 662 netif_dbg(efx, drv, efx->net_dev, 663 "RX buf len=%u step=%u bpp=%u; page batch=%u\n", 664 efx->rx_dma_len, efx->rx_page_buf_step, 665 efx->rx_bufs_per_page, efx->rx_pages_per_batch); 666 667 /* Restore previously fixed features in hw_features and remove 668 * features which are fixed now 669 */ 670 efx->net_dev->hw_features |= efx->net_dev->features; 671 efx->net_dev->hw_features &= ~efx->fixed_features; 672 efx->net_dev->features |= efx->fixed_features; 673 if (efx->net_dev->features != old_features) 674 netdev_features_change(efx->net_dev); 675 676 /* RX filters may also have scatter-enabled flags */ 677 if (efx->rx_scatter != old_rx_scatter) 678 efx->type->filter_update_rx_scatter(efx); 679 680 /* We must keep at least one descriptor in a TX ring empty. 681 * We could avoid this when the queue size does not exactly 682 * match the hardware ring size, but it's not that important. 683 * Therefore we stop the queue when one more skb might fill 684 * the ring completely. We wake it when half way back to 685 * empty. 686 */ 687 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); 688 efx->txq_wake_thresh = efx->txq_stop_thresh / 2; 689 690 /* Initialise the channels */ 691 efx_for_each_channel(channel, efx) { 692 efx_for_each_channel_tx_queue(tx_queue, channel) { 693 efx_init_tx_queue(tx_queue); 694 atomic_inc(&efx->active_queues); 695 } 696 697 efx_for_each_channel_rx_queue(rx_queue, channel) { 698 efx_init_rx_queue(rx_queue); 699 atomic_inc(&efx->active_queues); 700 efx_stop_eventq(channel); 701 efx_fast_push_rx_descriptors(rx_queue, false); 702 efx_start_eventq(channel); 703 } 704 705 WARN_ON(channel->rx_pkt_n_frags); 706 } 707 708 efx_ptp_start_datapath(efx); 709 710 if (netif_device_present(efx->net_dev)) 711 netif_tx_wake_all_queues(efx->net_dev); 712 } 713 714 static void efx_stop_datapath(struct efx_nic *efx) 715 { 716 struct efx_channel *channel; 717 struct efx_tx_queue *tx_queue; 718 struct efx_rx_queue *rx_queue; 719 int rc; 720 721 EFX_ASSERT_RESET_SERIALISED(efx); 722 BUG_ON(efx->port_enabled); 723 724 efx_ptp_stop_datapath(efx); 725 726 /* Stop RX refill */ 727 efx_for_each_channel(channel, efx) { 728 efx_for_each_channel_rx_queue(rx_queue, channel) 729 rx_queue->refill_enabled = false; 730 } 731 732 efx_for_each_channel(channel, efx) { 733 /* RX packet processing is pipelined, so wait for the 734 * NAPI handler to complete. At least event queue 0 735 * might be kept active by non-data events, so don't 736 * use napi_synchronize() but actually disable NAPI 737 * temporarily. 738 */ 739 if (efx_channel_has_rx_queue(channel)) { 740 efx_stop_eventq(channel); 741 efx_start_eventq(channel); 742 } 743 } 744 745 rc = efx->type->fini_dmaq(efx); 746 if (rc) { 747 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 748 } else { 749 netif_dbg(efx, drv, efx->net_dev, 750 "successfully flushed all queues\n"); 751 } 752 753 efx_for_each_channel(channel, efx) { 754 efx_for_each_channel_rx_queue(rx_queue, channel) 755 efx_fini_rx_queue(rx_queue); 756 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 757 efx_fini_tx_queue(tx_queue); 758 } 759 } 760 761 static void efx_remove_channel(struct efx_channel *channel) 762 { 763 struct efx_tx_queue *tx_queue; 764 struct efx_rx_queue *rx_queue; 765 766 netif_dbg(channel->efx, drv, channel->efx->net_dev, 767 "destroy chan %d\n", channel->channel); 768 769 efx_for_each_channel_rx_queue(rx_queue, channel) 770 efx_remove_rx_queue(rx_queue); 771 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 772 efx_remove_tx_queue(tx_queue); 773 efx_remove_eventq(channel); 774 channel->type->post_remove(channel); 775 } 776 777 static void efx_remove_channels(struct efx_nic *efx) 778 { 779 struct efx_channel *channel; 780 781 efx_for_each_channel(channel, efx) 782 efx_remove_channel(channel); 783 } 784 785 int 786 efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 787 { 788 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 789 u32 old_rxq_entries, old_txq_entries; 790 unsigned i, next_buffer_table = 0; 791 int rc, rc2; 792 793 rc = efx_check_disabled(efx); 794 if (rc) 795 return rc; 796 797 /* Not all channels should be reallocated. We must avoid 798 * reallocating their buffer table entries. 799 */ 800 efx_for_each_channel(channel, efx) { 801 struct efx_rx_queue *rx_queue; 802 struct efx_tx_queue *tx_queue; 803 804 if (channel->type->copy) 805 continue; 806 next_buffer_table = max(next_buffer_table, 807 channel->eventq.index + 808 channel->eventq.entries); 809 efx_for_each_channel_rx_queue(rx_queue, channel) 810 next_buffer_table = max(next_buffer_table, 811 rx_queue->rxd.index + 812 rx_queue->rxd.entries); 813 efx_for_each_channel_tx_queue(tx_queue, channel) 814 next_buffer_table = max(next_buffer_table, 815 tx_queue->txd.index + 816 tx_queue->txd.entries); 817 } 818 819 efx_device_detach_sync(efx); 820 efx_stop_all(efx); 821 efx_soft_disable_interrupts(efx); 822 823 /* Clone channels (where possible) */ 824 memset(other_channel, 0, sizeof(other_channel)); 825 for (i = 0; i < efx->n_channels; i++) { 826 channel = efx->channel[i]; 827 if (channel->type->copy) 828 channel = channel->type->copy(channel); 829 if (!channel) { 830 rc = -ENOMEM; 831 goto out; 832 } 833 other_channel[i] = channel; 834 } 835 836 /* Swap entry counts and channel pointers */ 837 old_rxq_entries = efx->rxq_entries; 838 old_txq_entries = efx->txq_entries; 839 efx->rxq_entries = rxq_entries; 840 efx->txq_entries = txq_entries; 841 for (i = 0; i < efx->n_channels; i++) { 842 channel = efx->channel[i]; 843 efx->channel[i] = other_channel[i]; 844 other_channel[i] = channel; 845 } 846 847 /* Restart buffer table allocation */ 848 efx->next_buffer_table = next_buffer_table; 849 850 for (i = 0; i < efx->n_channels; i++) { 851 channel = efx->channel[i]; 852 if (!channel->type->copy) 853 continue; 854 rc = efx_probe_channel(channel); 855 if (rc) 856 goto rollback; 857 efx_init_napi_channel(efx->channel[i]); 858 } 859 860 out: 861 /* Destroy unused channel structures */ 862 for (i = 0; i < efx->n_channels; i++) { 863 channel = other_channel[i]; 864 if (channel && channel->type->copy) { 865 efx_fini_napi_channel(channel); 866 efx_remove_channel(channel); 867 kfree(channel); 868 } 869 } 870 871 rc2 = efx_soft_enable_interrupts(efx); 872 if (rc2) { 873 rc = rc ? rc : rc2; 874 netif_err(efx, drv, efx->net_dev, 875 "unable to restart interrupts on channel reallocation\n"); 876 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 877 } else { 878 efx_start_all(efx); 879 efx_device_attach_if_not_resetting(efx); 880 } 881 return rc; 882 883 rollback: 884 /* Swap back */ 885 efx->rxq_entries = old_rxq_entries; 886 efx->txq_entries = old_txq_entries; 887 for (i = 0; i < efx->n_channels; i++) { 888 channel = efx->channel[i]; 889 efx->channel[i] = other_channel[i]; 890 other_channel[i] = channel; 891 } 892 goto out; 893 } 894 895 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) 896 { 897 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); 898 } 899 900 static const struct efx_channel_type efx_default_channel_type = { 901 .pre_probe = efx_channel_dummy_op_int, 902 .post_remove = efx_channel_dummy_op_void, 903 .get_name = efx_get_channel_name, 904 .copy = efx_copy_channel, 905 .keep_eventq = false, 906 }; 907 908 int efx_channel_dummy_op_int(struct efx_channel *channel) 909 { 910 return 0; 911 } 912 913 void efx_channel_dummy_op_void(struct efx_channel *channel) 914 { 915 } 916 917 /************************************************************************** 918 * 919 * Port handling 920 * 921 **************************************************************************/ 922 923 /* This ensures that the kernel is kept informed (via 924 * netif_carrier_on/off) of the link status, and also maintains the 925 * link status's stop on the port's TX queue. 926 */ 927 void efx_link_status_changed(struct efx_nic *efx) 928 { 929 struct efx_link_state *link_state = &efx->link_state; 930 931 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure 932 * that no events are triggered between unregister_netdev() and the 933 * driver unloading. A more general condition is that NETDEV_CHANGE 934 * can only be generated between NETDEV_UP and NETDEV_DOWN */ 935 if (!netif_running(efx->net_dev)) 936 return; 937 938 if (link_state->up != netif_carrier_ok(efx->net_dev)) { 939 efx->n_link_state_changes++; 940 941 if (link_state->up) 942 netif_carrier_on(efx->net_dev); 943 else 944 netif_carrier_off(efx->net_dev); 945 } 946 947 /* Status message for kernel log */ 948 if (link_state->up) 949 netif_info(efx, link, efx->net_dev, 950 "link up at %uMbps %s-duplex (MTU %d)\n", 951 link_state->speed, link_state->fd ? "full" : "half", 952 efx->net_dev->mtu); 953 else 954 netif_info(efx, link, efx->net_dev, "link down\n"); 955 } 956 957 void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) 958 { 959 efx->link_advertising = advertising; 960 if (advertising) { 961 if (advertising & ADVERTISED_Pause) 962 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); 963 else 964 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); 965 if (advertising & ADVERTISED_Asym_Pause) 966 efx->wanted_fc ^= EFX_FC_TX; 967 } 968 } 969 970 void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) 971 { 972 efx->wanted_fc = wanted_fc; 973 if (efx->link_advertising) { 974 if (wanted_fc & EFX_FC_RX) 975 efx->link_advertising |= (ADVERTISED_Pause | 976 ADVERTISED_Asym_Pause); 977 else 978 efx->link_advertising &= ~(ADVERTISED_Pause | 979 ADVERTISED_Asym_Pause); 980 if (wanted_fc & EFX_FC_TX) 981 efx->link_advertising ^= ADVERTISED_Asym_Pause; 982 } 983 } 984 985 static void efx_fini_port(struct efx_nic *efx); 986 987 /* We assume that efx->type->reconfigure_mac will always try to sync RX 988 * filters and therefore needs to read-lock the filter table against freeing 989 */ 990 void efx_mac_reconfigure(struct efx_nic *efx) 991 { 992 down_read(&efx->filter_sem); 993 efx->type->reconfigure_mac(efx); 994 up_read(&efx->filter_sem); 995 } 996 997 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure 998 * the MAC appropriately. All other PHY configuration changes are pushed 999 * through phy_op->set_settings(), and pushed asynchronously to the MAC 1000 * through efx_monitor(). 1001 * 1002 * Callers must hold the mac_lock 1003 */ 1004 int __efx_reconfigure_port(struct efx_nic *efx) 1005 { 1006 enum efx_phy_mode phy_mode; 1007 int rc; 1008 1009 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 1010 1011 /* Disable PHY transmit in mac level loopbacks */ 1012 phy_mode = efx->phy_mode; 1013 if (LOOPBACK_INTERNAL(efx)) 1014 efx->phy_mode |= PHY_MODE_TX_DISABLED; 1015 else 1016 efx->phy_mode &= ~PHY_MODE_TX_DISABLED; 1017 1018 rc = efx->type->reconfigure_port(efx); 1019 1020 if (rc) 1021 efx->phy_mode = phy_mode; 1022 1023 return rc; 1024 } 1025 1026 /* Reinitialise the MAC to pick up new PHY settings, even if the port is 1027 * disabled. */ 1028 int efx_reconfigure_port(struct efx_nic *efx) 1029 { 1030 int rc; 1031 1032 EFX_ASSERT_RESET_SERIALISED(efx); 1033 1034 mutex_lock(&efx->mac_lock); 1035 rc = __efx_reconfigure_port(efx); 1036 mutex_unlock(&efx->mac_lock); 1037 1038 return rc; 1039 } 1040 1041 /* Asynchronous work item for changing MAC promiscuity and multicast 1042 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current 1043 * MAC directly. */ 1044 static void efx_mac_work(struct work_struct *data) 1045 { 1046 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); 1047 1048 mutex_lock(&efx->mac_lock); 1049 if (efx->port_enabled) 1050 efx_mac_reconfigure(efx); 1051 mutex_unlock(&efx->mac_lock); 1052 } 1053 1054 static int efx_probe_port(struct efx_nic *efx) 1055 { 1056 int rc; 1057 1058 netif_dbg(efx, probe, efx->net_dev, "create port\n"); 1059 1060 if (phy_flash_cfg) 1061 efx->phy_mode = PHY_MODE_SPECIAL; 1062 1063 /* Connect up MAC/PHY operations table */ 1064 rc = efx->type->probe_port(efx); 1065 if (rc) 1066 return rc; 1067 1068 /* Initialise MAC address to permanent address */ 1069 ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr); 1070 1071 return 0; 1072 } 1073 1074 static int efx_init_port(struct efx_nic *efx) 1075 { 1076 int rc; 1077 1078 netif_dbg(efx, drv, efx->net_dev, "init port\n"); 1079 1080 mutex_lock(&efx->mac_lock); 1081 1082 rc = efx->phy_op->init(efx); 1083 if (rc) 1084 goto fail1; 1085 1086 efx->port_initialized = true; 1087 1088 /* Reconfigure the MAC before creating dma queues (required for 1089 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ 1090 efx_mac_reconfigure(efx); 1091 1092 /* Ensure the PHY advertises the correct flow control settings */ 1093 rc = efx->phy_op->reconfigure(efx); 1094 if (rc && rc != -EPERM) 1095 goto fail2; 1096 1097 mutex_unlock(&efx->mac_lock); 1098 return 0; 1099 1100 fail2: 1101 efx->phy_op->fini(efx); 1102 fail1: 1103 mutex_unlock(&efx->mac_lock); 1104 return rc; 1105 } 1106 1107 static void efx_start_port(struct efx_nic *efx) 1108 { 1109 netif_dbg(efx, ifup, efx->net_dev, "start port\n"); 1110 BUG_ON(efx->port_enabled); 1111 1112 mutex_lock(&efx->mac_lock); 1113 efx->port_enabled = true; 1114 1115 /* Ensure MAC ingress/egress is enabled */ 1116 efx_mac_reconfigure(efx); 1117 1118 mutex_unlock(&efx->mac_lock); 1119 } 1120 1121 /* Cancel work for MAC reconfiguration, periodic hardware monitoring 1122 * and the async self-test, wait for them to finish and prevent them 1123 * being scheduled again. This doesn't cover online resets, which 1124 * should only be cancelled when removing the device. 1125 */ 1126 static void efx_stop_port(struct efx_nic *efx) 1127 { 1128 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); 1129 1130 EFX_ASSERT_RESET_SERIALISED(efx); 1131 1132 mutex_lock(&efx->mac_lock); 1133 efx->port_enabled = false; 1134 mutex_unlock(&efx->mac_lock); 1135 1136 /* Serialise against efx_set_multicast_list() */ 1137 netif_addr_lock_bh(efx->net_dev); 1138 netif_addr_unlock_bh(efx->net_dev); 1139 1140 cancel_delayed_work_sync(&efx->monitor_work); 1141 efx_selftest_async_cancel(efx); 1142 cancel_work_sync(&efx->mac_work); 1143 } 1144 1145 static void efx_fini_port(struct efx_nic *efx) 1146 { 1147 netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); 1148 1149 if (!efx->port_initialized) 1150 return; 1151 1152 efx->phy_op->fini(efx); 1153 efx->port_initialized = false; 1154 1155 efx->link_state.up = false; 1156 efx_link_status_changed(efx); 1157 } 1158 1159 static void efx_remove_port(struct efx_nic *efx) 1160 { 1161 netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); 1162 1163 efx->type->remove_port(efx); 1164 } 1165 1166 /************************************************************************** 1167 * 1168 * NIC handling 1169 * 1170 **************************************************************************/ 1171 1172 static LIST_HEAD(efx_primary_list); 1173 static LIST_HEAD(efx_unassociated_list); 1174 1175 static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right) 1176 { 1177 return left->type == right->type && 1178 left->vpd_sn && right->vpd_sn && 1179 !strcmp(left->vpd_sn, right->vpd_sn); 1180 } 1181 1182 static void efx_associate(struct efx_nic *efx) 1183 { 1184 struct efx_nic *other, *next; 1185 1186 if (efx->primary == efx) { 1187 /* Adding primary function; look for secondaries */ 1188 1189 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); 1190 list_add_tail(&efx->node, &efx_primary_list); 1191 1192 list_for_each_entry_safe(other, next, &efx_unassociated_list, 1193 node) { 1194 if (efx_same_controller(efx, other)) { 1195 list_del(&other->node); 1196 netif_dbg(other, probe, other->net_dev, 1197 "moving to secondary list of %s %s\n", 1198 pci_name(efx->pci_dev), 1199 efx->net_dev->name); 1200 list_add_tail(&other->node, 1201 &efx->secondary_list); 1202 other->primary = efx; 1203 } 1204 } 1205 } else { 1206 /* Adding secondary function; look for primary */ 1207 1208 list_for_each_entry(other, &efx_primary_list, node) { 1209 if (efx_same_controller(efx, other)) { 1210 netif_dbg(efx, probe, efx->net_dev, 1211 "adding to secondary list of %s %s\n", 1212 pci_name(other->pci_dev), 1213 other->net_dev->name); 1214 list_add_tail(&efx->node, 1215 &other->secondary_list); 1216 efx->primary = other; 1217 return; 1218 } 1219 } 1220 1221 netif_dbg(efx, probe, efx->net_dev, 1222 "adding to unassociated list\n"); 1223 list_add_tail(&efx->node, &efx_unassociated_list); 1224 } 1225 } 1226 1227 static void efx_dissociate(struct efx_nic *efx) 1228 { 1229 struct efx_nic *other, *next; 1230 1231 list_del(&efx->node); 1232 efx->primary = NULL; 1233 1234 list_for_each_entry_safe(other, next, &efx->secondary_list, node) { 1235 list_del(&other->node); 1236 netif_dbg(other, probe, other->net_dev, 1237 "moving to unassociated list\n"); 1238 list_add_tail(&other->node, &efx_unassociated_list); 1239 other->primary = NULL; 1240 } 1241 } 1242 1243 /* This configures the PCI device to enable I/O and DMA. */ 1244 static int efx_init_io(struct efx_nic *efx) 1245 { 1246 struct pci_dev *pci_dev = efx->pci_dev; 1247 dma_addr_t dma_mask = efx->type->max_dma_mask; 1248 unsigned int mem_map_size = efx->type->mem_map_size(efx); 1249 int rc, bar; 1250 1251 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); 1252 1253 bar = efx->type->mem_bar; 1254 1255 rc = pci_enable_device(pci_dev); 1256 if (rc) { 1257 netif_err(efx, probe, efx->net_dev, 1258 "failed to enable PCI device\n"); 1259 goto fail1; 1260 } 1261 1262 pci_set_master(pci_dev); 1263 1264 /* Set the PCI DMA mask. Try all possibilities from our 1265 * genuine mask down to 32 bits, because some architectures 1266 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit 1267 * masks event though they reject 46 bit masks. 1268 */ 1269 while (dma_mask > 0x7fffffffUL) { 1270 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); 1271 if (rc == 0) 1272 break; 1273 dma_mask >>= 1; 1274 } 1275 if (rc) { 1276 netif_err(efx, probe, efx->net_dev, 1277 "could not find a suitable DMA mask\n"); 1278 goto fail2; 1279 } 1280 netif_dbg(efx, probe, efx->net_dev, 1281 "using DMA mask %llx\n", (unsigned long long) dma_mask); 1282 1283 efx->membase_phys = pci_resource_start(efx->pci_dev, bar); 1284 rc = pci_request_region(pci_dev, bar, "sfc"); 1285 if (rc) { 1286 netif_err(efx, probe, efx->net_dev, 1287 "request for memory BAR failed\n"); 1288 rc = -EIO; 1289 goto fail3; 1290 } 1291 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); 1292 if (!efx->membase) { 1293 netif_err(efx, probe, efx->net_dev, 1294 "could not map memory BAR at %llx+%x\n", 1295 (unsigned long long)efx->membase_phys, mem_map_size); 1296 rc = -ENOMEM; 1297 goto fail4; 1298 } 1299 netif_dbg(efx, probe, efx->net_dev, 1300 "memory BAR at %llx+%x (virtual %p)\n", 1301 (unsigned long long)efx->membase_phys, mem_map_size, 1302 efx->membase); 1303 1304 return 0; 1305 1306 fail4: 1307 pci_release_region(efx->pci_dev, bar); 1308 fail3: 1309 efx->membase_phys = 0; 1310 fail2: 1311 pci_disable_device(efx->pci_dev); 1312 fail1: 1313 return rc; 1314 } 1315 1316 static void efx_fini_io(struct efx_nic *efx) 1317 { 1318 int bar; 1319 1320 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); 1321 1322 if (efx->membase) { 1323 iounmap(efx->membase); 1324 efx->membase = NULL; 1325 } 1326 1327 if (efx->membase_phys) { 1328 bar = efx->type->mem_bar; 1329 pci_release_region(efx->pci_dev, bar); 1330 efx->membase_phys = 0; 1331 } 1332 1333 /* Don't disable bus-mastering if VFs are assigned */ 1334 if (!pci_vfs_assigned(efx->pci_dev)) 1335 pci_disable_device(efx->pci_dev); 1336 } 1337 1338 void efx_set_default_rx_indir_table(struct efx_nic *efx) 1339 { 1340 size_t i; 1341 1342 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) 1343 efx->rx_indir_table[i] = 1344 ethtool_rxfh_indir_default(i, efx->rss_spread); 1345 } 1346 1347 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 1348 { 1349 cpumask_var_t thread_mask; 1350 unsigned int count; 1351 int cpu; 1352 1353 if (rss_cpus) { 1354 count = rss_cpus; 1355 } else { 1356 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 1357 netif_warn(efx, probe, efx->net_dev, 1358 "RSS disabled due to allocation failure\n"); 1359 return 1; 1360 } 1361 1362 count = 0; 1363 for_each_online_cpu(cpu) { 1364 if (!cpumask_test_cpu(cpu, thread_mask)) { 1365 ++count; 1366 cpumask_or(thread_mask, thread_mask, 1367 topology_sibling_cpumask(cpu)); 1368 } 1369 } 1370 1371 free_cpumask_var(thread_mask); 1372 } 1373 1374 if (count > EFX_MAX_RX_QUEUES) { 1375 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, 1376 "Reducing number of rx queues from %u to %u.\n", 1377 count, EFX_MAX_RX_QUEUES); 1378 count = EFX_MAX_RX_QUEUES; 1379 } 1380 1381 /* If RSS is requested for the PF *and* VFs then we can't write RSS 1382 * table entries that are inaccessible to VFs 1383 */ 1384 #ifdef CONFIG_SFC_SRIOV 1385 if (efx->type->sriov_wanted) { 1386 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && 1387 count > efx_vf_size(efx)) { 1388 netif_warn(efx, probe, efx->net_dev, 1389 "Reducing number of RSS channels from %u to %u for " 1390 "VF support. Increase vf-msix-limit to use more " 1391 "channels on the PF.\n", 1392 count, efx_vf_size(efx)); 1393 count = efx_vf_size(efx); 1394 } 1395 } 1396 #endif 1397 1398 return count; 1399 } 1400 1401 /* Probe the number and type of interrupts we are able to obtain, and 1402 * the resulting numbers of channels and RX queues. 1403 */ 1404 static int efx_probe_interrupts(struct efx_nic *efx) 1405 { 1406 unsigned int extra_channels = 0; 1407 unsigned int i, j; 1408 int rc; 1409 1410 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 1411 if (efx->extra_channel_type[i]) 1412 ++extra_channels; 1413 1414 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 1415 struct msix_entry xentries[EFX_MAX_CHANNELS]; 1416 unsigned int n_channels; 1417 1418 n_channels = efx_wanted_parallelism(efx); 1419 if (efx_separate_tx_channels) 1420 n_channels *= 2; 1421 n_channels += extra_channels; 1422 n_channels = min(n_channels, efx->max_channels); 1423 1424 for (i = 0; i < n_channels; i++) 1425 xentries[i].entry = i; 1426 rc = pci_enable_msix_range(efx->pci_dev, 1427 xentries, 1, n_channels); 1428 if (rc < 0) { 1429 /* Fall back to single channel MSI */ 1430 netif_err(efx, drv, efx->net_dev, 1431 "could not enable MSI-X\n"); 1432 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) 1433 efx->interrupt_mode = EFX_INT_MODE_MSI; 1434 else 1435 return rc; 1436 } else if (rc < n_channels) { 1437 netif_err(efx, drv, efx->net_dev, 1438 "WARNING: Insufficient MSI-X vectors" 1439 " available (%d < %u).\n", rc, n_channels); 1440 netif_err(efx, drv, efx->net_dev, 1441 "WARNING: Performance may be reduced.\n"); 1442 n_channels = rc; 1443 } 1444 1445 if (rc > 0) { 1446 efx->n_channels = n_channels; 1447 if (n_channels > extra_channels) 1448 n_channels -= extra_channels; 1449 if (efx_separate_tx_channels) { 1450 efx->n_tx_channels = min(max(n_channels / 2, 1451 1U), 1452 efx->max_tx_channels); 1453 efx->n_rx_channels = max(n_channels - 1454 efx->n_tx_channels, 1455 1U); 1456 } else { 1457 efx->n_tx_channels = min(n_channels, 1458 efx->max_tx_channels); 1459 efx->n_rx_channels = n_channels; 1460 } 1461 for (i = 0; i < efx->n_channels; i++) 1462 efx_get_channel(efx, i)->irq = 1463 xentries[i].vector; 1464 } 1465 } 1466 1467 /* Try single interrupt MSI */ 1468 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 1469 efx->n_channels = 1; 1470 efx->n_rx_channels = 1; 1471 efx->n_tx_channels = 1; 1472 rc = pci_enable_msi(efx->pci_dev); 1473 if (rc == 0) { 1474 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 1475 } else { 1476 netif_err(efx, drv, efx->net_dev, 1477 "could not enable MSI\n"); 1478 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) 1479 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 1480 else 1481 return rc; 1482 } 1483 } 1484 1485 /* Assume legacy interrupts */ 1486 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 1487 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); 1488 efx->n_rx_channels = 1; 1489 efx->n_tx_channels = 1; 1490 efx->legacy_irq = efx->pci_dev->irq; 1491 } 1492 1493 /* Assign extra channels if possible */ 1494 j = efx->n_channels; 1495 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 1496 if (!efx->extra_channel_type[i]) 1497 continue; 1498 if (efx->interrupt_mode != EFX_INT_MODE_MSIX || 1499 efx->n_channels <= extra_channels) { 1500 efx->extra_channel_type[i]->handle_no_channel(efx); 1501 } else { 1502 --j; 1503 efx_get_channel(efx, j)->type = 1504 efx->extra_channel_type[i]; 1505 } 1506 } 1507 1508 /* RSS might be usable on VFs even if it is disabled on the PF */ 1509 #ifdef CONFIG_SFC_SRIOV 1510 if (efx->type->sriov_wanted) { 1511 efx->rss_spread = ((efx->n_rx_channels > 1 || 1512 !efx->type->sriov_wanted(efx)) ? 1513 efx->n_rx_channels : efx_vf_size(efx)); 1514 return 0; 1515 } 1516 #endif 1517 efx->rss_spread = efx->n_rx_channels; 1518 1519 return 0; 1520 } 1521 1522 static int efx_soft_enable_interrupts(struct efx_nic *efx) 1523 { 1524 struct efx_channel *channel, *end_channel; 1525 int rc; 1526 1527 BUG_ON(efx->state == STATE_DISABLED); 1528 1529 efx->irq_soft_enabled = true; 1530 smp_wmb(); 1531 1532 efx_for_each_channel(channel, efx) { 1533 if (!channel->type->keep_eventq) { 1534 rc = efx_init_eventq(channel); 1535 if (rc) 1536 goto fail; 1537 } 1538 efx_start_eventq(channel); 1539 } 1540 1541 efx_mcdi_mode_event(efx); 1542 1543 return 0; 1544 fail: 1545 end_channel = channel; 1546 efx_for_each_channel(channel, efx) { 1547 if (channel == end_channel) 1548 break; 1549 efx_stop_eventq(channel); 1550 if (!channel->type->keep_eventq) 1551 efx_fini_eventq(channel); 1552 } 1553 1554 return rc; 1555 } 1556 1557 static void efx_soft_disable_interrupts(struct efx_nic *efx) 1558 { 1559 struct efx_channel *channel; 1560 1561 if (efx->state == STATE_DISABLED) 1562 return; 1563 1564 efx_mcdi_mode_poll(efx); 1565 1566 efx->irq_soft_enabled = false; 1567 smp_wmb(); 1568 1569 if (efx->legacy_irq) 1570 synchronize_irq(efx->legacy_irq); 1571 1572 efx_for_each_channel(channel, efx) { 1573 if (channel->irq) 1574 synchronize_irq(channel->irq); 1575 1576 efx_stop_eventq(channel); 1577 if (!channel->type->keep_eventq) 1578 efx_fini_eventq(channel); 1579 } 1580 1581 /* Flush the asynchronous MCDI request queue */ 1582 efx_mcdi_flush_async(efx); 1583 } 1584 1585 static int efx_enable_interrupts(struct efx_nic *efx) 1586 { 1587 struct efx_channel *channel, *end_channel; 1588 int rc; 1589 1590 BUG_ON(efx->state == STATE_DISABLED); 1591 1592 if (efx->eeh_disabled_legacy_irq) { 1593 enable_irq(efx->legacy_irq); 1594 efx->eeh_disabled_legacy_irq = false; 1595 } 1596 1597 efx->type->irq_enable_master(efx); 1598 1599 efx_for_each_channel(channel, efx) { 1600 if (channel->type->keep_eventq) { 1601 rc = efx_init_eventq(channel); 1602 if (rc) 1603 goto fail; 1604 } 1605 } 1606 1607 rc = efx_soft_enable_interrupts(efx); 1608 if (rc) 1609 goto fail; 1610 1611 return 0; 1612 1613 fail: 1614 end_channel = channel; 1615 efx_for_each_channel(channel, efx) { 1616 if (channel == end_channel) 1617 break; 1618 if (channel->type->keep_eventq) 1619 efx_fini_eventq(channel); 1620 } 1621 1622 efx->type->irq_disable_non_ev(efx); 1623 1624 return rc; 1625 } 1626 1627 static void efx_disable_interrupts(struct efx_nic *efx) 1628 { 1629 struct efx_channel *channel; 1630 1631 efx_soft_disable_interrupts(efx); 1632 1633 efx_for_each_channel(channel, efx) { 1634 if (channel->type->keep_eventq) 1635 efx_fini_eventq(channel); 1636 } 1637 1638 efx->type->irq_disable_non_ev(efx); 1639 } 1640 1641 static void efx_remove_interrupts(struct efx_nic *efx) 1642 { 1643 struct efx_channel *channel; 1644 1645 /* Remove MSI/MSI-X interrupts */ 1646 efx_for_each_channel(channel, efx) 1647 channel->irq = 0; 1648 pci_disable_msi(efx->pci_dev); 1649 pci_disable_msix(efx->pci_dev); 1650 1651 /* Remove legacy interrupt */ 1652 efx->legacy_irq = 0; 1653 } 1654 1655 static void efx_set_channels(struct efx_nic *efx) 1656 { 1657 struct efx_channel *channel; 1658 struct efx_tx_queue *tx_queue; 1659 1660 efx->tx_channel_offset = 1661 efx_separate_tx_channels ? 1662 efx->n_channels - efx->n_tx_channels : 0; 1663 1664 /* We need to mark which channels really have RX and TX 1665 * queues, and adjust the TX queue numbers if we have separate 1666 * RX-only and TX-only channels. 1667 */ 1668 efx_for_each_channel(channel, efx) { 1669 if (channel->channel < efx->n_rx_channels) 1670 channel->rx_queue.core_index = channel->channel; 1671 else 1672 channel->rx_queue.core_index = -1; 1673 1674 efx_for_each_channel_tx_queue(tx_queue, channel) 1675 tx_queue->queue -= (efx->tx_channel_offset * 1676 EFX_TXQ_TYPES); 1677 } 1678 } 1679 1680 static int efx_probe_nic(struct efx_nic *efx) 1681 { 1682 int rc; 1683 1684 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); 1685 1686 /* Carry out hardware-type specific initialisation */ 1687 rc = efx->type->probe(efx); 1688 if (rc) 1689 return rc; 1690 1691 do { 1692 if (!efx->max_channels || !efx->max_tx_channels) { 1693 netif_err(efx, drv, efx->net_dev, 1694 "Insufficient resources to allocate" 1695 " any channels\n"); 1696 rc = -ENOSPC; 1697 goto fail1; 1698 } 1699 1700 /* Determine the number of channels and queues by trying 1701 * to hook in MSI-X interrupts. 1702 */ 1703 rc = efx_probe_interrupts(efx); 1704 if (rc) 1705 goto fail1; 1706 1707 efx_set_channels(efx); 1708 1709 /* dimension_resources can fail with EAGAIN */ 1710 rc = efx->type->dimension_resources(efx); 1711 if (rc != 0 && rc != -EAGAIN) 1712 goto fail2; 1713 1714 if (rc == -EAGAIN) 1715 /* try again with new max_channels */ 1716 efx_remove_interrupts(efx); 1717 1718 } while (rc == -EAGAIN); 1719 1720 if (efx->n_channels > 1) 1721 netdev_rss_key_fill(&efx->rx_hash_key, 1722 sizeof(efx->rx_hash_key)); 1723 efx_set_default_rx_indir_table(efx); 1724 1725 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 1726 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 1727 1728 /* Initialise the interrupt moderation settings */ 1729 efx->irq_mod_step_us = DIV_ROUND_UP(efx->timer_quantum_ns, 1000); 1730 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, 1731 true); 1732 1733 return 0; 1734 1735 fail2: 1736 efx_remove_interrupts(efx); 1737 fail1: 1738 efx->type->remove(efx); 1739 return rc; 1740 } 1741 1742 static void efx_remove_nic(struct efx_nic *efx) 1743 { 1744 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); 1745 1746 efx_remove_interrupts(efx); 1747 efx->type->remove(efx); 1748 } 1749 1750 static int efx_probe_filters(struct efx_nic *efx) 1751 { 1752 int rc; 1753 1754 spin_lock_init(&efx->filter_lock); 1755 init_rwsem(&efx->filter_sem); 1756 mutex_lock(&efx->mac_lock); 1757 down_write(&efx->filter_sem); 1758 rc = efx->type->filter_table_probe(efx); 1759 if (rc) 1760 goto out_unlock; 1761 1762 #ifdef CONFIG_RFS_ACCEL 1763 if (efx->type->offload_features & NETIF_F_NTUPLE) { 1764 struct efx_channel *channel; 1765 int i, success = 1; 1766 1767 efx_for_each_channel(channel, efx) { 1768 channel->rps_flow_id = 1769 kcalloc(efx->type->max_rx_ip_filters, 1770 sizeof(*channel->rps_flow_id), 1771 GFP_KERNEL); 1772 if (!channel->rps_flow_id) 1773 success = 0; 1774 else 1775 for (i = 0; 1776 i < efx->type->max_rx_ip_filters; 1777 ++i) 1778 channel->rps_flow_id[i] = 1779 RPS_FLOW_ID_INVALID; 1780 } 1781 1782 if (!success) { 1783 efx_for_each_channel(channel, efx) 1784 kfree(channel->rps_flow_id); 1785 efx->type->filter_table_remove(efx); 1786 rc = -ENOMEM; 1787 goto out_unlock; 1788 } 1789 1790 efx->rps_expire_index = efx->rps_expire_channel = 0; 1791 } 1792 #endif 1793 out_unlock: 1794 up_write(&efx->filter_sem); 1795 mutex_unlock(&efx->mac_lock); 1796 return rc; 1797 } 1798 1799 static void efx_remove_filters(struct efx_nic *efx) 1800 { 1801 #ifdef CONFIG_RFS_ACCEL 1802 struct efx_channel *channel; 1803 1804 efx_for_each_channel(channel, efx) 1805 kfree(channel->rps_flow_id); 1806 #endif 1807 down_write(&efx->filter_sem); 1808 efx->type->filter_table_remove(efx); 1809 up_write(&efx->filter_sem); 1810 } 1811 1812 static void efx_restore_filters(struct efx_nic *efx) 1813 { 1814 down_read(&efx->filter_sem); 1815 efx->type->filter_table_restore(efx); 1816 up_read(&efx->filter_sem); 1817 } 1818 1819 /************************************************************************** 1820 * 1821 * NIC startup/shutdown 1822 * 1823 *************************************************************************/ 1824 1825 static int efx_probe_all(struct efx_nic *efx) 1826 { 1827 int rc; 1828 1829 rc = efx_probe_nic(efx); 1830 if (rc) { 1831 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); 1832 goto fail1; 1833 } 1834 1835 rc = efx_probe_port(efx); 1836 if (rc) { 1837 netif_err(efx, probe, efx->net_dev, "failed to create port\n"); 1838 goto fail2; 1839 } 1840 1841 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); 1842 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { 1843 rc = -EINVAL; 1844 goto fail3; 1845 } 1846 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; 1847 1848 #ifdef CONFIG_SFC_SRIOV 1849 rc = efx->type->vswitching_probe(efx); 1850 if (rc) /* not fatal; the PF will still work fine */ 1851 netif_warn(efx, probe, efx->net_dev, 1852 "failed to setup vswitching rc=%d;" 1853 " VFs may not function\n", rc); 1854 #endif 1855 1856 rc = efx_probe_filters(efx); 1857 if (rc) { 1858 netif_err(efx, probe, efx->net_dev, 1859 "failed to create filter tables\n"); 1860 goto fail4; 1861 } 1862 1863 rc = efx_probe_channels(efx); 1864 if (rc) 1865 goto fail5; 1866 1867 return 0; 1868 1869 fail5: 1870 efx_remove_filters(efx); 1871 fail4: 1872 #ifdef CONFIG_SFC_SRIOV 1873 efx->type->vswitching_remove(efx); 1874 #endif 1875 fail3: 1876 efx_remove_port(efx); 1877 fail2: 1878 efx_remove_nic(efx); 1879 fail1: 1880 return rc; 1881 } 1882 1883 /* If the interface is supposed to be running but is not, start 1884 * the hardware and software data path, regular activity for the port 1885 * (MAC statistics, link polling, etc.) and schedule the port to be 1886 * reconfigured. Interrupts must already be enabled. This function 1887 * is safe to call multiple times, so long as the NIC is not disabled. 1888 * Requires the RTNL lock. 1889 */ 1890 static void efx_start_all(struct efx_nic *efx) 1891 { 1892 EFX_ASSERT_RESET_SERIALISED(efx); 1893 BUG_ON(efx->state == STATE_DISABLED); 1894 1895 /* Check that it is appropriate to restart the interface. All 1896 * of these flags are safe to read under just the rtnl lock */ 1897 if (efx->port_enabled || !netif_running(efx->net_dev) || 1898 efx->reset_pending) 1899 return; 1900 1901 efx_start_port(efx); 1902 efx_start_datapath(efx); 1903 1904 /* Start the hardware monitor if there is one */ 1905 if (efx->type->monitor != NULL) 1906 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1907 efx_monitor_interval); 1908 1909 /* Link state detection is normally event-driven; we have 1910 * to poll now because we could have missed a change 1911 */ 1912 mutex_lock(&efx->mac_lock); 1913 if (efx->phy_op->poll(efx)) 1914 efx_link_status_changed(efx); 1915 mutex_unlock(&efx->mac_lock); 1916 1917 efx->type->start_stats(efx); 1918 efx->type->pull_stats(efx); 1919 spin_lock_bh(&efx->stats_lock); 1920 efx->type->update_stats(efx, NULL, NULL); 1921 spin_unlock_bh(&efx->stats_lock); 1922 } 1923 1924 /* Quiesce the hardware and software data path, and regular activity 1925 * for the port without bringing the link down. Safe to call multiple 1926 * times with the NIC in almost any state, but interrupts should be 1927 * enabled. Requires the RTNL lock. 1928 */ 1929 static void efx_stop_all(struct efx_nic *efx) 1930 { 1931 EFX_ASSERT_RESET_SERIALISED(efx); 1932 1933 /* port_enabled can be read safely under the rtnl lock */ 1934 if (!efx->port_enabled) 1935 return; 1936 1937 /* update stats before we go down so we can accurately count 1938 * rx_nodesc_drops 1939 */ 1940 efx->type->pull_stats(efx); 1941 spin_lock_bh(&efx->stats_lock); 1942 efx->type->update_stats(efx, NULL, NULL); 1943 spin_unlock_bh(&efx->stats_lock); 1944 efx->type->stop_stats(efx); 1945 efx_stop_port(efx); 1946 1947 /* Stop the kernel transmit interface. This is only valid if 1948 * the device is stopped or detached; otherwise the watchdog 1949 * may fire immediately. 1950 */ 1951 WARN_ON(netif_running(efx->net_dev) && 1952 netif_device_present(efx->net_dev)); 1953 netif_tx_disable(efx->net_dev); 1954 1955 efx_stop_datapath(efx); 1956 } 1957 1958 static void efx_remove_all(struct efx_nic *efx) 1959 { 1960 efx_remove_channels(efx); 1961 efx_remove_filters(efx); 1962 #ifdef CONFIG_SFC_SRIOV 1963 efx->type->vswitching_remove(efx); 1964 #endif 1965 efx_remove_port(efx); 1966 efx_remove_nic(efx); 1967 } 1968 1969 /************************************************************************** 1970 * 1971 * Interrupt moderation 1972 * 1973 **************************************************************************/ 1974 unsigned int efx_usecs_to_ticks(struct efx_nic *efx, unsigned int usecs) 1975 { 1976 if (usecs == 0) 1977 return 0; 1978 if (usecs * 1000 < efx->timer_quantum_ns) 1979 return 1; /* never round down to 0 */ 1980 return usecs * 1000 / efx->timer_quantum_ns; 1981 } 1982 1983 unsigned int efx_ticks_to_usecs(struct efx_nic *efx, unsigned int ticks) 1984 { 1985 /* We must round up when converting ticks to microseconds 1986 * because we round down when converting the other way. 1987 */ 1988 return DIV_ROUND_UP(ticks * efx->timer_quantum_ns, 1000); 1989 } 1990 1991 /* Set interrupt moderation parameters */ 1992 int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, 1993 unsigned int rx_usecs, bool rx_adaptive, 1994 bool rx_may_override_tx) 1995 { 1996 struct efx_channel *channel; 1997 unsigned int timer_max_us; 1998 1999 EFX_ASSERT_RESET_SERIALISED(efx); 2000 2001 timer_max_us = efx->timer_max_ns / 1000; 2002 2003 if (tx_usecs > timer_max_us || rx_usecs > timer_max_us) 2004 return -EINVAL; 2005 2006 if (tx_usecs != rx_usecs && efx->tx_channel_offset == 0 && 2007 !rx_may_override_tx) { 2008 netif_err(efx, drv, efx->net_dev, "Channels are shared. " 2009 "RX and TX IRQ moderation must be equal\n"); 2010 return -EINVAL; 2011 } 2012 2013 efx->irq_rx_adaptive = rx_adaptive; 2014 efx->irq_rx_moderation_us = rx_usecs; 2015 efx_for_each_channel(channel, efx) { 2016 if (efx_channel_has_rx_queue(channel)) 2017 channel->irq_moderation_us = rx_usecs; 2018 else if (efx_channel_has_tx_queues(channel)) 2019 channel->irq_moderation_us = tx_usecs; 2020 } 2021 2022 return 0; 2023 } 2024 2025 void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, 2026 unsigned int *rx_usecs, bool *rx_adaptive) 2027 { 2028 *rx_adaptive = efx->irq_rx_adaptive; 2029 *rx_usecs = efx->irq_rx_moderation_us; 2030 2031 /* If channels are shared between RX and TX, so is IRQ 2032 * moderation. Otherwise, IRQ moderation is the same for all 2033 * TX channels and is not adaptive. 2034 */ 2035 if (efx->tx_channel_offset == 0) { 2036 *tx_usecs = *rx_usecs; 2037 } else { 2038 struct efx_channel *tx_channel; 2039 2040 tx_channel = efx->channel[efx->tx_channel_offset]; 2041 *tx_usecs = tx_channel->irq_moderation_us; 2042 } 2043 } 2044 2045 /************************************************************************** 2046 * 2047 * Hardware monitor 2048 * 2049 **************************************************************************/ 2050 2051 /* Run periodically off the general workqueue */ 2052 static void efx_monitor(struct work_struct *data) 2053 { 2054 struct efx_nic *efx = container_of(data, struct efx_nic, 2055 monitor_work.work); 2056 2057 netif_vdbg(efx, timer, efx->net_dev, 2058 "hardware monitor executing on CPU %d\n", 2059 raw_smp_processor_id()); 2060 BUG_ON(efx->type->monitor == NULL); 2061 2062 /* If the mac_lock is already held then it is likely a port 2063 * reconfiguration is already in place, which will likely do 2064 * most of the work of monitor() anyway. */ 2065 if (mutex_trylock(&efx->mac_lock)) { 2066 if (efx->port_enabled) 2067 efx->type->monitor(efx); 2068 mutex_unlock(&efx->mac_lock); 2069 } 2070 2071 queue_delayed_work(efx->workqueue, &efx->monitor_work, 2072 efx_monitor_interval); 2073 } 2074 2075 /************************************************************************** 2076 * 2077 * ioctls 2078 * 2079 *************************************************************************/ 2080 2081 /* Net device ioctl 2082 * Context: process, rtnl_lock() held. 2083 */ 2084 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 2085 { 2086 struct efx_nic *efx = netdev_priv(net_dev); 2087 struct mii_ioctl_data *data = if_mii(ifr); 2088 2089 if (cmd == SIOCSHWTSTAMP) 2090 return efx_ptp_set_ts_config(efx, ifr); 2091 if (cmd == SIOCGHWTSTAMP) 2092 return efx_ptp_get_ts_config(efx, ifr); 2093 2094 /* Convert phy_id from older PRTAD/DEVAD format */ 2095 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && 2096 (data->phy_id & 0xfc00) == 0x0400) 2097 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; 2098 2099 return mdio_mii_ioctl(&efx->mdio, data, cmd); 2100 } 2101 2102 /************************************************************************** 2103 * 2104 * NAPI interface 2105 * 2106 **************************************************************************/ 2107 2108 static void efx_init_napi_channel(struct efx_channel *channel) 2109 { 2110 struct efx_nic *efx = channel->efx; 2111 2112 channel->napi_dev = efx->net_dev; 2113 netif_napi_add(channel->napi_dev, &channel->napi_str, 2114 efx_poll, napi_weight); 2115 } 2116 2117 static void efx_init_napi(struct efx_nic *efx) 2118 { 2119 struct efx_channel *channel; 2120 2121 efx_for_each_channel(channel, efx) 2122 efx_init_napi_channel(channel); 2123 } 2124 2125 static void efx_fini_napi_channel(struct efx_channel *channel) 2126 { 2127 if (channel->napi_dev) 2128 netif_napi_del(&channel->napi_str); 2129 2130 channel->napi_dev = NULL; 2131 } 2132 2133 static void efx_fini_napi(struct efx_nic *efx) 2134 { 2135 struct efx_channel *channel; 2136 2137 efx_for_each_channel(channel, efx) 2138 efx_fini_napi_channel(channel); 2139 } 2140 2141 /************************************************************************** 2142 * 2143 * Kernel netpoll interface 2144 * 2145 *************************************************************************/ 2146 2147 #ifdef CONFIG_NET_POLL_CONTROLLER 2148 2149 /* Although in the common case interrupts will be disabled, this is not 2150 * guaranteed. However, all our work happens inside the NAPI callback, 2151 * so no locking is required. 2152 */ 2153 static void efx_netpoll(struct net_device *net_dev) 2154 { 2155 struct efx_nic *efx = netdev_priv(net_dev); 2156 struct efx_channel *channel; 2157 2158 efx_for_each_channel(channel, efx) 2159 efx_schedule_channel(channel); 2160 } 2161 2162 #endif 2163 2164 /************************************************************************** 2165 * 2166 * Kernel net device interface 2167 * 2168 *************************************************************************/ 2169 2170 /* Context: process, rtnl_lock() held. */ 2171 int efx_net_open(struct net_device *net_dev) 2172 { 2173 struct efx_nic *efx = netdev_priv(net_dev); 2174 int rc; 2175 2176 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", 2177 raw_smp_processor_id()); 2178 2179 rc = efx_check_disabled(efx); 2180 if (rc) 2181 return rc; 2182 if (efx->phy_mode & PHY_MODE_SPECIAL) 2183 return -EBUSY; 2184 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) 2185 return -EIO; 2186 2187 /* Notify the kernel of the link state polled during driver load, 2188 * before the monitor starts running */ 2189 efx_link_status_changed(efx); 2190 2191 efx_start_all(efx); 2192 if (efx->state == STATE_DISABLED || efx->reset_pending) 2193 netif_device_detach(efx->net_dev); 2194 efx_selftest_async_start(efx); 2195 return 0; 2196 } 2197 2198 /* Context: process, rtnl_lock() held. 2199 * Note that the kernel will ignore our return code; this method 2200 * should really be a void. 2201 */ 2202 int efx_net_stop(struct net_device *net_dev) 2203 { 2204 struct efx_nic *efx = netdev_priv(net_dev); 2205 2206 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", 2207 raw_smp_processor_id()); 2208 2209 /* Stop the device and flush all the channels */ 2210 efx_stop_all(efx); 2211 2212 return 0; 2213 } 2214 2215 /* Context: process, dev_base_lock or RTNL held, non-blocking. */ 2216 static void efx_net_stats(struct net_device *net_dev, 2217 struct rtnl_link_stats64 *stats) 2218 { 2219 struct efx_nic *efx = netdev_priv(net_dev); 2220 2221 spin_lock_bh(&efx->stats_lock); 2222 efx->type->update_stats(efx, NULL, stats); 2223 spin_unlock_bh(&efx->stats_lock); 2224 } 2225 2226 /* Context: netif_tx_lock held, BHs disabled. */ 2227 static void efx_watchdog(struct net_device *net_dev) 2228 { 2229 struct efx_nic *efx = netdev_priv(net_dev); 2230 2231 netif_err(efx, tx_err, efx->net_dev, 2232 "TX stuck with port_enabled=%d: resetting channels\n", 2233 efx->port_enabled); 2234 2235 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); 2236 } 2237 2238 2239 /* Context: process, rtnl_lock() held. */ 2240 static int efx_change_mtu(struct net_device *net_dev, int new_mtu) 2241 { 2242 struct efx_nic *efx = netdev_priv(net_dev); 2243 int rc; 2244 2245 rc = efx_check_disabled(efx); 2246 if (rc) 2247 return rc; 2248 2249 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); 2250 2251 efx_device_detach_sync(efx); 2252 efx_stop_all(efx); 2253 2254 mutex_lock(&efx->mac_lock); 2255 net_dev->mtu = new_mtu; 2256 efx_mac_reconfigure(efx); 2257 mutex_unlock(&efx->mac_lock); 2258 2259 efx_start_all(efx); 2260 efx_device_attach_if_not_resetting(efx); 2261 return 0; 2262 } 2263 2264 static int efx_set_mac_address(struct net_device *net_dev, void *data) 2265 { 2266 struct efx_nic *efx = netdev_priv(net_dev); 2267 struct sockaddr *addr = data; 2268 u8 *new_addr = addr->sa_data; 2269 u8 old_addr[6]; 2270 int rc; 2271 2272 if (!is_valid_ether_addr(new_addr)) { 2273 netif_err(efx, drv, efx->net_dev, 2274 "invalid ethernet MAC address requested: %pM\n", 2275 new_addr); 2276 return -EADDRNOTAVAIL; 2277 } 2278 2279 /* save old address */ 2280 ether_addr_copy(old_addr, net_dev->dev_addr); 2281 ether_addr_copy(net_dev->dev_addr, new_addr); 2282 if (efx->type->set_mac_address) { 2283 rc = efx->type->set_mac_address(efx); 2284 if (rc) { 2285 ether_addr_copy(net_dev->dev_addr, old_addr); 2286 return rc; 2287 } 2288 } 2289 2290 /* Reconfigure the MAC */ 2291 mutex_lock(&efx->mac_lock); 2292 efx_mac_reconfigure(efx); 2293 mutex_unlock(&efx->mac_lock); 2294 2295 return 0; 2296 } 2297 2298 /* Context: netif_addr_lock held, BHs disabled. */ 2299 static void efx_set_rx_mode(struct net_device *net_dev) 2300 { 2301 struct efx_nic *efx = netdev_priv(net_dev); 2302 2303 if (efx->port_enabled) 2304 queue_work(efx->workqueue, &efx->mac_work); 2305 /* Otherwise efx_start_port() will do this */ 2306 } 2307 2308 static int efx_set_features(struct net_device *net_dev, netdev_features_t data) 2309 { 2310 struct efx_nic *efx = netdev_priv(net_dev); 2311 int rc; 2312 2313 /* If disabling RX n-tuple filtering, clear existing filters */ 2314 if (net_dev->features & ~data & NETIF_F_NTUPLE) { 2315 rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); 2316 if (rc) 2317 return rc; 2318 } 2319 2320 /* If Rx VLAN filter is changed, update filters via mac_reconfigure */ 2321 if ((net_dev->features ^ data) & NETIF_F_HW_VLAN_CTAG_FILTER) { 2322 /* efx_set_rx_mode() will schedule MAC work to update filters 2323 * when a new features are finally set in net_dev. 2324 */ 2325 efx_set_rx_mode(net_dev); 2326 } 2327 2328 return 0; 2329 } 2330 2331 static int efx_get_phys_port_id(struct net_device *net_dev, 2332 struct netdev_phys_item_id *ppid) 2333 { 2334 struct efx_nic *efx = netdev_priv(net_dev); 2335 2336 if (efx->type->get_phys_port_id) 2337 return efx->type->get_phys_port_id(efx, ppid); 2338 else 2339 return -EOPNOTSUPP; 2340 } 2341 2342 static int efx_get_phys_port_name(struct net_device *net_dev, 2343 char *name, size_t len) 2344 { 2345 struct efx_nic *efx = netdev_priv(net_dev); 2346 2347 if (snprintf(name, len, "p%u", efx->port_num) >= len) 2348 return -EINVAL; 2349 return 0; 2350 } 2351 2352 static int efx_vlan_rx_add_vid(struct net_device *net_dev, __be16 proto, u16 vid) 2353 { 2354 struct efx_nic *efx = netdev_priv(net_dev); 2355 2356 if (efx->type->vlan_rx_add_vid) 2357 return efx->type->vlan_rx_add_vid(efx, proto, vid); 2358 else 2359 return -EOPNOTSUPP; 2360 } 2361 2362 static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vid) 2363 { 2364 struct efx_nic *efx = netdev_priv(net_dev); 2365 2366 if (efx->type->vlan_rx_kill_vid) 2367 return efx->type->vlan_rx_kill_vid(efx, proto, vid); 2368 else 2369 return -EOPNOTSUPP; 2370 } 2371 2372 static int efx_udp_tunnel_type_map(enum udp_parsable_tunnel_type in) 2373 { 2374 switch (in) { 2375 case UDP_TUNNEL_TYPE_VXLAN: 2376 return TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 2377 case UDP_TUNNEL_TYPE_GENEVE: 2378 return TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 2379 default: 2380 return -1; 2381 } 2382 } 2383 2384 static void efx_udp_tunnel_add(struct net_device *dev, struct udp_tunnel_info *ti) 2385 { 2386 struct efx_nic *efx = netdev_priv(dev); 2387 struct efx_udp_tunnel tnl; 2388 int efx_tunnel_type; 2389 2390 efx_tunnel_type = efx_udp_tunnel_type_map(ti->type); 2391 if (efx_tunnel_type < 0) 2392 return; 2393 2394 tnl.type = (u16)efx_tunnel_type; 2395 tnl.port = ti->port; 2396 2397 if (efx->type->udp_tnl_add_port) 2398 (void)efx->type->udp_tnl_add_port(efx, tnl); 2399 } 2400 2401 static void efx_udp_tunnel_del(struct net_device *dev, struct udp_tunnel_info *ti) 2402 { 2403 struct efx_nic *efx = netdev_priv(dev); 2404 struct efx_udp_tunnel tnl; 2405 int efx_tunnel_type; 2406 2407 efx_tunnel_type = efx_udp_tunnel_type_map(ti->type); 2408 if (efx_tunnel_type < 0) 2409 return; 2410 2411 tnl.type = (u16)efx_tunnel_type; 2412 tnl.port = ti->port; 2413 2414 if (efx->type->udp_tnl_del_port) 2415 (void)efx->type->udp_tnl_del_port(efx, tnl); 2416 } 2417 2418 static const struct net_device_ops efx_netdev_ops = { 2419 .ndo_open = efx_net_open, 2420 .ndo_stop = efx_net_stop, 2421 .ndo_get_stats64 = efx_net_stats, 2422 .ndo_tx_timeout = efx_watchdog, 2423 .ndo_start_xmit = efx_hard_start_xmit, 2424 .ndo_validate_addr = eth_validate_addr, 2425 .ndo_do_ioctl = efx_ioctl, 2426 .ndo_change_mtu = efx_change_mtu, 2427 .ndo_set_mac_address = efx_set_mac_address, 2428 .ndo_set_rx_mode = efx_set_rx_mode, 2429 .ndo_set_features = efx_set_features, 2430 .ndo_vlan_rx_add_vid = efx_vlan_rx_add_vid, 2431 .ndo_vlan_rx_kill_vid = efx_vlan_rx_kill_vid, 2432 #ifdef CONFIG_SFC_SRIOV 2433 .ndo_set_vf_mac = efx_sriov_set_vf_mac, 2434 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, 2435 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, 2436 .ndo_get_vf_config = efx_sriov_get_vf_config, 2437 .ndo_set_vf_link_state = efx_sriov_set_vf_link_state, 2438 #endif 2439 .ndo_get_phys_port_id = efx_get_phys_port_id, 2440 .ndo_get_phys_port_name = efx_get_phys_port_name, 2441 #ifdef CONFIG_NET_POLL_CONTROLLER 2442 .ndo_poll_controller = efx_netpoll, 2443 #endif 2444 .ndo_setup_tc = efx_setup_tc, 2445 #ifdef CONFIG_RFS_ACCEL 2446 .ndo_rx_flow_steer = efx_filter_rfs, 2447 #endif 2448 .ndo_udp_tunnel_add = efx_udp_tunnel_add, 2449 .ndo_udp_tunnel_del = efx_udp_tunnel_del, 2450 }; 2451 2452 static void efx_update_name(struct efx_nic *efx) 2453 { 2454 strcpy(efx->name, efx->net_dev->name); 2455 efx_mtd_rename(efx); 2456 efx_set_channel_names(efx); 2457 } 2458 2459 static int efx_netdev_event(struct notifier_block *this, 2460 unsigned long event, void *ptr) 2461 { 2462 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); 2463 2464 if ((net_dev->netdev_ops == &efx_netdev_ops) && 2465 event == NETDEV_CHANGENAME) 2466 efx_update_name(netdev_priv(net_dev)); 2467 2468 return NOTIFY_DONE; 2469 } 2470 2471 static struct notifier_block efx_netdev_notifier = { 2472 .notifier_call = efx_netdev_event, 2473 }; 2474 2475 static ssize_t 2476 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) 2477 { 2478 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2479 return sprintf(buf, "%d\n", efx->phy_type); 2480 } 2481 static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); 2482 2483 #ifdef CONFIG_SFC_MCDI_LOGGING 2484 static ssize_t show_mcdi_log(struct device *dev, struct device_attribute *attr, 2485 char *buf) 2486 { 2487 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2488 struct efx_mcdi_iface *mcdi = efx_mcdi(efx); 2489 2490 return scnprintf(buf, PAGE_SIZE, "%d\n", mcdi->logging_enabled); 2491 } 2492 static ssize_t set_mcdi_log(struct device *dev, struct device_attribute *attr, 2493 const char *buf, size_t count) 2494 { 2495 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2496 struct efx_mcdi_iface *mcdi = efx_mcdi(efx); 2497 bool enable = count > 0 && *buf != '0'; 2498 2499 mcdi->logging_enabled = enable; 2500 return count; 2501 } 2502 static DEVICE_ATTR(mcdi_logging, 0644, show_mcdi_log, set_mcdi_log); 2503 #endif 2504 2505 static int efx_register_netdev(struct efx_nic *efx) 2506 { 2507 struct net_device *net_dev = efx->net_dev; 2508 struct efx_channel *channel; 2509 int rc; 2510 2511 net_dev->watchdog_timeo = 5 * HZ; 2512 net_dev->irq = efx->pci_dev->irq; 2513 net_dev->netdev_ops = &efx_netdev_ops; 2514 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) 2515 net_dev->priv_flags |= IFF_UNICAST_FLT; 2516 net_dev->ethtool_ops = &efx_ethtool_ops; 2517 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; 2518 net_dev->min_mtu = EFX_MIN_MTU; 2519 net_dev->max_mtu = EFX_MAX_MTU; 2520 2521 rtnl_lock(); 2522 2523 /* Enable resets to be scheduled and check whether any were 2524 * already requested. If so, the NIC is probably hosed so we 2525 * abort. 2526 */ 2527 efx->state = STATE_READY; 2528 smp_mb(); /* ensure we change state before checking reset_pending */ 2529 if (efx->reset_pending) { 2530 netif_err(efx, probe, efx->net_dev, 2531 "aborting probe due to scheduled reset\n"); 2532 rc = -EIO; 2533 goto fail_locked; 2534 } 2535 2536 rc = dev_alloc_name(net_dev, net_dev->name); 2537 if (rc < 0) 2538 goto fail_locked; 2539 efx_update_name(efx); 2540 2541 /* Always start with carrier off; PHY events will detect the link */ 2542 netif_carrier_off(net_dev); 2543 2544 rc = register_netdevice(net_dev); 2545 if (rc) 2546 goto fail_locked; 2547 2548 efx_for_each_channel(channel, efx) { 2549 struct efx_tx_queue *tx_queue; 2550 efx_for_each_channel_tx_queue(tx_queue, channel) 2551 efx_init_tx_queue_core_txq(tx_queue); 2552 } 2553 2554 efx_associate(efx); 2555 2556 rtnl_unlock(); 2557 2558 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2559 if (rc) { 2560 netif_err(efx, drv, efx->net_dev, 2561 "failed to init net dev attributes\n"); 2562 goto fail_registered; 2563 } 2564 #ifdef CONFIG_SFC_MCDI_LOGGING 2565 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging); 2566 if (rc) { 2567 netif_err(efx, drv, efx->net_dev, 2568 "failed to init net dev attributes\n"); 2569 goto fail_attr_mcdi_logging; 2570 } 2571 #endif 2572 2573 return 0; 2574 2575 #ifdef CONFIG_SFC_MCDI_LOGGING 2576 fail_attr_mcdi_logging: 2577 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2578 #endif 2579 fail_registered: 2580 rtnl_lock(); 2581 efx_dissociate(efx); 2582 unregister_netdevice(net_dev); 2583 fail_locked: 2584 efx->state = STATE_UNINIT; 2585 rtnl_unlock(); 2586 netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); 2587 return rc; 2588 } 2589 2590 static void efx_unregister_netdev(struct efx_nic *efx) 2591 { 2592 if (!efx->net_dev) 2593 return; 2594 2595 BUG_ON(netdev_priv(efx->net_dev) != efx); 2596 2597 if (efx_dev_registered(efx)) { 2598 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); 2599 #ifdef CONFIG_SFC_MCDI_LOGGING 2600 device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging); 2601 #endif 2602 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2603 unregister_netdev(efx->net_dev); 2604 } 2605 } 2606 2607 /************************************************************************** 2608 * 2609 * Device reset and suspend 2610 * 2611 **************************************************************************/ 2612 2613 /* Tears down the entire software state and most of the hardware state 2614 * before reset. */ 2615 void efx_reset_down(struct efx_nic *efx, enum reset_type method) 2616 { 2617 EFX_ASSERT_RESET_SERIALISED(efx); 2618 2619 if (method == RESET_TYPE_MCDI_TIMEOUT) 2620 efx->type->prepare_flr(efx); 2621 2622 efx_stop_all(efx); 2623 efx_disable_interrupts(efx); 2624 2625 mutex_lock(&efx->mac_lock); 2626 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE && 2627 method != RESET_TYPE_DATAPATH) 2628 efx->phy_op->fini(efx); 2629 efx->type->fini(efx); 2630 } 2631 2632 /* This function will always ensure that the locks acquired in 2633 * efx_reset_down() are released. A failure return code indicates 2634 * that we were unable to reinitialise the hardware, and the 2635 * driver should be disabled. If ok is false, then the rx and tx 2636 * engines are not restarted, pending a RESET_DISABLE. */ 2637 int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) 2638 { 2639 int rc; 2640 2641 EFX_ASSERT_RESET_SERIALISED(efx); 2642 2643 if (method == RESET_TYPE_MCDI_TIMEOUT) 2644 efx->type->finish_flr(efx); 2645 2646 /* Ensure that SRAM is initialised even if we're disabling the device */ 2647 rc = efx->type->init(efx); 2648 if (rc) { 2649 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); 2650 goto fail; 2651 } 2652 2653 if (!ok) 2654 goto fail; 2655 2656 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE && 2657 method != RESET_TYPE_DATAPATH) { 2658 rc = efx->phy_op->init(efx); 2659 if (rc) 2660 goto fail; 2661 rc = efx->phy_op->reconfigure(efx); 2662 if (rc && rc != -EPERM) 2663 netif_err(efx, drv, efx->net_dev, 2664 "could not restore PHY settings\n"); 2665 } 2666 2667 rc = efx_enable_interrupts(efx); 2668 if (rc) 2669 goto fail; 2670 2671 #ifdef CONFIG_SFC_SRIOV 2672 rc = efx->type->vswitching_restore(efx); 2673 if (rc) /* not fatal; the PF will still work fine */ 2674 netif_warn(efx, probe, efx->net_dev, 2675 "failed to restore vswitching rc=%d;" 2676 " VFs may not function\n", rc); 2677 #endif 2678 2679 down_read(&efx->filter_sem); 2680 efx_restore_filters(efx); 2681 up_read(&efx->filter_sem); 2682 if (efx->type->sriov_reset) 2683 efx->type->sriov_reset(efx); 2684 2685 mutex_unlock(&efx->mac_lock); 2686 2687 efx_start_all(efx); 2688 2689 if (efx->type->udp_tnl_push_ports) 2690 efx->type->udp_tnl_push_ports(efx); 2691 2692 return 0; 2693 2694 fail: 2695 efx->port_initialized = false; 2696 2697 mutex_unlock(&efx->mac_lock); 2698 2699 return rc; 2700 } 2701 2702 /* Reset the NIC using the specified method. Note that the reset may 2703 * fail, in which case the card will be left in an unusable state. 2704 * 2705 * Caller must hold the rtnl_lock. 2706 */ 2707 int efx_reset(struct efx_nic *efx, enum reset_type method) 2708 { 2709 int rc, rc2; 2710 bool disabled; 2711 2712 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", 2713 RESET_TYPE(method)); 2714 2715 efx_device_detach_sync(efx); 2716 efx_reset_down(efx, method); 2717 2718 rc = efx->type->reset(efx, method); 2719 if (rc) { 2720 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); 2721 goto out; 2722 } 2723 2724 /* Clear flags for the scopes we covered. We assume the NIC and 2725 * driver are now quiescent so that there is no race here. 2726 */ 2727 if (method < RESET_TYPE_MAX_METHOD) 2728 efx->reset_pending &= -(1 << (method + 1)); 2729 else /* it doesn't fit into the well-ordered scope hierarchy */ 2730 __clear_bit(method, &efx->reset_pending); 2731 2732 /* Reinitialise bus-mastering, which may have been turned off before 2733 * the reset was scheduled. This is still appropriate, even in the 2734 * RESET_TYPE_DISABLE since this driver generally assumes the hardware 2735 * can respond to requests. */ 2736 pci_set_master(efx->pci_dev); 2737 2738 out: 2739 /* Leave device stopped if necessary */ 2740 disabled = rc || 2741 method == RESET_TYPE_DISABLE || 2742 method == RESET_TYPE_RECOVER_OR_DISABLE; 2743 rc2 = efx_reset_up(efx, method, !disabled); 2744 if (rc2) { 2745 disabled = true; 2746 if (!rc) 2747 rc = rc2; 2748 } 2749 2750 if (disabled) { 2751 dev_close(efx->net_dev); 2752 netif_err(efx, drv, efx->net_dev, "has been disabled\n"); 2753 efx->state = STATE_DISABLED; 2754 } else { 2755 netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); 2756 efx_device_attach_if_not_resetting(efx); 2757 } 2758 return rc; 2759 } 2760 2761 /* Try recovery mechanisms. 2762 * For now only EEH is supported. 2763 * Returns 0 if the recovery mechanisms are unsuccessful. 2764 * Returns a non-zero value otherwise. 2765 */ 2766 int efx_try_recovery(struct efx_nic *efx) 2767 { 2768 #ifdef CONFIG_EEH 2769 /* A PCI error can occur and not be seen by EEH because nothing 2770 * happens on the PCI bus. In this case the driver may fail and 2771 * schedule a 'recover or reset', leading to this recovery handler. 2772 * Manually call the eeh failure check function. 2773 */ 2774 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev); 2775 if (eeh_dev_check_failure(eehdev)) { 2776 /* The EEH mechanisms will handle the error and reset the 2777 * device if necessary. 2778 */ 2779 return 1; 2780 } 2781 #endif 2782 return 0; 2783 } 2784 2785 static void efx_wait_for_bist_end(struct efx_nic *efx) 2786 { 2787 int i; 2788 2789 for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { 2790 if (efx_mcdi_poll_reboot(efx)) 2791 goto out; 2792 msleep(BIST_WAIT_DELAY_MS); 2793 } 2794 2795 netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); 2796 out: 2797 /* Either way unset the BIST flag. If we found no reboot we probably 2798 * won't recover, but we should try. 2799 */ 2800 efx->mc_bist_for_other_fn = false; 2801 } 2802 2803 /* The worker thread exists so that code that cannot sleep can 2804 * schedule a reset for later. 2805 */ 2806 static void efx_reset_work(struct work_struct *data) 2807 { 2808 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); 2809 unsigned long pending; 2810 enum reset_type method; 2811 2812 pending = READ_ONCE(efx->reset_pending); 2813 method = fls(pending) - 1; 2814 2815 if (method == RESET_TYPE_MC_BIST) 2816 efx_wait_for_bist_end(efx); 2817 2818 if ((method == RESET_TYPE_RECOVER_OR_DISABLE || 2819 method == RESET_TYPE_RECOVER_OR_ALL) && 2820 efx_try_recovery(efx)) 2821 return; 2822 2823 if (!pending) 2824 return; 2825 2826 rtnl_lock(); 2827 2828 /* We checked the state in efx_schedule_reset() but it may 2829 * have changed by now. Now that we have the RTNL lock, 2830 * it cannot change again. 2831 */ 2832 if (efx->state == STATE_READY) 2833 (void)efx_reset(efx, method); 2834 2835 rtnl_unlock(); 2836 } 2837 2838 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) 2839 { 2840 enum reset_type method; 2841 2842 if (efx->state == STATE_RECOVERY) { 2843 netif_dbg(efx, drv, efx->net_dev, 2844 "recovering: skip scheduling %s reset\n", 2845 RESET_TYPE(type)); 2846 return; 2847 } 2848 2849 switch (type) { 2850 case RESET_TYPE_INVISIBLE: 2851 case RESET_TYPE_ALL: 2852 case RESET_TYPE_RECOVER_OR_ALL: 2853 case RESET_TYPE_WORLD: 2854 case RESET_TYPE_DISABLE: 2855 case RESET_TYPE_RECOVER_OR_DISABLE: 2856 case RESET_TYPE_DATAPATH: 2857 case RESET_TYPE_MC_BIST: 2858 case RESET_TYPE_MCDI_TIMEOUT: 2859 method = type; 2860 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", 2861 RESET_TYPE(method)); 2862 break; 2863 default: 2864 method = efx->type->map_reset_reason(type); 2865 netif_dbg(efx, drv, efx->net_dev, 2866 "scheduling %s reset for %s\n", 2867 RESET_TYPE(method), RESET_TYPE(type)); 2868 break; 2869 } 2870 2871 set_bit(method, &efx->reset_pending); 2872 smp_mb(); /* ensure we change reset_pending before checking state */ 2873 2874 /* If we're not READY then just leave the flags set as the cue 2875 * to abort probing or reschedule the reset later. 2876 */ 2877 if (READ_ONCE(efx->state) != STATE_READY) 2878 return; 2879 2880 /* efx_process_channel() will no longer read events once a 2881 * reset is scheduled. So switch back to poll'd MCDI completions. */ 2882 efx_mcdi_mode_poll(efx); 2883 2884 queue_work(reset_workqueue, &efx->reset_work); 2885 } 2886 2887 /************************************************************************** 2888 * 2889 * List of NICs we support 2890 * 2891 **************************************************************************/ 2892 2893 /* PCI device ID table */ 2894 static const struct pci_device_id efx_pci_table[] = { 2895 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ 2896 .driver_data = (unsigned long) &siena_a0_nic_type}, 2897 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ 2898 .driver_data = (unsigned long) &siena_a0_nic_type}, 2899 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ 2900 .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, 2901 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1903), /* SFC9120 VF */ 2902 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, 2903 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */ 2904 .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, 2905 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1923), /* SFC9140 VF */ 2906 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, 2907 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0a03), /* SFC9220 PF */ 2908 .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, 2909 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1a03), /* SFC9220 VF */ 2910 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, 2911 {0} /* end of list */ 2912 }; 2913 2914 /************************************************************************** 2915 * 2916 * Dummy PHY/MAC operations 2917 * 2918 * Can be used for some unimplemented operations 2919 * Needed so all function pointers are valid and do not have to be tested 2920 * before use 2921 * 2922 **************************************************************************/ 2923 int efx_port_dummy_op_int(struct efx_nic *efx) 2924 { 2925 return 0; 2926 } 2927 void efx_port_dummy_op_void(struct efx_nic *efx) {} 2928 2929 static bool efx_port_dummy_op_poll(struct efx_nic *efx) 2930 { 2931 return false; 2932 } 2933 2934 static const struct efx_phy_operations efx_dummy_phy_operations = { 2935 .init = efx_port_dummy_op_int, 2936 .reconfigure = efx_port_dummy_op_int, 2937 .poll = efx_port_dummy_op_poll, 2938 .fini = efx_port_dummy_op_void, 2939 }; 2940 2941 /************************************************************************** 2942 * 2943 * Data housekeeping 2944 * 2945 **************************************************************************/ 2946 2947 /* This zeroes out and then fills in the invariants in a struct 2948 * efx_nic (including all sub-structures). 2949 */ 2950 static int efx_init_struct(struct efx_nic *efx, 2951 struct pci_dev *pci_dev, struct net_device *net_dev) 2952 { 2953 int rc = -ENOMEM, i; 2954 2955 /* Initialise common structures */ 2956 INIT_LIST_HEAD(&efx->node); 2957 INIT_LIST_HEAD(&efx->secondary_list); 2958 spin_lock_init(&efx->biu_lock); 2959 #ifdef CONFIG_SFC_MTD 2960 INIT_LIST_HEAD(&efx->mtd_list); 2961 #endif 2962 INIT_WORK(&efx->reset_work, efx_reset_work); 2963 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); 2964 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); 2965 efx->pci_dev = pci_dev; 2966 efx->msg_enable = debug; 2967 efx->state = STATE_UNINIT; 2968 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); 2969 2970 efx->net_dev = net_dev; 2971 efx->rx_prefix_size = efx->type->rx_prefix_size; 2972 efx->rx_ip_align = 2973 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; 2974 efx->rx_packet_hash_offset = 2975 efx->type->rx_hash_offset - efx->type->rx_prefix_size; 2976 efx->rx_packet_ts_offset = 2977 efx->type->rx_ts_offset - efx->type->rx_prefix_size; 2978 spin_lock_init(&efx->stats_lock); 2979 mutex_init(&efx->mac_lock); 2980 efx->phy_op = &efx_dummy_phy_operations; 2981 efx->mdio.dev = net_dev; 2982 INIT_WORK(&efx->mac_work, efx_mac_work); 2983 init_waitqueue_head(&efx->flush_wq); 2984 2985 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 2986 efx->channel[i] = efx_alloc_channel(efx, i, NULL); 2987 if (!efx->channel[i]) 2988 goto fail; 2989 efx->msi_context[i].efx = efx; 2990 efx->msi_context[i].index = i; 2991 } 2992 2993 /* Higher numbered interrupt modes are less capable! */ 2994 if (WARN_ON_ONCE(efx->type->max_interrupt_mode > 2995 efx->type->min_interrupt_mode)) { 2996 rc = -EIO; 2997 goto fail; 2998 } 2999 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 3000 interrupt_mode); 3001 efx->interrupt_mode = min(efx->type->min_interrupt_mode, 3002 interrupt_mode); 3003 3004 /* Would be good to use the net_dev name, but we're too early */ 3005 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", 3006 pci_name(pci_dev)); 3007 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); 3008 if (!efx->workqueue) 3009 goto fail; 3010 3011 return 0; 3012 3013 fail: 3014 efx_fini_struct(efx); 3015 return rc; 3016 } 3017 3018 static void efx_fini_struct(struct efx_nic *efx) 3019 { 3020 int i; 3021 3022 for (i = 0; i < EFX_MAX_CHANNELS; i++) 3023 kfree(efx->channel[i]); 3024 3025 kfree(efx->vpd_sn); 3026 3027 if (efx->workqueue) { 3028 destroy_workqueue(efx->workqueue); 3029 efx->workqueue = NULL; 3030 } 3031 } 3032 3033 void efx_update_sw_stats(struct efx_nic *efx, u64 *stats) 3034 { 3035 u64 n_rx_nodesc_trunc = 0; 3036 struct efx_channel *channel; 3037 3038 efx_for_each_channel(channel, efx) 3039 n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc; 3040 stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc; 3041 stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops); 3042 } 3043 3044 /************************************************************************** 3045 * 3046 * PCI interface 3047 * 3048 **************************************************************************/ 3049 3050 /* Main body of final NIC shutdown code 3051 * This is called only at module unload (or hotplug removal). 3052 */ 3053 static void efx_pci_remove_main(struct efx_nic *efx) 3054 { 3055 /* Flush reset_work. It can no longer be scheduled since we 3056 * are not READY. 3057 */ 3058 BUG_ON(efx->state == STATE_READY); 3059 cancel_work_sync(&efx->reset_work); 3060 3061 efx_disable_interrupts(efx); 3062 efx_nic_fini_interrupt(efx); 3063 efx_fini_port(efx); 3064 efx->type->fini(efx); 3065 efx_fini_napi(efx); 3066 efx_remove_all(efx); 3067 } 3068 3069 /* Final NIC shutdown 3070 * This is called only at module unload (or hotplug removal). A PF can call 3071 * this on its VFs to ensure they are unbound first. 3072 */ 3073 static void efx_pci_remove(struct pci_dev *pci_dev) 3074 { 3075 struct efx_nic *efx; 3076 3077 efx = pci_get_drvdata(pci_dev); 3078 if (!efx) 3079 return; 3080 3081 /* Mark the NIC as fini, then stop the interface */ 3082 rtnl_lock(); 3083 efx_dissociate(efx); 3084 dev_close(efx->net_dev); 3085 efx_disable_interrupts(efx); 3086 efx->state = STATE_UNINIT; 3087 rtnl_unlock(); 3088 3089 if (efx->type->sriov_fini) 3090 efx->type->sriov_fini(efx); 3091 3092 efx_unregister_netdev(efx); 3093 3094 efx_mtd_remove(efx); 3095 3096 efx_pci_remove_main(efx); 3097 3098 efx_fini_io(efx); 3099 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); 3100 3101 efx_fini_struct(efx); 3102 free_netdev(efx->net_dev); 3103 3104 pci_disable_pcie_error_reporting(pci_dev); 3105 }; 3106 3107 /* NIC VPD information 3108 * Called during probe to display the part number of the 3109 * installed NIC. VPD is potentially very large but this should 3110 * always appear within the first 512 bytes. 3111 */ 3112 #define SFC_VPD_LEN 512 3113 static void efx_probe_vpd_strings(struct efx_nic *efx) 3114 { 3115 struct pci_dev *dev = efx->pci_dev; 3116 char vpd_data[SFC_VPD_LEN]; 3117 ssize_t vpd_size; 3118 int ro_start, ro_size, i, j; 3119 3120 /* Get the vpd data from the device */ 3121 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); 3122 if (vpd_size <= 0) { 3123 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); 3124 return; 3125 } 3126 3127 /* Get the Read only section */ 3128 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 3129 if (ro_start < 0) { 3130 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); 3131 return; 3132 } 3133 3134 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); 3135 j = ro_size; 3136 i = ro_start + PCI_VPD_LRDT_TAG_SIZE; 3137 if (i + j > vpd_size) 3138 j = vpd_size - i; 3139 3140 /* Get the Part number */ 3141 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); 3142 if (i < 0) { 3143 netif_err(efx, drv, efx->net_dev, "Part number not found\n"); 3144 return; 3145 } 3146 3147 j = pci_vpd_info_field_size(&vpd_data[i]); 3148 i += PCI_VPD_INFO_FLD_HDR_SIZE; 3149 if (i + j > vpd_size) { 3150 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); 3151 return; 3152 } 3153 3154 netif_info(efx, drv, efx->net_dev, 3155 "Part Number : %.*s\n", j, &vpd_data[i]); 3156 3157 i = ro_start + PCI_VPD_LRDT_TAG_SIZE; 3158 j = ro_size; 3159 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); 3160 if (i < 0) { 3161 netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); 3162 return; 3163 } 3164 3165 j = pci_vpd_info_field_size(&vpd_data[i]); 3166 i += PCI_VPD_INFO_FLD_HDR_SIZE; 3167 if (i + j > vpd_size) { 3168 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); 3169 return; 3170 } 3171 3172 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); 3173 if (!efx->vpd_sn) 3174 return; 3175 3176 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); 3177 } 3178 3179 3180 /* Main body of NIC initialisation 3181 * This is called at module load (or hotplug insertion, theoretically). 3182 */ 3183 static int efx_pci_probe_main(struct efx_nic *efx) 3184 { 3185 int rc; 3186 3187 /* Do start-of-day initialisation */ 3188 rc = efx_probe_all(efx); 3189 if (rc) 3190 goto fail1; 3191 3192 efx_init_napi(efx); 3193 3194 rc = efx->type->init(efx); 3195 if (rc) { 3196 netif_err(efx, probe, efx->net_dev, 3197 "failed to initialise NIC\n"); 3198 goto fail3; 3199 } 3200 3201 rc = efx_init_port(efx); 3202 if (rc) { 3203 netif_err(efx, probe, efx->net_dev, 3204 "failed to initialise port\n"); 3205 goto fail4; 3206 } 3207 3208 rc = efx_nic_init_interrupt(efx); 3209 if (rc) 3210 goto fail5; 3211 rc = efx_enable_interrupts(efx); 3212 if (rc) 3213 goto fail6; 3214 3215 return 0; 3216 3217 fail6: 3218 efx_nic_fini_interrupt(efx); 3219 fail5: 3220 efx_fini_port(efx); 3221 fail4: 3222 efx->type->fini(efx); 3223 fail3: 3224 efx_fini_napi(efx); 3225 efx_remove_all(efx); 3226 fail1: 3227 return rc; 3228 } 3229 3230 static int efx_pci_probe_post_io(struct efx_nic *efx) 3231 { 3232 struct net_device *net_dev = efx->net_dev; 3233 int rc = efx_pci_probe_main(efx); 3234 3235 if (rc) 3236 return rc; 3237 3238 if (efx->type->sriov_init) { 3239 rc = efx->type->sriov_init(efx); 3240 if (rc) 3241 netif_err(efx, probe, efx->net_dev, 3242 "SR-IOV can't be enabled rc %d\n", rc); 3243 } 3244 3245 /* Determine netdevice features */ 3246 net_dev->features |= (efx->type->offload_features | NETIF_F_SG | 3247 NETIF_F_TSO | NETIF_F_RXCSUM); 3248 if (efx->type->offload_features & (NETIF_F_IPV6_CSUM | NETIF_F_HW_CSUM)) 3249 net_dev->features |= NETIF_F_TSO6; 3250 /* Check whether device supports TSO */ 3251 if (!efx->type->tso_versions || !efx->type->tso_versions(efx)) 3252 net_dev->features &= ~NETIF_F_ALL_TSO; 3253 /* Mask for features that also apply to VLAN devices */ 3254 net_dev->vlan_features |= (NETIF_F_HW_CSUM | NETIF_F_SG | 3255 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | 3256 NETIF_F_RXCSUM); 3257 3258 net_dev->hw_features = net_dev->features & ~efx->fixed_features; 3259 3260 /* Disable VLAN filtering by default. It may be enforced if 3261 * the feature is fixed (i.e. VLAN filters are required to 3262 * receive VLAN tagged packets due to vPort restrictions). 3263 */ 3264 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 3265 net_dev->features |= efx->fixed_features; 3266 3267 rc = efx_register_netdev(efx); 3268 if (!rc) 3269 return 0; 3270 3271 efx_pci_remove_main(efx); 3272 return rc; 3273 } 3274 3275 /* NIC initialisation 3276 * 3277 * This is called at module load (or hotplug insertion, 3278 * theoretically). It sets up PCI mappings, resets the NIC, 3279 * sets up and registers the network devices with the kernel and hooks 3280 * the interrupt service routine. It does not prepare the device for 3281 * transmission; this is left to the first time one of the network 3282 * interfaces is brought up (i.e. efx_net_open). 3283 */ 3284 static int efx_pci_probe(struct pci_dev *pci_dev, 3285 const struct pci_device_id *entry) 3286 { 3287 struct net_device *net_dev; 3288 struct efx_nic *efx; 3289 int rc; 3290 3291 /* Allocate and initialise a struct net_device and struct efx_nic */ 3292 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, 3293 EFX_MAX_RX_QUEUES); 3294 if (!net_dev) 3295 return -ENOMEM; 3296 efx = netdev_priv(net_dev); 3297 efx->type = (const struct efx_nic_type *) entry->driver_data; 3298 efx->fixed_features |= NETIF_F_HIGHDMA; 3299 3300 pci_set_drvdata(pci_dev, efx); 3301 SET_NETDEV_DEV(net_dev, &pci_dev->dev); 3302 rc = efx_init_struct(efx, pci_dev, net_dev); 3303 if (rc) 3304 goto fail1; 3305 3306 netif_info(efx, probe, efx->net_dev, 3307 "Solarflare NIC detected\n"); 3308 3309 if (!efx->type->is_vf) 3310 efx_probe_vpd_strings(efx); 3311 3312 /* Set up basic I/O (BAR mappings etc) */ 3313 rc = efx_init_io(efx); 3314 if (rc) 3315 goto fail2; 3316 3317 rc = efx_pci_probe_post_io(efx); 3318 if (rc) { 3319 /* On failure, retry once immediately. 3320 * If we aborted probe due to a scheduled reset, dismiss it. 3321 */ 3322 efx->reset_pending = 0; 3323 rc = efx_pci_probe_post_io(efx); 3324 if (rc) { 3325 /* On another failure, retry once more 3326 * after a 50-305ms delay. 3327 */ 3328 unsigned char r; 3329 3330 get_random_bytes(&r, 1); 3331 msleep((unsigned int)r + 50); 3332 efx->reset_pending = 0; 3333 rc = efx_pci_probe_post_io(efx); 3334 } 3335 } 3336 if (rc) 3337 goto fail3; 3338 3339 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); 3340 3341 /* Try to create MTDs, but allow this to fail */ 3342 rtnl_lock(); 3343 rc = efx_mtd_probe(efx); 3344 rtnl_unlock(); 3345 if (rc && rc != -EPERM) 3346 netif_warn(efx, probe, efx->net_dev, 3347 "failed to create MTDs (%d)\n", rc); 3348 3349 rc = pci_enable_pcie_error_reporting(pci_dev); 3350 if (rc && rc != -EINVAL) 3351 netif_notice(efx, probe, efx->net_dev, 3352 "PCIE error reporting unavailable (%d).\n", 3353 rc); 3354 3355 if (efx->type->udp_tnl_push_ports) 3356 efx->type->udp_tnl_push_ports(efx); 3357 3358 return 0; 3359 3360 fail3: 3361 efx_fini_io(efx); 3362 fail2: 3363 efx_fini_struct(efx); 3364 fail1: 3365 WARN_ON(rc > 0); 3366 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); 3367 free_netdev(net_dev); 3368 return rc; 3369 } 3370 3371 /* efx_pci_sriov_configure returns the actual number of Virtual Functions 3372 * enabled on success 3373 */ 3374 #ifdef CONFIG_SFC_SRIOV 3375 static int efx_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 3376 { 3377 int rc; 3378 struct efx_nic *efx = pci_get_drvdata(dev); 3379 3380 if (efx->type->sriov_configure) { 3381 rc = efx->type->sriov_configure(efx, num_vfs); 3382 if (rc) 3383 return rc; 3384 else 3385 return num_vfs; 3386 } else 3387 return -EOPNOTSUPP; 3388 } 3389 #endif 3390 3391 static int efx_pm_freeze(struct device *dev) 3392 { 3393 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 3394 3395 rtnl_lock(); 3396 3397 if (efx->state != STATE_DISABLED) { 3398 efx->state = STATE_UNINIT; 3399 3400 efx_device_detach_sync(efx); 3401 3402 efx_stop_all(efx); 3403 efx_disable_interrupts(efx); 3404 } 3405 3406 rtnl_unlock(); 3407 3408 return 0; 3409 } 3410 3411 static int efx_pm_thaw(struct device *dev) 3412 { 3413 int rc; 3414 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 3415 3416 rtnl_lock(); 3417 3418 if (efx->state != STATE_DISABLED) { 3419 rc = efx_enable_interrupts(efx); 3420 if (rc) 3421 goto fail; 3422 3423 mutex_lock(&efx->mac_lock); 3424 efx->phy_op->reconfigure(efx); 3425 mutex_unlock(&efx->mac_lock); 3426 3427 efx_start_all(efx); 3428 3429 efx_device_attach_if_not_resetting(efx); 3430 3431 efx->state = STATE_READY; 3432 3433 efx->type->resume_wol(efx); 3434 } 3435 3436 rtnl_unlock(); 3437 3438 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ 3439 queue_work(reset_workqueue, &efx->reset_work); 3440 3441 return 0; 3442 3443 fail: 3444 rtnl_unlock(); 3445 3446 return rc; 3447 } 3448 3449 static int efx_pm_poweroff(struct device *dev) 3450 { 3451 struct pci_dev *pci_dev = to_pci_dev(dev); 3452 struct efx_nic *efx = pci_get_drvdata(pci_dev); 3453 3454 efx->type->fini(efx); 3455 3456 efx->reset_pending = 0; 3457 3458 pci_save_state(pci_dev); 3459 return pci_set_power_state(pci_dev, PCI_D3hot); 3460 } 3461 3462 /* Used for both resume and restore */ 3463 static int efx_pm_resume(struct device *dev) 3464 { 3465 struct pci_dev *pci_dev = to_pci_dev(dev); 3466 struct efx_nic *efx = pci_get_drvdata(pci_dev); 3467 int rc; 3468 3469 rc = pci_set_power_state(pci_dev, PCI_D0); 3470 if (rc) 3471 return rc; 3472 pci_restore_state(pci_dev); 3473 rc = pci_enable_device(pci_dev); 3474 if (rc) 3475 return rc; 3476 pci_set_master(efx->pci_dev); 3477 rc = efx->type->reset(efx, RESET_TYPE_ALL); 3478 if (rc) 3479 return rc; 3480 rc = efx->type->init(efx); 3481 if (rc) 3482 return rc; 3483 rc = efx_pm_thaw(dev); 3484 return rc; 3485 } 3486 3487 static int efx_pm_suspend(struct device *dev) 3488 { 3489 int rc; 3490 3491 efx_pm_freeze(dev); 3492 rc = efx_pm_poweroff(dev); 3493 if (rc) 3494 efx_pm_resume(dev); 3495 return rc; 3496 } 3497 3498 static const struct dev_pm_ops efx_pm_ops = { 3499 .suspend = efx_pm_suspend, 3500 .resume = efx_pm_resume, 3501 .freeze = efx_pm_freeze, 3502 .thaw = efx_pm_thaw, 3503 .poweroff = efx_pm_poweroff, 3504 .restore = efx_pm_resume, 3505 }; 3506 3507 /* A PCI error affecting this device was detected. 3508 * At this point MMIO and DMA may be disabled. 3509 * Stop the software path and request a slot reset. 3510 */ 3511 static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, 3512 enum pci_channel_state state) 3513 { 3514 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3515 struct efx_nic *efx = pci_get_drvdata(pdev); 3516 3517 if (state == pci_channel_io_perm_failure) 3518 return PCI_ERS_RESULT_DISCONNECT; 3519 3520 rtnl_lock(); 3521 3522 if (efx->state != STATE_DISABLED) { 3523 efx->state = STATE_RECOVERY; 3524 efx->reset_pending = 0; 3525 3526 efx_device_detach_sync(efx); 3527 3528 efx_stop_all(efx); 3529 efx_disable_interrupts(efx); 3530 3531 status = PCI_ERS_RESULT_NEED_RESET; 3532 } else { 3533 /* If the interface is disabled we don't want to do anything 3534 * with it. 3535 */ 3536 status = PCI_ERS_RESULT_RECOVERED; 3537 } 3538 3539 rtnl_unlock(); 3540 3541 pci_disable_device(pdev); 3542 3543 return status; 3544 } 3545 3546 /* Fake a successful reset, which will be performed later in efx_io_resume. */ 3547 static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) 3548 { 3549 struct efx_nic *efx = pci_get_drvdata(pdev); 3550 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3551 int rc; 3552 3553 if (pci_enable_device(pdev)) { 3554 netif_err(efx, hw, efx->net_dev, 3555 "Cannot re-enable PCI device after reset.\n"); 3556 status = PCI_ERS_RESULT_DISCONNECT; 3557 } 3558 3559 rc = pci_cleanup_aer_uncorrect_error_status(pdev); 3560 if (rc) { 3561 netif_err(efx, hw, efx->net_dev, 3562 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); 3563 /* Non-fatal error. Continue. */ 3564 } 3565 3566 return status; 3567 } 3568 3569 /* Perform the actual reset and resume I/O operations. */ 3570 static void efx_io_resume(struct pci_dev *pdev) 3571 { 3572 struct efx_nic *efx = pci_get_drvdata(pdev); 3573 int rc; 3574 3575 rtnl_lock(); 3576 3577 if (efx->state == STATE_DISABLED) 3578 goto out; 3579 3580 rc = efx_reset(efx, RESET_TYPE_ALL); 3581 if (rc) { 3582 netif_err(efx, hw, efx->net_dev, 3583 "efx_reset failed after PCI error (%d)\n", rc); 3584 } else { 3585 efx->state = STATE_READY; 3586 netif_dbg(efx, hw, efx->net_dev, 3587 "Done resetting and resuming IO after PCI error.\n"); 3588 } 3589 3590 out: 3591 rtnl_unlock(); 3592 } 3593 3594 /* For simplicity and reliability, we always require a slot reset and try to 3595 * reset the hardware when a pci error affecting the device is detected. 3596 * We leave both the link_reset and mmio_enabled callback unimplemented: 3597 * with our request for slot reset the mmio_enabled callback will never be 3598 * called, and the link_reset callback is not used by AER or EEH mechanisms. 3599 */ 3600 static const struct pci_error_handlers efx_err_handlers = { 3601 .error_detected = efx_io_error_detected, 3602 .slot_reset = efx_io_slot_reset, 3603 .resume = efx_io_resume, 3604 }; 3605 3606 static struct pci_driver efx_pci_driver = { 3607 .name = KBUILD_MODNAME, 3608 .id_table = efx_pci_table, 3609 .probe = efx_pci_probe, 3610 .remove = efx_pci_remove, 3611 .driver.pm = &efx_pm_ops, 3612 .err_handler = &efx_err_handlers, 3613 #ifdef CONFIG_SFC_SRIOV 3614 .sriov_configure = efx_pci_sriov_configure, 3615 #endif 3616 }; 3617 3618 /************************************************************************** 3619 * 3620 * Kernel module interface 3621 * 3622 *************************************************************************/ 3623 3624 module_param(interrupt_mode, uint, 0444); 3625 MODULE_PARM_DESC(interrupt_mode, 3626 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 3627 3628 static int __init efx_init_module(void) 3629 { 3630 int rc; 3631 3632 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); 3633 3634 rc = register_netdevice_notifier(&efx_netdev_notifier); 3635 if (rc) 3636 goto err_notifier; 3637 3638 #ifdef CONFIG_SFC_SRIOV 3639 rc = efx_init_sriov(); 3640 if (rc) 3641 goto err_sriov; 3642 #endif 3643 3644 reset_workqueue = create_singlethread_workqueue("sfc_reset"); 3645 if (!reset_workqueue) { 3646 rc = -ENOMEM; 3647 goto err_reset; 3648 } 3649 3650 rc = pci_register_driver(&efx_pci_driver); 3651 if (rc < 0) 3652 goto err_pci; 3653 3654 return 0; 3655 3656 err_pci: 3657 destroy_workqueue(reset_workqueue); 3658 err_reset: 3659 #ifdef CONFIG_SFC_SRIOV 3660 efx_fini_sriov(); 3661 err_sriov: 3662 #endif 3663 unregister_netdevice_notifier(&efx_netdev_notifier); 3664 err_notifier: 3665 return rc; 3666 } 3667 3668 static void __exit efx_exit_module(void) 3669 { 3670 printk(KERN_INFO "Solarflare NET driver unloading\n"); 3671 3672 pci_unregister_driver(&efx_pci_driver); 3673 destroy_workqueue(reset_workqueue); 3674 #ifdef CONFIG_SFC_SRIOV 3675 efx_fini_sriov(); 3676 #endif 3677 unregister_netdevice_notifier(&efx_netdev_notifier); 3678 3679 } 3680 3681 module_init(efx_init_module); 3682 module_exit(efx_exit_module); 3683 3684 MODULE_AUTHOR("Solarflare Communications and " 3685 "Michael Brown <mbrown@fensystems.co.uk>"); 3686 MODULE_DESCRIPTION("Solarflare network driver"); 3687 MODULE_LICENSE("GPL"); 3688 MODULE_DEVICE_TABLE(pci, efx_pci_table); 3689 MODULE_VERSION(EFX_DRIVER_VERSION); 3690