1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/delay.h> 16 #include <linux/notifier.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/in.h> 20 #include <linux/ethtool.h> 21 #include <linux/topology.h> 22 #include <linux/gfp.h> 23 #include <linux/aer.h> 24 #include <linux/interrupt.h> 25 #include "net_driver.h" 26 #include "efx.h" 27 #include "nic.h" 28 #include "selftest.h" 29 30 #include "mcdi.h" 31 #include "workarounds.h" 32 33 /************************************************************************** 34 * 35 * Type name strings 36 * 37 ************************************************************************** 38 */ 39 40 /* Loopback mode names (see LOOPBACK_MODE()) */ 41 const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; 42 const char *const efx_loopback_mode_names[] = { 43 [LOOPBACK_NONE] = "NONE", 44 [LOOPBACK_DATA] = "DATAPATH", 45 [LOOPBACK_GMAC] = "GMAC", 46 [LOOPBACK_XGMII] = "XGMII", 47 [LOOPBACK_XGXS] = "XGXS", 48 [LOOPBACK_XAUI] = "XAUI", 49 [LOOPBACK_GMII] = "GMII", 50 [LOOPBACK_SGMII] = "SGMII", 51 [LOOPBACK_XGBR] = "XGBR", 52 [LOOPBACK_XFI] = "XFI", 53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR", 54 [LOOPBACK_GMII_FAR] = "GMII_FAR", 55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR", 56 [LOOPBACK_XFI_FAR] = "XFI_FAR", 57 [LOOPBACK_GPHY] = "GPHY", 58 [LOOPBACK_PHYXS] = "PHYXS", 59 [LOOPBACK_PCS] = "PCS", 60 [LOOPBACK_PMAPMD] = "PMA/PMD", 61 [LOOPBACK_XPORT] = "XPORT", 62 [LOOPBACK_XGMII_WS] = "XGMII_WS", 63 [LOOPBACK_XAUI_WS] = "XAUI_WS", 64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", 65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", 66 [LOOPBACK_GMII_WS] = "GMII_WS", 67 [LOOPBACK_XFI_WS] = "XFI_WS", 68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS", 70 }; 71 72 const unsigned int efx_reset_type_max = RESET_TYPE_MAX; 73 const char *const efx_reset_type_names[] = { 74 [RESET_TYPE_INVISIBLE] = "INVISIBLE", 75 [RESET_TYPE_ALL] = "ALL", 76 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", 77 [RESET_TYPE_WORLD] = "WORLD", 78 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", 79 [RESET_TYPE_DISABLE] = "DISABLE", 80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", 81 [RESET_TYPE_INT_ERROR] = "INT_ERROR", 82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", 83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", 84 [RESET_TYPE_TX_SKIP] = "TX_SKIP", 85 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", 86 [RESET_TYPE_MC_BIST] = "MC_BIST", 87 }; 88 89 /* Reset workqueue. If any NIC has a hardware failure then a reset will be 90 * queued onto this work queue. This is not a per-nic work queue, because 91 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. 92 */ 93 static struct workqueue_struct *reset_workqueue; 94 95 /* How often and how many times to poll for a reset while waiting for a 96 * BIST that another function started to complete. 97 */ 98 #define BIST_WAIT_DELAY_MS 100 99 #define BIST_WAIT_DELAY_COUNT 100 100 101 /************************************************************************** 102 * 103 * Configurable values 104 * 105 *************************************************************************/ 106 107 /* 108 * Use separate channels for TX and RX events 109 * 110 * Set this to 1 to use separate channels for TX and RX. It allows us 111 * to control interrupt affinity separately for TX and RX. 112 * 113 * This is only used in MSI-X interrupt mode 114 */ 115 static bool separate_tx_channels; 116 module_param(separate_tx_channels, bool, 0444); 117 MODULE_PARM_DESC(separate_tx_channels, 118 "Use separate channels for TX and RX"); 119 120 /* This is the weight assigned to each of the (per-channel) virtual 121 * NAPI devices. 122 */ 123 static int napi_weight = 64; 124 125 /* This is the time (in jiffies) between invocations of the hardware 126 * monitor. 127 * On Falcon-based NICs, this will: 128 * - Check the on-board hardware monitor; 129 * - Poll the link state and reconfigure the hardware as necessary. 130 * On Siena-based NICs for power systems with EEH support, this will give EEH a 131 * chance to start. 132 */ 133 static unsigned int efx_monitor_interval = 1 * HZ; 134 135 /* Initial interrupt moderation settings. They can be modified after 136 * module load with ethtool. 137 * 138 * The default for RX should strike a balance between increasing the 139 * round-trip latency and reducing overhead. 140 */ 141 static unsigned int rx_irq_mod_usec = 60; 142 143 /* Initial interrupt moderation settings. They can be modified after 144 * module load with ethtool. 145 * 146 * This default is chosen to ensure that a 10G link does not go idle 147 * while a TX queue is stopped after it has become full. A queue is 148 * restarted when it drops below half full. The time this takes (assuming 149 * worst case 3 descriptors per packet and 1024 descriptors) is 150 * 512 / 3 * 1.2 = 205 usec. 151 */ 152 static unsigned int tx_irq_mod_usec = 150; 153 154 /* This is the first interrupt mode to try out of: 155 * 0 => MSI-X 156 * 1 => MSI 157 * 2 => legacy 158 */ 159 static unsigned int interrupt_mode; 160 161 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 162 * i.e. the number of CPUs among which we may distribute simultaneous 163 * interrupt handling. 164 * 165 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 166 * The default (0) means to assign an interrupt to each core. 167 */ 168 static unsigned int rss_cpus; 169 module_param(rss_cpus, uint, 0444); 170 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 171 172 static bool phy_flash_cfg; 173 module_param(phy_flash_cfg, bool, 0644); 174 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); 175 176 static unsigned irq_adapt_low_thresh = 8000; 177 module_param(irq_adapt_low_thresh, uint, 0644); 178 MODULE_PARM_DESC(irq_adapt_low_thresh, 179 "Threshold score for reducing IRQ moderation"); 180 181 static unsigned irq_adapt_high_thresh = 16000; 182 module_param(irq_adapt_high_thresh, uint, 0644); 183 MODULE_PARM_DESC(irq_adapt_high_thresh, 184 "Threshold score for increasing IRQ moderation"); 185 186 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 187 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 188 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | 189 NETIF_MSG_TX_ERR | NETIF_MSG_HW); 190 module_param(debug, uint, 0); 191 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); 192 193 /************************************************************************** 194 * 195 * Utility functions and prototypes 196 * 197 *************************************************************************/ 198 199 static int efx_soft_enable_interrupts(struct efx_nic *efx); 200 static void efx_soft_disable_interrupts(struct efx_nic *efx); 201 static void efx_remove_channel(struct efx_channel *channel); 202 static void efx_remove_channels(struct efx_nic *efx); 203 static const struct efx_channel_type efx_default_channel_type; 204 static void efx_remove_port(struct efx_nic *efx); 205 static void efx_init_napi_channel(struct efx_channel *channel); 206 static void efx_fini_napi(struct efx_nic *efx); 207 static void efx_fini_napi_channel(struct efx_channel *channel); 208 static void efx_fini_struct(struct efx_nic *efx); 209 static void efx_start_all(struct efx_nic *efx); 210 static void efx_stop_all(struct efx_nic *efx); 211 212 #define EFX_ASSERT_RESET_SERIALISED(efx) \ 213 do { \ 214 if ((efx->state == STATE_READY) || \ 215 (efx->state == STATE_RECOVERY) || \ 216 (efx->state == STATE_DISABLED)) \ 217 ASSERT_RTNL(); \ 218 } while (0) 219 220 static int efx_check_disabled(struct efx_nic *efx) 221 { 222 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { 223 netif_err(efx, drv, efx->net_dev, 224 "device is disabled due to earlier errors\n"); 225 return -EIO; 226 } 227 return 0; 228 } 229 230 /************************************************************************** 231 * 232 * Event queue processing 233 * 234 *************************************************************************/ 235 236 /* Process channel's event queue 237 * 238 * This function is responsible for processing the event queue of a 239 * single channel. The caller must guarantee that this function will 240 * never be concurrently called more than once on the same channel, 241 * though different channels may be being processed concurrently. 242 */ 243 static int efx_process_channel(struct efx_channel *channel, int budget) 244 { 245 int spent; 246 247 if (unlikely(!channel->enabled)) 248 return 0; 249 250 spent = efx_nic_process_eventq(channel, budget); 251 if (spent && efx_channel_has_rx_queue(channel)) { 252 struct efx_rx_queue *rx_queue = 253 efx_channel_get_rx_queue(channel); 254 255 efx_rx_flush_packet(channel); 256 efx_fast_push_rx_descriptors(rx_queue, true); 257 } 258 259 return spent; 260 } 261 262 /* NAPI poll handler 263 * 264 * NAPI guarantees serialisation of polls of the same device, which 265 * provides the guarantee required by efx_process_channel(). 266 */ 267 static int efx_poll(struct napi_struct *napi, int budget) 268 { 269 struct efx_channel *channel = 270 container_of(napi, struct efx_channel, napi_str); 271 struct efx_nic *efx = channel->efx; 272 int spent; 273 274 netif_vdbg(efx, intr, efx->net_dev, 275 "channel %d NAPI poll executing on CPU %d\n", 276 channel->channel, raw_smp_processor_id()); 277 278 spent = efx_process_channel(channel, budget); 279 280 if (spent < budget) { 281 if (efx_channel_has_rx_queue(channel) && 282 efx->irq_rx_adaptive && 283 unlikely(++channel->irq_count == 1000)) { 284 if (unlikely(channel->irq_mod_score < 285 irq_adapt_low_thresh)) { 286 if (channel->irq_moderation > 1) { 287 channel->irq_moderation -= 1; 288 efx->type->push_irq_moderation(channel); 289 } 290 } else if (unlikely(channel->irq_mod_score > 291 irq_adapt_high_thresh)) { 292 if (channel->irq_moderation < 293 efx->irq_rx_moderation) { 294 channel->irq_moderation += 1; 295 efx->type->push_irq_moderation(channel); 296 } 297 } 298 channel->irq_count = 0; 299 channel->irq_mod_score = 0; 300 } 301 302 efx_filter_rfs_expire(channel); 303 304 /* There is no race here; although napi_disable() will 305 * only wait for napi_complete(), this isn't a problem 306 * since efx_nic_eventq_read_ack() will have no effect if 307 * interrupts have already been disabled. 308 */ 309 napi_complete(napi); 310 efx_nic_eventq_read_ack(channel); 311 } 312 313 return spent; 314 } 315 316 /* Create event queue 317 * Event queue memory allocations are done only once. If the channel 318 * is reset, the memory buffer will be reused; this guards against 319 * errors during channel reset and also simplifies interrupt handling. 320 */ 321 static int efx_probe_eventq(struct efx_channel *channel) 322 { 323 struct efx_nic *efx = channel->efx; 324 unsigned long entries; 325 326 netif_dbg(efx, probe, efx->net_dev, 327 "chan %d create event queue\n", channel->channel); 328 329 /* Build an event queue with room for one event per tx and rx buffer, 330 * plus some extra for link state events and MCDI completions. */ 331 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 332 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 333 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 334 335 return efx_nic_probe_eventq(channel); 336 } 337 338 /* Prepare channel's event queue */ 339 static int efx_init_eventq(struct efx_channel *channel) 340 { 341 struct efx_nic *efx = channel->efx; 342 int rc; 343 344 EFX_WARN_ON_PARANOID(channel->eventq_init); 345 346 netif_dbg(efx, drv, efx->net_dev, 347 "chan %d init event queue\n", channel->channel); 348 349 rc = efx_nic_init_eventq(channel); 350 if (rc == 0) { 351 efx->type->push_irq_moderation(channel); 352 channel->eventq_read_ptr = 0; 353 channel->eventq_init = true; 354 } 355 return rc; 356 } 357 358 /* Enable event queue processing and NAPI */ 359 static void efx_start_eventq(struct efx_channel *channel) 360 { 361 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 362 "chan %d start event queue\n", channel->channel); 363 364 /* Make sure the NAPI handler sees the enabled flag set */ 365 channel->enabled = true; 366 smp_wmb(); 367 368 napi_enable(&channel->napi_str); 369 efx_nic_eventq_read_ack(channel); 370 } 371 372 /* Disable event queue processing and NAPI */ 373 static void efx_stop_eventq(struct efx_channel *channel) 374 { 375 if (!channel->enabled) 376 return; 377 378 napi_disable(&channel->napi_str); 379 channel->enabled = false; 380 } 381 382 static void efx_fini_eventq(struct efx_channel *channel) 383 { 384 if (!channel->eventq_init) 385 return; 386 387 netif_dbg(channel->efx, drv, channel->efx->net_dev, 388 "chan %d fini event queue\n", channel->channel); 389 390 efx_nic_fini_eventq(channel); 391 channel->eventq_init = false; 392 } 393 394 static void efx_remove_eventq(struct efx_channel *channel) 395 { 396 netif_dbg(channel->efx, drv, channel->efx->net_dev, 397 "chan %d remove event queue\n", channel->channel); 398 399 efx_nic_remove_eventq(channel); 400 } 401 402 /************************************************************************** 403 * 404 * Channel handling 405 * 406 *************************************************************************/ 407 408 /* Allocate and initialise a channel structure. */ 409 static struct efx_channel * 410 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) 411 { 412 struct efx_channel *channel; 413 struct efx_rx_queue *rx_queue; 414 struct efx_tx_queue *tx_queue; 415 int j; 416 417 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 418 if (!channel) 419 return NULL; 420 421 channel->efx = efx; 422 channel->channel = i; 423 channel->type = &efx_default_channel_type; 424 425 for (j = 0; j < EFX_TXQ_TYPES; j++) { 426 tx_queue = &channel->tx_queue[j]; 427 tx_queue->efx = efx; 428 tx_queue->queue = i * EFX_TXQ_TYPES + j; 429 tx_queue->channel = channel; 430 } 431 432 rx_queue = &channel->rx_queue; 433 rx_queue->efx = efx; 434 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 435 (unsigned long)rx_queue); 436 437 return channel; 438 } 439 440 /* Allocate and initialise a channel structure, copying parameters 441 * (but not resources) from an old channel structure. 442 */ 443 static struct efx_channel * 444 efx_copy_channel(const struct efx_channel *old_channel) 445 { 446 struct efx_channel *channel; 447 struct efx_rx_queue *rx_queue; 448 struct efx_tx_queue *tx_queue; 449 int j; 450 451 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 452 if (!channel) 453 return NULL; 454 455 *channel = *old_channel; 456 457 channel->napi_dev = NULL; 458 memset(&channel->eventq, 0, sizeof(channel->eventq)); 459 460 for (j = 0; j < EFX_TXQ_TYPES; j++) { 461 tx_queue = &channel->tx_queue[j]; 462 if (tx_queue->channel) 463 tx_queue->channel = channel; 464 tx_queue->buffer = NULL; 465 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 466 } 467 468 rx_queue = &channel->rx_queue; 469 rx_queue->buffer = NULL; 470 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 471 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 472 (unsigned long)rx_queue); 473 474 return channel; 475 } 476 477 static int efx_probe_channel(struct efx_channel *channel) 478 { 479 struct efx_tx_queue *tx_queue; 480 struct efx_rx_queue *rx_queue; 481 int rc; 482 483 netif_dbg(channel->efx, probe, channel->efx->net_dev, 484 "creating channel %d\n", channel->channel); 485 486 rc = channel->type->pre_probe(channel); 487 if (rc) 488 goto fail; 489 490 rc = efx_probe_eventq(channel); 491 if (rc) 492 goto fail; 493 494 efx_for_each_channel_tx_queue(tx_queue, channel) { 495 rc = efx_probe_tx_queue(tx_queue); 496 if (rc) 497 goto fail; 498 } 499 500 efx_for_each_channel_rx_queue(rx_queue, channel) { 501 rc = efx_probe_rx_queue(rx_queue); 502 if (rc) 503 goto fail; 504 } 505 506 channel->n_rx_frm_trunc = 0; 507 508 return 0; 509 510 fail: 511 efx_remove_channel(channel); 512 return rc; 513 } 514 515 static void 516 efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 517 { 518 struct efx_nic *efx = channel->efx; 519 const char *type; 520 int number; 521 522 number = channel->channel; 523 if (efx->tx_channel_offset == 0) { 524 type = ""; 525 } else if (channel->channel < efx->tx_channel_offset) { 526 type = "-rx"; 527 } else { 528 type = "-tx"; 529 number -= efx->tx_channel_offset; 530 } 531 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 532 } 533 534 static void efx_set_channel_names(struct efx_nic *efx) 535 { 536 struct efx_channel *channel; 537 538 efx_for_each_channel(channel, efx) 539 channel->type->get_name(channel, 540 efx->msi_context[channel->channel].name, 541 sizeof(efx->msi_context[0].name)); 542 } 543 544 static int efx_probe_channels(struct efx_nic *efx) 545 { 546 struct efx_channel *channel; 547 int rc; 548 549 /* Restart special buffer allocation */ 550 efx->next_buffer_table = 0; 551 552 /* Probe channels in reverse, so that any 'extra' channels 553 * use the start of the buffer table. This allows the traffic 554 * channels to be resized without moving them or wasting the 555 * entries before them. 556 */ 557 efx_for_each_channel_rev(channel, efx) { 558 rc = efx_probe_channel(channel); 559 if (rc) { 560 netif_err(efx, probe, efx->net_dev, 561 "failed to create channel %d\n", 562 channel->channel); 563 goto fail; 564 } 565 } 566 efx_set_channel_names(efx); 567 568 return 0; 569 570 fail: 571 efx_remove_channels(efx); 572 return rc; 573 } 574 575 /* Channels are shutdown and reinitialised whilst the NIC is running 576 * to propagate configuration changes (mtu, checksum offload), or 577 * to clear hardware error conditions 578 */ 579 static void efx_start_datapath(struct efx_nic *efx) 580 { 581 bool old_rx_scatter = efx->rx_scatter; 582 struct efx_tx_queue *tx_queue; 583 struct efx_rx_queue *rx_queue; 584 struct efx_channel *channel; 585 size_t rx_buf_len; 586 587 /* Calculate the rx buffer allocation parameters required to 588 * support the current MTU, including padding for header 589 * alignment and overruns. 590 */ 591 efx->rx_dma_len = (efx->rx_prefix_size + 592 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + 593 efx->type->rx_buffer_padding); 594 rx_buf_len = (sizeof(struct efx_rx_page_state) + 595 efx->rx_ip_align + efx->rx_dma_len); 596 if (rx_buf_len <= PAGE_SIZE) { 597 efx->rx_scatter = efx->type->always_rx_scatter; 598 efx->rx_buffer_order = 0; 599 } else if (efx->type->can_rx_scatter) { 600 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); 601 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + 602 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, 603 EFX_RX_BUF_ALIGNMENT) > 604 PAGE_SIZE); 605 efx->rx_scatter = true; 606 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; 607 efx->rx_buffer_order = 0; 608 } else { 609 efx->rx_scatter = false; 610 efx->rx_buffer_order = get_order(rx_buf_len); 611 } 612 613 efx_rx_config_page_split(efx); 614 if (efx->rx_buffer_order) 615 netif_dbg(efx, drv, efx->net_dev, 616 "RX buf len=%u; page order=%u batch=%u\n", 617 efx->rx_dma_len, efx->rx_buffer_order, 618 efx->rx_pages_per_batch); 619 else 620 netif_dbg(efx, drv, efx->net_dev, 621 "RX buf len=%u step=%u bpp=%u; page batch=%u\n", 622 efx->rx_dma_len, efx->rx_page_buf_step, 623 efx->rx_bufs_per_page, efx->rx_pages_per_batch); 624 625 /* RX filters may also have scatter-enabled flags */ 626 if (efx->rx_scatter != old_rx_scatter) 627 efx->type->filter_update_rx_scatter(efx); 628 629 /* We must keep at least one descriptor in a TX ring empty. 630 * We could avoid this when the queue size does not exactly 631 * match the hardware ring size, but it's not that important. 632 * Therefore we stop the queue when one more skb might fill 633 * the ring completely. We wake it when half way back to 634 * empty. 635 */ 636 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); 637 efx->txq_wake_thresh = efx->txq_stop_thresh / 2; 638 639 /* Initialise the channels */ 640 efx_for_each_channel(channel, efx) { 641 efx_for_each_channel_tx_queue(tx_queue, channel) { 642 efx_init_tx_queue(tx_queue); 643 atomic_inc(&efx->active_queues); 644 } 645 646 efx_for_each_channel_rx_queue(rx_queue, channel) { 647 efx_init_rx_queue(rx_queue); 648 atomic_inc(&efx->active_queues); 649 efx_stop_eventq(channel); 650 efx_fast_push_rx_descriptors(rx_queue, false); 651 efx_start_eventq(channel); 652 } 653 654 WARN_ON(channel->rx_pkt_n_frags); 655 } 656 657 efx_ptp_start_datapath(efx); 658 659 if (netif_device_present(efx->net_dev)) 660 netif_tx_wake_all_queues(efx->net_dev); 661 } 662 663 static void efx_stop_datapath(struct efx_nic *efx) 664 { 665 struct efx_channel *channel; 666 struct efx_tx_queue *tx_queue; 667 struct efx_rx_queue *rx_queue; 668 int rc; 669 670 EFX_ASSERT_RESET_SERIALISED(efx); 671 BUG_ON(efx->port_enabled); 672 673 efx_ptp_stop_datapath(efx); 674 675 /* Stop RX refill */ 676 efx_for_each_channel(channel, efx) { 677 efx_for_each_channel_rx_queue(rx_queue, channel) 678 rx_queue->refill_enabled = false; 679 } 680 681 efx_for_each_channel(channel, efx) { 682 /* RX packet processing is pipelined, so wait for the 683 * NAPI handler to complete. At least event queue 0 684 * might be kept active by non-data events, so don't 685 * use napi_synchronize() but actually disable NAPI 686 * temporarily. 687 */ 688 if (efx_channel_has_rx_queue(channel)) { 689 efx_stop_eventq(channel); 690 efx_start_eventq(channel); 691 } 692 } 693 694 rc = efx->type->fini_dmaq(efx); 695 if (rc && EFX_WORKAROUND_7803(efx)) { 696 /* Schedule a reset to recover from the flush failure. The 697 * descriptor caches reference memory we're about to free, 698 * but falcon_reconfigure_mac_wrapper() won't reconnect 699 * the MACs because of the pending reset. 700 */ 701 netif_err(efx, drv, efx->net_dev, 702 "Resetting to recover from flush failure\n"); 703 efx_schedule_reset(efx, RESET_TYPE_ALL); 704 } else if (rc) { 705 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 706 } else { 707 netif_dbg(efx, drv, efx->net_dev, 708 "successfully flushed all queues\n"); 709 } 710 711 efx_for_each_channel(channel, efx) { 712 efx_for_each_channel_rx_queue(rx_queue, channel) 713 efx_fini_rx_queue(rx_queue); 714 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 715 efx_fini_tx_queue(tx_queue); 716 } 717 } 718 719 static void efx_remove_channel(struct efx_channel *channel) 720 { 721 struct efx_tx_queue *tx_queue; 722 struct efx_rx_queue *rx_queue; 723 724 netif_dbg(channel->efx, drv, channel->efx->net_dev, 725 "destroy chan %d\n", channel->channel); 726 727 efx_for_each_channel_rx_queue(rx_queue, channel) 728 efx_remove_rx_queue(rx_queue); 729 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 730 efx_remove_tx_queue(tx_queue); 731 efx_remove_eventq(channel); 732 channel->type->post_remove(channel); 733 } 734 735 static void efx_remove_channels(struct efx_nic *efx) 736 { 737 struct efx_channel *channel; 738 739 efx_for_each_channel(channel, efx) 740 efx_remove_channel(channel); 741 } 742 743 int 744 efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 745 { 746 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 747 u32 old_rxq_entries, old_txq_entries; 748 unsigned i, next_buffer_table = 0; 749 int rc, rc2; 750 751 rc = efx_check_disabled(efx); 752 if (rc) 753 return rc; 754 755 /* Not all channels should be reallocated. We must avoid 756 * reallocating their buffer table entries. 757 */ 758 efx_for_each_channel(channel, efx) { 759 struct efx_rx_queue *rx_queue; 760 struct efx_tx_queue *tx_queue; 761 762 if (channel->type->copy) 763 continue; 764 next_buffer_table = max(next_buffer_table, 765 channel->eventq.index + 766 channel->eventq.entries); 767 efx_for_each_channel_rx_queue(rx_queue, channel) 768 next_buffer_table = max(next_buffer_table, 769 rx_queue->rxd.index + 770 rx_queue->rxd.entries); 771 efx_for_each_channel_tx_queue(tx_queue, channel) 772 next_buffer_table = max(next_buffer_table, 773 tx_queue->txd.index + 774 tx_queue->txd.entries); 775 } 776 777 efx_device_detach_sync(efx); 778 efx_stop_all(efx); 779 efx_soft_disable_interrupts(efx); 780 781 /* Clone channels (where possible) */ 782 memset(other_channel, 0, sizeof(other_channel)); 783 for (i = 0; i < efx->n_channels; i++) { 784 channel = efx->channel[i]; 785 if (channel->type->copy) 786 channel = channel->type->copy(channel); 787 if (!channel) { 788 rc = -ENOMEM; 789 goto out; 790 } 791 other_channel[i] = channel; 792 } 793 794 /* Swap entry counts and channel pointers */ 795 old_rxq_entries = efx->rxq_entries; 796 old_txq_entries = efx->txq_entries; 797 efx->rxq_entries = rxq_entries; 798 efx->txq_entries = txq_entries; 799 for (i = 0; i < efx->n_channels; i++) { 800 channel = efx->channel[i]; 801 efx->channel[i] = other_channel[i]; 802 other_channel[i] = channel; 803 } 804 805 /* Restart buffer table allocation */ 806 efx->next_buffer_table = next_buffer_table; 807 808 for (i = 0; i < efx->n_channels; i++) { 809 channel = efx->channel[i]; 810 if (!channel->type->copy) 811 continue; 812 rc = efx_probe_channel(channel); 813 if (rc) 814 goto rollback; 815 efx_init_napi_channel(efx->channel[i]); 816 } 817 818 out: 819 /* Destroy unused channel structures */ 820 for (i = 0; i < efx->n_channels; i++) { 821 channel = other_channel[i]; 822 if (channel && channel->type->copy) { 823 efx_fini_napi_channel(channel); 824 efx_remove_channel(channel); 825 kfree(channel); 826 } 827 } 828 829 rc2 = efx_soft_enable_interrupts(efx); 830 if (rc2) { 831 rc = rc ? rc : rc2; 832 netif_err(efx, drv, efx->net_dev, 833 "unable to restart interrupts on channel reallocation\n"); 834 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 835 } else { 836 efx_start_all(efx); 837 netif_device_attach(efx->net_dev); 838 } 839 return rc; 840 841 rollback: 842 /* Swap back */ 843 efx->rxq_entries = old_rxq_entries; 844 efx->txq_entries = old_txq_entries; 845 for (i = 0; i < efx->n_channels; i++) { 846 channel = efx->channel[i]; 847 efx->channel[i] = other_channel[i]; 848 other_channel[i] = channel; 849 } 850 goto out; 851 } 852 853 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) 854 { 855 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); 856 } 857 858 static const struct efx_channel_type efx_default_channel_type = { 859 .pre_probe = efx_channel_dummy_op_int, 860 .post_remove = efx_channel_dummy_op_void, 861 .get_name = efx_get_channel_name, 862 .copy = efx_copy_channel, 863 .keep_eventq = false, 864 }; 865 866 int efx_channel_dummy_op_int(struct efx_channel *channel) 867 { 868 return 0; 869 } 870 871 void efx_channel_dummy_op_void(struct efx_channel *channel) 872 { 873 } 874 875 /************************************************************************** 876 * 877 * Port handling 878 * 879 **************************************************************************/ 880 881 /* This ensures that the kernel is kept informed (via 882 * netif_carrier_on/off) of the link status, and also maintains the 883 * link status's stop on the port's TX queue. 884 */ 885 void efx_link_status_changed(struct efx_nic *efx) 886 { 887 struct efx_link_state *link_state = &efx->link_state; 888 889 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure 890 * that no events are triggered between unregister_netdev() and the 891 * driver unloading. A more general condition is that NETDEV_CHANGE 892 * can only be generated between NETDEV_UP and NETDEV_DOWN */ 893 if (!netif_running(efx->net_dev)) 894 return; 895 896 if (link_state->up != netif_carrier_ok(efx->net_dev)) { 897 efx->n_link_state_changes++; 898 899 if (link_state->up) 900 netif_carrier_on(efx->net_dev); 901 else 902 netif_carrier_off(efx->net_dev); 903 } 904 905 /* Status message for kernel log */ 906 if (link_state->up) 907 netif_info(efx, link, efx->net_dev, 908 "link up at %uMbps %s-duplex (MTU %d)\n", 909 link_state->speed, link_state->fd ? "full" : "half", 910 efx->net_dev->mtu); 911 else 912 netif_info(efx, link, efx->net_dev, "link down\n"); 913 } 914 915 void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) 916 { 917 efx->link_advertising = advertising; 918 if (advertising) { 919 if (advertising & ADVERTISED_Pause) 920 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); 921 else 922 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); 923 if (advertising & ADVERTISED_Asym_Pause) 924 efx->wanted_fc ^= EFX_FC_TX; 925 } 926 } 927 928 void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) 929 { 930 efx->wanted_fc = wanted_fc; 931 if (efx->link_advertising) { 932 if (wanted_fc & EFX_FC_RX) 933 efx->link_advertising |= (ADVERTISED_Pause | 934 ADVERTISED_Asym_Pause); 935 else 936 efx->link_advertising &= ~(ADVERTISED_Pause | 937 ADVERTISED_Asym_Pause); 938 if (wanted_fc & EFX_FC_TX) 939 efx->link_advertising ^= ADVERTISED_Asym_Pause; 940 } 941 } 942 943 static void efx_fini_port(struct efx_nic *efx); 944 945 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure 946 * the MAC appropriately. All other PHY configuration changes are pushed 947 * through phy_op->set_settings(), and pushed asynchronously to the MAC 948 * through efx_monitor(). 949 * 950 * Callers must hold the mac_lock 951 */ 952 int __efx_reconfigure_port(struct efx_nic *efx) 953 { 954 enum efx_phy_mode phy_mode; 955 int rc; 956 957 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 958 959 /* Disable PHY transmit in mac level loopbacks */ 960 phy_mode = efx->phy_mode; 961 if (LOOPBACK_INTERNAL(efx)) 962 efx->phy_mode |= PHY_MODE_TX_DISABLED; 963 else 964 efx->phy_mode &= ~PHY_MODE_TX_DISABLED; 965 966 rc = efx->type->reconfigure_port(efx); 967 968 if (rc) 969 efx->phy_mode = phy_mode; 970 971 return rc; 972 } 973 974 /* Reinitialise the MAC to pick up new PHY settings, even if the port is 975 * disabled. */ 976 int efx_reconfigure_port(struct efx_nic *efx) 977 { 978 int rc; 979 980 EFX_ASSERT_RESET_SERIALISED(efx); 981 982 mutex_lock(&efx->mac_lock); 983 rc = __efx_reconfigure_port(efx); 984 mutex_unlock(&efx->mac_lock); 985 986 return rc; 987 } 988 989 /* Asynchronous work item for changing MAC promiscuity and multicast 990 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current 991 * MAC directly. */ 992 static void efx_mac_work(struct work_struct *data) 993 { 994 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); 995 996 mutex_lock(&efx->mac_lock); 997 if (efx->port_enabled) 998 efx->type->reconfigure_mac(efx); 999 mutex_unlock(&efx->mac_lock); 1000 } 1001 1002 static int efx_probe_port(struct efx_nic *efx) 1003 { 1004 int rc; 1005 1006 netif_dbg(efx, probe, efx->net_dev, "create port\n"); 1007 1008 if (phy_flash_cfg) 1009 efx->phy_mode = PHY_MODE_SPECIAL; 1010 1011 /* Connect up MAC/PHY operations table */ 1012 rc = efx->type->probe_port(efx); 1013 if (rc) 1014 return rc; 1015 1016 /* Initialise MAC address to permanent address */ 1017 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); 1018 1019 return 0; 1020 } 1021 1022 static int efx_init_port(struct efx_nic *efx) 1023 { 1024 int rc; 1025 1026 netif_dbg(efx, drv, efx->net_dev, "init port\n"); 1027 1028 mutex_lock(&efx->mac_lock); 1029 1030 rc = efx->phy_op->init(efx); 1031 if (rc) 1032 goto fail1; 1033 1034 efx->port_initialized = true; 1035 1036 /* Reconfigure the MAC before creating dma queues (required for 1037 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ 1038 efx->type->reconfigure_mac(efx); 1039 1040 /* Ensure the PHY advertises the correct flow control settings */ 1041 rc = efx->phy_op->reconfigure(efx); 1042 if (rc) 1043 goto fail2; 1044 1045 mutex_unlock(&efx->mac_lock); 1046 return 0; 1047 1048 fail2: 1049 efx->phy_op->fini(efx); 1050 fail1: 1051 mutex_unlock(&efx->mac_lock); 1052 return rc; 1053 } 1054 1055 static void efx_start_port(struct efx_nic *efx) 1056 { 1057 netif_dbg(efx, ifup, efx->net_dev, "start port\n"); 1058 BUG_ON(efx->port_enabled); 1059 1060 mutex_lock(&efx->mac_lock); 1061 efx->port_enabled = true; 1062 1063 /* Ensure MAC ingress/egress is enabled */ 1064 efx->type->reconfigure_mac(efx); 1065 1066 mutex_unlock(&efx->mac_lock); 1067 } 1068 1069 /* Cancel work for MAC reconfiguration, periodic hardware monitoring 1070 * and the async self-test, wait for them to finish and prevent them 1071 * being scheduled again. This doesn't cover online resets, which 1072 * should only be cancelled when removing the device. 1073 */ 1074 static void efx_stop_port(struct efx_nic *efx) 1075 { 1076 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); 1077 1078 EFX_ASSERT_RESET_SERIALISED(efx); 1079 1080 mutex_lock(&efx->mac_lock); 1081 efx->port_enabled = false; 1082 mutex_unlock(&efx->mac_lock); 1083 1084 /* Serialise against efx_set_multicast_list() */ 1085 netif_addr_lock_bh(efx->net_dev); 1086 netif_addr_unlock_bh(efx->net_dev); 1087 1088 cancel_delayed_work_sync(&efx->monitor_work); 1089 efx_selftest_async_cancel(efx); 1090 cancel_work_sync(&efx->mac_work); 1091 } 1092 1093 static void efx_fini_port(struct efx_nic *efx) 1094 { 1095 netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); 1096 1097 if (!efx->port_initialized) 1098 return; 1099 1100 efx->phy_op->fini(efx); 1101 efx->port_initialized = false; 1102 1103 efx->link_state.up = false; 1104 efx_link_status_changed(efx); 1105 } 1106 1107 static void efx_remove_port(struct efx_nic *efx) 1108 { 1109 netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); 1110 1111 efx->type->remove_port(efx); 1112 } 1113 1114 /************************************************************************** 1115 * 1116 * NIC handling 1117 * 1118 **************************************************************************/ 1119 1120 static LIST_HEAD(efx_primary_list); 1121 static LIST_HEAD(efx_unassociated_list); 1122 1123 static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right) 1124 { 1125 return left->type == right->type && 1126 left->vpd_sn && right->vpd_sn && 1127 !strcmp(left->vpd_sn, right->vpd_sn); 1128 } 1129 1130 static void efx_associate(struct efx_nic *efx) 1131 { 1132 struct efx_nic *other, *next; 1133 1134 if (efx->primary == efx) { 1135 /* Adding primary function; look for secondaries */ 1136 1137 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); 1138 list_add_tail(&efx->node, &efx_primary_list); 1139 1140 list_for_each_entry_safe(other, next, &efx_unassociated_list, 1141 node) { 1142 if (efx_same_controller(efx, other)) { 1143 list_del(&other->node); 1144 netif_dbg(other, probe, other->net_dev, 1145 "moving to secondary list of %s %s\n", 1146 pci_name(efx->pci_dev), 1147 efx->net_dev->name); 1148 list_add_tail(&other->node, 1149 &efx->secondary_list); 1150 other->primary = efx; 1151 } 1152 } 1153 } else { 1154 /* Adding secondary function; look for primary */ 1155 1156 list_for_each_entry(other, &efx_primary_list, node) { 1157 if (efx_same_controller(efx, other)) { 1158 netif_dbg(efx, probe, efx->net_dev, 1159 "adding to secondary list of %s %s\n", 1160 pci_name(other->pci_dev), 1161 other->net_dev->name); 1162 list_add_tail(&efx->node, 1163 &other->secondary_list); 1164 efx->primary = other; 1165 return; 1166 } 1167 } 1168 1169 netif_dbg(efx, probe, efx->net_dev, 1170 "adding to unassociated list\n"); 1171 list_add_tail(&efx->node, &efx_unassociated_list); 1172 } 1173 } 1174 1175 static void efx_dissociate(struct efx_nic *efx) 1176 { 1177 struct efx_nic *other, *next; 1178 1179 list_del(&efx->node); 1180 efx->primary = NULL; 1181 1182 list_for_each_entry_safe(other, next, &efx->secondary_list, node) { 1183 list_del(&other->node); 1184 netif_dbg(other, probe, other->net_dev, 1185 "moving to unassociated list\n"); 1186 list_add_tail(&other->node, &efx_unassociated_list); 1187 other->primary = NULL; 1188 } 1189 } 1190 1191 /* This configures the PCI device to enable I/O and DMA. */ 1192 static int efx_init_io(struct efx_nic *efx) 1193 { 1194 struct pci_dev *pci_dev = efx->pci_dev; 1195 dma_addr_t dma_mask = efx->type->max_dma_mask; 1196 unsigned int mem_map_size = efx->type->mem_map_size(efx); 1197 int rc; 1198 1199 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); 1200 1201 rc = pci_enable_device(pci_dev); 1202 if (rc) { 1203 netif_err(efx, probe, efx->net_dev, 1204 "failed to enable PCI device\n"); 1205 goto fail1; 1206 } 1207 1208 pci_set_master(pci_dev); 1209 1210 /* Set the PCI DMA mask. Try all possibilities from our 1211 * genuine mask down to 32 bits, because some architectures 1212 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit 1213 * masks event though they reject 46 bit masks. 1214 */ 1215 while (dma_mask > 0x7fffffffUL) { 1216 if (dma_supported(&pci_dev->dev, dma_mask)) { 1217 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); 1218 if (rc == 0) 1219 break; 1220 } 1221 dma_mask >>= 1; 1222 } 1223 if (rc) { 1224 netif_err(efx, probe, efx->net_dev, 1225 "could not find a suitable DMA mask\n"); 1226 goto fail2; 1227 } 1228 netif_dbg(efx, probe, efx->net_dev, 1229 "using DMA mask %llx\n", (unsigned long long) dma_mask); 1230 1231 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); 1232 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); 1233 if (rc) { 1234 netif_err(efx, probe, efx->net_dev, 1235 "request for memory BAR failed\n"); 1236 rc = -EIO; 1237 goto fail3; 1238 } 1239 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); 1240 if (!efx->membase) { 1241 netif_err(efx, probe, efx->net_dev, 1242 "could not map memory BAR at %llx+%x\n", 1243 (unsigned long long)efx->membase_phys, mem_map_size); 1244 rc = -ENOMEM; 1245 goto fail4; 1246 } 1247 netif_dbg(efx, probe, efx->net_dev, 1248 "memory BAR at %llx+%x (virtual %p)\n", 1249 (unsigned long long)efx->membase_phys, mem_map_size, 1250 efx->membase); 1251 1252 return 0; 1253 1254 fail4: 1255 pci_release_region(efx->pci_dev, EFX_MEM_BAR); 1256 fail3: 1257 efx->membase_phys = 0; 1258 fail2: 1259 pci_disable_device(efx->pci_dev); 1260 fail1: 1261 return rc; 1262 } 1263 1264 static void efx_fini_io(struct efx_nic *efx) 1265 { 1266 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); 1267 1268 if (efx->membase) { 1269 iounmap(efx->membase); 1270 efx->membase = NULL; 1271 } 1272 1273 if (efx->membase_phys) { 1274 pci_release_region(efx->pci_dev, EFX_MEM_BAR); 1275 efx->membase_phys = 0; 1276 } 1277 1278 pci_disable_device(efx->pci_dev); 1279 } 1280 1281 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 1282 { 1283 cpumask_var_t thread_mask; 1284 unsigned int count; 1285 int cpu; 1286 1287 if (rss_cpus) { 1288 count = rss_cpus; 1289 } else { 1290 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 1291 netif_warn(efx, probe, efx->net_dev, 1292 "RSS disabled due to allocation failure\n"); 1293 return 1; 1294 } 1295 1296 count = 0; 1297 for_each_online_cpu(cpu) { 1298 if (!cpumask_test_cpu(cpu, thread_mask)) { 1299 ++count; 1300 cpumask_or(thread_mask, thread_mask, 1301 topology_thread_cpumask(cpu)); 1302 } 1303 } 1304 1305 free_cpumask_var(thread_mask); 1306 } 1307 1308 /* If RSS is requested for the PF *and* VFs then we can't write RSS 1309 * table entries that are inaccessible to VFs 1310 */ 1311 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && 1312 count > efx_vf_size(efx)) { 1313 netif_warn(efx, probe, efx->net_dev, 1314 "Reducing number of RSS channels from %u to %u for " 1315 "VF support. Increase vf-msix-limit to use more " 1316 "channels on the PF.\n", 1317 count, efx_vf_size(efx)); 1318 count = efx_vf_size(efx); 1319 } 1320 1321 return count; 1322 } 1323 1324 /* Probe the number and type of interrupts we are able to obtain, and 1325 * the resulting numbers of channels and RX queues. 1326 */ 1327 static int efx_probe_interrupts(struct efx_nic *efx) 1328 { 1329 unsigned int extra_channels = 0; 1330 unsigned int i, j; 1331 int rc; 1332 1333 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 1334 if (efx->extra_channel_type[i]) 1335 ++extra_channels; 1336 1337 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 1338 struct msix_entry xentries[EFX_MAX_CHANNELS]; 1339 unsigned int n_channels; 1340 1341 n_channels = efx_wanted_parallelism(efx); 1342 if (separate_tx_channels) 1343 n_channels *= 2; 1344 n_channels += extra_channels; 1345 n_channels = min(n_channels, efx->max_channels); 1346 1347 for (i = 0; i < n_channels; i++) 1348 xentries[i].entry = i; 1349 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); 1350 if (rc > 0) { 1351 netif_err(efx, drv, efx->net_dev, 1352 "WARNING: Insufficient MSI-X vectors" 1353 " available (%d < %u).\n", rc, n_channels); 1354 netif_err(efx, drv, efx->net_dev, 1355 "WARNING: Performance may be reduced.\n"); 1356 EFX_BUG_ON_PARANOID(rc >= n_channels); 1357 n_channels = rc; 1358 rc = pci_enable_msix(efx->pci_dev, xentries, 1359 n_channels); 1360 } 1361 1362 if (rc == 0) { 1363 efx->n_channels = n_channels; 1364 if (n_channels > extra_channels) 1365 n_channels -= extra_channels; 1366 if (separate_tx_channels) { 1367 efx->n_tx_channels = max(n_channels / 2, 1U); 1368 efx->n_rx_channels = max(n_channels - 1369 efx->n_tx_channels, 1370 1U); 1371 } else { 1372 efx->n_tx_channels = n_channels; 1373 efx->n_rx_channels = n_channels; 1374 } 1375 for (i = 0; i < efx->n_channels; i++) 1376 efx_get_channel(efx, i)->irq = 1377 xentries[i].vector; 1378 } else { 1379 /* Fall back to single channel MSI */ 1380 efx->interrupt_mode = EFX_INT_MODE_MSI; 1381 netif_err(efx, drv, efx->net_dev, 1382 "could not enable MSI-X\n"); 1383 } 1384 } 1385 1386 /* Try single interrupt MSI */ 1387 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 1388 efx->n_channels = 1; 1389 efx->n_rx_channels = 1; 1390 efx->n_tx_channels = 1; 1391 rc = pci_enable_msi(efx->pci_dev); 1392 if (rc == 0) { 1393 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 1394 } else { 1395 netif_err(efx, drv, efx->net_dev, 1396 "could not enable MSI\n"); 1397 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 1398 } 1399 } 1400 1401 /* Assume legacy interrupts */ 1402 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 1403 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); 1404 efx->n_rx_channels = 1; 1405 efx->n_tx_channels = 1; 1406 efx->legacy_irq = efx->pci_dev->irq; 1407 } 1408 1409 /* Assign extra channels if possible */ 1410 j = efx->n_channels; 1411 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 1412 if (!efx->extra_channel_type[i]) 1413 continue; 1414 if (efx->interrupt_mode != EFX_INT_MODE_MSIX || 1415 efx->n_channels <= extra_channels) { 1416 efx->extra_channel_type[i]->handle_no_channel(efx); 1417 } else { 1418 --j; 1419 efx_get_channel(efx, j)->type = 1420 efx->extra_channel_type[i]; 1421 } 1422 } 1423 1424 /* RSS might be usable on VFs even if it is disabled on the PF */ 1425 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? 1426 efx->n_rx_channels : efx_vf_size(efx)); 1427 1428 return 0; 1429 } 1430 1431 static int efx_soft_enable_interrupts(struct efx_nic *efx) 1432 { 1433 struct efx_channel *channel, *end_channel; 1434 int rc; 1435 1436 BUG_ON(efx->state == STATE_DISABLED); 1437 1438 efx->irq_soft_enabled = true; 1439 smp_wmb(); 1440 1441 efx_for_each_channel(channel, efx) { 1442 if (!channel->type->keep_eventq) { 1443 rc = efx_init_eventq(channel); 1444 if (rc) 1445 goto fail; 1446 } 1447 efx_start_eventq(channel); 1448 } 1449 1450 efx_mcdi_mode_event(efx); 1451 1452 return 0; 1453 fail: 1454 end_channel = channel; 1455 efx_for_each_channel(channel, efx) { 1456 if (channel == end_channel) 1457 break; 1458 efx_stop_eventq(channel); 1459 if (!channel->type->keep_eventq) 1460 efx_fini_eventq(channel); 1461 } 1462 1463 return rc; 1464 } 1465 1466 static void efx_soft_disable_interrupts(struct efx_nic *efx) 1467 { 1468 struct efx_channel *channel; 1469 1470 if (efx->state == STATE_DISABLED) 1471 return; 1472 1473 efx_mcdi_mode_poll(efx); 1474 1475 efx->irq_soft_enabled = false; 1476 smp_wmb(); 1477 1478 if (efx->legacy_irq) 1479 synchronize_irq(efx->legacy_irq); 1480 1481 efx_for_each_channel(channel, efx) { 1482 if (channel->irq) 1483 synchronize_irq(channel->irq); 1484 1485 efx_stop_eventq(channel); 1486 if (!channel->type->keep_eventq) 1487 efx_fini_eventq(channel); 1488 } 1489 1490 /* Flush the asynchronous MCDI request queue */ 1491 efx_mcdi_flush_async(efx); 1492 } 1493 1494 static int efx_enable_interrupts(struct efx_nic *efx) 1495 { 1496 struct efx_channel *channel, *end_channel; 1497 int rc; 1498 1499 BUG_ON(efx->state == STATE_DISABLED); 1500 1501 if (efx->eeh_disabled_legacy_irq) { 1502 enable_irq(efx->legacy_irq); 1503 efx->eeh_disabled_legacy_irq = false; 1504 } 1505 1506 efx->type->irq_enable_master(efx); 1507 1508 efx_for_each_channel(channel, efx) { 1509 if (channel->type->keep_eventq) { 1510 rc = efx_init_eventq(channel); 1511 if (rc) 1512 goto fail; 1513 } 1514 } 1515 1516 rc = efx_soft_enable_interrupts(efx); 1517 if (rc) 1518 goto fail; 1519 1520 return 0; 1521 1522 fail: 1523 end_channel = channel; 1524 efx_for_each_channel(channel, efx) { 1525 if (channel == end_channel) 1526 break; 1527 if (channel->type->keep_eventq) 1528 efx_fini_eventq(channel); 1529 } 1530 1531 efx->type->irq_disable_non_ev(efx); 1532 1533 return rc; 1534 } 1535 1536 static void efx_disable_interrupts(struct efx_nic *efx) 1537 { 1538 struct efx_channel *channel; 1539 1540 efx_soft_disable_interrupts(efx); 1541 1542 efx_for_each_channel(channel, efx) { 1543 if (channel->type->keep_eventq) 1544 efx_fini_eventq(channel); 1545 } 1546 1547 efx->type->irq_disable_non_ev(efx); 1548 } 1549 1550 static void efx_remove_interrupts(struct efx_nic *efx) 1551 { 1552 struct efx_channel *channel; 1553 1554 /* Remove MSI/MSI-X interrupts */ 1555 efx_for_each_channel(channel, efx) 1556 channel->irq = 0; 1557 pci_disable_msi(efx->pci_dev); 1558 pci_disable_msix(efx->pci_dev); 1559 1560 /* Remove legacy interrupt */ 1561 efx->legacy_irq = 0; 1562 } 1563 1564 static void efx_set_channels(struct efx_nic *efx) 1565 { 1566 struct efx_channel *channel; 1567 struct efx_tx_queue *tx_queue; 1568 1569 efx->tx_channel_offset = 1570 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; 1571 1572 /* We need to mark which channels really have RX and TX 1573 * queues, and adjust the TX queue numbers if we have separate 1574 * RX-only and TX-only channels. 1575 */ 1576 efx_for_each_channel(channel, efx) { 1577 if (channel->channel < efx->n_rx_channels) 1578 channel->rx_queue.core_index = channel->channel; 1579 else 1580 channel->rx_queue.core_index = -1; 1581 1582 efx_for_each_channel_tx_queue(tx_queue, channel) 1583 tx_queue->queue -= (efx->tx_channel_offset * 1584 EFX_TXQ_TYPES); 1585 } 1586 } 1587 1588 static int efx_probe_nic(struct efx_nic *efx) 1589 { 1590 size_t i; 1591 int rc; 1592 1593 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); 1594 1595 /* Carry out hardware-type specific initialisation */ 1596 rc = efx->type->probe(efx); 1597 if (rc) 1598 return rc; 1599 1600 /* Determine the number of channels and queues by trying to hook 1601 * in MSI-X interrupts. */ 1602 rc = efx_probe_interrupts(efx); 1603 if (rc) 1604 goto fail1; 1605 1606 rc = efx->type->dimension_resources(efx); 1607 if (rc) 1608 goto fail2; 1609 1610 if (efx->n_channels > 1) 1611 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); 1612 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) 1613 efx->rx_indir_table[i] = 1614 ethtool_rxfh_indir_default(i, efx->rss_spread); 1615 1616 efx_set_channels(efx); 1617 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 1618 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 1619 1620 /* Initialise the interrupt moderation settings */ 1621 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, 1622 true); 1623 1624 return 0; 1625 1626 fail2: 1627 efx_remove_interrupts(efx); 1628 fail1: 1629 efx->type->remove(efx); 1630 return rc; 1631 } 1632 1633 static void efx_remove_nic(struct efx_nic *efx) 1634 { 1635 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); 1636 1637 efx_remove_interrupts(efx); 1638 efx->type->remove(efx); 1639 } 1640 1641 static int efx_probe_filters(struct efx_nic *efx) 1642 { 1643 int rc; 1644 1645 spin_lock_init(&efx->filter_lock); 1646 1647 rc = efx->type->filter_table_probe(efx); 1648 if (rc) 1649 return rc; 1650 1651 #ifdef CONFIG_RFS_ACCEL 1652 if (efx->type->offload_features & NETIF_F_NTUPLE) { 1653 efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters, 1654 sizeof(*efx->rps_flow_id), 1655 GFP_KERNEL); 1656 if (!efx->rps_flow_id) { 1657 efx->type->filter_table_remove(efx); 1658 return -ENOMEM; 1659 } 1660 } 1661 #endif 1662 1663 return 0; 1664 } 1665 1666 static void efx_remove_filters(struct efx_nic *efx) 1667 { 1668 #ifdef CONFIG_RFS_ACCEL 1669 kfree(efx->rps_flow_id); 1670 #endif 1671 efx->type->filter_table_remove(efx); 1672 } 1673 1674 static void efx_restore_filters(struct efx_nic *efx) 1675 { 1676 efx->type->filter_table_restore(efx); 1677 } 1678 1679 /************************************************************************** 1680 * 1681 * NIC startup/shutdown 1682 * 1683 *************************************************************************/ 1684 1685 static int efx_probe_all(struct efx_nic *efx) 1686 { 1687 int rc; 1688 1689 rc = efx_probe_nic(efx); 1690 if (rc) { 1691 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); 1692 goto fail1; 1693 } 1694 1695 rc = efx_probe_port(efx); 1696 if (rc) { 1697 netif_err(efx, probe, efx->net_dev, "failed to create port\n"); 1698 goto fail2; 1699 } 1700 1701 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); 1702 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { 1703 rc = -EINVAL; 1704 goto fail3; 1705 } 1706 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; 1707 1708 rc = efx_probe_filters(efx); 1709 if (rc) { 1710 netif_err(efx, probe, efx->net_dev, 1711 "failed to create filter tables\n"); 1712 goto fail3; 1713 } 1714 1715 rc = efx_probe_channels(efx); 1716 if (rc) 1717 goto fail4; 1718 1719 return 0; 1720 1721 fail4: 1722 efx_remove_filters(efx); 1723 fail3: 1724 efx_remove_port(efx); 1725 fail2: 1726 efx_remove_nic(efx); 1727 fail1: 1728 return rc; 1729 } 1730 1731 /* If the interface is supposed to be running but is not, start 1732 * the hardware and software data path, regular activity for the port 1733 * (MAC statistics, link polling, etc.) and schedule the port to be 1734 * reconfigured. Interrupts must already be enabled. This function 1735 * is safe to call multiple times, so long as the NIC is not disabled. 1736 * Requires the RTNL lock. 1737 */ 1738 static void efx_start_all(struct efx_nic *efx) 1739 { 1740 EFX_ASSERT_RESET_SERIALISED(efx); 1741 BUG_ON(efx->state == STATE_DISABLED); 1742 1743 /* Check that it is appropriate to restart the interface. All 1744 * of these flags are safe to read under just the rtnl lock */ 1745 if (efx->port_enabled || !netif_running(efx->net_dev)) 1746 return; 1747 1748 efx_start_port(efx); 1749 efx_start_datapath(efx); 1750 1751 /* Start the hardware monitor if there is one */ 1752 if (efx->type->monitor != NULL) 1753 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1754 efx_monitor_interval); 1755 1756 /* If link state detection is normally event-driven, we have 1757 * to poll now because we could have missed a change 1758 */ 1759 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { 1760 mutex_lock(&efx->mac_lock); 1761 if (efx->phy_op->poll(efx)) 1762 efx_link_status_changed(efx); 1763 mutex_unlock(&efx->mac_lock); 1764 } 1765 1766 efx->type->start_stats(efx); 1767 efx->type->pull_stats(efx); 1768 spin_lock_bh(&efx->stats_lock); 1769 efx->type->update_stats(efx, NULL, NULL); 1770 spin_unlock_bh(&efx->stats_lock); 1771 } 1772 1773 /* Quiesce the hardware and software data path, and regular activity 1774 * for the port without bringing the link down. Safe to call multiple 1775 * times with the NIC in almost any state, but interrupts should be 1776 * enabled. Requires the RTNL lock. 1777 */ 1778 static void efx_stop_all(struct efx_nic *efx) 1779 { 1780 EFX_ASSERT_RESET_SERIALISED(efx); 1781 1782 /* port_enabled can be read safely under the rtnl lock */ 1783 if (!efx->port_enabled) 1784 return; 1785 1786 /* update stats before we go down so we can accurately count 1787 * rx_nodesc_drops 1788 */ 1789 efx->type->pull_stats(efx); 1790 spin_lock_bh(&efx->stats_lock); 1791 efx->type->update_stats(efx, NULL, NULL); 1792 spin_unlock_bh(&efx->stats_lock); 1793 efx->type->stop_stats(efx); 1794 efx_stop_port(efx); 1795 1796 /* Stop the kernel transmit interface. This is only valid if 1797 * the device is stopped or detached; otherwise the watchdog 1798 * may fire immediately. 1799 */ 1800 WARN_ON(netif_running(efx->net_dev) && 1801 netif_device_present(efx->net_dev)); 1802 netif_tx_disable(efx->net_dev); 1803 1804 efx_stop_datapath(efx); 1805 } 1806 1807 static void efx_remove_all(struct efx_nic *efx) 1808 { 1809 efx_remove_channels(efx); 1810 efx_remove_filters(efx); 1811 efx_remove_port(efx); 1812 efx_remove_nic(efx); 1813 } 1814 1815 /************************************************************************** 1816 * 1817 * Interrupt moderation 1818 * 1819 **************************************************************************/ 1820 1821 static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) 1822 { 1823 if (usecs == 0) 1824 return 0; 1825 if (usecs * 1000 < quantum_ns) 1826 return 1; /* never round down to 0 */ 1827 return usecs * 1000 / quantum_ns; 1828 } 1829 1830 /* Set interrupt moderation parameters */ 1831 int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, 1832 unsigned int rx_usecs, bool rx_adaptive, 1833 bool rx_may_override_tx) 1834 { 1835 struct efx_channel *channel; 1836 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * 1837 efx->timer_quantum_ns, 1838 1000); 1839 unsigned int tx_ticks; 1840 unsigned int rx_ticks; 1841 1842 EFX_ASSERT_RESET_SERIALISED(efx); 1843 1844 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) 1845 return -EINVAL; 1846 1847 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); 1848 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); 1849 1850 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && 1851 !rx_may_override_tx) { 1852 netif_err(efx, drv, efx->net_dev, "Channels are shared. " 1853 "RX and TX IRQ moderation must be equal\n"); 1854 return -EINVAL; 1855 } 1856 1857 efx->irq_rx_adaptive = rx_adaptive; 1858 efx->irq_rx_moderation = rx_ticks; 1859 efx_for_each_channel(channel, efx) { 1860 if (efx_channel_has_rx_queue(channel)) 1861 channel->irq_moderation = rx_ticks; 1862 else if (efx_channel_has_tx_queues(channel)) 1863 channel->irq_moderation = tx_ticks; 1864 } 1865 1866 return 0; 1867 } 1868 1869 void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, 1870 unsigned int *rx_usecs, bool *rx_adaptive) 1871 { 1872 /* We must round up when converting ticks to microseconds 1873 * because we round down when converting the other way. 1874 */ 1875 1876 *rx_adaptive = efx->irq_rx_adaptive; 1877 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * 1878 efx->timer_quantum_ns, 1879 1000); 1880 1881 /* If channels are shared between RX and TX, so is IRQ 1882 * moderation. Otherwise, IRQ moderation is the same for all 1883 * TX channels and is not adaptive. 1884 */ 1885 if (efx->tx_channel_offset == 0) 1886 *tx_usecs = *rx_usecs; 1887 else 1888 *tx_usecs = DIV_ROUND_UP( 1889 efx->channel[efx->tx_channel_offset]->irq_moderation * 1890 efx->timer_quantum_ns, 1891 1000); 1892 } 1893 1894 /************************************************************************** 1895 * 1896 * Hardware monitor 1897 * 1898 **************************************************************************/ 1899 1900 /* Run periodically off the general workqueue */ 1901 static void efx_monitor(struct work_struct *data) 1902 { 1903 struct efx_nic *efx = container_of(data, struct efx_nic, 1904 monitor_work.work); 1905 1906 netif_vdbg(efx, timer, efx->net_dev, 1907 "hardware monitor executing on CPU %d\n", 1908 raw_smp_processor_id()); 1909 BUG_ON(efx->type->monitor == NULL); 1910 1911 /* If the mac_lock is already held then it is likely a port 1912 * reconfiguration is already in place, which will likely do 1913 * most of the work of monitor() anyway. */ 1914 if (mutex_trylock(&efx->mac_lock)) { 1915 if (efx->port_enabled) 1916 efx->type->monitor(efx); 1917 mutex_unlock(&efx->mac_lock); 1918 } 1919 1920 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1921 efx_monitor_interval); 1922 } 1923 1924 /************************************************************************** 1925 * 1926 * ioctls 1927 * 1928 *************************************************************************/ 1929 1930 /* Net device ioctl 1931 * Context: process, rtnl_lock() held. 1932 */ 1933 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1934 { 1935 struct efx_nic *efx = netdev_priv(net_dev); 1936 struct mii_ioctl_data *data = if_mii(ifr); 1937 1938 if (cmd == SIOCSHWTSTAMP) 1939 return efx_ptp_set_ts_config(efx, ifr); 1940 if (cmd == SIOCGHWTSTAMP) 1941 return efx_ptp_get_ts_config(efx, ifr); 1942 1943 /* Convert phy_id from older PRTAD/DEVAD format */ 1944 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && 1945 (data->phy_id & 0xfc00) == 0x0400) 1946 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; 1947 1948 return mdio_mii_ioctl(&efx->mdio, data, cmd); 1949 } 1950 1951 /************************************************************************** 1952 * 1953 * NAPI interface 1954 * 1955 **************************************************************************/ 1956 1957 static void efx_init_napi_channel(struct efx_channel *channel) 1958 { 1959 struct efx_nic *efx = channel->efx; 1960 1961 channel->napi_dev = efx->net_dev; 1962 netif_napi_add(channel->napi_dev, &channel->napi_str, 1963 efx_poll, napi_weight); 1964 } 1965 1966 static void efx_init_napi(struct efx_nic *efx) 1967 { 1968 struct efx_channel *channel; 1969 1970 efx_for_each_channel(channel, efx) 1971 efx_init_napi_channel(channel); 1972 } 1973 1974 static void efx_fini_napi_channel(struct efx_channel *channel) 1975 { 1976 if (channel->napi_dev) 1977 netif_napi_del(&channel->napi_str); 1978 channel->napi_dev = NULL; 1979 } 1980 1981 static void efx_fini_napi(struct efx_nic *efx) 1982 { 1983 struct efx_channel *channel; 1984 1985 efx_for_each_channel(channel, efx) 1986 efx_fini_napi_channel(channel); 1987 } 1988 1989 /************************************************************************** 1990 * 1991 * Kernel netpoll interface 1992 * 1993 *************************************************************************/ 1994 1995 #ifdef CONFIG_NET_POLL_CONTROLLER 1996 1997 /* Although in the common case interrupts will be disabled, this is not 1998 * guaranteed. However, all our work happens inside the NAPI callback, 1999 * so no locking is required. 2000 */ 2001 static void efx_netpoll(struct net_device *net_dev) 2002 { 2003 struct efx_nic *efx = netdev_priv(net_dev); 2004 struct efx_channel *channel; 2005 2006 efx_for_each_channel(channel, efx) 2007 efx_schedule_channel(channel); 2008 } 2009 2010 #endif 2011 2012 /************************************************************************** 2013 * 2014 * Kernel net device interface 2015 * 2016 *************************************************************************/ 2017 2018 /* Context: process, rtnl_lock() held. */ 2019 static int efx_net_open(struct net_device *net_dev) 2020 { 2021 struct efx_nic *efx = netdev_priv(net_dev); 2022 int rc; 2023 2024 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", 2025 raw_smp_processor_id()); 2026 2027 rc = efx_check_disabled(efx); 2028 if (rc) 2029 return rc; 2030 if (efx->phy_mode & PHY_MODE_SPECIAL) 2031 return -EBUSY; 2032 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) 2033 return -EIO; 2034 2035 /* Notify the kernel of the link state polled during driver load, 2036 * before the monitor starts running */ 2037 efx_link_status_changed(efx); 2038 2039 efx_start_all(efx); 2040 efx_selftest_async_start(efx); 2041 return 0; 2042 } 2043 2044 /* Context: process, rtnl_lock() held. 2045 * Note that the kernel will ignore our return code; this method 2046 * should really be a void. 2047 */ 2048 static int efx_net_stop(struct net_device *net_dev) 2049 { 2050 struct efx_nic *efx = netdev_priv(net_dev); 2051 2052 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", 2053 raw_smp_processor_id()); 2054 2055 /* Stop the device and flush all the channels */ 2056 efx_stop_all(efx); 2057 2058 return 0; 2059 } 2060 2061 /* Context: process, dev_base_lock or RTNL held, non-blocking. */ 2062 static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, 2063 struct rtnl_link_stats64 *stats) 2064 { 2065 struct efx_nic *efx = netdev_priv(net_dev); 2066 2067 spin_lock_bh(&efx->stats_lock); 2068 efx->type->update_stats(efx, NULL, stats); 2069 spin_unlock_bh(&efx->stats_lock); 2070 2071 return stats; 2072 } 2073 2074 /* Context: netif_tx_lock held, BHs disabled. */ 2075 static void efx_watchdog(struct net_device *net_dev) 2076 { 2077 struct efx_nic *efx = netdev_priv(net_dev); 2078 2079 netif_err(efx, tx_err, efx->net_dev, 2080 "TX stuck with port_enabled=%d: resetting channels\n", 2081 efx->port_enabled); 2082 2083 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); 2084 } 2085 2086 2087 /* Context: process, rtnl_lock() held. */ 2088 static int efx_change_mtu(struct net_device *net_dev, int new_mtu) 2089 { 2090 struct efx_nic *efx = netdev_priv(net_dev); 2091 int rc; 2092 2093 rc = efx_check_disabled(efx); 2094 if (rc) 2095 return rc; 2096 if (new_mtu > EFX_MAX_MTU) 2097 return -EINVAL; 2098 2099 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); 2100 2101 efx_device_detach_sync(efx); 2102 efx_stop_all(efx); 2103 2104 mutex_lock(&efx->mac_lock); 2105 net_dev->mtu = new_mtu; 2106 efx->type->reconfigure_mac(efx); 2107 mutex_unlock(&efx->mac_lock); 2108 2109 efx_start_all(efx); 2110 netif_device_attach(efx->net_dev); 2111 return 0; 2112 } 2113 2114 static int efx_set_mac_address(struct net_device *net_dev, void *data) 2115 { 2116 struct efx_nic *efx = netdev_priv(net_dev); 2117 struct sockaddr *addr = data; 2118 char *new_addr = addr->sa_data; 2119 2120 if (!is_valid_ether_addr(new_addr)) { 2121 netif_err(efx, drv, efx->net_dev, 2122 "invalid ethernet MAC address requested: %pM\n", 2123 new_addr); 2124 return -EADDRNOTAVAIL; 2125 } 2126 2127 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); 2128 efx_sriov_mac_address_changed(efx); 2129 2130 /* Reconfigure the MAC */ 2131 mutex_lock(&efx->mac_lock); 2132 efx->type->reconfigure_mac(efx); 2133 mutex_unlock(&efx->mac_lock); 2134 2135 return 0; 2136 } 2137 2138 /* Context: netif_addr_lock held, BHs disabled. */ 2139 static void efx_set_rx_mode(struct net_device *net_dev) 2140 { 2141 struct efx_nic *efx = netdev_priv(net_dev); 2142 2143 if (efx->port_enabled) 2144 queue_work(efx->workqueue, &efx->mac_work); 2145 /* Otherwise efx_start_port() will do this */ 2146 } 2147 2148 static int efx_set_features(struct net_device *net_dev, netdev_features_t data) 2149 { 2150 struct efx_nic *efx = netdev_priv(net_dev); 2151 2152 /* If disabling RX n-tuple filtering, clear existing filters */ 2153 if (net_dev->features & ~data & NETIF_F_NTUPLE) 2154 return efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); 2155 2156 return 0; 2157 } 2158 2159 static const struct net_device_ops efx_farch_netdev_ops = { 2160 .ndo_open = efx_net_open, 2161 .ndo_stop = efx_net_stop, 2162 .ndo_get_stats64 = efx_net_stats, 2163 .ndo_tx_timeout = efx_watchdog, 2164 .ndo_start_xmit = efx_hard_start_xmit, 2165 .ndo_validate_addr = eth_validate_addr, 2166 .ndo_do_ioctl = efx_ioctl, 2167 .ndo_change_mtu = efx_change_mtu, 2168 .ndo_set_mac_address = efx_set_mac_address, 2169 .ndo_set_rx_mode = efx_set_rx_mode, 2170 .ndo_set_features = efx_set_features, 2171 #ifdef CONFIG_SFC_SRIOV 2172 .ndo_set_vf_mac = efx_sriov_set_vf_mac, 2173 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, 2174 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, 2175 .ndo_get_vf_config = efx_sriov_get_vf_config, 2176 #endif 2177 #ifdef CONFIG_NET_POLL_CONTROLLER 2178 .ndo_poll_controller = efx_netpoll, 2179 #endif 2180 .ndo_setup_tc = efx_setup_tc, 2181 #ifdef CONFIG_RFS_ACCEL 2182 .ndo_rx_flow_steer = efx_filter_rfs, 2183 #endif 2184 }; 2185 2186 static const struct net_device_ops efx_ef10_netdev_ops = { 2187 .ndo_open = efx_net_open, 2188 .ndo_stop = efx_net_stop, 2189 .ndo_get_stats64 = efx_net_stats, 2190 .ndo_tx_timeout = efx_watchdog, 2191 .ndo_start_xmit = efx_hard_start_xmit, 2192 .ndo_validate_addr = eth_validate_addr, 2193 .ndo_do_ioctl = efx_ioctl, 2194 .ndo_change_mtu = efx_change_mtu, 2195 .ndo_set_mac_address = efx_set_mac_address, 2196 .ndo_set_rx_mode = efx_set_rx_mode, 2197 .ndo_set_features = efx_set_features, 2198 #ifdef CONFIG_NET_POLL_CONTROLLER 2199 .ndo_poll_controller = efx_netpoll, 2200 #endif 2201 #ifdef CONFIG_RFS_ACCEL 2202 .ndo_rx_flow_steer = efx_filter_rfs, 2203 #endif 2204 }; 2205 2206 static void efx_update_name(struct efx_nic *efx) 2207 { 2208 strcpy(efx->name, efx->net_dev->name); 2209 efx_mtd_rename(efx); 2210 efx_set_channel_names(efx); 2211 } 2212 2213 static int efx_netdev_event(struct notifier_block *this, 2214 unsigned long event, void *ptr) 2215 { 2216 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); 2217 2218 if ((net_dev->netdev_ops == &efx_farch_netdev_ops || 2219 net_dev->netdev_ops == &efx_ef10_netdev_ops) && 2220 event == NETDEV_CHANGENAME) 2221 efx_update_name(netdev_priv(net_dev)); 2222 2223 return NOTIFY_DONE; 2224 } 2225 2226 static struct notifier_block efx_netdev_notifier = { 2227 .notifier_call = efx_netdev_event, 2228 }; 2229 2230 static ssize_t 2231 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) 2232 { 2233 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2234 return sprintf(buf, "%d\n", efx->phy_type); 2235 } 2236 static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); 2237 2238 static int efx_register_netdev(struct efx_nic *efx) 2239 { 2240 struct net_device *net_dev = efx->net_dev; 2241 struct efx_channel *channel; 2242 int rc; 2243 2244 net_dev->watchdog_timeo = 5 * HZ; 2245 net_dev->irq = efx->pci_dev->irq; 2246 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) { 2247 net_dev->netdev_ops = &efx_ef10_netdev_ops; 2248 net_dev->priv_flags |= IFF_UNICAST_FLT; 2249 } else { 2250 net_dev->netdev_ops = &efx_farch_netdev_ops; 2251 } 2252 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); 2253 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; 2254 2255 rtnl_lock(); 2256 2257 /* Enable resets to be scheduled and check whether any were 2258 * already requested. If so, the NIC is probably hosed so we 2259 * abort. 2260 */ 2261 efx->state = STATE_READY; 2262 smp_mb(); /* ensure we change state before checking reset_pending */ 2263 if (efx->reset_pending) { 2264 netif_err(efx, probe, efx->net_dev, 2265 "aborting probe due to scheduled reset\n"); 2266 rc = -EIO; 2267 goto fail_locked; 2268 } 2269 2270 rc = dev_alloc_name(net_dev, net_dev->name); 2271 if (rc < 0) 2272 goto fail_locked; 2273 efx_update_name(efx); 2274 2275 /* Always start with carrier off; PHY events will detect the link */ 2276 netif_carrier_off(net_dev); 2277 2278 rc = register_netdevice(net_dev); 2279 if (rc) 2280 goto fail_locked; 2281 2282 efx_for_each_channel(channel, efx) { 2283 struct efx_tx_queue *tx_queue; 2284 efx_for_each_channel_tx_queue(tx_queue, channel) 2285 efx_init_tx_queue_core_txq(tx_queue); 2286 } 2287 2288 efx_associate(efx); 2289 2290 rtnl_unlock(); 2291 2292 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2293 if (rc) { 2294 netif_err(efx, drv, efx->net_dev, 2295 "failed to init net dev attributes\n"); 2296 goto fail_registered; 2297 } 2298 2299 return 0; 2300 2301 fail_registered: 2302 rtnl_lock(); 2303 efx_dissociate(efx); 2304 unregister_netdevice(net_dev); 2305 fail_locked: 2306 efx->state = STATE_UNINIT; 2307 rtnl_unlock(); 2308 netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); 2309 return rc; 2310 } 2311 2312 static void efx_unregister_netdev(struct efx_nic *efx) 2313 { 2314 if (!efx->net_dev) 2315 return; 2316 2317 BUG_ON(netdev_priv(efx->net_dev) != efx); 2318 2319 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); 2320 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2321 2322 rtnl_lock(); 2323 unregister_netdevice(efx->net_dev); 2324 efx->state = STATE_UNINIT; 2325 rtnl_unlock(); 2326 } 2327 2328 /************************************************************************** 2329 * 2330 * Device reset and suspend 2331 * 2332 **************************************************************************/ 2333 2334 /* Tears down the entire software state and most of the hardware state 2335 * before reset. */ 2336 void efx_reset_down(struct efx_nic *efx, enum reset_type method) 2337 { 2338 EFX_ASSERT_RESET_SERIALISED(efx); 2339 2340 efx_stop_all(efx); 2341 efx_disable_interrupts(efx); 2342 2343 mutex_lock(&efx->mac_lock); 2344 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) 2345 efx->phy_op->fini(efx); 2346 efx->type->fini(efx); 2347 } 2348 2349 /* This function will always ensure that the locks acquired in 2350 * efx_reset_down() are released. A failure return code indicates 2351 * that we were unable to reinitialise the hardware, and the 2352 * driver should be disabled. If ok is false, then the rx and tx 2353 * engines are not restarted, pending a RESET_DISABLE. */ 2354 int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) 2355 { 2356 int rc; 2357 2358 EFX_ASSERT_RESET_SERIALISED(efx); 2359 2360 rc = efx->type->init(efx); 2361 if (rc) { 2362 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); 2363 goto fail; 2364 } 2365 2366 if (!ok) 2367 goto fail; 2368 2369 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { 2370 rc = efx->phy_op->init(efx); 2371 if (rc) 2372 goto fail; 2373 if (efx->phy_op->reconfigure(efx)) 2374 netif_err(efx, drv, efx->net_dev, 2375 "could not restore PHY settings\n"); 2376 } 2377 2378 rc = efx_enable_interrupts(efx); 2379 if (rc) 2380 goto fail; 2381 efx_restore_filters(efx); 2382 efx_sriov_reset(efx); 2383 2384 mutex_unlock(&efx->mac_lock); 2385 2386 efx_start_all(efx); 2387 2388 return 0; 2389 2390 fail: 2391 efx->port_initialized = false; 2392 2393 mutex_unlock(&efx->mac_lock); 2394 2395 return rc; 2396 } 2397 2398 /* Reset the NIC using the specified method. Note that the reset may 2399 * fail, in which case the card will be left in an unusable state. 2400 * 2401 * Caller must hold the rtnl_lock. 2402 */ 2403 int efx_reset(struct efx_nic *efx, enum reset_type method) 2404 { 2405 int rc, rc2; 2406 bool disabled; 2407 2408 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", 2409 RESET_TYPE(method)); 2410 2411 efx_device_detach_sync(efx); 2412 efx_reset_down(efx, method); 2413 2414 rc = efx->type->reset(efx, method); 2415 if (rc) { 2416 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); 2417 goto out; 2418 } 2419 2420 /* Clear flags for the scopes we covered. We assume the NIC and 2421 * driver are now quiescent so that there is no race here. 2422 */ 2423 efx->reset_pending &= -(1 << (method + 1)); 2424 2425 /* Reinitialise bus-mastering, which may have been turned off before 2426 * the reset was scheduled. This is still appropriate, even in the 2427 * RESET_TYPE_DISABLE since this driver generally assumes the hardware 2428 * can respond to requests. */ 2429 pci_set_master(efx->pci_dev); 2430 2431 out: 2432 /* Leave device stopped if necessary */ 2433 disabled = rc || 2434 method == RESET_TYPE_DISABLE || 2435 method == RESET_TYPE_RECOVER_OR_DISABLE; 2436 rc2 = efx_reset_up(efx, method, !disabled); 2437 if (rc2) { 2438 disabled = true; 2439 if (!rc) 2440 rc = rc2; 2441 } 2442 2443 if (disabled) { 2444 dev_close(efx->net_dev); 2445 netif_err(efx, drv, efx->net_dev, "has been disabled\n"); 2446 efx->state = STATE_DISABLED; 2447 } else { 2448 netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); 2449 netif_device_attach(efx->net_dev); 2450 } 2451 return rc; 2452 } 2453 2454 /* Try recovery mechanisms. 2455 * For now only EEH is supported. 2456 * Returns 0 if the recovery mechanisms are unsuccessful. 2457 * Returns a non-zero value otherwise. 2458 */ 2459 int efx_try_recovery(struct efx_nic *efx) 2460 { 2461 #ifdef CONFIG_EEH 2462 /* A PCI error can occur and not be seen by EEH because nothing 2463 * happens on the PCI bus. In this case the driver may fail and 2464 * schedule a 'recover or reset', leading to this recovery handler. 2465 * Manually call the eeh failure check function. 2466 */ 2467 struct eeh_dev *eehdev = 2468 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev)); 2469 2470 if (eeh_dev_check_failure(eehdev)) { 2471 /* The EEH mechanisms will handle the error and reset the 2472 * device if necessary. 2473 */ 2474 return 1; 2475 } 2476 #endif 2477 return 0; 2478 } 2479 2480 static void efx_wait_for_bist_end(struct efx_nic *efx) 2481 { 2482 int i; 2483 2484 for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { 2485 if (efx_mcdi_poll_reboot(efx)) 2486 goto out; 2487 msleep(BIST_WAIT_DELAY_MS); 2488 } 2489 2490 netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); 2491 out: 2492 /* Either way unset the BIST flag. If we found no reboot we probably 2493 * won't recover, but we should try. 2494 */ 2495 efx->mc_bist_for_other_fn = false; 2496 } 2497 2498 /* The worker thread exists so that code that cannot sleep can 2499 * schedule a reset for later. 2500 */ 2501 static void efx_reset_work(struct work_struct *data) 2502 { 2503 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); 2504 unsigned long pending; 2505 enum reset_type method; 2506 2507 pending = ACCESS_ONCE(efx->reset_pending); 2508 method = fls(pending) - 1; 2509 2510 if (method == RESET_TYPE_MC_BIST) 2511 efx_wait_for_bist_end(efx); 2512 2513 if ((method == RESET_TYPE_RECOVER_OR_DISABLE || 2514 method == RESET_TYPE_RECOVER_OR_ALL) && 2515 efx_try_recovery(efx)) 2516 return; 2517 2518 if (!pending) 2519 return; 2520 2521 rtnl_lock(); 2522 2523 /* We checked the state in efx_schedule_reset() but it may 2524 * have changed by now. Now that we have the RTNL lock, 2525 * it cannot change again. 2526 */ 2527 if (efx->state == STATE_READY) 2528 (void)efx_reset(efx, method); 2529 2530 rtnl_unlock(); 2531 } 2532 2533 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) 2534 { 2535 enum reset_type method; 2536 2537 if (efx->state == STATE_RECOVERY) { 2538 netif_dbg(efx, drv, efx->net_dev, 2539 "recovering: skip scheduling %s reset\n", 2540 RESET_TYPE(type)); 2541 return; 2542 } 2543 2544 switch (type) { 2545 case RESET_TYPE_INVISIBLE: 2546 case RESET_TYPE_ALL: 2547 case RESET_TYPE_RECOVER_OR_ALL: 2548 case RESET_TYPE_WORLD: 2549 case RESET_TYPE_DISABLE: 2550 case RESET_TYPE_RECOVER_OR_DISABLE: 2551 case RESET_TYPE_MC_BIST: 2552 method = type; 2553 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", 2554 RESET_TYPE(method)); 2555 break; 2556 default: 2557 method = efx->type->map_reset_reason(type); 2558 netif_dbg(efx, drv, efx->net_dev, 2559 "scheduling %s reset for %s\n", 2560 RESET_TYPE(method), RESET_TYPE(type)); 2561 break; 2562 } 2563 2564 set_bit(method, &efx->reset_pending); 2565 smp_mb(); /* ensure we change reset_pending before checking state */ 2566 2567 /* If we're not READY then just leave the flags set as the cue 2568 * to abort probing or reschedule the reset later. 2569 */ 2570 if (ACCESS_ONCE(efx->state) != STATE_READY) 2571 return; 2572 2573 /* efx_process_channel() will no longer read events once a 2574 * reset is scheduled. So switch back to poll'd MCDI completions. */ 2575 efx_mcdi_mode_poll(efx); 2576 2577 queue_work(reset_workqueue, &efx->reset_work); 2578 } 2579 2580 /************************************************************************** 2581 * 2582 * List of NICs we support 2583 * 2584 **************************************************************************/ 2585 2586 /* PCI device ID table */ 2587 static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { 2588 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2589 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), 2590 .driver_data = (unsigned long) &falcon_a1_nic_type}, 2591 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2592 PCI_DEVICE_ID_SOLARFLARE_SFC4000B), 2593 .driver_data = (unsigned long) &falcon_b0_nic_type}, 2594 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ 2595 .driver_data = (unsigned long) &siena_a0_nic_type}, 2596 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ 2597 .driver_data = (unsigned long) &siena_a0_nic_type}, 2598 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ 2599 .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, 2600 {0} /* end of list */ 2601 }; 2602 2603 /************************************************************************** 2604 * 2605 * Dummy PHY/MAC operations 2606 * 2607 * Can be used for some unimplemented operations 2608 * Needed so all function pointers are valid and do not have to be tested 2609 * before use 2610 * 2611 **************************************************************************/ 2612 int efx_port_dummy_op_int(struct efx_nic *efx) 2613 { 2614 return 0; 2615 } 2616 void efx_port_dummy_op_void(struct efx_nic *efx) {} 2617 2618 static bool efx_port_dummy_op_poll(struct efx_nic *efx) 2619 { 2620 return false; 2621 } 2622 2623 static const struct efx_phy_operations efx_dummy_phy_operations = { 2624 .init = efx_port_dummy_op_int, 2625 .reconfigure = efx_port_dummy_op_int, 2626 .poll = efx_port_dummy_op_poll, 2627 .fini = efx_port_dummy_op_void, 2628 }; 2629 2630 /************************************************************************** 2631 * 2632 * Data housekeeping 2633 * 2634 **************************************************************************/ 2635 2636 /* This zeroes out and then fills in the invariants in a struct 2637 * efx_nic (including all sub-structures). 2638 */ 2639 static int efx_init_struct(struct efx_nic *efx, 2640 struct pci_dev *pci_dev, struct net_device *net_dev) 2641 { 2642 int i; 2643 2644 /* Initialise common structures */ 2645 INIT_LIST_HEAD(&efx->node); 2646 INIT_LIST_HEAD(&efx->secondary_list); 2647 spin_lock_init(&efx->biu_lock); 2648 #ifdef CONFIG_SFC_MTD 2649 INIT_LIST_HEAD(&efx->mtd_list); 2650 #endif 2651 INIT_WORK(&efx->reset_work, efx_reset_work); 2652 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); 2653 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); 2654 efx->pci_dev = pci_dev; 2655 efx->msg_enable = debug; 2656 efx->state = STATE_UNINIT; 2657 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); 2658 2659 efx->net_dev = net_dev; 2660 efx->rx_prefix_size = efx->type->rx_prefix_size; 2661 efx->rx_ip_align = 2662 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; 2663 efx->rx_packet_hash_offset = 2664 efx->type->rx_hash_offset - efx->type->rx_prefix_size; 2665 efx->rx_packet_ts_offset = 2666 efx->type->rx_ts_offset - efx->type->rx_prefix_size; 2667 spin_lock_init(&efx->stats_lock); 2668 mutex_init(&efx->mac_lock); 2669 efx->phy_op = &efx_dummy_phy_operations; 2670 efx->mdio.dev = net_dev; 2671 INIT_WORK(&efx->mac_work, efx_mac_work); 2672 init_waitqueue_head(&efx->flush_wq); 2673 2674 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 2675 efx->channel[i] = efx_alloc_channel(efx, i, NULL); 2676 if (!efx->channel[i]) 2677 goto fail; 2678 efx->msi_context[i].efx = efx; 2679 efx->msi_context[i].index = i; 2680 } 2681 2682 /* Higher numbered interrupt modes are less capable! */ 2683 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 2684 interrupt_mode); 2685 2686 /* Would be good to use the net_dev name, but we're too early */ 2687 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", 2688 pci_name(pci_dev)); 2689 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); 2690 if (!efx->workqueue) 2691 goto fail; 2692 2693 return 0; 2694 2695 fail: 2696 efx_fini_struct(efx); 2697 return -ENOMEM; 2698 } 2699 2700 static void efx_fini_struct(struct efx_nic *efx) 2701 { 2702 int i; 2703 2704 for (i = 0; i < EFX_MAX_CHANNELS; i++) 2705 kfree(efx->channel[i]); 2706 2707 kfree(efx->vpd_sn); 2708 2709 if (efx->workqueue) { 2710 destroy_workqueue(efx->workqueue); 2711 efx->workqueue = NULL; 2712 } 2713 } 2714 2715 /************************************************************************** 2716 * 2717 * PCI interface 2718 * 2719 **************************************************************************/ 2720 2721 /* Main body of final NIC shutdown code 2722 * This is called only at module unload (or hotplug removal). 2723 */ 2724 static void efx_pci_remove_main(struct efx_nic *efx) 2725 { 2726 /* Flush reset_work. It can no longer be scheduled since we 2727 * are not READY. 2728 */ 2729 BUG_ON(efx->state == STATE_READY); 2730 cancel_work_sync(&efx->reset_work); 2731 2732 efx_disable_interrupts(efx); 2733 efx_nic_fini_interrupt(efx); 2734 efx_fini_port(efx); 2735 efx->type->fini(efx); 2736 efx_fini_napi(efx); 2737 efx_remove_all(efx); 2738 } 2739 2740 /* Final NIC shutdown 2741 * This is called only at module unload (or hotplug removal). 2742 */ 2743 static void efx_pci_remove(struct pci_dev *pci_dev) 2744 { 2745 struct efx_nic *efx; 2746 2747 efx = pci_get_drvdata(pci_dev); 2748 if (!efx) 2749 return; 2750 2751 /* Mark the NIC as fini, then stop the interface */ 2752 rtnl_lock(); 2753 efx_dissociate(efx); 2754 dev_close(efx->net_dev); 2755 efx_disable_interrupts(efx); 2756 rtnl_unlock(); 2757 2758 efx_sriov_fini(efx); 2759 efx_unregister_netdev(efx); 2760 2761 efx_mtd_remove(efx); 2762 2763 efx_pci_remove_main(efx); 2764 2765 efx_fini_io(efx); 2766 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); 2767 2768 efx_fini_struct(efx); 2769 free_netdev(efx->net_dev); 2770 2771 pci_disable_pcie_error_reporting(pci_dev); 2772 }; 2773 2774 /* NIC VPD information 2775 * Called during probe to display the part number of the 2776 * installed NIC. VPD is potentially very large but this should 2777 * always appear within the first 512 bytes. 2778 */ 2779 #define SFC_VPD_LEN 512 2780 static void efx_probe_vpd_strings(struct efx_nic *efx) 2781 { 2782 struct pci_dev *dev = efx->pci_dev; 2783 char vpd_data[SFC_VPD_LEN]; 2784 ssize_t vpd_size; 2785 int ro_start, ro_size, i, j; 2786 2787 /* Get the vpd data from the device */ 2788 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); 2789 if (vpd_size <= 0) { 2790 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); 2791 return; 2792 } 2793 2794 /* Get the Read only section */ 2795 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 2796 if (ro_start < 0) { 2797 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); 2798 return; 2799 } 2800 2801 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); 2802 j = ro_size; 2803 i = ro_start + PCI_VPD_LRDT_TAG_SIZE; 2804 if (i + j > vpd_size) 2805 j = vpd_size - i; 2806 2807 /* Get the Part number */ 2808 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); 2809 if (i < 0) { 2810 netif_err(efx, drv, efx->net_dev, "Part number not found\n"); 2811 return; 2812 } 2813 2814 j = pci_vpd_info_field_size(&vpd_data[i]); 2815 i += PCI_VPD_INFO_FLD_HDR_SIZE; 2816 if (i + j > vpd_size) { 2817 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); 2818 return; 2819 } 2820 2821 netif_info(efx, drv, efx->net_dev, 2822 "Part Number : %.*s\n", j, &vpd_data[i]); 2823 2824 i = ro_start + PCI_VPD_LRDT_TAG_SIZE; 2825 j = ro_size; 2826 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); 2827 if (i < 0) { 2828 netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); 2829 return; 2830 } 2831 2832 j = pci_vpd_info_field_size(&vpd_data[i]); 2833 i += PCI_VPD_INFO_FLD_HDR_SIZE; 2834 if (i + j > vpd_size) { 2835 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); 2836 return; 2837 } 2838 2839 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); 2840 if (!efx->vpd_sn) 2841 return; 2842 2843 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); 2844 } 2845 2846 2847 /* Main body of NIC initialisation 2848 * This is called at module load (or hotplug insertion, theoretically). 2849 */ 2850 static int efx_pci_probe_main(struct efx_nic *efx) 2851 { 2852 int rc; 2853 2854 /* Do start-of-day initialisation */ 2855 rc = efx_probe_all(efx); 2856 if (rc) 2857 goto fail1; 2858 2859 efx_init_napi(efx); 2860 2861 rc = efx->type->init(efx); 2862 if (rc) { 2863 netif_err(efx, probe, efx->net_dev, 2864 "failed to initialise NIC\n"); 2865 goto fail3; 2866 } 2867 2868 rc = efx_init_port(efx); 2869 if (rc) { 2870 netif_err(efx, probe, efx->net_dev, 2871 "failed to initialise port\n"); 2872 goto fail4; 2873 } 2874 2875 rc = efx_nic_init_interrupt(efx); 2876 if (rc) 2877 goto fail5; 2878 rc = efx_enable_interrupts(efx); 2879 if (rc) 2880 goto fail6; 2881 2882 return 0; 2883 2884 fail6: 2885 efx_nic_fini_interrupt(efx); 2886 fail5: 2887 efx_fini_port(efx); 2888 fail4: 2889 efx->type->fini(efx); 2890 fail3: 2891 efx_fini_napi(efx); 2892 efx_remove_all(efx); 2893 fail1: 2894 return rc; 2895 } 2896 2897 /* NIC initialisation 2898 * 2899 * This is called at module load (or hotplug insertion, 2900 * theoretically). It sets up PCI mappings, resets the NIC, 2901 * sets up and registers the network devices with the kernel and hooks 2902 * the interrupt service routine. It does not prepare the device for 2903 * transmission; this is left to the first time one of the network 2904 * interfaces is brought up (i.e. efx_net_open). 2905 */ 2906 static int efx_pci_probe(struct pci_dev *pci_dev, 2907 const struct pci_device_id *entry) 2908 { 2909 struct net_device *net_dev; 2910 struct efx_nic *efx; 2911 int rc; 2912 2913 /* Allocate and initialise a struct net_device and struct efx_nic */ 2914 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, 2915 EFX_MAX_RX_QUEUES); 2916 if (!net_dev) 2917 return -ENOMEM; 2918 efx = netdev_priv(net_dev); 2919 efx->type = (const struct efx_nic_type *) entry->driver_data; 2920 net_dev->features |= (efx->type->offload_features | NETIF_F_SG | 2921 NETIF_F_HIGHDMA | NETIF_F_TSO | 2922 NETIF_F_RXCSUM); 2923 if (efx->type->offload_features & NETIF_F_V6_CSUM) 2924 net_dev->features |= NETIF_F_TSO6; 2925 /* Mask for features that also apply to VLAN devices */ 2926 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | 2927 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | 2928 NETIF_F_RXCSUM); 2929 /* All offloads can be toggled */ 2930 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; 2931 pci_set_drvdata(pci_dev, efx); 2932 SET_NETDEV_DEV(net_dev, &pci_dev->dev); 2933 rc = efx_init_struct(efx, pci_dev, net_dev); 2934 if (rc) 2935 goto fail1; 2936 2937 netif_info(efx, probe, efx->net_dev, 2938 "Solarflare NIC detected\n"); 2939 2940 efx_probe_vpd_strings(efx); 2941 2942 /* Set up basic I/O (BAR mappings etc) */ 2943 rc = efx_init_io(efx); 2944 if (rc) 2945 goto fail2; 2946 2947 rc = efx_pci_probe_main(efx); 2948 if (rc) 2949 goto fail3; 2950 2951 rc = efx_register_netdev(efx); 2952 if (rc) 2953 goto fail4; 2954 2955 rc = efx_sriov_init(efx); 2956 if (rc) 2957 netif_err(efx, probe, efx->net_dev, 2958 "SR-IOV can't be enabled rc %d\n", rc); 2959 2960 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); 2961 2962 /* Try to create MTDs, but allow this to fail */ 2963 rtnl_lock(); 2964 rc = efx_mtd_probe(efx); 2965 rtnl_unlock(); 2966 if (rc) 2967 netif_warn(efx, probe, efx->net_dev, 2968 "failed to create MTDs (%d)\n", rc); 2969 2970 rc = pci_enable_pcie_error_reporting(pci_dev); 2971 if (rc && rc != -EINVAL) 2972 netif_warn(efx, probe, efx->net_dev, 2973 "pci_enable_pcie_error_reporting failed (%d)\n", rc); 2974 2975 return 0; 2976 2977 fail4: 2978 efx_pci_remove_main(efx); 2979 fail3: 2980 efx_fini_io(efx); 2981 fail2: 2982 efx_fini_struct(efx); 2983 fail1: 2984 WARN_ON(rc > 0); 2985 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); 2986 free_netdev(net_dev); 2987 return rc; 2988 } 2989 2990 static int efx_pm_freeze(struct device *dev) 2991 { 2992 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2993 2994 rtnl_lock(); 2995 2996 if (efx->state != STATE_DISABLED) { 2997 efx->state = STATE_UNINIT; 2998 2999 efx_device_detach_sync(efx); 3000 3001 efx_stop_all(efx); 3002 efx_disable_interrupts(efx); 3003 } 3004 3005 rtnl_unlock(); 3006 3007 return 0; 3008 } 3009 3010 static int efx_pm_thaw(struct device *dev) 3011 { 3012 int rc; 3013 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 3014 3015 rtnl_lock(); 3016 3017 if (efx->state != STATE_DISABLED) { 3018 rc = efx_enable_interrupts(efx); 3019 if (rc) 3020 goto fail; 3021 3022 mutex_lock(&efx->mac_lock); 3023 efx->phy_op->reconfigure(efx); 3024 mutex_unlock(&efx->mac_lock); 3025 3026 efx_start_all(efx); 3027 3028 netif_device_attach(efx->net_dev); 3029 3030 efx->state = STATE_READY; 3031 3032 efx->type->resume_wol(efx); 3033 } 3034 3035 rtnl_unlock(); 3036 3037 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ 3038 queue_work(reset_workqueue, &efx->reset_work); 3039 3040 return 0; 3041 3042 fail: 3043 rtnl_unlock(); 3044 3045 return rc; 3046 } 3047 3048 static int efx_pm_poweroff(struct device *dev) 3049 { 3050 struct pci_dev *pci_dev = to_pci_dev(dev); 3051 struct efx_nic *efx = pci_get_drvdata(pci_dev); 3052 3053 efx->type->fini(efx); 3054 3055 efx->reset_pending = 0; 3056 3057 pci_save_state(pci_dev); 3058 return pci_set_power_state(pci_dev, PCI_D3hot); 3059 } 3060 3061 /* Used for both resume and restore */ 3062 static int efx_pm_resume(struct device *dev) 3063 { 3064 struct pci_dev *pci_dev = to_pci_dev(dev); 3065 struct efx_nic *efx = pci_get_drvdata(pci_dev); 3066 int rc; 3067 3068 rc = pci_set_power_state(pci_dev, PCI_D0); 3069 if (rc) 3070 return rc; 3071 pci_restore_state(pci_dev); 3072 rc = pci_enable_device(pci_dev); 3073 if (rc) 3074 return rc; 3075 pci_set_master(efx->pci_dev); 3076 rc = efx->type->reset(efx, RESET_TYPE_ALL); 3077 if (rc) 3078 return rc; 3079 rc = efx->type->init(efx); 3080 if (rc) 3081 return rc; 3082 rc = efx_pm_thaw(dev); 3083 return rc; 3084 } 3085 3086 static int efx_pm_suspend(struct device *dev) 3087 { 3088 int rc; 3089 3090 efx_pm_freeze(dev); 3091 rc = efx_pm_poweroff(dev); 3092 if (rc) 3093 efx_pm_resume(dev); 3094 return rc; 3095 } 3096 3097 static const struct dev_pm_ops efx_pm_ops = { 3098 .suspend = efx_pm_suspend, 3099 .resume = efx_pm_resume, 3100 .freeze = efx_pm_freeze, 3101 .thaw = efx_pm_thaw, 3102 .poweroff = efx_pm_poweroff, 3103 .restore = efx_pm_resume, 3104 }; 3105 3106 /* A PCI error affecting this device was detected. 3107 * At this point MMIO and DMA may be disabled. 3108 * Stop the software path and request a slot reset. 3109 */ 3110 static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, 3111 enum pci_channel_state state) 3112 { 3113 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3114 struct efx_nic *efx = pci_get_drvdata(pdev); 3115 3116 if (state == pci_channel_io_perm_failure) 3117 return PCI_ERS_RESULT_DISCONNECT; 3118 3119 rtnl_lock(); 3120 3121 if (efx->state != STATE_DISABLED) { 3122 efx->state = STATE_RECOVERY; 3123 efx->reset_pending = 0; 3124 3125 efx_device_detach_sync(efx); 3126 3127 efx_stop_all(efx); 3128 efx_disable_interrupts(efx); 3129 3130 status = PCI_ERS_RESULT_NEED_RESET; 3131 } else { 3132 /* If the interface is disabled we don't want to do anything 3133 * with it. 3134 */ 3135 status = PCI_ERS_RESULT_RECOVERED; 3136 } 3137 3138 rtnl_unlock(); 3139 3140 pci_disable_device(pdev); 3141 3142 return status; 3143 } 3144 3145 /* Fake a successfull reset, which will be performed later in efx_io_resume. */ 3146 static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) 3147 { 3148 struct efx_nic *efx = pci_get_drvdata(pdev); 3149 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3150 int rc; 3151 3152 if (pci_enable_device(pdev)) { 3153 netif_err(efx, hw, efx->net_dev, 3154 "Cannot re-enable PCI device after reset.\n"); 3155 status = PCI_ERS_RESULT_DISCONNECT; 3156 } 3157 3158 rc = pci_cleanup_aer_uncorrect_error_status(pdev); 3159 if (rc) { 3160 netif_err(efx, hw, efx->net_dev, 3161 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); 3162 /* Non-fatal error. Continue. */ 3163 } 3164 3165 return status; 3166 } 3167 3168 /* Perform the actual reset and resume I/O operations. */ 3169 static void efx_io_resume(struct pci_dev *pdev) 3170 { 3171 struct efx_nic *efx = pci_get_drvdata(pdev); 3172 int rc; 3173 3174 rtnl_lock(); 3175 3176 if (efx->state == STATE_DISABLED) 3177 goto out; 3178 3179 rc = efx_reset(efx, RESET_TYPE_ALL); 3180 if (rc) { 3181 netif_err(efx, hw, efx->net_dev, 3182 "efx_reset failed after PCI error (%d)\n", rc); 3183 } else { 3184 efx->state = STATE_READY; 3185 netif_dbg(efx, hw, efx->net_dev, 3186 "Done resetting and resuming IO after PCI error.\n"); 3187 } 3188 3189 out: 3190 rtnl_unlock(); 3191 } 3192 3193 /* For simplicity and reliability, we always require a slot reset and try to 3194 * reset the hardware when a pci error affecting the device is detected. 3195 * We leave both the link_reset and mmio_enabled callback unimplemented: 3196 * with our request for slot reset the mmio_enabled callback will never be 3197 * called, and the link_reset callback is not used by AER or EEH mechanisms. 3198 */ 3199 static struct pci_error_handlers efx_err_handlers = { 3200 .error_detected = efx_io_error_detected, 3201 .slot_reset = efx_io_slot_reset, 3202 .resume = efx_io_resume, 3203 }; 3204 3205 static struct pci_driver efx_pci_driver = { 3206 .name = KBUILD_MODNAME, 3207 .id_table = efx_pci_table, 3208 .probe = efx_pci_probe, 3209 .remove = efx_pci_remove, 3210 .driver.pm = &efx_pm_ops, 3211 .err_handler = &efx_err_handlers, 3212 }; 3213 3214 /************************************************************************** 3215 * 3216 * Kernel module interface 3217 * 3218 *************************************************************************/ 3219 3220 module_param(interrupt_mode, uint, 0444); 3221 MODULE_PARM_DESC(interrupt_mode, 3222 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 3223 3224 static int __init efx_init_module(void) 3225 { 3226 int rc; 3227 3228 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); 3229 3230 rc = register_netdevice_notifier(&efx_netdev_notifier); 3231 if (rc) 3232 goto err_notifier; 3233 3234 rc = efx_init_sriov(); 3235 if (rc) 3236 goto err_sriov; 3237 3238 reset_workqueue = create_singlethread_workqueue("sfc_reset"); 3239 if (!reset_workqueue) { 3240 rc = -ENOMEM; 3241 goto err_reset; 3242 } 3243 3244 rc = pci_register_driver(&efx_pci_driver); 3245 if (rc < 0) 3246 goto err_pci; 3247 3248 return 0; 3249 3250 err_pci: 3251 destroy_workqueue(reset_workqueue); 3252 err_reset: 3253 efx_fini_sriov(); 3254 err_sriov: 3255 unregister_netdevice_notifier(&efx_netdev_notifier); 3256 err_notifier: 3257 return rc; 3258 } 3259 3260 static void __exit efx_exit_module(void) 3261 { 3262 printk(KERN_INFO "Solarflare NET driver unloading\n"); 3263 3264 pci_unregister_driver(&efx_pci_driver); 3265 destroy_workqueue(reset_workqueue); 3266 efx_fini_sriov(); 3267 unregister_netdevice_notifier(&efx_netdev_notifier); 3268 3269 } 3270 3271 module_init(efx_init_module); 3272 module_exit(efx_exit_module); 3273 3274 MODULE_AUTHOR("Solarflare Communications and " 3275 "Michael Brown <mbrown@fensystems.co.uk>"); 3276 MODULE_DESCRIPTION("Solarflare Communications network driver"); 3277 MODULE_LICENSE("GPL"); 3278 MODULE_DEVICE_TABLE(pci, efx_pci_table); 3279