1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/delay.h> 16 #include <linux/notifier.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/in.h> 20 #include <linux/ethtool.h> 21 #include <linux/topology.h> 22 #include <linux/gfp.h> 23 #include <linux/aer.h> 24 #include <linux/interrupt.h> 25 #include "net_driver.h" 26 #include <net/gre.h> 27 #include <net/udp_tunnel.h> 28 #include "efx.h" 29 #include "nic.h" 30 #include "selftest.h" 31 #include "sriov.h" 32 33 #include "mcdi.h" 34 #include "mcdi_pcol.h" 35 #include "workarounds.h" 36 37 /************************************************************************** 38 * 39 * Type name strings 40 * 41 ************************************************************************** 42 */ 43 44 /* Loopback mode names (see LOOPBACK_MODE()) */ 45 const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; 46 const char *const efx_loopback_mode_names[] = { 47 [LOOPBACK_NONE] = "NONE", 48 [LOOPBACK_DATA] = "DATAPATH", 49 [LOOPBACK_GMAC] = "GMAC", 50 [LOOPBACK_XGMII] = "XGMII", 51 [LOOPBACK_XGXS] = "XGXS", 52 [LOOPBACK_XAUI] = "XAUI", 53 [LOOPBACK_GMII] = "GMII", 54 [LOOPBACK_SGMII] = "SGMII", 55 [LOOPBACK_XGBR] = "XGBR", 56 [LOOPBACK_XFI] = "XFI", 57 [LOOPBACK_XAUI_FAR] = "XAUI_FAR", 58 [LOOPBACK_GMII_FAR] = "GMII_FAR", 59 [LOOPBACK_SGMII_FAR] = "SGMII_FAR", 60 [LOOPBACK_XFI_FAR] = "XFI_FAR", 61 [LOOPBACK_GPHY] = "GPHY", 62 [LOOPBACK_PHYXS] = "PHYXS", 63 [LOOPBACK_PCS] = "PCS", 64 [LOOPBACK_PMAPMD] = "PMA/PMD", 65 [LOOPBACK_XPORT] = "XPORT", 66 [LOOPBACK_XGMII_WS] = "XGMII_WS", 67 [LOOPBACK_XAUI_WS] = "XAUI_WS", 68 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", 69 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", 70 [LOOPBACK_GMII_WS] = "GMII_WS", 71 [LOOPBACK_XFI_WS] = "XFI_WS", 72 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", 73 [LOOPBACK_PHYXS_WS] = "PHYXS_WS", 74 }; 75 76 const unsigned int efx_reset_type_max = RESET_TYPE_MAX; 77 const char *const efx_reset_type_names[] = { 78 [RESET_TYPE_INVISIBLE] = "INVISIBLE", 79 [RESET_TYPE_ALL] = "ALL", 80 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", 81 [RESET_TYPE_WORLD] = "WORLD", 82 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", 83 [RESET_TYPE_DATAPATH] = "DATAPATH", 84 [RESET_TYPE_MC_BIST] = "MC_BIST", 85 [RESET_TYPE_DISABLE] = "DISABLE", 86 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", 87 [RESET_TYPE_INT_ERROR] = "INT_ERROR", 88 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", 89 [RESET_TYPE_TX_SKIP] = "TX_SKIP", 90 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", 91 [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)", 92 }; 93 94 /* UDP tunnel type names */ 95 static const char *const efx_udp_tunnel_type_names[] = { 96 [TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN] = "vxlan", 97 [TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE] = "geneve", 98 }; 99 100 void efx_get_udp_tunnel_type_name(u16 type, char *buf, size_t buflen) 101 { 102 if (type < ARRAY_SIZE(efx_udp_tunnel_type_names) && 103 efx_udp_tunnel_type_names[type] != NULL) 104 snprintf(buf, buflen, "%s", efx_udp_tunnel_type_names[type]); 105 else 106 snprintf(buf, buflen, "type %d", type); 107 } 108 109 /* Reset workqueue. If any NIC has a hardware failure then a reset will be 110 * queued onto this work queue. This is not a per-nic work queue, because 111 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. 112 */ 113 static struct workqueue_struct *reset_workqueue; 114 115 /* How often and how many times to poll for a reset while waiting for a 116 * BIST that another function started to complete. 117 */ 118 #define BIST_WAIT_DELAY_MS 100 119 #define BIST_WAIT_DELAY_COUNT 100 120 121 /************************************************************************** 122 * 123 * Configurable values 124 * 125 *************************************************************************/ 126 127 /* 128 * Use separate channels for TX and RX events 129 * 130 * Set this to 1 to use separate channels for TX and RX. It allows us 131 * to control interrupt affinity separately for TX and RX. 132 * 133 * This is only used in MSI-X interrupt mode 134 */ 135 bool efx_separate_tx_channels; 136 module_param(efx_separate_tx_channels, bool, 0444); 137 MODULE_PARM_DESC(efx_separate_tx_channels, 138 "Use separate channels for TX and RX"); 139 140 /* This is the weight assigned to each of the (per-channel) virtual 141 * NAPI devices. 142 */ 143 static int napi_weight = 64; 144 145 /* This is the time (in jiffies) between invocations of the hardware 146 * monitor. 147 * On Falcon-based NICs, this will: 148 * - Check the on-board hardware monitor; 149 * - Poll the link state and reconfigure the hardware as necessary. 150 * On Siena-based NICs for power systems with EEH support, this will give EEH a 151 * chance to start. 152 */ 153 static unsigned int efx_monitor_interval = 1 * HZ; 154 155 /* Initial interrupt moderation settings. They can be modified after 156 * module load with ethtool. 157 * 158 * The default for RX should strike a balance between increasing the 159 * round-trip latency and reducing overhead. 160 */ 161 static unsigned int rx_irq_mod_usec = 60; 162 163 /* Initial interrupt moderation settings. They can be modified after 164 * module load with ethtool. 165 * 166 * This default is chosen to ensure that a 10G link does not go idle 167 * while a TX queue is stopped after it has become full. A queue is 168 * restarted when it drops below half full. The time this takes (assuming 169 * worst case 3 descriptors per packet and 1024 descriptors) is 170 * 512 / 3 * 1.2 = 205 usec. 171 */ 172 static unsigned int tx_irq_mod_usec = 150; 173 174 /* This is the first interrupt mode to try out of: 175 * 0 => MSI-X 176 * 1 => MSI 177 * 2 => legacy 178 */ 179 static unsigned int interrupt_mode; 180 181 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 182 * i.e. the number of CPUs among which we may distribute simultaneous 183 * interrupt handling. 184 * 185 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 186 * The default (0) means to assign an interrupt to each core. 187 */ 188 static unsigned int rss_cpus; 189 module_param(rss_cpus, uint, 0444); 190 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 191 192 static bool phy_flash_cfg; 193 module_param(phy_flash_cfg, bool, 0644); 194 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); 195 196 static unsigned irq_adapt_low_thresh = 8000; 197 module_param(irq_adapt_low_thresh, uint, 0644); 198 MODULE_PARM_DESC(irq_adapt_low_thresh, 199 "Threshold score for reducing IRQ moderation"); 200 201 static unsigned irq_adapt_high_thresh = 16000; 202 module_param(irq_adapt_high_thresh, uint, 0644); 203 MODULE_PARM_DESC(irq_adapt_high_thresh, 204 "Threshold score for increasing IRQ moderation"); 205 206 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 207 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 208 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | 209 NETIF_MSG_TX_ERR | NETIF_MSG_HW); 210 module_param(debug, uint, 0); 211 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); 212 213 /************************************************************************** 214 * 215 * Utility functions and prototypes 216 * 217 *************************************************************************/ 218 219 static int efx_soft_enable_interrupts(struct efx_nic *efx); 220 static void efx_soft_disable_interrupts(struct efx_nic *efx); 221 static void efx_remove_channel(struct efx_channel *channel); 222 static void efx_remove_channels(struct efx_nic *efx); 223 static const struct efx_channel_type efx_default_channel_type; 224 static void efx_remove_port(struct efx_nic *efx); 225 static void efx_init_napi_channel(struct efx_channel *channel); 226 static void efx_fini_napi(struct efx_nic *efx); 227 static void efx_fini_napi_channel(struct efx_channel *channel); 228 static void efx_fini_struct(struct efx_nic *efx); 229 static void efx_start_all(struct efx_nic *efx); 230 static void efx_stop_all(struct efx_nic *efx); 231 232 #define EFX_ASSERT_RESET_SERIALISED(efx) \ 233 do { \ 234 if ((efx->state == STATE_READY) || \ 235 (efx->state == STATE_RECOVERY) || \ 236 (efx->state == STATE_DISABLED)) \ 237 ASSERT_RTNL(); \ 238 } while (0) 239 240 static int efx_check_disabled(struct efx_nic *efx) 241 { 242 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { 243 netif_err(efx, drv, efx->net_dev, 244 "device is disabled due to earlier errors\n"); 245 return -EIO; 246 } 247 return 0; 248 } 249 250 /************************************************************************** 251 * 252 * Event queue processing 253 * 254 *************************************************************************/ 255 256 /* Process channel's event queue 257 * 258 * This function is responsible for processing the event queue of a 259 * single channel. The caller must guarantee that this function will 260 * never be concurrently called more than once on the same channel, 261 * though different channels may be being processed concurrently. 262 */ 263 static int efx_process_channel(struct efx_channel *channel, int budget) 264 { 265 struct efx_tx_queue *tx_queue; 266 int spent; 267 268 if (unlikely(!channel->enabled)) 269 return 0; 270 271 efx_for_each_channel_tx_queue(tx_queue, channel) { 272 tx_queue->pkts_compl = 0; 273 tx_queue->bytes_compl = 0; 274 } 275 276 spent = efx_nic_process_eventq(channel, budget); 277 if (spent && efx_channel_has_rx_queue(channel)) { 278 struct efx_rx_queue *rx_queue = 279 efx_channel_get_rx_queue(channel); 280 281 efx_rx_flush_packet(channel); 282 efx_fast_push_rx_descriptors(rx_queue, true); 283 } 284 285 /* Update BQL */ 286 efx_for_each_channel_tx_queue(tx_queue, channel) { 287 if (tx_queue->bytes_compl) { 288 netdev_tx_completed_queue(tx_queue->core_txq, 289 tx_queue->pkts_compl, tx_queue->bytes_compl); 290 } 291 } 292 293 return spent; 294 } 295 296 /* NAPI poll handler 297 * 298 * NAPI guarantees serialisation of polls of the same device, which 299 * provides the guarantee required by efx_process_channel(). 300 */ 301 static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel) 302 { 303 int step = efx->irq_mod_step_us; 304 305 if (channel->irq_mod_score < irq_adapt_low_thresh) { 306 if (channel->irq_moderation_us > step) { 307 channel->irq_moderation_us -= step; 308 efx->type->push_irq_moderation(channel); 309 } 310 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { 311 if (channel->irq_moderation_us < 312 efx->irq_rx_moderation_us) { 313 channel->irq_moderation_us += step; 314 efx->type->push_irq_moderation(channel); 315 } 316 } 317 318 channel->irq_count = 0; 319 channel->irq_mod_score = 0; 320 } 321 322 static int efx_poll(struct napi_struct *napi, int budget) 323 { 324 struct efx_channel *channel = 325 container_of(napi, struct efx_channel, napi_str); 326 struct efx_nic *efx = channel->efx; 327 int spent; 328 329 netif_vdbg(efx, intr, efx->net_dev, 330 "channel %d NAPI poll executing on CPU %d\n", 331 channel->channel, raw_smp_processor_id()); 332 333 spent = efx_process_channel(channel, budget); 334 335 if (spent < budget) { 336 if (efx_channel_has_rx_queue(channel) && 337 efx->irq_rx_adaptive && 338 unlikely(++channel->irq_count == 1000)) { 339 efx_update_irq_mod(efx, channel); 340 } 341 342 efx_filter_rfs_expire(channel); 343 344 /* There is no race here; although napi_disable() will 345 * only wait for napi_complete(), this isn't a problem 346 * since efx_nic_eventq_read_ack() will have no effect if 347 * interrupts have already been disabled. 348 */ 349 if (napi_complete_done(napi, spent)) 350 efx_nic_eventq_read_ack(channel); 351 } 352 353 return spent; 354 } 355 356 /* Create event queue 357 * Event queue memory allocations are done only once. If the channel 358 * is reset, the memory buffer will be reused; this guards against 359 * errors during channel reset and also simplifies interrupt handling. 360 */ 361 static int efx_probe_eventq(struct efx_channel *channel) 362 { 363 struct efx_nic *efx = channel->efx; 364 unsigned long entries; 365 366 netif_dbg(efx, probe, efx->net_dev, 367 "chan %d create event queue\n", channel->channel); 368 369 /* Build an event queue with room for one event per tx and rx buffer, 370 * plus some extra for link state events and MCDI completions. */ 371 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 372 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 373 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 374 375 return efx_nic_probe_eventq(channel); 376 } 377 378 /* Prepare channel's event queue */ 379 static int efx_init_eventq(struct efx_channel *channel) 380 { 381 struct efx_nic *efx = channel->efx; 382 int rc; 383 384 EFX_WARN_ON_PARANOID(channel->eventq_init); 385 386 netif_dbg(efx, drv, efx->net_dev, 387 "chan %d init event queue\n", channel->channel); 388 389 rc = efx_nic_init_eventq(channel); 390 if (rc == 0) { 391 efx->type->push_irq_moderation(channel); 392 channel->eventq_read_ptr = 0; 393 channel->eventq_init = true; 394 } 395 return rc; 396 } 397 398 /* Enable event queue processing and NAPI */ 399 void efx_start_eventq(struct efx_channel *channel) 400 { 401 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 402 "chan %d start event queue\n", channel->channel); 403 404 /* Make sure the NAPI handler sees the enabled flag set */ 405 channel->enabled = true; 406 smp_wmb(); 407 408 napi_enable(&channel->napi_str); 409 efx_nic_eventq_read_ack(channel); 410 } 411 412 /* Disable event queue processing and NAPI */ 413 void efx_stop_eventq(struct efx_channel *channel) 414 { 415 if (!channel->enabled) 416 return; 417 418 napi_disable(&channel->napi_str); 419 channel->enabled = false; 420 } 421 422 static void efx_fini_eventq(struct efx_channel *channel) 423 { 424 if (!channel->eventq_init) 425 return; 426 427 netif_dbg(channel->efx, drv, channel->efx->net_dev, 428 "chan %d fini event queue\n", channel->channel); 429 430 efx_nic_fini_eventq(channel); 431 channel->eventq_init = false; 432 } 433 434 static void efx_remove_eventq(struct efx_channel *channel) 435 { 436 netif_dbg(channel->efx, drv, channel->efx->net_dev, 437 "chan %d remove event queue\n", channel->channel); 438 439 efx_nic_remove_eventq(channel); 440 } 441 442 /************************************************************************** 443 * 444 * Channel handling 445 * 446 *************************************************************************/ 447 448 /* Allocate and initialise a channel structure. */ 449 static struct efx_channel * 450 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) 451 { 452 struct efx_channel *channel; 453 struct efx_rx_queue *rx_queue; 454 struct efx_tx_queue *tx_queue; 455 int j; 456 457 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 458 if (!channel) 459 return NULL; 460 461 channel->efx = efx; 462 channel->channel = i; 463 channel->type = &efx_default_channel_type; 464 465 for (j = 0; j < EFX_TXQ_TYPES; j++) { 466 tx_queue = &channel->tx_queue[j]; 467 tx_queue->efx = efx; 468 tx_queue->queue = i * EFX_TXQ_TYPES + j; 469 tx_queue->channel = channel; 470 } 471 472 rx_queue = &channel->rx_queue; 473 rx_queue->efx = efx; 474 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 475 (unsigned long)rx_queue); 476 477 return channel; 478 } 479 480 /* Allocate and initialise a channel structure, copying parameters 481 * (but not resources) from an old channel structure. 482 */ 483 static struct efx_channel * 484 efx_copy_channel(const struct efx_channel *old_channel) 485 { 486 struct efx_channel *channel; 487 struct efx_rx_queue *rx_queue; 488 struct efx_tx_queue *tx_queue; 489 int j; 490 491 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 492 if (!channel) 493 return NULL; 494 495 *channel = *old_channel; 496 497 channel->napi_dev = NULL; 498 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); 499 channel->napi_str.napi_id = 0; 500 channel->napi_str.state = 0; 501 memset(&channel->eventq, 0, sizeof(channel->eventq)); 502 503 for (j = 0; j < EFX_TXQ_TYPES; j++) { 504 tx_queue = &channel->tx_queue[j]; 505 if (tx_queue->channel) 506 tx_queue->channel = channel; 507 tx_queue->buffer = NULL; 508 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 509 } 510 511 rx_queue = &channel->rx_queue; 512 rx_queue->buffer = NULL; 513 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 514 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 515 (unsigned long)rx_queue); 516 517 return channel; 518 } 519 520 static int efx_probe_channel(struct efx_channel *channel) 521 { 522 struct efx_tx_queue *tx_queue; 523 struct efx_rx_queue *rx_queue; 524 int rc; 525 526 netif_dbg(channel->efx, probe, channel->efx->net_dev, 527 "creating channel %d\n", channel->channel); 528 529 rc = channel->type->pre_probe(channel); 530 if (rc) 531 goto fail; 532 533 rc = efx_probe_eventq(channel); 534 if (rc) 535 goto fail; 536 537 efx_for_each_channel_tx_queue(tx_queue, channel) { 538 rc = efx_probe_tx_queue(tx_queue); 539 if (rc) 540 goto fail; 541 } 542 543 efx_for_each_channel_rx_queue(rx_queue, channel) { 544 rc = efx_probe_rx_queue(rx_queue); 545 if (rc) 546 goto fail; 547 } 548 549 return 0; 550 551 fail: 552 efx_remove_channel(channel); 553 return rc; 554 } 555 556 static void 557 efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 558 { 559 struct efx_nic *efx = channel->efx; 560 const char *type; 561 int number; 562 563 number = channel->channel; 564 if (efx->tx_channel_offset == 0) { 565 type = ""; 566 } else if (channel->channel < efx->tx_channel_offset) { 567 type = "-rx"; 568 } else { 569 type = "-tx"; 570 number -= efx->tx_channel_offset; 571 } 572 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 573 } 574 575 static void efx_set_channel_names(struct efx_nic *efx) 576 { 577 struct efx_channel *channel; 578 579 efx_for_each_channel(channel, efx) 580 channel->type->get_name(channel, 581 efx->msi_context[channel->channel].name, 582 sizeof(efx->msi_context[0].name)); 583 } 584 585 static int efx_probe_channels(struct efx_nic *efx) 586 { 587 struct efx_channel *channel; 588 int rc; 589 590 /* Restart special buffer allocation */ 591 efx->next_buffer_table = 0; 592 593 /* Probe channels in reverse, so that any 'extra' channels 594 * use the start of the buffer table. This allows the traffic 595 * channels to be resized without moving them or wasting the 596 * entries before them. 597 */ 598 efx_for_each_channel_rev(channel, efx) { 599 rc = efx_probe_channel(channel); 600 if (rc) { 601 netif_err(efx, probe, efx->net_dev, 602 "failed to create channel %d\n", 603 channel->channel); 604 goto fail; 605 } 606 } 607 efx_set_channel_names(efx); 608 609 return 0; 610 611 fail: 612 efx_remove_channels(efx); 613 return rc; 614 } 615 616 /* Channels are shutdown and reinitialised whilst the NIC is running 617 * to propagate configuration changes (mtu, checksum offload), or 618 * to clear hardware error conditions 619 */ 620 static void efx_start_datapath(struct efx_nic *efx) 621 { 622 netdev_features_t old_features = efx->net_dev->features; 623 bool old_rx_scatter = efx->rx_scatter; 624 struct efx_tx_queue *tx_queue; 625 struct efx_rx_queue *rx_queue; 626 struct efx_channel *channel; 627 size_t rx_buf_len; 628 629 /* Calculate the rx buffer allocation parameters required to 630 * support the current MTU, including padding for header 631 * alignment and overruns. 632 */ 633 efx->rx_dma_len = (efx->rx_prefix_size + 634 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + 635 efx->type->rx_buffer_padding); 636 rx_buf_len = (sizeof(struct efx_rx_page_state) + 637 efx->rx_ip_align + efx->rx_dma_len); 638 if (rx_buf_len <= PAGE_SIZE) { 639 efx->rx_scatter = efx->type->always_rx_scatter; 640 efx->rx_buffer_order = 0; 641 } else if (efx->type->can_rx_scatter) { 642 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); 643 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + 644 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, 645 EFX_RX_BUF_ALIGNMENT) > 646 PAGE_SIZE); 647 efx->rx_scatter = true; 648 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; 649 efx->rx_buffer_order = 0; 650 } else { 651 efx->rx_scatter = false; 652 efx->rx_buffer_order = get_order(rx_buf_len); 653 } 654 655 efx_rx_config_page_split(efx); 656 if (efx->rx_buffer_order) 657 netif_dbg(efx, drv, efx->net_dev, 658 "RX buf len=%u; page order=%u batch=%u\n", 659 efx->rx_dma_len, efx->rx_buffer_order, 660 efx->rx_pages_per_batch); 661 else 662 netif_dbg(efx, drv, efx->net_dev, 663 "RX buf len=%u step=%u bpp=%u; page batch=%u\n", 664 efx->rx_dma_len, efx->rx_page_buf_step, 665 efx->rx_bufs_per_page, efx->rx_pages_per_batch); 666 667 /* Restore previously fixed features in hw_features and remove 668 * features which are fixed now 669 */ 670 efx->net_dev->hw_features |= efx->net_dev->features; 671 efx->net_dev->hw_features &= ~efx->fixed_features; 672 efx->net_dev->features |= efx->fixed_features; 673 if (efx->net_dev->features != old_features) 674 netdev_features_change(efx->net_dev); 675 676 /* RX filters may also have scatter-enabled flags */ 677 if (efx->rx_scatter != old_rx_scatter) 678 efx->type->filter_update_rx_scatter(efx); 679 680 /* We must keep at least one descriptor in a TX ring empty. 681 * We could avoid this when the queue size does not exactly 682 * match the hardware ring size, but it's not that important. 683 * Therefore we stop the queue when one more skb might fill 684 * the ring completely. We wake it when half way back to 685 * empty. 686 */ 687 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); 688 efx->txq_wake_thresh = efx->txq_stop_thresh / 2; 689 690 /* Initialise the channels */ 691 efx_for_each_channel(channel, efx) { 692 efx_for_each_channel_tx_queue(tx_queue, channel) { 693 efx_init_tx_queue(tx_queue); 694 atomic_inc(&efx->active_queues); 695 } 696 697 efx_for_each_channel_rx_queue(rx_queue, channel) { 698 efx_init_rx_queue(rx_queue); 699 atomic_inc(&efx->active_queues); 700 efx_stop_eventq(channel); 701 efx_fast_push_rx_descriptors(rx_queue, false); 702 efx_start_eventq(channel); 703 } 704 705 WARN_ON(channel->rx_pkt_n_frags); 706 } 707 708 efx_ptp_start_datapath(efx); 709 710 if (netif_device_present(efx->net_dev)) 711 netif_tx_wake_all_queues(efx->net_dev); 712 } 713 714 static void efx_stop_datapath(struct efx_nic *efx) 715 { 716 struct efx_channel *channel; 717 struct efx_tx_queue *tx_queue; 718 struct efx_rx_queue *rx_queue; 719 int rc; 720 721 EFX_ASSERT_RESET_SERIALISED(efx); 722 BUG_ON(efx->port_enabled); 723 724 efx_ptp_stop_datapath(efx); 725 726 /* Stop RX refill */ 727 efx_for_each_channel(channel, efx) { 728 efx_for_each_channel_rx_queue(rx_queue, channel) 729 rx_queue->refill_enabled = false; 730 } 731 732 efx_for_each_channel(channel, efx) { 733 /* RX packet processing is pipelined, so wait for the 734 * NAPI handler to complete. At least event queue 0 735 * might be kept active by non-data events, so don't 736 * use napi_synchronize() but actually disable NAPI 737 * temporarily. 738 */ 739 if (efx_channel_has_rx_queue(channel)) { 740 efx_stop_eventq(channel); 741 efx_start_eventq(channel); 742 } 743 } 744 745 rc = efx->type->fini_dmaq(efx); 746 if (rc) { 747 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 748 } else { 749 netif_dbg(efx, drv, efx->net_dev, 750 "successfully flushed all queues\n"); 751 } 752 753 efx_for_each_channel(channel, efx) { 754 efx_for_each_channel_rx_queue(rx_queue, channel) 755 efx_fini_rx_queue(rx_queue); 756 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 757 efx_fini_tx_queue(tx_queue); 758 } 759 } 760 761 static void efx_remove_channel(struct efx_channel *channel) 762 { 763 struct efx_tx_queue *tx_queue; 764 struct efx_rx_queue *rx_queue; 765 766 netif_dbg(channel->efx, drv, channel->efx->net_dev, 767 "destroy chan %d\n", channel->channel); 768 769 efx_for_each_channel_rx_queue(rx_queue, channel) 770 efx_remove_rx_queue(rx_queue); 771 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 772 efx_remove_tx_queue(tx_queue); 773 efx_remove_eventq(channel); 774 channel->type->post_remove(channel); 775 } 776 777 static void efx_remove_channels(struct efx_nic *efx) 778 { 779 struct efx_channel *channel; 780 781 efx_for_each_channel(channel, efx) 782 efx_remove_channel(channel); 783 } 784 785 int 786 efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 787 { 788 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 789 u32 old_rxq_entries, old_txq_entries; 790 unsigned i, next_buffer_table = 0; 791 int rc, rc2; 792 793 rc = efx_check_disabled(efx); 794 if (rc) 795 return rc; 796 797 /* Not all channels should be reallocated. We must avoid 798 * reallocating their buffer table entries. 799 */ 800 efx_for_each_channel(channel, efx) { 801 struct efx_rx_queue *rx_queue; 802 struct efx_tx_queue *tx_queue; 803 804 if (channel->type->copy) 805 continue; 806 next_buffer_table = max(next_buffer_table, 807 channel->eventq.index + 808 channel->eventq.entries); 809 efx_for_each_channel_rx_queue(rx_queue, channel) 810 next_buffer_table = max(next_buffer_table, 811 rx_queue->rxd.index + 812 rx_queue->rxd.entries); 813 efx_for_each_channel_tx_queue(tx_queue, channel) 814 next_buffer_table = max(next_buffer_table, 815 tx_queue->txd.index + 816 tx_queue->txd.entries); 817 } 818 819 efx_device_detach_sync(efx); 820 efx_stop_all(efx); 821 efx_soft_disable_interrupts(efx); 822 823 /* Clone channels (where possible) */ 824 memset(other_channel, 0, sizeof(other_channel)); 825 for (i = 0; i < efx->n_channels; i++) { 826 channel = efx->channel[i]; 827 if (channel->type->copy) 828 channel = channel->type->copy(channel); 829 if (!channel) { 830 rc = -ENOMEM; 831 goto out; 832 } 833 other_channel[i] = channel; 834 } 835 836 /* Swap entry counts and channel pointers */ 837 old_rxq_entries = efx->rxq_entries; 838 old_txq_entries = efx->txq_entries; 839 efx->rxq_entries = rxq_entries; 840 efx->txq_entries = txq_entries; 841 for (i = 0; i < efx->n_channels; i++) { 842 channel = efx->channel[i]; 843 efx->channel[i] = other_channel[i]; 844 other_channel[i] = channel; 845 } 846 847 /* Restart buffer table allocation */ 848 efx->next_buffer_table = next_buffer_table; 849 850 for (i = 0; i < efx->n_channels; i++) { 851 channel = efx->channel[i]; 852 if (!channel->type->copy) 853 continue; 854 rc = efx_probe_channel(channel); 855 if (rc) 856 goto rollback; 857 efx_init_napi_channel(efx->channel[i]); 858 } 859 860 out: 861 /* Destroy unused channel structures */ 862 for (i = 0; i < efx->n_channels; i++) { 863 channel = other_channel[i]; 864 if (channel && channel->type->copy) { 865 efx_fini_napi_channel(channel); 866 efx_remove_channel(channel); 867 kfree(channel); 868 } 869 } 870 871 rc2 = efx_soft_enable_interrupts(efx); 872 if (rc2) { 873 rc = rc ? rc : rc2; 874 netif_err(efx, drv, efx->net_dev, 875 "unable to restart interrupts on channel reallocation\n"); 876 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 877 } else { 878 efx_start_all(efx); 879 efx_device_attach_if_not_resetting(efx); 880 } 881 return rc; 882 883 rollback: 884 /* Swap back */ 885 efx->rxq_entries = old_rxq_entries; 886 efx->txq_entries = old_txq_entries; 887 for (i = 0; i < efx->n_channels; i++) { 888 channel = efx->channel[i]; 889 efx->channel[i] = other_channel[i]; 890 other_channel[i] = channel; 891 } 892 goto out; 893 } 894 895 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) 896 { 897 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); 898 } 899 900 static const struct efx_channel_type efx_default_channel_type = { 901 .pre_probe = efx_channel_dummy_op_int, 902 .post_remove = efx_channel_dummy_op_void, 903 .get_name = efx_get_channel_name, 904 .copy = efx_copy_channel, 905 .keep_eventq = false, 906 }; 907 908 int efx_channel_dummy_op_int(struct efx_channel *channel) 909 { 910 return 0; 911 } 912 913 void efx_channel_dummy_op_void(struct efx_channel *channel) 914 { 915 } 916 917 /************************************************************************** 918 * 919 * Port handling 920 * 921 **************************************************************************/ 922 923 /* This ensures that the kernel is kept informed (via 924 * netif_carrier_on/off) of the link status, and also maintains the 925 * link status's stop on the port's TX queue. 926 */ 927 void efx_link_status_changed(struct efx_nic *efx) 928 { 929 struct efx_link_state *link_state = &efx->link_state; 930 931 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure 932 * that no events are triggered between unregister_netdev() and the 933 * driver unloading. A more general condition is that NETDEV_CHANGE 934 * can only be generated between NETDEV_UP and NETDEV_DOWN */ 935 if (!netif_running(efx->net_dev)) 936 return; 937 938 if (link_state->up != netif_carrier_ok(efx->net_dev)) { 939 efx->n_link_state_changes++; 940 941 if (link_state->up) 942 netif_carrier_on(efx->net_dev); 943 else 944 netif_carrier_off(efx->net_dev); 945 } 946 947 /* Status message for kernel log */ 948 if (link_state->up) 949 netif_info(efx, link, efx->net_dev, 950 "link up at %uMbps %s-duplex (MTU %d)\n", 951 link_state->speed, link_state->fd ? "full" : "half", 952 efx->net_dev->mtu); 953 else 954 netif_info(efx, link, efx->net_dev, "link down\n"); 955 } 956 957 void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) 958 { 959 efx->link_advertising = advertising; 960 if (advertising) { 961 if (advertising & ADVERTISED_Pause) 962 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); 963 else 964 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); 965 if (advertising & ADVERTISED_Asym_Pause) 966 efx->wanted_fc ^= EFX_FC_TX; 967 } 968 } 969 970 void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) 971 { 972 efx->wanted_fc = wanted_fc; 973 if (efx->link_advertising) { 974 if (wanted_fc & EFX_FC_RX) 975 efx->link_advertising |= (ADVERTISED_Pause | 976 ADVERTISED_Asym_Pause); 977 else 978 efx->link_advertising &= ~(ADVERTISED_Pause | 979 ADVERTISED_Asym_Pause); 980 if (wanted_fc & EFX_FC_TX) 981 efx->link_advertising ^= ADVERTISED_Asym_Pause; 982 } 983 } 984 985 static void efx_fini_port(struct efx_nic *efx); 986 987 /* We assume that efx->type->reconfigure_mac will always try to sync RX 988 * filters and therefore needs to read-lock the filter table against freeing 989 */ 990 void efx_mac_reconfigure(struct efx_nic *efx) 991 { 992 down_read(&efx->filter_sem); 993 efx->type->reconfigure_mac(efx); 994 up_read(&efx->filter_sem); 995 } 996 997 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure 998 * the MAC appropriately. All other PHY configuration changes are pushed 999 * through phy_op->set_settings(), and pushed asynchronously to the MAC 1000 * through efx_monitor(). 1001 * 1002 * Callers must hold the mac_lock 1003 */ 1004 int __efx_reconfigure_port(struct efx_nic *efx) 1005 { 1006 enum efx_phy_mode phy_mode; 1007 int rc; 1008 1009 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 1010 1011 /* Disable PHY transmit in mac level loopbacks */ 1012 phy_mode = efx->phy_mode; 1013 if (LOOPBACK_INTERNAL(efx)) 1014 efx->phy_mode |= PHY_MODE_TX_DISABLED; 1015 else 1016 efx->phy_mode &= ~PHY_MODE_TX_DISABLED; 1017 1018 rc = efx->type->reconfigure_port(efx); 1019 1020 if (rc) 1021 efx->phy_mode = phy_mode; 1022 1023 return rc; 1024 } 1025 1026 /* Reinitialise the MAC to pick up new PHY settings, even if the port is 1027 * disabled. */ 1028 int efx_reconfigure_port(struct efx_nic *efx) 1029 { 1030 int rc; 1031 1032 EFX_ASSERT_RESET_SERIALISED(efx); 1033 1034 mutex_lock(&efx->mac_lock); 1035 rc = __efx_reconfigure_port(efx); 1036 mutex_unlock(&efx->mac_lock); 1037 1038 return rc; 1039 } 1040 1041 /* Asynchronous work item for changing MAC promiscuity and multicast 1042 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current 1043 * MAC directly. */ 1044 static void efx_mac_work(struct work_struct *data) 1045 { 1046 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); 1047 1048 mutex_lock(&efx->mac_lock); 1049 if (efx->port_enabled) 1050 efx_mac_reconfigure(efx); 1051 mutex_unlock(&efx->mac_lock); 1052 } 1053 1054 static int efx_probe_port(struct efx_nic *efx) 1055 { 1056 int rc; 1057 1058 netif_dbg(efx, probe, efx->net_dev, "create port\n"); 1059 1060 if (phy_flash_cfg) 1061 efx->phy_mode = PHY_MODE_SPECIAL; 1062 1063 /* Connect up MAC/PHY operations table */ 1064 rc = efx->type->probe_port(efx); 1065 if (rc) 1066 return rc; 1067 1068 /* Initialise MAC address to permanent address */ 1069 ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr); 1070 1071 return 0; 1072 } 1073 1074 static int efx_init_port(struct efx_nic *efx) 1075 { 1076 int rc; 1077 1078 netif_dbg(efx, drv, efx->net_dev, "init port\n"); 1079 1080 mutex_lock(&efx->mac_lock); 1081 1082 rc = efx->phy_op->init(efx); 1083 if (rc) 1084 goto fail1; 1085 1086 efx->port_initialized = true; 1087 1088 /* Reconfigure the MAC before creating dma queues (required for 1089 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ 1090 efx_mac_reconfigure(efx); 1091 1092 /* Ensure the PHY advertises the correct flow control settings */ 1093 rc = efx->phy_op->reconfigure(efx); 1094 if (rc && rc != -EPERM) 1095 goto fail2; 1096 1097 mutex_unlock(&efx->mac_lock); 1098 return 0; 1099 1100 fail2: 1101 efx->phy_op->fini(efx); 1102 fail1: 1103 mutex_unlock(&efx->mac_lock); 1104 return rc; 1105 } 1106 1107 static void efx_start_port(struct efx_nic *efx) 1108 { 1109 netif_dbg(efx, ifup, efx->net_dev, "start port\n"); 1110 BUG_ON(efx->port_enabled); 1111 1112 mutex_lock(&efx->mac_lock); 1113 efx->port_enabled = true; 1114 1115 /* Ensure MAC ingress/egress is enabled */ 1116 efx_mac_reconfigure(efx); 1117 1118 mutex_unlock(&efx->mac_lock); 1119 } 1120 1121 /* Cancel work for MAC reconfiguration, periodic hardware monitoring 1122 * and the async self-test, wait for them to finish and prevent them 1123 * being scheduled again. This doesn't cover online resets, which 1124 * should only be cancelled when removing the device. 1125 */ 1126 static void efx_stop_port(struct efx_nic *efx) 1127 { 1128 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); 1129 1130 EFX_ASSERT_RESET_SERIALISED(efx); 1131 1132 mutex_lock(&efx->mac_lock); 1133 efx->port_enabled = false; 1134 mutex_unlock(&efx->mac_lock); 1135 1136 /* Serialise against efx_set_multicast_list() */ 1137 netif_addr_lock_bh(efx->net_dev); 1138 netif_addr_unlock_bh(efx->net_dev); 1139 1140 cancel_delayed_work_sync(&efx->monitor_work); 1141 efx_selftest_async_cancel(efx); 1142 cancel_work_sync(&efx->mac_work); 1143 } 1144 1145 static void efx_fini_port(struct efx_nic *efx) 1146 { 1147 netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); 1148 1149 if (!efx->port_initialized) 1150 return; 1151 1152 efx->phy_op->fini(efx); 1153 efx->port_initialized = false; 1154 1155 efx->link_state.up = false; 1156 efx_link_status_changed(efx); 1157 } 1158 1159 static void efx_remove_port(struct efx_nic *efx) 1160 { 1161 netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); 1162 1163 efx->type->remove_port(efx); 1164 } 1165 1166 /************************************************************************** 1167 * 1168 * NIC handling 1169 * 1170 **************************************************************************/ 1171 1172 static LIST_HEAD(efx_primary_list); 1173 static LIST_HEAD(efx_unassociated_list); 1174 1175 static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right) 1176 { 1177 return left->type == right->type && 1178 left->vpd_sn && right->vpd_sn && 1179 !strcmp(left->vpd_sn, right->vpd_sn); 1180 } 1181 1182 static void efx_associate(struct efx_nic *efx) 1183 { 1184 struct efx_nic *other, *next; 1185 1186 if (efx->primary == efx) { 1187 /* Adding primary function; look for secondaries */ 1188 1189 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); 1190 list_add_tail(&efx->node, &efx_primary_list); 1191 1192 list_for_each_entry_safe(other, next, &efx_unassociated_list, 1193 node) { 1194 if (efx_same_controller(efx, other)) { 1195 list_del(&other->node); 1196 netif_dbg(other, probe, other->net_dev, 1197 "moving to secondary list of %s %s\n", 1198 pci_name(efx->pci_dev), 1199 efx->net_dev->name); 1200 list_add_tail(&other->node, 1201 &efx->secondary_list); 1202 other->primary = efx; 1203 } 1204 } 1205 } else { 1206 /* Adding secondary function; look for primary */ 1207 1208 list_for_each_entry(other, &efx_primary_list, node) { 1209 if (efx_same_controller(efx, other)) { 1210 netif_dbg(efx, probe, efx->net_dev, 1211 "adding to secondary list of %s %s\n", 1212 pci_name(other->pci_dev), 1213 other->net_dev->name); 1214 list_add_tail(&efx->node, 1215 &other->secondary_list); 1216 efx->primary = other; 1217 return; 1218 } 1219 } 1220 1221 netif_dbg(efx, probe, efx->net_dev, 1222 "adding to unassociated list\n"); 1223 list_add_tail(&efx->node, &efx_unassociated_list); 1224 } 1225 } 1226 1227 static void efx_dissociate(struct efx_nic *efx) 1228 { 1229 struct efx_nic *other, *next; 1230 1231 list_del(&efx->node); 1232 efx->primary = NULL; 1233 1234 list_for_each_entry_safe(other, next, &efx->secondary_list, node) { 1235 list_del(&other->node); 1236 netif_dbg(other, probe, other->net_dev, 1237 "moving to unassociated list\n"); 1238 list_add_tail(&other->node, &efx_unassociated_list); 1239 other->primary = NULL; 1240 } 1241 } 1242 1243 /* This configures the PCI device to enable I/O and DMA. */ 1244 static int efx_init_io(struct efx_nic *efx) 1245 { 1246 struct pci_dev *pci_dev = efx->pci_dev; 1247 dma_addr_t dma_mask = efx->type->max_dma_mask; 1248 unsigned int mem_map_size = efx->type->mem_map_size(efx); 1249 int rc, bar; 1250 1251 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); 1252 1253 bar = efx->type->mem_bar; 1254 1255 rc = pci_enable_device(pci_dev); 1256 if (rc) { 1257 netif_err(efx, probe, efx->net_dev, 1258 "failed to enable PCI device\n"); 1259 goto fail1; 1260 } 1261 1262 pci_set_master(pci_dev); 1263 1264 /* Set the PCI DMA mask. Try all possibilities from our 1265 * genuine mask down to 32 bits, because some architectures 1266 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit 1267 * masks event though they reject 46 bit masks. 1268 */ 1269 while (dma_mask > 0x7fffffffUL) { 1270 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); 1271 if (rc == 0) 1272 break; 1273 dma_mask >>= 1; 1274 } 1275 if (rc) { 1276 netif_err(efx, probe, efx->net_dev, 1277 "could not find a suitable DMA mask\n"); 1278 goto fail2; 1279 } 1280 netif_dbg(efx, probe, efx->net_dev, 1281 "using DMA mask %llx\n", (unsigned long long) dma_mask); 1282 1283 efx->membase_phys = pci_resource_start(efx->pci_dev, bar); 1284 rc = pci_request_region(pci_dev, bar, "sfc"); 1285 if (rc) { 1286 netif_err(efx, probe, efx->net_dev, 1287 "request for memory BAR failed\n"); 1288 rc = -EIO; 1289 goto fail3; 1290 } 1291 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); 1292 if (!efx->membase) { 1293 netif_err(efx, probe, efx->net_dev, 1294 "could not map memory BAR at %llx+%x\n", 1295 (unsigned long long)efx->membase_phys, mem_map_size); 1296 rc = -ENOMEM; 1297 goto fail4; 1298 } 1299 netif_dbg(efx, probe, efx->net_dev, 1300 "memory BAR at %llx+%x (virtual %p)\n", 1301 (unsigned long long)efx->membase_phys, mem_map_size, 1302 efx->membase); 1303 1304 return 0; 1305 1306 fail4: 1307 pci_release_region(efx->pci_dev, bar); 1308 fail3: 1309 efx->membase_phys = 0; 1310 fail2: 1311 pci_disable_device(efx->pci_dev); 1312 fail1: 1313 return rc; 1314 } 1315 1316 static void efx_fini_io(struct efx_nic *efx) 1317 { 1318 int bar; 1319 1320 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); 1321 1322 if (efx->membase) { 1323 iounmap(efx->membase); 1324 efx->membase = NULL; 1325 } 1326 1327 if (efx->membase_phys) { 1328 bar = efx->type->mem_bar; 1329 pci_release_region(efx->pci_dev, bar); 1330 efx->membase_phys = 0; 1331 } 1332 1333 /* Don't disable bus-mastering if VFs are assigned */ 1334 if (!pci_vfs_assigned(efx->pci_dev)) 1335 pci_disable_device(efx->pci_dev); 1336 } 1337 1338 void efx_set_default_rx_indir_table(struct efx_nic *efx) 1339 { 1340 size_t i; 1341 1342 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) 1343 efx->rx_indir_table[i] = 1344 ethtool_rxfh_indir_default(i, efx->rss_spread); 1345 } 1346 1347 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 1348 { 1349 cpumask_var_t thread_mask; 1350 unsigned int count; 1351 int cpu; 1352 1353 if (rss_cpus) { 1354 count = rss_cpus; 1355 } else { 1356 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 1357 netif_warn(efx, probe, efx->net_dev, 1358 "RSS disabled due to allocation failure\n"); 1359 return 1; 1360 } 1361 1362 count = 0; 1363 for_each_online_cpu(cpu) { 1364 if (!cpumask_test_cpu(cpu, thread_mask)) { 1365 ++count; 1366 cpumask_or(thread_mask, thread_mask, 1367 topology_sibling_cpumask(cpu)); 1368 } 1369 } 1370 1371 free_cpumask_var(thread_mask); 1372 } 1373 1374 /* If RSS is requested for the PF *and* VFs then we can't write RSS 1375 * table entries that are inaccessible to VFs 1376 */ 1377 #ifdef CONFIG_SFC_SRIOV 1378 if (efx->type->sriov_wanted) { 1379 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && 1380 count > efx_vf_size(efx)) { 1381 netif_warn(efx, probe, efx->net_dev, 1382 "Reducing number of RSS channels from %u to %u for " 1383 "VF support. Increase vf-msix-limit to use more " 1384 "channels on the PF.\n", 1385 count, efx_vf_size(efx)); 1386 count = efx_vf_size(efx); 1387 } 1388 } 1389 #endif 1390 1391 return count; 1392 } 1393 1394 /* Probe the number and type of interrupts we are able to obtain, and 1395 * the resulting numbers of channels and RX queues. 1396 */ 1397 static int efx_probe_interrupts(struct efx_nic *efx) 1398 { 1399 unsigned int extra_channels = 0; 1400 unsigned int i, j; 1401 int rc; 1402 1403 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 1404 if (efx->extra_channel_type[i]) 1405 ++extra_channels; 1406 1407 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 1408 struct msix_entry xentries[EFX_MAX_CHANNELS]; 1409 unsigned int n_channels; 1410 1411 n_channels = efx_wanted_parallelism(efx); 1412 if (efx_separate_tx_channels) 1413 n_channels *= 2; 1414 n_channels += extra_channels; 1415 n_channels = min(n_channels, efx->max_channels); 1416 1417 for (i = 0; i < n_channels; i++) 1418 xentries[i].entry = i; 1419 rc = pci_enable_msix_range(efx->pci_dev, 1420 xentries, 1, n_channels); 1421 if (rc < 0) { 1422 /* Fall back to single channel MSI */ 1423 netif_err(efx, drv, efx->net_dev, 1424 "could not enable MSI-X\n"); 1425 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) 1426 efx->interrupt_mode = EFX_INT_MODE_MSI; 1427 else 1428 return rc; 1429 } else if (rc < n_channels) { 1430 netif_err(efx, drv, efx->net_dev, 1431 "WARNING: Insufficient MSI-X vectors" 1432 " available (%d < %u).\n", rc, n_channels); 1433 netif_err(efx, drv, efx->net_dev, 1434 "WARNING: Performance may be reduced.\n"); 1435 n_channels = rc; 1436 } 1437 1438 if (rc > 0) { 1439 efx->n_channels = n_channels; 1440 if (n_channels > extra_channels) 1441 n_channels -= extra_channels; 1442 if (efx_separate_tx_channels) { 1443 efx->n_tx_channels = min(max(n_channels / 2, 1444 1U), 1445 efx->max_tx_channels); 1446 efx->n_rx_channels = max(n_channels - 1447 efx->n_tx_channels, 1448 1U); 1449 } else { 1450 efx->n_tx_channels = min(n_channels, 1451 efx->max_tx_channels); 1452 efx->n_rx_channels = n_channels; 1453 } 1454 for (i = 0; i < efx->n_channels; i++) 1455 efx_get_channel(efx, i)->irq = 1456 xentries[i].vector; 1457 } 1458 } 1459 1460 /* Try single interrupt MSI */ 1461 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 1462 efx->n_channels = 1; 1463 efx->n_rx_channels = 1; 1464 efx->n_tx_channels = 1; 1465 rc = pci_enable_msi(efx->pci_dev); 1466 if (rc == 0) { 1467 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 1468 } else { 1469 netif_err(efx, drv, efx->net_dev, 1470 "could not enable MSI\n"); 1471 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) 1472 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 1473 else 1474 return rc; 1475 } 1476 } 1477 1478 /* Assume legacy interrupts */ 1479 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 1480 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); 1481 efx->n_rx_channels = 1; 1482 efx->n_tx_channels = 1; 1483 efx->legacy_irq = efx->pci_dev->irq; 1484 } 1485 1486 /* Assign extra channels if possible */ 1487 j = efx->n_channels; 1488 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 1489 if (!efx->extra_channel_type[i]) 1490 continue; 1491 if (efx->interrupt_mode != EFX_INT_MODE_MSIX || 1492 efx->n_channels <= extra_channels) { 1493 efx->extra_channel_type[i]->handle_no_channel(efx); 1494 } else { 1495 --j; 1496 efx_get_channel(efx, j)->type = 1497 efx->extra_channel_type[i]; 1498 } 1499 } 1500 1501 /* RSS might be usable on VFs even if it is disabled on the PF */ 1502 #ifdef CONFIG_SFC_SRIOV 1503 if (efx->type->sriov_wanted) { 1504 efx->rss_spread = ((efx->n_rx_channels > 1 || 1505 !efx->type->sriov_wanted(efx)) ? 1506 efx->n_rx_channels : efx_vf_size(efx)); 1507 return 0; 1508 } 1509 #endif 1510 efx->rss_spread = efx->n_rx_channels; 1511 1512 return 0; 1513 } 1514 1515 static int efx_soft_enable_interrupts(struct efx_nic *efx) 1516 { 1517 struct efx_channel *channel, *end_channel; 1518 int rc; 1519 1520 BUG_ON(efx->state == STATE_DISABLED); 1521 1522 efx->irq_soft_enabled = true; 1523 smp_wmb(); 1524 1525 efx_for_each_channel(channel, efx) { 1526 if (!channel->type->keep_eventq) { 1527 rc = efx_init_eventq(channel); 1528 if (rc) 1529 goto fail; 1530 } 1531 efx_start_eventq(channel); 1532 } 1533 1534 efx_mcdi_mode_event(efx); 1535 1536 return 0; 1537 fail: 1538 end_channel = channel; 1539 efx_for_each_channel(channel, efx) { 1540 if (channel == end_channel) 1541 break; 1542 efx_stop_eventq(channel); 1543 if (!channel->type->keep_eventq) 1544 efx_fini_eventq(channel); 1545 } 1546 1547 return rc; 1548 } 1549 1550 static void efx_soft_disable_interrupts(struct efx_nic *efx) 1551 { 1552 struct efx_channel *channel; 1553 1554 if (efx->state == STATE_DISABLED) 1555 return; 1556 1557 efx_mcdi_mode_poll(efx); 1558 1559 efx->irq_soft_enabled = false; 1560 smp_wmb(); 1561 1562 if (efx->legacy_irq) 1563 synchronize_irq(efx->legacy_irq); 1564 1565 efx_for_each_channel(channel, efx) { 1566 if (channel->irq) 1567 synchronize_irq(channel->irq); 1568 1569 efx_stop_eventq(channel); 1570 if (!channel->type->keep_eventq) 1571 efx_fini_eventq(channel); 1572 } 1573 1574 /* Flush the asynchronous MCDI request queue */ 1575 efx_mcdi_flush_async(efx); 1576 } 1577 1578 static int efx_enable_interrupts(struct efx_nic *efx) 1579 { 1580 struct efx_channel *channel, *end_channel; 1581 int rc; 1582 1583 BUG_ON(efx->state == STATE_DISABLED); 1584 1585 if (efx->eeh_disabled_legacy_irq) { 1586 enable_irq(efx->legacy_irq); 1587 efx->eeh_disabled_legacy_irq = false; 1588 } 1589 1590 efx->type->irq_enable_master(efx); 1591 1592 efx_for_each_channel(channel, efx) { 1593 if (channel->type->keep_eventq) { 1594 rc = efx_init_eventq(channel); 1595 if (rc) 1596 goto fail; 1597 } 1598 } 1599 1600 rc = efx_soft_enable_interrupts(efx); 1601 if (rc) 1602 goto fail; 1603 1604 return 0; 1605 1606 fail: 1607 end_channel = channel; 1608 efx_for_each_channel(channel, efx) { 1609 if (channel == end_channel) 1610 break; 1611 if (channel->type->keep_eventq) 1612 efx_fini_eventq(channel); 1613 } 1614 1615 efx->type->irq_disable_non_ev(efx); 1616 1617 return rc; 1618 } 1619 1620 static void efx_disable_interrupts(struct efx_nic *efx) 1621 { 1622 struct efx_channel *channel; 1623 1624 efx_soft_disable_interrupts(efx); 1625 1626 efx_for_each_channel(channel, efx) { 1627 if (channel->type->keep_eventq) 1628 efx_fini_eventq(channel); 1629 } 1630 1631 efx->type->irq_disable_non_ev(efx); 1632 } 1633 1634 static void efx_remove_interrupts(struct efx_nic *efx) 1635 { 1636 struct efx_channel *channel; 1637 1638 /* Remove MSI/MSI-X interrupts */ 1639 efx_for_each_channel(channel, efx) 1640 channel->irq = 0; 1641 pci_disable_msi(efx->pci_dev); 1642 pci_disable_msix(efx->pci_dev); 1643 1644 /* Remove legacy interrupt */ 1645 efx->legacy_irq = 0; 1646 } 1647 1648 static void efx_set_channels(struct efx_nic *efx) 1649 { 1650 struct efx_channel *channel; 1651 struct efx_tx_queue *tx_queue; 1652 1653 efx->tx_channel_offset = 1654 efx_separate_tx_channels ? 1655 efx->n_channels - efx->n_tx_channels : 0; 1656 1657 /* We need to mark which channels really have RX and TX 1658 * queues, and adjust the TX queue numbers if we have separate 1659 * RX-only and TX-only channels. 1660 */ 1661 efx_for_each_channel(channel, efx) { 1662 if (channel->channel < efx->n_rx_channels) 1663 channel->rx_queue.core_index = channel->channel; 1664 else 1665 channel->rx_queue.core_index = -1; 1666 1667 efx_for_each_channel_tx_queue(tx_queue, channel) 1668 tx_queue->queue -= (efx->tx_channel_offset * 1669 EFX_TXQ_TYPES); 1670 } 1671 } 1672 1673 static int efx_probe_nic(struct efx_nic *efx) 1674 { 1675 int rc; 1676 1677 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); 1678 1679 /* Carry out hardware-type specific initialisation */ 1680 rc = efx->type->probe(efx); 1681 if (rc) 1682 return rc; 1683 1684 do { 1685 if (!efx->max_channels || !efx->max_tx_channels) { 1686 netif_err(efx, drv, efx->net_dev, 1687 "Insufficient resources to allocate" 1688 " any channels\n"); 1689 rc = -ENOSPC; 1690 goto fail1; 1691 } 1692 1693 /* Determine the number of channels and queues by trying 1694 * to hook in MSI-X interrupts. 1695 */ 1696 rc = efx_probe_interrupts(efx); 1697 if (rc) 1698 goto fail1; 1699 1700 efx_set_channels(efx); 1701 1702 /* dimension_resources can fail with EAGAIN */ 1703 rc = efx->type->dimension_resources(efx); 1704 if (rc != 0 && rc != -EAGAIN) 1705 goto fail2; 1706 1707 if (rc == -EAGAIN) 1708 /* try again with new max_channels */ 1709 efx_remove_interrupts(efx); 1710 1711 } while (rc == -EAGAIN); 1712 1713 if (efx->n_channels > 1) 1714 netdev_rss_key_fill(&efx->rx_hash_key, 1715 sizeof(efx->rx_hash_key)); 1716 efx_set_default_rx_indir_table(efx); 1717 1718 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 1719 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 1720 1721 /* Initialise the interrupt moderation settings */ 1722 efx->irq_mod_step_us = DIV_ROUND_UP(efx->timer_quantum_ns, 1000); 1723 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, 1724 true); 1725 1726 return 0; 1727 1728 fail2: 1729 efx_remove_interrupts(efx); 1730 fail1: 1731 efx->type->remove(efx); 1732 return rc; 1733 } 1734 1735 static void efx_remove_nic(struct efx_nic *efx) 1736 { 1737 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); 1738 1739 efx_remove_interrupts(efx); 1740 efx->type->remove(efx); 1741 } 1742 1743 static int efx_probe_filters(struct efx_nic *efx) 1744 { 1745 int rc; 1746 1747 spin_lock_init(&efx->filter_lock); 1748 init_rwsem(&efx->filter_sem); 1749 mutex_lock(&efx->mac_lock); 1750 down_write(&efx->filter_sem); 1751 rc = efx->type->filter_table_probe(efx); 1752 if (rc) 1753 goto out_unlock; 1754 1755 #ifdef CONFIG_RFS_ACCEL 1756 if (efx->type->offload_features & NETIF_F_NTUPLE) { 1757 struct efx_channel *channel; 1758 int i, success = 1; 1759 1760 efx_for_each_channel(channel, efx) { 1761 channel->rps_flow_id = 1762 kcalloc(efx->type->max_rx_ip_filters, 1763 sizeof(*channel->rps_flow_id), 1764 GFP_KERNEL); 1765 if (!channel->rps_flow_id) 1766 success = 0; 1767 else 1768 for (i = 0; 1769 i < efx->type->max_rx_ip_filters; 1770 ++i) 1771 channel->rps_flow_id[i] = 1772 RPS_FLOW_ID_INVALID; 1773 } 1774 1775 if (!success) { 1776 efx_for_each_channel(channel, efx) 1777 kfree(channel->rps_flow_id); 1778 efx->type->filter_table_remove(efx); 1779 rc = -ENOMEM; 1780 goto out_unlock; 1781 } 1782 1783 efx->rps_expire_index = efx->rps_expire_channel = 0; 1784 } 1785 #endif 1786 out_unlock: 1787 up_write(&efx->filter_sem); 1788 mutex_unlock(&efx->mac_lock); 1789 return rc; 1790 } 1791 1792 static void efx_remove_filters(struct efx_nic *efx) 1793 { 1794 #ifdef CONFIG_RFS_ACCEL 1795 struct efx_channel *channel; 1796 1797 efx_for_each_channel(channel, efx) 1798 kfree(channel->rps_flow_id); 1799 #endif 1800 down_write(&efx->filter_sem); 1801 efx->type->filter_table_remove(efx); 1802 up_write(&efx->filter_sem); 1803 } 1804 1805 static void efx_restore_filters(struct efx_nic *efx) 1806 { 1807 down_read(&efx->filter_sem); 1808 efx->type->filter_table_restore(efx); 1809 up_read(&efx->filter_sem); 1810 } 1811 1812 /************************************************************************** 1813 * 1814 * NIC startup/shutdown 1815 * 1816 *************************************************************************/ 1817 1818 static int efx_probe_all(struct efx_nic *efx) 1819 { 1820 int rc; 1821 1822 rc = efx_probe_nic(efx); 1823 if (rc) { 1824 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); 1825 goto fail1; 1826 } 1827 1828 rc = efx_probe_port(efx); 1829 if (rc) { 1830 netif_err(efx, probe, efx->net_dev, "failed to create port\n"); 1831 goto fail2; 1832 } 1833 1834 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); 1835 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { 1836 rc = -EINVAL; 1837 goto fail3; 1838 } 1839 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; 1840 1841 #ifdef CONFIG_SFC_SRIOV 1842 rc = efx->type->vswitching_probe(efx); 1843 if (rc) /* not fatal; the PF will still work fine */ 1844 netif_warn(efx, probe, efx->net_dev, 1845 "failed to setup vswitching rc=%d;" 1846 " VFs may not function\n", rc); 1847 #endif 1848 1849 rc = efx_probe_filters(efx); 1850 if (rc) { 1851 netif_err(efx, probe, efx->net_dev, 1852 "failed to create filter tables\n"); 1853 goto fail4; 1854 } 1855 1856 rc = efx_probe_channels(efx); 1857 if (rc) 1858 goto fail5; 1859 1860 return 0; 1861 1862 fail5: 1863 efx_remove_filters(efx); 1864 fail4: 1865 #ifdef CONFIG_SFC_SRIOV 1866 efx->type->vswitching_remove(efx); 1867 #endif 1868 fail3: 1869 efx_remove_port(efx); 1870 fail2: 1871 efx_remove_nic(efx); 1872 fail1: 1873 return rc; 1874 } 1875 1876 /* If the interface is supposed to be running but is not, start 1877 * the hardware and software data path, regular activity for the port 1878 * (MAC statistics, link polling, etc.) and schedule the port to be 1879 * reconfigured. Interrupts must already be enabled. This function 1880 * is safe to call multiple times, so long as the NIC is not disabled. 1881 * Requires the RTNL lock. 1882 */ 1883 static void efx_start_all(struct efx_nic *efx) 1884 { 1885 EFX_ASSERT_RESET_SERIALISED(efx); 1886 BUG_ON(efx->state == STATE_DISABLED); 1887 1888 /* Check that it is appropriate to restart the interface. All 1889 * of these flags are safe to read under just the rtnl lock */ 1890 if (efx->port_enabled || !netif_running(efx->net_dev) || 1891 efx->reset_pending) 1892 return; 1893 1894 efx_start_port(efx); 1895 efx_start_datapath(efx); 1896 1897 /* Start the hardware monitor if there is one */ 1898 if (efx->type->monitor != NULL) 1899 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1900 efx_monitor_interval); 1901 1902 /* Link state detection is normally event-driven; we have 1903 * to poll now because we could have missed a change 1904 */ 1905 mutex_lock(&efx->mac_lock); 1906 if (efx->phy_op->poll(efx)) 1907 efx_link_status_changed(efx); 1908 mutex_unlock(&efx->mac_lock); 1909 1910 efx->type->start_stats(efx); 1911 efx->type->pull_stats(efx); 1912 spin_lock_bh(&efx->stats_lock); 1913 efx->type->update_stats(efx, NULL, NULL); 1914 spin_unlock_bh(&efx->stats_lock); 1915 } 1916 1917 /* Quiesce the hardware and software data path, and regular activity 1918 * for the port without bringing the link down. Safe to call multiple 1919 * times with the NIC in almost any state, but interrupts should be 1920 * enabled. Requires the RTNL lock. 1921 */ 1922 static void efx_stop_all(struct efx_nic *efx) 1923 { 1924 EFX_ASSERT_RESET_SERIALISED(efx); 1925 1926 /* port_enabled can be read safely under the rtnl lock */ 1927 if (!efx->port_enabled) 1928 return; 1929 1930 /* update stats before we go down so we can accurately count 1931 * rx_nodesc_drops 1932 */ 1933 efx->type->pull_stats(efx); 1934 spin_lock_bh(&efx->stats_lock); 1935 efx->type->update_stats(efx, NULL, NULL); 1936 spin_unlock_bh(&efx->stats_lock); 1937 efx->type->stop_stats(efx); 1938 efx_stop_port(efx); 1939 1940 /* Stop the kernel transmit interface. This is only valid if 1941 * the device is stopped or detached; otherwise the watchdog 1942 * may fire immediately. 1943 */ 1944 WARN_ON(netif_running(efx->net_dev) && 1945 netif_device_present(efx->net_dev)); 1946 netif_tx_disable(efx->net_dev); 1947 1948 efx_stop_datapath(efx); 1949 } 1950 1951 static void efx_remove_all(struct efx_nic *efx) 1952 { 1953 efx_remove_channels(efx); 1954 efx_remove_filters(efx); 1955 #ifdef CONFIG_SFC_SRIOV 1956 efx->type->vswitching_remove(efx); 1957 #endif 1958 efx_remove_port(efx); 1959 efx_remove_nic(efx); 1960 } 1961 1962 /************************************************************************** 1963 * 1964 * Interrupt moderation 1965 * 1966 **************************************************************************/ 1967 unsigned int efx_usecs_to_ticks(struct efx_nic *efx, unsigned int usecs) 1968 { 1969 if (usecs == 0) 1970 return 0; 1971 if (usecs * 1000 < efx->timer_quantum_ns) 1972 return 1; /* never round down to 0 */ 1973 return usecs * 1000 / efx->timer_quantum_ns; 1974 } 1975 1976 unsigned int efx_ticks_to_usecs(struct efx_nic *efx, unsigned int ticks) 1977 { 1978 /* We must round up when converting ticks to microseconds 1979 * because we round down when converting the other way. 1980 */ 1981 return DIV_ROUND_UP(ticks * efx->timer_quantum_ns, 1000); 1982 } 1983 1984 /* Set interrupt moderation parameters */ 1985 int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, 1986 unsigned int rx_usecs, bool rx_adaptive, 1987 bool rx_may_override_tx) 1988 { 1989 struct efx_channel *channel; 1990 unsigned int timer_max_us; 1991 1992 EFX_ASSERT_RESET_SERIALISED(efx); 1993 1994 timer_max_us = efx->timer_max_ns / 1000; 1995 1996 if (tx_usecs > timer_max_us || rx_usecs > timer_max_us) 1997 return -EINVAL; 1998 1999 if (tx_usecs != rx_usecs && efx->tx_channel_offset == 0 && 2000 !rx_may_override_tx) { 2001 netif_err(efx, drv, efx->net_dev, "Channels are shared. " 2002 "RX and TX IRQ moderation must be equal\n"); 2003 return -EINVAL; 2004 } 2005 2006 efx->irq_rx_adaptive = rx_adaptive; 2007 efx->irq_rx_moderation_us = rx_usecs; 2008 efx_for_each_channel(channel, efx) { 2009 if (efx_channel_has_rx_queue(channel)) 2010 channel->irq_moderation_us = rx_usecs; 2011 else if (efx_channel_has_tx_queues(channel)) 2012 channel->irq_moderation_us = tx_usecs; 2013 } 2014 2015 return 0; 2016 } 2017 2018 void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, 2019 unsigned int *rx_usecs, bool *rx_adaptive) 2020 { 2021 *rx_adaptive = efx->irq_rx_adaptive; 2022 *rx_usecs = efx->irq_rx_moderation_us; 2023 2024 /* If channels are shared between RX and TX, so is IRQ 2025 * moderation. Otherwise, IRQ moderation is the same for all 2026 * TX channels and is not adaptive. 2027 */ 2028 if (efx->tx_channel_offset == 0) { 2029 *tx_usecs = *rx_usecs; 2030 } else { 2031 struct efx_channel *tx_channel; 2032 2033 tx_channel = efx->channel[efx->tx_channel_offset]; 2034 *tx_usecs = tx_channel->irq_moderation_us; 2035 } 2036 } 2037 2038 /************************************************************************** 2039 * 2040 * Hardware monitor 2041 * 2042 **************************************************************************/ 2043 2044 /* Run periodically off the general workqueue */ 2045 static void efx_monitor(struct work_struct *data) 2046 { 2047 struct efx_nic *efx = container_of(data, struct efx_nic, 2048 monitor_work.work); 2049 2050 netif_vdbg(efx, timer, efx->net_dev, 2051 "hardware monitor executing on CPU %d\n", 2052 raw_smp_processor_id()); 2053 BUG_ON(efx->type->monitor == NULL); 2054 2055 /* If the mac_lock is already held then it is likely a port 2056 * reconfiguration is already in place, which will likely do 2057 * most of the work of monitor() anyway. */ 2058 if (mutex_trylock(&efx->mac_lock)) { 2059 if (efx->port_enabled) 2060 efx->type->monitor(efx); 2061 mutex_unlock(&efx->mac_lock); 2062 } 2063 2064 queue_delayed_work(efx->workqueue, &efx->monitor_work, 2065 efx_monitor_interval); 2066 } 2067 2068 /************************************************************************** 2069 * 2070 * ioctls 2071 * 2072 *************************************************************************/ 2073 2074 /* Net device ioctl 2075 * Context: process, rtnl_lock() held. 2076 */ 2077 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 2078 { 2079 struct efx_nic *efx = netdev_priv(net_dev); 2080 struct mii_ioctl_data *data = if_mii(ifr); 2081 2082 if (cmd == SIOCSHWTSTAMP) 2083 return efx_ptp_set_ts_config(efx, ifr); 2084 if (cmd == SIOCGHWTSTAMP) 2085 return efx_ptp_get_ts_config(efx, ifr); 2086 2087 /* Convert phy_id from older PRTAD/DEVAD format */ 2088 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && 2089 (data->phy_id & 0xfc00) == 0x0400) 2090 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; 2091 2092 return mdio_mii_ioctl(&efx->mdio, data, cmd); 2093 } 2094 2095 /************************************************************************** 2096 * 2097 * NAPI interface 2098 * 2099 **************************************************************************/ 2100 2101 static void efx_init_napi_channel(struct efx_channel *channel) 2102 { 2103 struct efx_nic *efx = channel->efx; 2104 2105 channel->napi_dev = efx->net_dev; 2106 netif_napi_add(channel->napi_dev, &channel->napi_str, 2107 efx_poll, napi_weight); 2108 } 2109 2110 static void efx_init_napi(struct efx_nic *efx) 2111 { 2112 struct efx_channel *channel; 2113 2114 efx_for_each_channel(channel, efx) 2115 efx_init_napi_channel(channel); 2116 } 2117 2118 static void efx_fini_napi_channel(struct efx_channel *channel) 2119 { 2120 if (channel->napi_dev) 2121 netif_napi_del(&channel->napi_str); 2122 2123 channel->napi_dev = NULL; 2124 } 2125 2126 static void efx_fini_napi(struct efx_nic *efx) 2127 { 2128 struct efx_channel *channel; 2129 2130 efx_for_each_channel(channel, efx) 2131 efx_fini_napi_channel(channel); 2132 } 2133 2134 /************************************************************************** 2135 * 2136 * Kernel netpoll interface 2137 * 2138 *************************************************************************/ 2139 2140 #ifdef CONFIG_NET_POLL_CONTROLLER 2141 2142 /* Although in the common case interrupts will be disabled, this is not 2143 * guaranteed. However, all our work happens inside the NAPI callback, 2144 * so no locking is required. 2145 */ 2146 static void efx_netpoll(struct net_device *net_dev) 2147 { 2148 struct efx_nic *efx = netdev_priv(net_dev); 2149 struct efx_channel *channel; 2150 2151 efx_for_each_channel(channel, efx) 2152 efx_schedule_channel(channel); 2153 } 2154 2155 #endif 2156 2157 /************************************************************************** 2158 * 2159 * Kernel net device interface 2160 * 2161 *************************************************************************/ 2162 2163 /* Context: process, rtnl_lock() held. */ 2164 int efx_net_open(struct net_device *net_dev) 2165 { 2166 struct efx_nic *efx = netdev_priv(net_dev); 2167 int rc; 2168 2169 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", 2170 raw_smp_processor_id()); 2171 2172 rc = efx_check_disabled(efx); 2173 if (rc) 2174 return rc; 2175 if (efx->phy_mode & PHY_MODE_SPECIAL) 2176 return -EBUSY; 2177 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) 2178 return -EIO; 2179 2180 /* Notify the kernel of the link state polled during driver load, 2181 * before the monitor starts running */ 2182 efx_link_status_changed(efx); 2183 2184 efx_start_all(efx); 2185 if (efx->state == STATE_DISABLED || efx->reset_pending) 2186 netif_device_detach(efx->net_dev); 2187 efx_selftest_async_start(efx); 2188 return 0; 2189 } 2190 2191 /* Context: process, rtnl_lock() held. 2192 * Note that the kernel will ignore our return code; this method 2193 * should really be a void. 2194 */ 2195 int efx_net_stop(struct net_device *net_dev) 2196 { 2197 struct efx_nic *efx = netdev_priv(net_dev); 2198 2199 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", 2200 raw_smp_processor_id()); 2201 2202 /* Stop the device and flush all the channels */ 2203 efx_stop_all(efx); 2204 2205 return 0; 2206 } 2207 2208 /* Context: process, dev_base_lock or RTNL held, non-blocking. */ 2209 static void efx_net_stats(struct net_device *net_dev, 2210 struct rtnl_link_stats64 *stats) 2211 { 2212 struct efx_nic *efx = netdev_priv(net_dev); 2213 2214 spin_lock_bh(&efx->stats_lock); 2215 efx->type->update_stats(efx, NULL, stats); 2216 spin_unlock_bh(&efx->stats_lock); 2217 } 2218 2219 /* Context: netif_tx_lock held, BHs disabled. */ 2220 static void efx_watchdog(struct net_device *net_dev) 2221 { 2222 struct efx_nic *efx = netdev_priv(net_dev); 2223 2224 netif_err(efx, tx_err, efx->net_dev, 2225 "TX stuck with port_enabled=%d: resetting channels\n", 2226 efx->port_enabled); 2227 2228 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); 2229 } 2230 2231 2232 /* Context: process, rtnl_lock() held. */ 2233 static int efx_change_mtu(struct net_device *net_dev, int new_mtu) 2234 { 2235 struct efx_nic *efx = netdev_priv(net_dev); 2236 int rc; 2237 2238 rc = efx_check_disabled(efx); 2239 if (rc) 2240 return rc; 2241 2242 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); 2243 2244 efx_device_detach_sync(efx); 2245 efx_stop_all(efx); 2246 2247 mutex_lock(&efx->mac_lock); 2248 net_dev->mtu = new_mtu; 2249 efx_mac_reconfigure(efx); 2250 mutex_unlock(&efx->mac_lock); 2251 2252 efx_start_all(efx); 2253 efx_device_attach_if_not_resetting(efx); 2254 return 0; 2255 } 2256 2257 static int efx_set_mac_address(struct net_device *net_dev, void *data) 2258 { 2259 struct efx_nic *efx = netdev_priv(net_dev); 2260 struct sockaddr *addr = data; 2261 u8 *new_addr = addr->sa_data; 2262 u8 old_addr[6]; 2263 int rc; 2264 2265 if (!is_valid_ether_addr(new_addr)) { 2266 netif_err(efx, drv, efx->net_dev, 2267 "invalid ethernet MAC address requested: %pM\n", 2268 new_addr); 2269 return -EADDRNOTAVAIL; 2270 } 2271 2272 /* save old address */ 2273 ether_addr_copy(old_addr, net_dev->dev_addr); 2274 ether_addr_copy(net_dev->dev_addr, new_addr); 2275 if (efx->type->set_mac_address) { 2276 rc = efx->type->set_mac_address(efx); 2277 if (rc) { 2278 ether_addr_copy(net_dev->dev_addr, old_addr); 2279 return rc; 2280 } 2281 } 2282 2283 /* Reconfigure the MAC */ 2284 mutex_lock(&efx->mac_lock); 2285 efx_mac_reconfigure(efx); 2286 mutex_unlock(&efx->mac_lock); 2287 2288 return 0; 2289 } 2290 2291 /* Context: netif_addr_lock held, BHs disabled. */ 2292 static void efx_set_rx_mode(struct net_device *net_dev) 2293 { 2294 struct efx_nic *efx = netdev_priv(net_dev); 2295 2296 if (efx->port_enabled) 2297 queue_work(efx->workqueue, &efx->mac_work); 2298 /* Otherwise efx_start_port() will do this */ 2299 } 2300 2301 static int efx_set_features(struct net_device *net_dev, netdev_features_t data) 2302 { 2303 struct efx_nic *efx = netdev_priv(net_dev); 2304 int rc; 2305 2306 /* If disabling RX n-tuple filtering, clear existing filters */ 2307 if (net_dev->features & ~data & NETIF_F_NTUPLE) { 2308 rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); 2309 if (rc) 2310 return rc; 2311 } 2312 2313 /* If Rx VLAN filter is changed, update filters via mac_reconfigure */ 2314 if ((net_dev->features ^ data) & NETIF_F_HW_VLAN_CTAG_FILTER) { 2315 /* efx_set_rx_mode() will schedule MAC work to update filters 2316 * when a new features are finally set in net_dev. 2317 */ 2318 efx_set_rx_mode(net_dev); 2319 } 2320 2321 return 0; 2322 } 2323 2324 static int efx_get_phys_port_id(struct net_device *net_dev, 2325 struct netdev_phys_item_id *ppid) 2326 { 2327 struct efx_nic *efx = netdev_priv(net_dev); 2328 2329 if (efx->type->get_phys_port_id) 2330 return efx->type->get_phys_port_id(efx, ppid); 2331 else 2332 return -EOPNOTSUPP; 2333 } 2334 2335 static int efx_get_phys_port_name(struct net_device *net_dev, 2336 char *name, size_t len) 2337 { 2338 struct efx_nic *efx = netdev_priv(net_dev); 2339 2340 if (snprintf(name, len, "p%u", efx->port_num) >= len) 2341 return -EINVAL; 2342 return 0; 2343 } 2344 2345 static int efx_vlan_rx_add_vid(struct net_device *net_dev, __be16 proto, u16 vid) 2346 { 2347 struct efx_nic *efx = netdev_priv(net_dev); 2348 2349 if (efx->type->vlan_rx_add_vid) 2350 return efx->type->vlan_rx_add_vid(efx, proto, vid); 2351 else 2352 return -EOPNOTSUPP; 2353 } 2354 2355 static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vid) 2356 { 2357 struct efx_nic *efx = netdev_priv(net_dev); 2358 2359 if (efx->type->vlan_rx_kill_vid) 2360 return efx->type->vlan_rx_kill_vid(efx, proto, vid); 2361 else 2362 return -EOPNOTSUPP; 2363 } 2364 2365 static int efx_udp_tunnel_type_map(enum udp_parsable_tunnel_type in) 2366 { 2367 switch (in) { 2368 case UDP_TUNNEL_TYPE_VXLAN: 2369 return TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 2370 case UDP_TUNNEL_TYPE_GENEVE: 2371 return TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 2372 default: 2373 return -1; 2374 } 2375 } 2376 2377 static void efx_udp_tunnel_add(struct net_device *dev, struct udp_tunnel_info *ti) 2378 { 2379 struct efx_nic *efx = netdev_priv(dev); 2380 struct efx_udp_tunnel tnl; 2381 int efx_tunnel_type; 2382 2383 efx_tunnel_type = efx_udp_tunnel_type_map(ti->type); 2384 if (efx_tunnel_type < 0) 2385 return; 2386 2387 tnl.type = (u16)efx_tunnel_type; 2388 tnl.port = ti->port; 2389 2390 if (efx->type->udp_tnl_add_port) 2391 (void)efx->type->udp_tnl_add_port(efx, tnl); 2392 } 2393 2394 static void efx_udp_tunnel_del(struct net_device *dev, struct udp_tunnel_info *ti) 2395 { 2396 struct efx_nic *efx = netdev_priv(dev); 2397 struct efx_udp_tunnel tnl; 2398 int efx_tunnel_type; 2399 2400 efx_tunnel_type = efx_udp_tunnel_type_map(ti->type); 2401 if (efx_tunnel_type < 0) 2402 return; 2403 2404 tnl.type = (u16)efx_tunnel_type; 2405 tnl.port = ti->port; 2406 2407 if (efx->type->udp_tnl_del_port) 2408 (void)efx->type->udp_tnl_del_port(efx, tnl); 2409 } 2410 2411 static const struct net_device_ops efx_netdev_ops = { 2412 .ndo_open = efx_net_open, 2413 .ndo_stop = efx_net_stop, 2414 .ndo_get_stats64 = efx_net_stats, 2415 .ndo_tx_timeout = efx_watchdog, 2416 .ndo_start_xmit = efx_hard_start_xmit, 2417 .ndo_validate_addr = eth_validate_addr, 2418 .ndo_do_ioctl = efx_ioctl, 2419 .ndo_change_mtu = efx_change_mtu, 2420 .ndo_set_mac_address = efx_set_mac_address, 2421 .ndo_set_rx_mode = efx_set_rx_mode, 2422 .ndo_set_features = efx_set_features, 2423 .ndo_vlan_rx_add_vid = efx_vlan_rx_add_vid, 2424 .ndo_vlan_rx_kill_vid = efx_vlan_rx_kill_vid, 2425 #ifdef CONFIG_SFC_SRIOV 2426 .ndo_set_vf_mac = efx_sriov_set_vf_mac, 2427 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, 2428 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, 2429 .ndo_get_vf_config = efx_sriov_get_vf_config, 2430 .ndo_set_vf_link_state = efx_sriov_set_vf_link_state, 2431 #endif 2432 .ndo_get_phys_port_id = efx_get_phys_port_id, 2433 .ndo_get_phys_port_name = efx_get_phys_port_name, 2434 #ifdef CONFIG_NET_POLL_CONTROLLER 2435 .ndo_poll_controller = efx_netpoll, 2436 #endif 2437 .ndo_setup_tc = efx_setup_tc, 2438 #ifdef CONFIG_RFS_ACCEL 2439 .ndo_rx_flow_steer = efx_filter_rfs, 2440 #endif 2441 .ndo_udp_tunnel_add = efx_udp_tunnel_add, 2442 .ndo_udp_tunnel_del = efx_udp_tunnel_del, 2443 }; 2444 2445 static void efx_update_name(struct efx_nic *efx) 2446 { 2447 strcpy(efx->name, efx->net_dev->name); 2448 efx_mtd_rename(efx); 2449 efx_set_channel_names(efx); 2450 } 2451 2452 static int efx_netdev_event(struct notifier_block *this, 2453 unsigned long event, void *ptr) 2454 { 2455 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); 2456 2457 if ((net_dev->netdev_ops == &efx_netdev_ops) && 2458 event == NETDEV_CHANGENAME) 2459 efx_update_name(netdev_priv(net_dev)); 2460 2461 return NOTIFY_DONE; 2462 } 2463 2464 static struct notifier_block efx_netdev_notifier = { 2465 .notifier_call = efx_netdev_event, 2466 }; 2467 2468 static ssize_t 2469 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) 2470 { 2471 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2472 return sprintf(buf, "%d\n", efx->phy_type); 2473 } 2474 static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); 2475 2476 #ifdef CONFIG_SFC_MCDI_LOGGING 2477 static ssize_t show_mcdi_log(struct device *dev, struct device_attribute *attr, 2478 char *buf) 2479 { 2480 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2481 struct efx_mcdi_iface *mcdi = efx_mcdi(efx); 2482 2483 return scnprintf(buf, PAGE_SIZE, "%d\n", mcdi->logging_enabled); 2484 } 2485 static ssize_t set_mcdi_log(struct device *dev, struct device_attribute *attr, 2486 const char *buf, size_t count) 2487 { 2488 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2489 struct efx_mcdi_iface *mcdi = efx_mcdi(efx); 2490 bool enable = count > 0 && *buf != '0'; 2491 2492 mcdi->logging_enabled = enable; 2493 return count; 2494 } 2495 static DEVICE_ATTR(mcdi_logging, 0644, show_mcdi_log, set_mcdi_log); 2496 #endif 2497 2498 static int efx_register_netdev(struct efx_nic *efx) 2499 { 2500 struct net_device *net_dev = efx->net_dev; 2501 struct efx_channel *channel; 2502 int rc; 2503 2504 net_dev->watchdog_timeo = 5 * HZ; 2505 net_dev->irq = efx->pci_dev->irq; 2506 net_dev->netdev_ops = &efx_netdev_ops; 2507 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) 2508 net_dev->priv_flags |= IFF_UNICAST_FLT; 2509 net_dev->ethtool_ops = &efx_ethtool_ops; 2510 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; 2511 net_dev->min_mtu = EFX_MIN_MTU; 2512 net_dev->max_mtu = EFX_MAX_MTU; 2513 2514 rtnl_lock(); 2515 2516 /* Enable resets to be scheduled and check whether any were 2517 * already requested. If so, the NIC is probably hosed so we 2518 * abort. 2519 */ 2520 efx->state = STATE_READY; 2521 smp_mb(); /* ensure we change state before checking reset_pending */ 2522 if (efx->reset_pending) { 2523 netif_err(efx, probe, efx->net_dev, 2524 "aborting probe due to scheduled reset\n"); 2525 rc = -EIO; 2526 goto fail_locked; 2527 } 2528 2529 rc = dev_alloc_name(net_dev, net_dev->name); 2530 if (rc < 0) 2531 goto fail_locked; 2532 efx_update_name(efx); 2533 2534 /* Always start with carrier off; PHY events will detect the link */ 2535 netif_carrier_off(net_dev); 2536 2537 rc = register_netdevice(net_dev); 2538 if (rc) 2539 goto fail_locked; 2540 2541 efx_for_each_channel(channel, efx) { 2542 struct efx_tx_queue *tx_queue; 2543 efx_for_each_channel_tx_queue(tx_queue, channel) 2544 efx_init_tx_queue_core_txq(tx_queue); 2545 } 2546 2547 efx_associate(efx); 2548 2549 rtnl_unlock(); 2550 2551 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2552 if (rc) { 2553 netif_err(efx, drv, efx->net_dev, 2554 "failed to init net dev attributes\n"); 2555 goto fail_registered; 2556 } 2557 #ifdef CONFIG_SFC_MCDI_LOGGING 2558 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging); 2559 if (rc) { 2560 netif_err(efx, drv, efx->net_dev, 2561 "failed to init net dev attributes\n"); 2562 goto fail_attr_mcdi_logging; 2563 } 2564 #endif 2565 2566 return 0; 2567 2568 #ifdef CONFIG_SFC_MCDI_LOGGING 2569 fail_attr_mcdi_logging: 2570 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2571 #endif 2572 fail_registered: 2573 rtnl_lock(); 2574 efx_dissociate(efx); 2575 unregister_netdevice(net_dev); 2576 fail_locked: 2577 efx->state = STATE_UNINIT; 2578 rtnl_unlock(); 2579 netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); 2580 return rc; 2581 } 2582 2583 static void efx_unregister_netdev(struct efx_nic *efx) 2584 { 2585 if (!efx->net_dev) 2586 return; 2587 2588 BUG_ON(netdev_priv(efx->net_dev) != efx); 2589 2590 if (efx_dev_registered(efx)) { 2591 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); 2592 #ifdef CONFIG_SFC_MCDI_LOGGING 2593 device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging); 2594 #endif 2595 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2596 unregister_netdev(efx->net_dev); 2597 } 2598 } 2599 2600 /************************************************************************** 2601 * 2602 * Device reset and suspend 2603 * 2604 **************************************************************************/ 2605 2606 /* Tears down the entire software state and most of the hardware state 2607 * before reset. */ 2608 void efx_reset_down(struct efx_nic *efx, enum reset_type method) 2609 { 2610 EFX_ASSERT_RESET_SERIALISED(efx); 2611 2612 if (method == RESET_TYPE_MCDI_TIMEOUT) 2613 efx->type->prepare_flr(efx); 2614 2615 efx_stop_all(efx); 2616 efx_disable_interrupts(efx); 2617 2618 mutex_lock(&efx->mac_lock); 2619 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE && 2620 method != RESET_TYPE_DATAPATH) 2621 efx->phy_op->fini(efx); 2622 efx->type->fini(efx); 2623 } 2624 2625 /* This function will always ensure that the locks acquired in 2626 * efx_reset_down() are released. A failure return code indicates 2627 * that we were unable to reinitialise the hardware, and the 2628 * driver should be disabled. If ok is false, then the rx and tx 2629 * engines are not restarted, pending a RESET_DISABLE. */ 2630 int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) 2631 { 2632 int rc; 2633 2634 EFX_ASSERT_RESET_SERIALISED(efx); 2635 2636 if (method == RESET_TYPE_MCDI_TIMEOUT) 2637 efx->type->finish_flr(efx); 2638 2639 /* Ensure that SRAM is initialised even if we're disabling the device */ 2640 rc = efx->type->init(efx); 2641 if (rc) { 2642 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); 2643 goto fail; 2644 } 2645 2646 if (!ok) 2647 goto fail; 2648 2649 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE && 2650 method != RESET_TYPE_DATAPATH) { 2651 rc = efx->phy_op->init(efx); 2652 if (rc) 2653 goto fail; 2654 rc = efx->phy_op->reconfigure(efx); 2655 if (rc && rc != -EPERM) 2656 netif_err(efx, drv, efx->net_dev, 2657 "could not restore PHY settings\n"); 2658 } 2659 2660 rc = efx_enable_interrupts(efx); 2661 if (rc) 2662 goto fail; 2663 2664 #ifdef CONFIG_SFC_SRIOV 2665 rc = efx->type->vswitching_restore(efx); 2666 if (rc) /* not fatal; the PF will still work fine */ 2667 netif_warn(efx, probe, efx->net_dev, 2668 "failed to restore vswitching rc=%d;" 2669 " VFs may not function\n", rc); 2670 #endif 2671 2672 down_read(&efx->filter_sem); 2673 efx_restore_filters(efx); 2674 up_read(&efx->filter_sem); 2675 if (efx->type->sriov_reset) 2676 efx->type->sriov_reset(efx); 2677 2678 mutex_unlock(&efx->mac_lock); 2679 2680 efx_start_all(efx); 2681 2682 if (efx->type->udp_tnl_push_ports) 2683 efx->type->udp_tnl_push_ports(efx); 2684 2685 return 0; 2686 2687 fail: 2688 efx->port_initialized = false; 2689 2690 mutex_unlock(&efx->mac_lock); 2691 2692 return rc; 2693 } 2694 2695 /* Reset the NIC using the specified method. Note that the reset may 2696 * fail, in which case the card will be left in an unusable state. 2697 * 2698 * Caller must hold the rtnl_lock. 2699 */ 2700 int efx_reset(struct efx_nic *efx, enum reset_type method) 2701 { 2702 int rc, rc2; 2703 bool disabled; 2704 2705 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", 2706 RESET_TYPE(method)); 2707 2708 efx_device_detach_sync(efx); 2709 efx_reset_down(efx, method); 2710 2711 rc = efx->type->reset(efx, method); 2712 if (rc) { 2713 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); 2714 goto out; 2715 } 2716 2717 /* Clear flags for the scopes we covered. We assume the NIC and 2718 * driver are now quiescent so that there is no race here. 2719 */ 2720 if (method < RESET_TYPE_MAX_METHOD) 2721 efx->reset_pending &= -(1 << (method + 1)); 2722 else /* it doesn't fit into the well-ordered scope hierarchy */ 2723 __clear_bit(method, &efx->reset_pending); 2724 2725 /* Reinitialise bus-mastering, which may have been turned off before 2726 * the reset was scheduled. This is still appropriate, even in the 2727 * RESET_TYPE_DISABLE since this driver generally assumes the hardware 2728 * can respond to requests. */ 2729 pci_set_master(efx->pci_dev); 2730 2731 out: 2732 /* Leave device stopped if necessary */ 2733 disabled = rc || 2734 method == RESET_TYPE_DISABLE || 2735 method == RESET_TYPE_RECOVER_OR_DISABLE; 2736 rc2 = efx_reset_up(efx, method, !disabled); 2737 if (rc2) { 2738 disabled = true; 2739 if (!rc) 2740 rc = rc2; 2741 } 2742 2743 if (disabled) { 2744 dev_close(efx->net_dev); 2745 netif_err(efx, drv, efx->net_dev, "has been disabled\n"); 2746 efx->state = STATE_DISABLED; 2747 } else { 2748 netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); 2749 efx_device_attach_if_not_resetting(efx); 2750 } 2751 return rc; 2752 } 2753 2754 /* Try recovery mechanisms. 2755 * For now only EEH is supported. 2756 * Returns 0 if the recovery mechanisms are unsuccessful. 2757 * Returns a non-zero value otherwise. 2758 */ 2759 int efx_try_recovery(struct efx_nic *efx) 2760 { 2761 #ifdef CONFIG_EEH 2762 /* A PCI error can occur and not be seen by EEH because nothing 2763 * happens on the PCI bus. In this case the driver may fail and 2764 * schedule a 'recover or reset', leading to this recovery handler. 2765 * Manually call the eeh failure check function. 2766 */ 2767 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev); 2768 if (eeh_dev_check_failure(eehdev)) { 2769 /* The EEH mechanisms will handle the error and reset the 2770 * device if necessary. 2771 */ 2772 return 1; 2773 } 2774 #endif 2775 return 0; 2776 } 2777 2778 static void efx_wait_for_bist_end(struct efx_nic *efx) 2779 { 2780 int i; 2781 2782 for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { 2783 if (efx_mcdi_poll_reboot(efx)) 2784 goto out; 2785 msleep(BIST_WAIT_DELAY_MS); 2786 } 2787 2788 netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); 2789 out: 2790 /* Either way unset the BIST flag. If we found no reboot we probably 2791 * won't recover, but we should try. 2792 */ 2793 efx->mc_bist_for_other_fn = false; 2794 } 2795 2796 /* The worker thread exists so that code that cannot sleep can 2797 * schedule a reset for later. 2798 */ 2799 static void efx_reset_work(struct work_struct *data) 2800 { 2801 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); 2802 unsigned long pending; 2803 enum reset_type method; 2804 2805 pending = ACCESS_ONCE(efx->reset_pending); 2806 method = fls(pending) - 1; 2807 2808 if (method == RESET_TYPE_MC_BIST) 2809 efx_wait_for_bist_end(efx); 2810 2811 if ((method == RESET_TYPE_RECOVER_OR_DISABLE || 2812 method == RESET_TYPE_RECOVER_OR_ALL) && 2813 efx_try_recovery(efx)) 2814 return; 2815 2816 if (!pending) 2817 return; 2818 2819 rtnl_lock(); 2820 2821 /* We checked the state in efx_schedule_reset() but it may 2822 * have changed by now. Now that we have the RTNL lock, 2823 * it cannot change again. 2824 */ 2825 if (efx->state == STATE_READY) 2826 (void)efx_reset(efx, method); 2827 2828 rtnl_unlock(); 2829 } 2830 2831 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) 2832 { 2833 enum reset_type method; 2834 2835 if (efx->state == STATE_RECOVERY) { 2836 netif_dbg(efx, drv, efx->net_dev, 2837 "recovering: skip scheduling %s reset\n", 2838 RESET_TYPE(type)); 2839 return; 2840 } 2841 2842 switch (type) { 2843 case RESET_TYPE_INVISIBLE: 2844 case RESET_TYPE_ALL: 2845 case RESET_TYPE_RECOVER_OR_ALL: 2846 case RESET_TYPE_WORLD: 2847 case RESET_TYPE_DISABLE: 2848 case RESET_TYPE_RECOVER_OR_DISABLE: 2849 case RESET_TYPE_DATAPATH: 2850 case RESET_TYPE_MC_BIST: 2851 case RESET_TYPE_MCDI_TIMEOUT: 2852 method = type; 2853 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", 2854 RESET_TYPE(method)); 2855 break; 2856 default: 2857 method = efx->type->map_reset_reason(type); 2858 netif_dbg(efx, drv, efx->net_dev, 2859 "scheduling %s reset for %s\n", 2860 RESET_TYPE(method), RESET_TYPE(type)); 2861 break; 2862 } 2863 2864 set_bit(method, &efx->reset_pending); 2865 smp_mb(); /* ensure we change reset_pending before checking state */ 2866 2867 /* If we're not READY then just leave the flags set as the cue 2868 * to abort probing or reschedule the reset later. 2869 */ 2870 if (ACCESS_ONCE(efx->state) != STATE_READY) 2871 return; 2872 2873 /* efx_process_channel() will no longer read events once a 2874 * reset is scheduled. So switch back to poll'd MCDI completions. */ 2875 efx_mcdi_mode_poll(efx); 2876 2877 queue_work(reset_workqueue, &efx->reset_work); 2878 } 2879 2880 /************************************************************************** 2881 * 2882 * List of NICs we support 2883 * 2884 **************************************************************************/ 2885 2886 /* PCI device ID table */ 2887 static const struct pci_device_id efx_pci_table[] = { 2888 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ 2889 .driver_data = (unsigned long) &siena_a0_nic_type}, 2890 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ 2891 .driver_data = (unsigned long) &siena_a0_nic_type}, 2892 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ 2893 .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, 2894 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1903), /* SFC9120 VF */ 2895 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, 2896 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */ 2897 .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, 2898 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1923), /* SFC9140 VF */ 2899 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, 2900 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0a03), /* SFC9220 PF */ 2901 .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, 2902 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1a03), /* SFC9220 VF */ 2903 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type}, 2904 {0} /* end of list */ 2905 }; 2906 2907 /************************************************************************** 2908 * 2909 * Dummy PHY/MAC operations 2910 * 2911 * Can be used for some unimplemented operations 2912 * Needed so all function pointers are valid and do not have to be tested 2913 * before use 2914 * 2915 **************************************************************************/ 2916 int efx_port_dummy_op_int(struct efx_nic *efx) 2917 { 2918 return 0; 2919 } 2920 void efx_port_dummy_op_void(struct efx_nic *efx) {} 2921 2922 static bool efx_port_dummy_op_poll(struct efx_nic *efx) 2923 { 2924 return false; 2925 } 2926 2927 static const struct efx_phy_operations efx_dummy_phy_operations = { 2928 .init = efx_port_dummy_op_int, 2929 .reconfigure = efx_port_dummy_op_int, 2930 .poll = efx_port_dummy_op_poll, 2931 .fini = efx_port_dummy_op_void, 2932 }; 2933 2934 /************************************************************************** 2935 * 2936 * Data housekeeping 2937 * 2938 **************************************************************************/ 2939 2940 /* This zeroes out and then fills in the invariants in a struct 2941 * efx_nic (including all sub-structures). 2942 */ 2943 static int efx_init_struct(struct efx_nic *efx, 2944 struct pci_dev *pci_dev, struct net_device *net_dev) 2945 { 2946 int rc = -ENOMEM, i; 2947 2948 /* Initialise common structures */ 2949 INIT_LIST_HEAD(&efx->node); 2950 INIT_LIST_HEAD(&efx->secondary_list); 2951 spin_lock_init(&efx->biu_lock); 2952 #ifdef CONFIG_SFC_MTD 2953 INIT_LIST_HEAD(&efx->mtd_list); 2954 #endif 2955 INIT_WORK(&efx->reset_work, efx_reset_work); 2956 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); 2957 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); 2958 efx->pci_dev = pci_dev; 2959 efx->msg_enable = debug; 2960 efx->state = STATE_UNINIT; 2961 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); 2962 2963 efx->net_dev = net_dev; 2964 efx->rx_prefix_size = efx->type->rx_prefix_size; 2965 efx->rx_ip_align = 2966 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; 2967 efx->rx_packet_hash_offset = 2968 efx->type->rx_hash_offset - efx->type->rx_prefix_size; 2969 efx->rx_packet_ts_offset = 2970 efx->type->rx_ts_offset - efx->type->rx_prefix_size; 2971 spin_lock_init(&efx->stats_lock); 2972 mutex_init(&efx->mac_lock); 2973 efx->phy_op = &efx_dummy_phy_operations; 2974 efx->mdio.dev = net_dev; 2975 INIT_WORK(&efx->mac_work, efx_mac_work); 2976 init_waitqueue_head(&efx->flush_wq); 2977 2978 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 2979 efx->channel[i] = efx_alloc_channel(efx, i, NULL); 2980 if (!efx->channel[i]) 2981 goto fail; 2982 efx->msi_context[i].efx = efx; 2983 efx->msi_context[i].index = i; 2984 } 2985 2986 /* Higher numbered interrupt modes are less capable! */ 2987 if (WARN_ON_ONCE(efx->type->max_interrupt_mode > 2988 efx->type->min_interrupt_mode)) { 2989 rc = -EIO; 2990 goto fail; 2991 } 2992 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 2993 interrupt_mode); 2994 efx->interrupt_mode = min(efx->type->min_interrupt_mode, 2995 interrupt_mode); 2996 2997 /* Would be good to use the net_dev name, but we're too early */ 2998 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", 2999 pci_name(pci_dev)); 3000 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); 3001 if (!efx->workqueue) 3002 goto fail; 3003 3004 return 0; 3005 3006 fail: 3007 efx_fini_struct(efx); 3008 return rc; 3009 } 3010 3011 static void efx_fini_struct(struct efx_nic *efx) 3012 { 3013 int i; 3014 3015 for (i = 0; i < EFX_MAX_CHANNELS; i++) 3016 kfree(efx->channel[i]); 3017 3018 kfree(efx->vpd_sn); 3019 3020 if (efx->workqueue) { 3021 destroy_workqueue(efx->workqueue); 3022 efx->workqueue = NULL; 3023 } 3024 } 3025 3026 void efx_update_sw_stats(struct efx_nic *efx, u64 *stats) 3027 { 3028 u64 n_rx_nodesc_trunc = 0; 3029 struct efx_channel *channel; 3030 3031 efx_for_each_channel(channel, efx) 3032 n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc; 3033 stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc; 3034 stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops); 3035 } 3036 3037 /************************************************************************** 3038 * 3039 * PCI interface 3040 * 3041 **************************************************************************/ 3042 3043 /* Main body of final NIC shutdown code 3044 * This is called only at module unload (or hotplug removal). 3045 */ 3046 static void efx_pci_remove_main(struct efx_nic *efx) 3047 { 3048 /* Flush reset_work. It can no longer be scheduled since we 3049 * are not READY. 3050 */ 3051 BUG_ON(efx->state == STATE_READY); 3052 cancel_work_sync(&efx->reset_work); 3053 3054 efx_disable_interrupts(efx); 3055 efx_nic_fini_interrupt(efx); 3056 efx_fini_port(efx); 3057 efx->type->fini(efx); 3058 efx_fini_napi(efx); 3059 efx_remove_all(efx); 3060 } 3061 3062 /* Final NIC shutdown 3063 * This is called only at module unload (or hotplug removal). A PF can call 3064 * this on its VFs to ensure they are unbound first. 3065 */ 3066 static void efx_pci_remove(struct pci_dev *pci_dev) 3067 { 3068 struct efx_nic *efx; 3069 3070 efx = pci_get_drvdata(pci_dev); 3071 if (!efx) 3072 return; 3073 3074 /* Mark the NIC as fini, then stop the interface */ 3075 rtnl_lock(); 3076 efx_dissociate(efx); 3077 dev_close(efx->net_dev); 3078 efx_disable_interrupts(efx); 3079 efx->state = STATE_UNINIT; 3080 rtnl_unlock(); 3081 3082 if (efx->type->sriov_fini) 3083 efx->type->sriov_fini(efx); 3084 3085 efx_unregister_netdev(efx); 3086 3087 efx_mtd_remove(efx); 3088 3089 efx_pci_remove_main(efx); 3090 3091 efx_fini_io(efx); 3092 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); 3093 3094 efx_fini_struct(efx); 3095 free_netdev(efx->net_dev); 3096 3097 pci_disable_pcie_error_reporting(pci_dev); 3098 }; 3099 3100 /* NIC VPD information 3101 * Called during probe to display the part number of the 3102 * installed NIC. VPD is potentially very large but this should 3103 * always appear within the first 512 bytes. 3104 */ 3105 #define SFC_VPD_LEN 512 3106 static void efx_probe_vpd_strings(struct efx_nic *efx) 3107 { 3108 struct pci_dev *dev = efx->pci_dev; 3109 char vpd_data[SFC_VPD_LEN]; 3110 ssize_t vpd_size; 3111 int ro_start, ro_size, i, j; 3112 3113 /* Get the vpd data from the device */ 3114 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); 3115 if (vpd_size <= 0) { 3116 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); 3117 return; 3118 } 3119 3120 /* Get the Read only section */ 3121 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 3122 if (ro_start < 0) { 3123 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); 3124 return; 3125 } 3126 3127 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); 3128 j = ro_size; 3129 i = ro_start + PCI_VPD_LRDT_TAG_SIZE; 3130 if (i + j > vpd_size) 3131 j = vpd_size - i; 3132 3133 /* Get the Part number */ 3134 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); 3135 if (i < 0) { 3136 netif_err(efx, drv, efx->net_dev, "Part number not found\n"); 3137 return; 3138 } 3139 3140 j = pci_vpd_info_field_size(&vpd_data[i]); 3141 i += PCI_VPD_INFO_FLD_HDR_SIZE; 3142 if (i + j > vpd_size) { 3143 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); 3144 return; 3145 } 3146 3147 netif_info(efx, drv, efx->net_dev, 3148 "Part Number : %.*s\n", j, &vpd_data[i]); 3149 3150 i = ro_start + PCI_VPD_LRDT_TAG_SIZE; 3151 j = ro_size; 3152 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); 3153 if (i < 0) { 3154 netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); 3155 return; 3156 } 3157 3158 j = pci_vpd_info_field_size(&vpd_data[i]); 3159 i += PCI_VPD_INFO_FLD_HDR_SIZE; 3160 if (i + j > vpd_size) { 3161 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); 3162 return; 3163 } 3164 3165 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); 3166 if (!efx->vpd_sn) 3167 return; 3168 3169 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); 3170 } 3171 3172 3173 /* Main body of NIC initialisation 3174 * This is called at module load (or hotplug insertion, theoretically). 3175 */ 3176 static int efx_pci_probe_main(struct efx_nic *efx) 3177 { 3178 int rc; 3179 3180 /* Do start-of-day initialisation */ 3181 rc = efx_probe_all(efx); 3182 if (rc) 3183 goto fail1; 3184 3185 efx_init_napi(efx); 3186 3187 rc = efx->type->init(efx); 3188 if (rc) { 3189 netif_err(efx, probe, efx->net_dev, 3190 "failed to initialise NIC\n"); 3191 goto fail3; 3192 } 3193 3194 rc = efx_init_port(efx); 3195 if (rc) { 3196 netif_err(efx, probe, efx->net_dev, 3197 "failed to initialise port\n"); 3198 goto fail4; 3199 } 3200 3201 rc = efx_nic_init_interrupt(efx); 3202 if (rc) 3203 goto fail5; 3204 rc = efx_enable_interrupts(efx); 3205 if (rc) 3206 goto fail6; 3207 3208 return 0; 3209 3210 fail6: 3211 efx_nic_fini_interrupt(efx); 3212 fail5: 3213 efx_fini_port(efx); 3214 fail4: 3215 efx->type->fini(efx); 3216 fail3: 3217 efx_fini_napi(efx); 3218 efx_remove_all(efx); 3219 fail1: 3220 return rc; 3221 } 3222 3223 static int efx_pci_probe_post_io(struct efx_nic *efx) 3224 { 3225 struct net_device *net_dev = efx->net_dev; 3226 int rc = efx_pci_probe_main(efx); 3227 3228 if (rc) 3229 return rc; 3230 3231 if (efx->type->sriov_init) { 3232 rc = efx->type->sriov_init(efx); 3233 if (rc) 3234 netif_err(efx, probe, efx->net_dev, 3235 "SR-IOV can't be enabled rc %d\n", rc); 3236 } 3237 3238 /* Determine netdevice features */ 3239 net_dev->features |= (efx->type->offload_features | NETIF_F_SG | 3240 NETIF_F_TSO | NETIF_F_RXCSUM); 3241 if (efx->type->offload_features & (NETIF_F_IPV6_CSUM | NETIF_F_HW_CSUM)) 3242 net_dev->features |= NETIF_F_TSO6; 3243 /* Check whether device supports TSO */ 3244 if (!efx->type->tso_versions || !efx->type->tso_versions(efx)) 3245 net_dev->features &= ~NETIF_F_ALL_TSO; 3246 /* Mask for features that also apply to VLAN devices */ 3247 net_dev->vlan_features |= (NETIF_F_HW_CSUM | NETIF_F_SG | 3248 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | 3249 NETIF_F_RXCSUM); 3250 3251 net_dev->hw_features = net_dev->features & ~efx->fixed_features; 3252 3253 /* Disable VLAN filtering by default. It may be enforced if 3254 * the feature is fixed (i.e. VLAN filters are required to 3255 * receive VLAN tagged packets due to vPort restrictions). 3256 */ 3257 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 3258 net_dev->features |= efx->fixed_features; 3259 3260 rc = efx_register_netdev(efx); 3261 if (!rc) 3262 return 0; 3263 3264 efx_pci_remove_main(efx); 3265 return rc; 3266 } 3267 3268 /* NIC initialisation 3269 * 3270 * This is called at module load (or hotplug insertion, 3271 * theoretically). It sets up PCI mappings, resets the NIC, 3272 * sets up and registers the network devices with the kernel and hooks 3273 * the interrupt service routine. It does not prepare the device for 3274 * transmission; this is left to the first time one of the network 3275 * interfaces is brought up (i.e. efx_net_open). 3276 */ 3277 static int efx_pci_probe(struct pci_dev *pci_dev, 3278 const struct pci_device_id *entry) 3279 { 3280 struct net_device *net_dev; 3281 struct efx_nic *efx; 3282 int rc; 3283 3284 /* Allocate and initialise a struct net_device and struct efx_nic */ 3285 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, 3286 EFX_MAX_RX_QUEUES); 3287 if (!net_dev) 3288 return -ENOMEM; 3289 efx = netdev_priv(net_dev); 3290 efx->type = (const struct efx_nic_type *) entry->driver_data; 3291 efx->fixed_features |= NETIF_F_HIGHDMA; 3292 3293 pci_set_drvdata(pci_dev, efx); 3294 SET_NETDEV_DEV(net_dev, &pci_dev->dev); 3295 rc = efx_init_struct(efx, pci_dev, net_dev); 3296 if (rc) 3297 goto fail1; 3298 3299 netif_info(efx, probe, efx->net_dev, 3300 "Solarflare NIC detected\n"); 3301 3302 if (!efx->type->is_vf) 3303 efx_probe_vpd_strings(efx); 3304 3305 /* Set up basic I/O (BAR mappings etc) */ 3306 rc = efx_init_io(efx); 3307 if (rc) 3308 goto fail2; 3309 3310 rc = efx_pci_probe_post_io(efx); 3311 if (rc) { 3312 /* On failure, retry once immediately. 3313 * If we aborted probe due to a scheduled reset, dismiss it. 3314 */ 3315 efx->reset_pending = 0; 3316 rc = efx_pci_probe_post_io(efx); 3317 if (rc) { 3318 /* On another failure, retry once more 3319 * after a 50-305ms delay. 3320 */ 3321 unsigned char r; 3322 3323 get_random_bytes(&r, 1); 3324 msleep((unsigned int)r + 50); 3325 efx->reset_pending = 0; 3326 rc = efx_pci_probe_post_io(efx); 3327 } 3328 } 3329 if (rc) 3330 goto fail3; 3331 3332 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); 3333 3334 /* Try to create MTDs, but allow this to fail */ 3335 rtnl_lock(); 3336 rc = efx_mtd_probe(efx); 3337 rtnl_unlock(); 3338 if (rc && rc != -EPERM) 3339 netif_warn(efx, probe, efx->net_dev, 3340 "failed to create MTDs (%d)\n", rc); 3341 3342 rc = pci_enable_pcie_error_reporting(pci_dev); 3343 if (rc && rc != -EINVAL) 3344 netif_notice(efx, probe, efx->net_dev, 3345 "PCIE error reporting unavailable (%d).\n", 3346 rc); 3347 3348 if (efx->type->udp_tnl_push_ports) 3349 efx->type->udp_tnl_push_ports(efx); 3350 3351 return 0; 3352 3353 fail3: 3354 efx_fini_io(efx); 3355 fail2: 3356 efx_fini_struct(efx); 3357 fail1: 3358 WARN_ON(rc > 0); 3359 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); 3360 free_netdev(net_dev); 3361 return rc; 3362 } 3363 3364 /* efx_pci_sriov_configure returns the actual number of Virtual Functions 3365 * enabled on success 3366 */ 3367 #ifdef CONFIG_SFC_SRIOV 3368 static int efx_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 3369 { 3370 int rc; 3371 struct efx_nic *efx = pci_get_drvdata(dev); 3372 3373 if (efx->type->sriov_configure) { 3374 rc = efx->type->sriov_configure(efx, num_vfs); 3375 if (rc) 3376 return rc; 3377 else 3378 return num_vfs; 3379 } else 3380 return -EOPNOTSUPP; 3381 } 3382 #endif 3383 3384 static int efx_pm_freeze(struct device *dev) 3385 { 3386 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 3387 3388 rtnl_lock(); 3389 3390 if (efx->state != STATE_DISABLED) { 3391 efx->state = STATE_UNINIT; 3392 3393 efx_device_detach_sync(efx); 3394 3395 efx_stop_all(efx); 3396 efx_disable_interrupts(efx); 3397 } 3398 3399 rtnl_unlock(); 3400 3401 return 0; 3402 } 3403 3404 static int efx_pm_thaw(struct device *dev) 3405 { 3406 int rc; 3407 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 3408 3409 rtnl_lock(); 3410 3411 if (efx->state != STATE_DISABLED) { 3412 rc = efx_enable_interrupts(efx); 3413 if (rc) 3414 goto fail; 3415 3416 mutex_lock(&efx->mac_lock); 3417 efx->phy_op->reconfigure(efx); 3418 mutex_unlock(&efx->mac_lock); 3419 3420 efx_start_all(efx); 3421 3422 efx_device_attach_if_not_resetting(efx); 3423 3424 efx->state = STATE_READY; 3425 3426 efx->type->resume_wol(efx); 3427 } 3428 3429 rtnl_unlock(); 3430 3431 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ 3432 queue_work(reset_workqueue, &efx->reset_work); 3433 3434 return 0; 3435 3436 fail: 3437 rtnl_unlock(); 3438 3439 return rc; 3440 } 3441 3442 static int efx_pm_poweroff(struct device *dev) 3443 { 3444 struct pci_dev *pci_dev = to_pci_dev(dev); 3445 struct efx_nic *efx = pci_get_drvdata(pci_dev); 3446 3447 efx->type->fini(efx); 3448 3449 efx->reset_pending = 0; 3450 3451 pci_save_state(pci_dev); 3452 return pci_set_power_state(pci_dev, PCI_D3hot); 3453 } 3454 3455 /* Used for both resume and restore */ 3456 static int efx_pm_resume(struct device *dev) 3457 { 3458 struct pci_dev *pci_dev = to_pci_dev(dev); 3459 struct efx_nic *efx = pci_get_drvdata(pci_dev); 3460 int rc; 3461 3462 rc = pci_set_power_state(pci_dev, PCI_D0); 3463 if (rc) 3464 return rc; 3465 pci_restore_state(pci_dev); 3466 rc = pci_enable_device(pci_dev); 3467 if (rc) 3468 return rc; 3469 pci_set_master(efx->pci_dev); 3470 rc = efx->type->reset(efx, RESET_TYPE_ALL); 3471 if (rc) 3472 return rc; 3473 rc = efx->type->init(efx); 3474 if (rc) 3475 return rc; 3476 rc = efx_pm_thaw(dev); 3477 return rc; 3478 } 3479 3480 static int efx_pm_suspend(struct device *dev) 3481 { 3482 int rc; 3483 3484 efx_pm_freeze(dev); 3485 rc = efx_pm_poweroff(dev); 3486 if (rc) 3487 efx_pm_resume(dev); 3488 return rc; 3489 } 3490 3491 static const struct dev_pm_ops efx_pm_ops = { 3492 .suspend = efx_pm_suspend, 3493 .resume = efx_pm_resume, 3494 .freeze = efx_pm_freeze, 3495 .thaw = efx_pm_thaw, 3496 .poweroff = efx_pm_poweroff, 3497 .restore = efx_pm_resume, 3498 }; 3499 3500 /* A PCI error affecting this device was detected. 3501 * At this point MMIO and DMA may be disabled. 3502 * Stop the software path and request a slot reset. 3503 */ 3504 static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, 3505 enum pci_channel_state state) 3506 { 3507 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3508 struct efx_nic *efx = pci_get_drvdata(pdev); 3509 3510 if (state == pci_channel_io_perm_failure) 3511 return PCI_ERS_RESULT_DISCONNECT; 3512 3513 rtnl_lock(); 3514 3515 if (efx->state != STATE_DISABLED) { 3516 efx->state = STATE_RECOVERY; 3517 efx->reset_pending = 0; 3518 3519 efx_device_detach_sync(efx); 3520 3521 efx_stop_all(efx); 3522 efx_disable_interrupts(efx); 3523 3524 status = PCI_ERS_RESULT_NEED_RESET; 3525 } else { 3526 /* If the interface is disabled we don't want to do anything 3527 * with it. 3528 */ 3529 status = PCI_ERS_RESULT_RECOVERED; 3530 } 3531 3532 rtnl_unlock(); 3533 3534 pci_disable_device(pdev); 3535 3536 return status; 3537 } 3538 3539 /* Fake a successful reset, which will be performed later in efx_io_resume. */ 3540 static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) 3541 { 3542 struct efx_nic *efx = pci_get_drvdata(pdev); 3543 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3544 int rc; 3545 3546 if (pci_enable_device(pdev)) { 3547 netif_err(efx, hw, efx->net_dev, 3548 "Cannot re-enable PCI device after reset.\n"); 3549 status = PCI_ERS_RESULT_DISCONNECT; 3550 } 3551 3552 rc = pci_cleanup_aer_uncorrect_error_status(pdev); 3553 if (rc) { 3554 netif_err(efx, hw, efx->net_dev, 3555 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); 3556 /* Non-fatal error. Continue. */ 3557 } 3558 3559 return status; 3560 } 3561 3562 /* Perform the actual reset and resume I/O operations. */ 3563 static void efx_io_resume(struct pci_dev *pdev) 3564 { 3565 struct efx_nic *efx = pci_get_drvdata(pdev); 3566 int rc; 3567 3568 rtnl_lock(); 3569 3570 if (efx->state == STATE_DISABLED) 3571 goto out; 3572 3573 rc = efx_reset(efx, RESET_TYPE_ALL); 3574 if (rc) { 3575 netif_err(efx, hw, efx->net_dev, 3576 "efx_reset failed after PCI error (%d)\n", rc); 3577 } else { 3578 efx->state = STATE_READY; 3579 netif_dbg(efx, hw, efx->net_dev, 3580 "Done resetting and resuming IO after PCI error.\n"); 3581 } 3582 3583 out: 3584 rtnl_unlock(); 3585 } 3586 3587 /* For simplicity and reliability, we always require a slot reset and try to 3588 * reset the hardware when a pci error affecting the device is detected. 3589 * We leave both the link_reset and mmio_enabled callback unimplemented: 3590 * with our request for slot reset the mmio_enabled callback will never be 3591 * called, and the link_reset callback is not used by AER or EEH mechanisms. 3592 */ 3593 static const struct pci_error_handlers efx_err_handlers = { 3594 .error_detected = efx_io_error_detected, 3595 .slot_reset = efx_io_slot_reset, 3596 .resume = efx_io_resume, 3597 }; 3598 3599 static struct pci_driver efx_pci_driver = { 3600 .name = KBUILD_MODNAME, 3601 .id_table = efx_pci_table, 3602 .probe = efx_pci_probe, 3603 .remove = efx_pci_remove, 3604 .driver.pm = &efx_pm_ops, 3605 .err_handler = &efx_err_handlers, 3606 #ifdef CONFIG_SFC_SRIOV 3607 .sriov_configure = efx_pci_sriov_configure, 3608 #endif 3609 }; 3610 3611 /************************************************************************** 3612 * 3613 * Kernel module interface 3614 * 3615 *************************************************************************/ 3616 3617 module_param(interrupt_mode, uint, 0444); 3618 MODULE_PARM_DESC(interrupt_mode, 3619 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 3620 3621 static int __init efx_init_module(void) 3622 { 3623 int rc; 3624 3625 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); 3626 3627 rc = register_netdevice_notifier(&efx_netdev_notifier); 3628 if (rc) 3629 goto err_notifier; 3630 3631 #ifdef CONFIG_SFC_SRIOV 3632 rc = efx_init_sriov(); 3633 if (rc) 3634 goto err_sriov; 3635 #endif 3636 3637 reset_workqueue = create_singlethread_workqueue("sfc_reset"); 3638 if (!reset_workqueue) { 3639 rc = -ENOMEM; 3640 goto err_reset; 3641 } 3642 3643 rc = pci_register_driver(&efx_pci_driver); 3644 if (rc < 0) 3645 goto err_pci; 3646 3647 return 0; 3648 3649 err_pci: 3650 destroy_workqueue(reset_workqueue); 3651 err_reset: 3652 #ifdef CONFIG_SFC_SRIOV 3653 efx_fini_sriov(); 3654 err_sriov: 3655 #endif 3656 unregister_netdevice_notifier(&efx_netdev_notifier); 3657 err_notifier: 3658 return rc; 3659 } 3660 3661 static void __exit efx_exit_module(void) 3662 { 3663 printk(KERN_INFO "Solarflare NET driver unloading\n"); 3664 3665 pci_unregister_driver(&efx_pci_driver); 3666 destroy_workqueue(reset_workqueue); 3667 #ifdef CONFIG_SFC_SRIOV 3668 efx_fini_sriov(); 3669 #endif 3670 unregister_netdevice_notifier(&efx_netdev_notifier); 3671 3672 } 3673 3674 module_init(efx_init_module); 3675 module_exit(efx_exit_module); 3676 3677 MODULE_AUTHOR("Solarflare Communications and " 3678 "Michael Brown <mbrown@fensystems.co.uk>"); 3679 MODULE_DESCRIPTION("Solarflare network driver"); 3680 MODULE_LICENSE("GPL"); 3681 MODULE_DEVICE_TABLE(pci, efx_pci_table); 3682 MODULE_VERSION(EFX_DRIVER_VERSION); 3683