1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/module.h> 5 #include <linux/netdevice.h> 6 #include <linux/sfp.h> 7 8 #include "ionic.h" 9 #include "ionic_bus.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethtool.h" 12 #include "ionic_stats.h" 13 14 static void ionic_get_stats_strings(struct ionic_lif *lif, u8 *buf) 15 { 16 u32 i; 17 18 for (i = 0; i < ionic_num_stats_grps; i++) 19 ionic_stats_groups[i].get_strings(lif, &buf); 20 } 21 22 static void ionic_get_stats(struct net_device *netdev, 23 struct ethtool_stats *stats, u64 *buf) 24 { 25 struct ionic_lif *lif = netdev_priv(netdev); 26 u32 i; 27 28 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 29 return; 30 31 memset(buf, 0, stats->n_stats * sizeof(*buf)); 32 for (i = 0; i < ionic_num_stats_grps; i++) 33 ionic_stats_groups[i].get_values(lif, &buf); 34 } 35 36 static int ionic_get_stats_count(struct ionic_lif *lif) 37 { 38 int i, num_stats = 0; 39 40 for (i = 0; i < ionic_num_stats_grps; i++) 41 num_stats += ionic_stats_groups[i].get_count(lif); 42 43 return num_stats; 44 } 45 46 static int ionic_get_sset_count(struct net_device *netdev, int sset) 47 { 48 struct ionic_lif *lif = netdev_priv(netdev); 49 int count = 0; 50 51 switch (sset) { 52 case ETH_SS_STATS: 53 count = ionic_get_stats_count(lif); 54 break; 55 } 56 return count; 57 } 58 59 static void ionic_get_strings(struct net_device *netdev, 60 u32 sset, u8 *buf) 61 { 62 struct ionic_lif *lif = netdev_priv(netdev); 63 64 switch (sset) { 65 case ETH_SS_STATS: 66 ionic_get_stats_strings(lif, buf); 67 break; 68 } 69 } 70 71 static void ionic_get_drvinfo(struct net_device *netdev, 72 struct ethtool_drvinfo *drvinfo) 73 { 74 struct ionic_lif *lif = netdev_priv(netdev); 75 struct ionic *ionic = lif->ionic; 76 77 strlcpy(drvinfo->driver, IONIC_DRV_NAME, sizeof(drvinfo->driver)); 78 strlcpy(drvinfo->fw_version, ionic->idev.dev_info.fw_version, 79 sizeof(drvinfo->fw_version)); 80 strlcpy(drvinfo->bus_info, ionic_bus_info(ionic), 81 sizeof(drvinfo->bus_info)); 82 } 83 84 static int ionic_get_regs_len(struct net_device *netdev) 85 { 86 return (IONIC_DEV_INFO_REG_COUNT + IONIC_DEV_CMD_REG_COUNT) * sizeof(u32); 87 } 88 89 static void ionic_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 90 void *p) 91 { 92 struct ionic_lif *lif = netdev_priv(netdev); 93 unsigned int offset; 94 unsigned int size; 95 96 regs->version = IONIC_DEV_CMD_REG_VERSION; 97 98 offset = 0; 99 size = IONIC_DEV_INFO_REG_COUNT * sizeof(u32); 100 memcpy_fromio(p + offset, lif->ionic->idev.dev_info_regs->words, size); 101 102 offset += size; 103 size = IONIC_DEV_CMD_REG_COUNT * sizeof(u32); 104 memcpy_fromio(p + offset, lif->ionic->idev.dev_cmd_regs->words, size); 105 } 106 107 static int ionic_get_link_ksettings(struct net_device *netdev, 108 struct ethtool_link_ksettings *ks) 109 { 110 struct ionic_lif *lif = netdev_priv(netdev); 111 struct ionic_dev *idev = &lif->ionic->idev; 112 int copper_seen = 0; 113 114 ethtool_link_ksettings_zero_link_mode(ks, supported); 115 116 if (!idev->port_info) { 117 netdev_err(netdev, "port_info not initialized\n"); 118 return -EOPNOTSUPP; 119 } 120 121 /* The port_info data is found in a DMA space that the NIC keeps 122 * up-to-date, so there's no need to request the data from the 123 * NIC, we already have it in our memory space. 124 */ 125 126 switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) { 127 /* Copper */ 128 case IONIC_XCVR_PID_QSFP_100G_CR4: 129 ethtool_link_ksettings_add_link_mode(ks, supported, 130 100000baseCR4_Full); 131 copper_seen++; 132 break; 133 case IONIC_XCVR_PID_QSFP_40GBASE_CR4: 134 ethtool_link_ksettings_add_link_mode(ks, supported, 135 40000baseCR4_Full); 136 copper_seen++; 137 break; 138 case IONIC_XCVR_PID_SFP_25GBASE_CR_S: 139 case IONIC_XCVR_PID_SFP_25GBASE_CR_L: 140 case IONIC_XCVR_PID_SFP_25GBASE_CR_N: 141 ethtool_link_ksettings_add_link_mode(ks, supported, 142 25000baseCR_Full); 143 copper_seen++; 144 break; 145 case IONIC_XCVR_PID_SFP_10GBASE_AOC: 146 case IONIC_XCVR_PID_SFP_10GBASE_CU: 147 ethtool_link_ksettings_add_link_mode(ks, supported, 148 10000baseCR_Full); 149 copper_seen++; 150 break; 151 152 /* Fibre */ 153 case IONIC_XCVR_PID_QSFP_100G_SR4: 154 case IONIC_XCVR_PID_QSFP_100G_AOC: 155 ethtool_link_ksettings_add_link_mode(ks, supported, 156 100000baseSR4_Full); 157 break; 158 case IONIC_XCVR_PID_QSFP_100G_CWDM4: 159 case IONIC_XCVR_PID_QSFP_100G_PSM4: 160 case IONIC_XCVR_PID_QSFP_100G_LR4: 161 ethtool_link_ksettings_add_link_mode(ks, supported, 162 100000baseLR4_ER4_Full); 163 break; 164 case IONIC_XCVR_PID_QSFP_100G_ER4: 165 ethtool_link_ksettings_add_link_mode(ks, supported, 166 100000baseLR4_ER4_Full); 167 break; 168 case IONIC_XCVR_PID_QSFP_40GBASE_SR4: 169 case IONIC_XCVR_PID_QSFP_40GBASE_AOC: 170 ethtool_link_ksettings_add_link_mode(ks, supported, 171 40000baseSR4_Full); 172 break; 173 case IONIC_XCVR_PID_QSFP_40GBASE_LR4: 174 ethtool_link_ksettings_add_link_mode(ks, supported, 175 40000baseLR4_Full); 176 break; 177 case IONIC_XCVR_PID_SFP_25GBASE_SR: 178 case IONIC_XCVR_PID_SFP_25GBASE_AOC: 179 case IONIC_XCVR_PID_SFP_25GBASE_ACC: 180 ethtool_link_ksettings_add_link_mode(ks, supported, 181 25000baseSR_Full); 182 break; 183 case IONIC_XCVR_PID_SFP_10GBASE_SR: 184 ethtool_link_ksettings_add_link_mode(ks, supported, 185 10000baseSR_Full); 186 break; 187 case IONIC_XCVR_PID_SFP_10GBASE_LR: 188 ethtool_link_ksettings_add_link_mode(ks, supported, 189 10000baseLR_Full); 190 break; 191 case IONIC_XCVR_PID_SFP_10GBASE_LRM: 192 ethtool_link_ksettings_add_link_mode(ks, supported, 193 10000baseLRM_Full); 194 break; 195 case IONIC_XCVR_PID_SFP_10GBASE_ER: 196 ethtool_link_ksettings_add_link_mode(ks, supported, 197 10000baseER_Full); 198 break; 199 case IONIC_XCVR_PID_SFP_10GBASE_T: 200 ethtool_link_ksettings_add_link_mode(ks, supported, 201 10000baseT_Full); 202 break; 203 case IONIC_XCVR_PID_SFP_1000BASE_T: 204 ethtool_link_ksettings_add_link_mode(ks, supported, 205 1000baseT_Full); 206 break; 207 case IONIC_XCVR_PID_UNKNOWN: 208 /* This means there's no module plugged in */ 209 break; 210 default: 211 dev_info(lif->ionic->dev, "unknown xcvr type pid=%d / 0x%x\n", 212 idev->port_info->status.xcvr.pid, 213 idev->port_info->status.xcvr.pid); 214 break; 215 } 216 217 bitmap_copy(ks->link_modes.advertising, ks->link_modes.supported, 218 __ETHTOOL_LINK_MODE_MASK_NBITS); 219 220 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER); 221 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS); 222 if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_FC) 223 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_BASER); 224 else if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_RS) 225 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS); 226 227 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE); 228 ethtool_link_ksettings_add_link_mode(ks, supported, Pause); 229 230 if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_COPPER || 231 copper_seen) 232 ks->base.port = PORT_DA; 233 else if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_FIBER) 234 ks->base.port = PORT_FIBRE; 235 else 236 ks->base.port = PORT_NONE; 237 238 if (ks->base.port != PORT_NONE) { 239 ks->base.speed = le32_to_cpu(lif->info->status.link_speed); 240 241 if (le16_to_cpu(lif->info->status.link_status)) 242 ks->base.duplex = DUPLEX_FULL; 243 else 244 ks->base.duplex = DUPLEX_UNKNOWN; 245 246 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg); 247 248 if (idev->port_info->config.an_enable) { 249 ethtool_link_ksettings_add_link_mode(ks, advertising, 250 Autoneg); 251 ks->base.autoneg = AUTONEG_ENABLE; 252 } 253 } 254 255 return 0; 256 } 257 258 static int ionic_set_link_ksettings(struct net_device *netdev, 259 const struct ethtool_link_ksettings *ks) 260 { 261 struct ionic_lif *lif = netdev_priv(netdev); 262 struct ionic_dev *idev = &lif->ionic->idev; 263 struct ionic *ionic = lif->ionic; 264 int err = 0; 265 266 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 267 return -EBUSY; 268 269 /* set autoneg */ 270 if (ks->base.autoneg != idev->port_info->config.an_enable) { 271 mutex_lock(&ionic->dev_cmd_lock); 272 ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg); 273 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 274 mutex_unlock(&ionic->dev_cmd_lock); 275 if (err) 276 return err; 277 } 278 279 /* set speed */ 280 if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) { 281 mutex_lock(&ionic->dev_cmd_lock); 282 ionic_dev_cmd_port_speed(idev, ks->base.speed); 283 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 284 mutex_unlock(&ionic->dev_cmd_lock); 285 if (err) 286 return err; 287 } 288 289 return 0; 290 } 291 292 static void ionic_get_pauseparam(struct net_device *netdev, 293 struct ethtool_pauseparam *pause) 294 { 295 struct ionic_lif *lif = netdev_priv(netdev); 296 u8 pause_type; 297 298 pause->autoneg = 0; 299 300 pause_type = lif->ionic->idev.port_info->config.pause_type; 301 if (pause_type) { 302 pause->rx_pause = (pause_type & IONIC_PAUSE_F_RX) ? 1 : 0; 303 pause->tx_pause = (pause_type & IONIC_PAUSE_F_TX) ? 1 : 0; 304 } 305 } 306 307 static int ionic_set_pauseparam(struct net_device *netdev, 308 struct ethtool_pauseparam *pause) 309 { 310 struct ionic_lif *lif = netdev_priv(netdev); 311 struct ionic *ionic = lif->ionic; 312 u32 requested_pause; 313 int err; 314 315 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 316 return -EBUSY; 317 318 if (pause->autoneg) 319 return -EOPNOTSUPP; 320 321 /* change both at the same time */ 322 requested_pause = IONIC_PORT_PAUSE_TYPE_LINK; 323 if (pause->rx_pause) 324 requested_pause |= IONIC_PAUSE_F_RX; 325 if (pause->tx_pause) 326 requested_pause |= IONIC_PAUSE_F_TX; 327 328 if (requested_pause == lif->ionic->idev.port_info->config.pause_type) 329 return 0; 330 331 mutex_lock(&ionic->dev_cmd_lock); 332 ionic_dev_cmd_port_pause(&lif->ionic->idev, requested_pause); 333 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 334 mutex_unlock(&ionic->dev_cmd_lock); 335 if (err) 336 return err; 337 338 return 0; 339 } 340 341 static int ionic_get_fecparam(struct net_device *netdev, 342 struct ethtool_fecparam *fec) 343 { 344 struct ionic_lif *lif = netdev_priv(netdev); 345 346 switch (lif->ionic->idev.port_info->config.fec_type) { 347 case IONIC_PORT_FEC_TYPE_NONE: 348 fec->active_fec = ETHTOOL_FEC_OFF; 349 break; 350 case IONIC_PORT_FEC_TYPE_RS: 351 fec->active_fec = ETHTOOL_FEC_RS; 352 break; 353 case IONIC_PORT_FEC_TYPE_FC: 354 fec->active_fec = ETHTOOL_FEC_BASER; 355 break; 356 } 357 358 fec->fec = ETHTOOL_FEC_OFF | ETHTOOL_FEC_RS | ETHTOOL_FEC_BASER; 359 360 return 0; 361 } 362 363 static int ionic_set_fecparam(struct net_device *netdev, 364 struct ethtool_fecparam *fec) 365 { 366 struct ionic_lif *lif = netdev_priv(netdev); 367 u8 fec_type; 368 int ret = 0; 369 370 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 371 return -EBUSY; 372 373 if (lif->ionic->idev.port_info->config.an_enable) { 374 netdev_err(netdev, "FEC request not allowed while autoneg is enabled\n"); 375 return -EINVAL; 376 } 377 378 switch (fec->fec) { 379 case ETHTOOL_FEC_NONE: 380 fec_type = IONIC_PORT_FEC_TYPE_NONE; 381 break; 382 case ETHTOOL_FEC_OFF: 383 fec_type = IONIC_PORT_FEC_TYPE_NONE; 384 break; 385 case ETHTOOL_FEC_RS: 386 fec_type = IONIC_PORT_FEC_TYPE_RS; 387 break; 388 case ETHTOOL_FEC_BASER: 389 fec_type = IONIC_PORT_FEC_TYPE_FC; 390 break; 391 case ETHTOOL_FEC_AUTO: 392 default: 393 netdev_err(netdev, "FEC request 0x%04x not supported\n", 394 fec->fec); 395 return -EINVAL; 396 } 397 398 if (fec_type != lif->ionic->idev.port_info->config.fec_type) { 399 mutex_lock(&lif->ionic->dev_cmd_lock); 400 ionic_dev_cmd_port_fec(&lif->ionic->idev, fec_type); 401 ret = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 402 mutex_unlock(&lif->ionic->dev_cmd_lock); 403 } 404 405 return ret; 406 } 407 408 static int ionic_get_coalesce(struct net_device *netdev, 409 struct ethtool_coalesce *coalesce, 410 struct kernel_ethtool_coalesce *kernel_coal, 411 struct netlink_ext_ack *extack) 412 { 413 struct ionic_lif *lif = netdev_priv(netdev); 414 415 coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs; 416 coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs; 417 418 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 419 coalesce->use_adaptive_tx_coalesce = test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 420 else 421 coalesce->use_adaptive_tx_coalesce = 0; 422 423 coalesce->use_adaptive_rx_coalesce = test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 424 425 return 0; 426 } 427 428 static int ionic_set_coalesce(struct net_device *netdev, 429 struct ethtool_coalesce *coalesce, 430 struct kernel_ethtool_coalesce *kernel_coal, 431 struct netlink_ext_ack *extack) 432 { 433 struct ionic_lif *lif = netdev_priv(netdev); 434 struct ionic_identity *ident; 435 u32 rx_coal, rx_dim; 436 u32 tx_coal, tx_dim; 437 unsigned int i; 438 439 ident = &lif->ionic->ident; 440 if (ident->dev.intr_coal_div == 0) { 441 netdev_warn(netdev, "bad HW value in dev.intr_coal_div = %d\n", 442 ident->dev.intr_coal_div); 443 return -EIO; 444 } 445 446 /* Tx normally shares Rx interrupt, so only change Rx if not split */ 447 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) && 448 (coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs || 449 coalesce->use_adaptive_tx_coalesce)) { 450 netdev_warn(netdev, "only rx parameters can be changed\n"); 451 return -EINVAL; 452 } 453 454 /* Convert the usec request to a HW usable value. If they asked 455 * for non-zero and it resolved to zero, bump it up 456 */ 457 rx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->rx_coalesce_usecs); 458 if (!rx_coal && coalesce->rx_coalesce_usecs) 459 rx_coal = 1; 460 tx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->tx_coalesce_usecs); 461 if (!tx_coal && coalesce->tx_coalesce_usecs) 462 tx_coal = 1; 463 464 if (rx_coal > IONIC_INTR_CTRL_COAL_MAX || 465 tx_coal > IONIC_INTR_CTRL_COAL_MAX) 466 return -ERANGE; 467 468 /* Save the new values */ 469 lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs; 470 lif->rx_coalesce_hw = rx_coal; 471 472 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 473 lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs; 474 else 475 lif->tx_coalesce_usecs = coalesce->rx_coalesce_usecs; 476 lif->tx_coalesce_hw = tx_coal; 477 478 if (coalesce->use_adaptive_rx_coalesce) { 479 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 480 rx_dim = rx_coal; 481 } else { 482 clear_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 483 rx_dim = 0; 484 } 485 486 if (coalesce->use_adaptive_tx_coalesce) { 487 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 488 tx_dim = tx_coal; 489 } else { 490 clear_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 491 tx_dim = 0; 492 } 493 494 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 495 for (i = 0; i < lif->nxqs; i++) { 496 if (lif->rxqcqs[i]->flags & IONIC_QCQ_F_INTR) { 497 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 498 lif->rxqcqs[i]->intr.index, 499 lif->rx_coalesce_hw); 500 lif->rxqcqs[i]->intr.dim_coal_hw = rx_dim; 501 } 502 503 if (lif->txqcqs[i]->flags & IONIC_QCQ_F_INTR) { 504 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 505 lif->txqcqs[i]->intr.index, 506 lif->tx_coalesce_hw); 507 lif->txqcqs[i]->intr.dim_coal_hw = tx_dim; 508 } 509 } 510 } 511 512 return 0; 513 } 514 515 static void ionic_get_ringparam(struct net_device *netdev, 516 struct ethtool_ringparam *ring) 517 { 518 struct ionic_lif *lif = netdev_priv(netdev); 519 520 ring->tx_max_pending = IONIC_MAX_TX_DESC; 521 ring->tx_pending = lif->ntxq_descs; 522 ring->rx_max_pending = IONIC_MAX_RX_DESC; 523 ring->rx_pending = lif->nrxq_descs; 524 } 525 526 static int ionic_set_ringparam(struct net_device *netdev, 527 struct ethtool_ringparam *ring) 528 { 529 struct ionic_lif *lif = netdev_priv(netdev); 530 struct ionic_queue_params qparam; 531 int err; 532 533 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 534 return -EBUSY; 535 536 ionic_init_queue_params(lif, &qparam); 537 538 if (ring->rx_mini_pending || ring->rx_jumbo_pending) { 539 netdev_info(netdev, "Changing jumbo or mini descriptors not supported\n"); 540 return -EINVAL; 541 } 542 543 if (!is_power_of_2(ring->tx_pending) || 544 !is_power_of_2(ring->rx_pending)) { 545 netdev_info(netdev, "Descriptor count must be a power of 2\n"); 546 return -EINVAL; 547 } 548 549 /* if nothing to do return success */ 550 if (ring->tx_pending == lif->ntxq_descs && 551 ring->rx_pending == lif->nrxq_descs) 552 return 0; 553 554 if (ring->tx_pending != lif->ntxq_descs) 555 netdev_info(netdev, "Changing Tx ring size from %d to %d\n", 556 lif->ntxq_descs, ring->tx_pending); 557 558 if (ring->rx_pending != lif->nrxq_descs) 559 netdev_info(netdev, "Changing Rx ring size from %d to %d\n", 560 lif->nrxq_descs, ring->rx_pending); 561 562 /* if we're not running, just set the values and return */ 563 if (!netif_running(lif->netdev)) { 564 lif->ntxq_descs = ring->tx_pending; 565 lif->nrxq_descs = ring->rx_pending; 566 return 0; 567 } 568 569 qparam.ntxq_descs = ring->tx_pending; 570 qparam.nrxq_descs = ring->rx_pending; 571 572 mutex_lock(&lif->queue_lock); 573 err = ionic_reconfigure_queues(lif, &qparam); 574 mutex_unlock(&lif->queue_lock); 575 if (err) 576 netdev_info(netdev, "Ring reconfiguration failed, changes canceled: %d\n", err); 577 578 return err; 579 } 580 581 static void ionic_get_channels(struct net_device *netdev, 582 struct ethtool_channels *ch) 583 { 584 struct ionic_lif *lif = netdev_priv(netdev); 585 586 /* report maximum channels */ 587 ch->max_combined = lif->ionic->ntxqs_per_lif; 588 ch->max_rx = lif->ionic->ntxqs_per_lif / 2; 589 ch->max_tx = lif->ionic->ntxqs_per_lif / 2; 590 591 /* report current channels */ 592 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 593 ch->rx_count = lif->nxqs; 594 ch->tx_count = lif->nxqs; 595 } else { 596 ch->combined_count = lif->nxqs; 597 } 598 } 599 600 static int ionic_set_channels(struct net_device *netdev, 601 struct ethtool_channels *ch) 602 { 603 struct ionic_lif *lif = netdev_priv(netdev); 604 struct ionic_queue_params qparam; 605 int max_cnt; 606 int err; 607 608 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 609 return -EBUSY; 610 611 ionic_init_queue_params(lif, &qparam); 612 613 if (ch->rx_count != ch->tx_count) { 614 netdev_info(netdev, "The rx and tx count must be equal\n"); 615 return -EINVAL; 616 } 617 618 if (ch->combined_count && ch->rx_count) { 619 netdev_info(netdev, "Use either combined or rx and tx, not both\n"); 620 return -EINVAL; 621 } 622 623 max_cnt = lif->ionic->ntxqs_per_lif; 624 if (ch->combined_count) { 625 if (ch->combined_count > max_cnt) 626 return -EINVAL; 627 628 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 629 netdev_info(lif->netdev, "Sharing queue interrupts\n"); 630 else if (ch->combined_count == lif->nxqs) 631 return 0; 632 633 if (lif->nxqs != ch->combined_count) 634 netdev_info(netdev, "Changing queue count from %d to %d\n", 635 lif->nxqs, ch->combined_count); 636 637 qparam.nxqs = ch->combined_count; 638 qparam.intr_split = 0; 639 } else { 640 max_cnt /= 2; 641 if (ch->rx_count > max_cnt) 642 return -EINVAL; 643 644 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 645 netdev_info(lif->netdev, "Splitting queue interrupts\n"); 646 else if (ch->rx_count == lif->nxqs) 647 return 0; 648 649 if (lif->nxqs != ch->rx_count) 650 netdev_info(netdev, "Changing queue count from %d to %d\n", 651 lif->nxqs, ch->rx_count); 652 653 qparam.nxqs = ch->rx_count; 654 qparam.intr_split = 1; 655 } 656 657 /* if we're not running, just set the values and return */ 658 if (!netif_running(lif->netdev)) { 659 lif->nxqs = qparam.nxqs; 660 661 if (qparam.intr_split) { 662 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 663 } else { 664 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 665 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 666 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 667 } 668 return 0; 669 } 670 671 mutex_lock(&lif->queue_lock); 672 err = ionic_reconfigure_queues(lif, &qparam); 673 mutex_unlock(&lif->queue_lock); 674 if (err) 675 netdev_info(netdev, "Queue reconfiguration failed, changes canceled: %d\n", err); 676 677 return err; 678 } 679 680 static int ionic_get_rxnfc(struct net_device *netdev, 681 struct ethtool_rxnfc *info, u32 *rules) 682 { 683 struct ionic_lif *lif = netdev_priv(netdev); 684 int err = 0; 685 686 switch (info->cmd) { 687 case ETHTOOL_GRXRINGS: 688 info->data = lif->nxqs; 689 break; 690 default: 691 netdev_err(netdev, "Command parameter %d is not supported\n", 692 info->cmd); 693 err = -EOPNOTSUPP; 694 } 695 696 return err; 697 } 698 699 static u32 ionic_get_rxfh_indir_size(struct net_device *netdev) 700 { 701 struct ionic_lif *lif = netdev_priv(netdev); 702 703 return le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 704 } 705 706 static u32 ionic_get_rxfh_key_size(struct net_device *netdev) 707 { 708 return IONIC_RSS_HASH_KEY_SIZE; 709 } 710 711 static int ionic_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 712 u8 *hfunc) 713 { 714 struct ionic_lif *lif = netdev_priv(netdev); 715 unsigned int i, tbl_sz; 716 717 if (indir) { 718 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 719 for (i = 0; i < tbl_sz; i++) 720 indir[i] = lif->rss_ind_tbl[i]; 721 } 722 723 if (key) 724 memcpy(key, lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 725 726 if (hfunc) 727 *hfunc = ETH_RSS_HASH_TOP; 728 729 return 0; 730 } 731 732 static int ionic_set_rxfh(struct net_device *netdev, const u32 *indir, 733 const u8 *key, const u8 hfunc) 734 { 735 struct ionic_lif *lif = netdev_priv(netdev); 736 737 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) 738 return -EOPNOTSUPP; 739 740 return ionic_lif_rss_config(lif, lif->rss_types, key, indir); 741 } 742 743 static int ionic_set_tunable(struct net_device *dev, 744 const struct ethtool_tunable *tuna, 745 const void *data) 746 { 747 struct ionic_lif *lif = netdev_priv(dev); 748 749 switch (tuna->id) { 750 case ETHTOOL_RX_COPYBREAK: 751 lif->rx_copybreak = *(u32 *)data; 752 break; 753 default: 754 return -EOPNOTSUPP; 755 } 756 757 return 0; 758 } 759 760 static int ionic_get_tunable(struct net_device *netdev, 761 const struct ethtool_tunable *tuna, void *data) 762 { 763 struct ionic_lif *lif = netdev_priv(netdev); 764 765 switch (tuna->id) { 766 case ETHTOOL_RX_COPYBREAK: 767 *(u32 *)data = lif->rx_copybreak; 768 break; 769 default: 770 return -EOPNOTSUPP; 771 } 772 773 return 0; 774 } 775 776 static int ionic_get_module_info(struct net_device *netdev, 777 struct ethtool_modinfo *modinfo) 778 779 { 780 struct ionic_lif *lif = netdev_priv(netdev); 781 struct ionic_dev *idev = &lif->ionic->idev; 782 struct ionic_xcvr_status *xcvr; 783 struct sfp_eeprom_base *sfp; 784 785 xcvr = &idev->port_info->status.xcvr; 786 sfp = (struct sfp_eeprom_base *) xcvr->sprom; 787 788 /* report the module data type and length */ 789 switch (sfp->phys_id) { 790 case SFF8024_ID_SFP: 791 modinfo->type = ETH_MODULE_SFF_8079; 792 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 793 break; 794 case SFF8024_ID_QSFP_8436_8636: 795 case SFF8024_ID_QSFP28_8636: 796 modinfo->type = ETH_MODULE_SFF_8436; 797 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 798 break; 799 default: 800 netdev_info(netdev, "unknown xcvr type 0x%02x\n", 801 xcvr->sprom[0]); 802 modinfo->type = 0; 803 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 804 break; 805 } 806 807 return 0; 808 } 809 810 static int ionic_get_module_eeprom(struct net_device *netdev, 811 struct ethtool_eeprom *ee, 812 u8 *data) 813 { 814 struct ionic_lif *lif = netdev_priv(netdev); 815 struct ionic_dev *idev = &lif->ionic->idev; 816 struct ionic_xcvr_status *xcvr; 817 char tbuf[sizeof(xcvr->sprom)]; 818 int count = 10; 819 u32 len; 820 821 /* The NIC keeps the module prom up-to-date in the DMA space 822 * so we can simply copy the module bytes into the data buffer. 823 */ 824 xcvr = &idev->port_info->status.xcvr; 825 len = min_t(u32, sizeof(xcvr->sprom), ee->len); 826 827 do { 828 memcpy(data, xcvr->sprom, len); 829 memcpy(tbuf, xcvr->sprom, len); 830 831 /* Let's make sure we got a consistent copy */ 832 if (!memcmp(data, tbuf, len)) 833 break; 834 835 } while (--count); 836 837 if (!count) 838 return -ETIMEDOUT; 839 840 return 0; 841 } 842 843 static int ionic_get_ts_info(struct net_device *netdev, 844 struct ethtool_ts_info *info) 845 { 846 struct ionic_lif *lif = netdev_priv(netdev); 847 struct ionic *ionic = lif->ionic; 848 __le64 mask; 849 850 if (!lif->phc || !lif->phc->ptp) 851 return ethtool_op_get_ts_info(netdev, info); 852 853 info->phc_index = ptp_clock_index(lif->phc->ptp); 854 855 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 856 SOF_TIMESTAMPING_RX_SOFTWARE | 857 SOF_TIMESTAMPING_SOFTWARE | 858 SOF_TIMESTAMPING_TX_HARDWARE | 859 SOF_TIMESTAMPING_RX_HARDWARE | 860 SOF_TIMESTAMPING_RAW_HARDWARE; 861 862 /* tx modes */ 863 864 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 865 BIT(HWTSTAMP_TX_ON); 866 867 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_SYNC)); 868 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 869 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC); 870 871 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_P2P)); 872 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 873 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_P2P); 874 875 /* rx filters */ 876 877 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 878 BIT(HWTSTAMP_FILTER_ALL); 879 880 mask = cpu_to_le64(IONIC_PKT_CLS_NTP_ALL); 881 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 882 info->rx_filters |= BIT(HWTSTAMP_FILTER_NTP_ALL); 883 884 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_SYNC); 885 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 886 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC); 887 888 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_DREQ); 889 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 890 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 891 892 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_ALL); 893 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 894 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 895 896 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_SYNC); 897 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 898 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC); 899 900 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_DREQ); 901 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 902 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); 903 904 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_ALL); 905 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 906 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 907 908 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_SYNC); 909 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 910 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC); 911 912 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_DREQ); 913 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 914 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); 915 916 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_ALL); 917 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 918 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT); 919 920 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_SYNC); 921 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 922 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_SYNC); 923 924 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_DREQ); 925 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 926 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 927 928 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_ALL); 929 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 930 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 931 932 return 0; 933 } 934 935 static int ionic_nway_reset(struct net_device *netdev) 936 { 937 struct ionic_lif *lif = netdev_priv(netdev); 938 struct ionic *ionic = lif->ionic; 939 int err = 0; 940 941 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 942 return -EBUSY; 943 944 /* flap the link to force auto-negotiation */ 945 946 mutex_lock(&ionic->dev_cmd_lock); 947 948 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_DOWN); 949 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 950 951 if (!err) { 952 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 953 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 954 } 955 956 mutex_unlock(&ionic->dev_cmd_lock); 957 958 return err; 959 } 960 961 static const struct ethtool_ops ionic_ethtool_ops = { 962 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 963 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 964 ETHTOOL_COALESCE_USE_ADAPTIVE_TX, 965 .get_drvinfo = ionic_get_drvinfo, 966 .get_regs_len = ionic_get_regs_len, 967 .get_regs = ionic_get_regs, 968 .get_link = ethtool_op_get_link, 969 .get_link_ksettings = ionic_get_link_ksettings, 970 .set_link_ksettings = ionic_set_link_ksettings, 971 .get_coalesce = ionic_get_coalesce, 972 .set_coalesce = ionic_set_coalesce, 973 .get_ringparam = ionic_get_ringparam, 974 .set_ringparam = ionic_set_ringparam, 975 .get_channels = ionic_get_channels, 976 .set_channels = ionic_set_channels, 977 .get_strings = ionic_get_strings, 978 .get_ethtool_stats = ionic_get_stats, 979 .get_sset_count = ionic_get_sset_count, 980 .get_rxnfc = ionic_get_rxnfc, 981 .get_rxfh_indir_size = ionic_get_rxfh_indir_size, 982 .get_rxfh_key_size = ionic_get_rxfh_key_size, 983 .get_rxfh = ionic_get_rxfh, 984 .set_rxfh = ionic_set_rxfh, 985 .get_tunable = ionic_get_tunable, 986 .set_tunable = ionic_set_tunable, 987 .get_module_info = ionic_get_module_info, 988 .get_module_eeprom = ionic_get_module_eeprom, 989 .get_pauseparam = ionic_get_pauseparam, 990 .set_pauseparam = ionic_set_pauseparam, 991 .get_fecparam = ionic_get_fecparam, 992 .set_fecparam = ionic_set_fecparam, 993 .get_ts_info = ionic_get_ts_info, 994 .nway_reset = ionic_nway_reset, 995 }; 996 997 void ionic_ethtool_set_ops(struct net_device *netdev) 998 { 999 netdev->ethtool_ops = &ionic_ethtool_ops; 1000 } 1001