1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/mlx5/driver.h>
34 #include <linux/mlx5/eswitch.h>
35 #include "mlx5_core.h"
36 #include "../../mlxfw/mlxfw.h"
37 #include "lib/tout.h"
38
39 enum {
40 MCQS_IDENTIFIER_BOOT_IMG = 0x1,
41 MCQS_IDENTIFIER_OEM_NVCONFIG = 0x4,
42 MCQS_IDENTIFIER_MLNX_NVCONFIG = 0x5,
43 MCQS_IDENTIFIER_CS_TOKEN = 0x6,
44 MCQS_IDENTIFIER_DBG_TOKEN = 0x7,
45 MCQS_IDENTIFIER_GEARBOX = 0xA,
46 };
47
48 enum {
49 MCQS_UPDATE_STATE_IDLE,
50 MCQS_UPDATE_STATE_IN_PROGRESS,
51 MCQS_UPDATE_STATE_APPLIED,
52 MCQS_UPDATE_STATE_ACTIVE,
53 MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET,
54 MCQS_UPDATE_STATE_FAILED,
55 MCQS_UPDATE_STATE_CANCELED,
56 MCQS_UPDATE_STATE_BUSY,
57 };
58
59 enum {
60 MCQI_INFO_TYPE_CAPABILITIES = 0x0,
61 MCQI_INFO_TYPE_VERSION = 0x1,
62 MCQI_INFO_TYPE_ACTIVATION_METHOD = 0x5,
63 };
64
65 enum {
66 MCQI_FW_RUNNING_VERSION = 0,
67 MCQI_FW_STORED_VERSION = 1,
68 };
69
mlx5_query_board_id(struct mlx5_core_dev * dev)70 int mlx5_query_board_id(struct mlx5_core_dev *dev)
71 {
72 u32 *out;
73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
75 int err;
76
77 out = kzalloc(outlen, GFP_KERNEL);
78 if (!out)
79 return -ENOMEM;
80
81 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
82 err = mlx5_cmd_exec_inout(dev, query_adapter, in, out);
83 if (err)
84 goto out;
85
86 memcpy(dev->board_id,
87 MLX5_ADDR_OF(query_adapter_out, out,
88 query_adapter_struct.vsd_contd_psid),
89 MLX5_FLD_SZ_BYTES(query_adapter_out,
90 query_adapter_struct.vsd_contd_psid));
91
92 out:
93 kfree(out);
94 return err;
95 }
96
mlx5_core_query_vendor_id(struct mlx5_core_dev * mdev,u32 * vendor_id)97 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
98 {
99 u32 *out;
100 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
101 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
102 int err;
103
104 out = kzalloc(outlen, GFP_KERNEL);
105 if (!out)
106 return -ENOMEM;
107
108 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
109 err = mlx5_cmd_exec_inout(mdev, query_adapter, in, out);
110 if (err)
111 goto out;
112
113 *vendor_id = MLX5_GET(query_adapter_out, out,
114 query_adapter_struct.ieee_vendor_id);
115 out:
116 kfree(out);
117 return err;
118 }
119 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
120
mlx5_get_pcam_reg(struct mlx5_core_dev * dev)121 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
122 {
123 return mlx5_query_pcam_reg(dev, dev->caps.pcam,
124 MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
125 MLX5_PCAM_REGS_5000_TO_507F);
126 }
127
mlx5_get_mcam_access_reg_group(struct mlx5_core_dev * dev,enum mlx5_mcam_reg_groups group)128 static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
129 enum mlx5_mcam_reg_groups group)
130 {
131 return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
132 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
133 }
134
mlx5_get_qcam_reg(struct mlx5_core_dev * dev)135 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
136 {
137 return mlx5_query_qcam_reg(dev, dev->caps.qcam,
138 MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
139 MLX5_QCAM_REGS_FIRST_128);
140 }
141
mlx5_query_hca_caps(struct mlx5_core_dev * dev)142 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
143 {
144 int err;
145
146 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
147 if (err)
148 return err;
149
150 if (MLX5_CAP_GEN(dev, port_selection_cap)) {
151 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_PORT_SELECTION, HCA_CAP_OPMOD_GET_CUR);
152 if (err)
153 return err;
154 }
155
156 if (MLX5_CAP_GEN(dev, hca_cap_2)) {
157 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_GENERAL_2, HCA_CAP_OPMOD_GET_CUR);
158 if (err)
159 return err;
160 }
161
162 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
163 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
164 HCA_CAP_OPMOD_GET_CUR);
165 if (err)
166 return err;
167 }
168
169 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
170 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
171 HCA_CAP_OPMOD_GET_CUR);
172 if (err)
173 return err;
174 }
175
176 if (MLX5_CAP_GEN(dev, pg)) {
177 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ODP, HCA_CAP_OPMOD_GET_CUR);
178 if (err)
179 return err;
180 }
181
182 if (MLX5_CAP_GEN(dev, atomic)) {
183 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ATOMIC, HCA_CAP_OPMOD_GET_CUR);
184 if (err)
185 return err;
186 }
187
188 if (MLX5_CAP_GEN(dev, roce)) {
189 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ROCE, HCA_CAP_OPMOD_GET_CUR);
190 if (err)
191 return err;
192 }
193
194 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
195 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
196 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, HCA_CAP_OPMOD_GET_CUR);
197 if (err)
198 return err;
199 }
200
201 if (MLX5_ESWITCH_MANAGER(dev)) {
202 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ESWITCH_FLOW_TABLE,
203 HCA_CAP_OPMOD_GET_CUR);
204 if (err)
205 return err;
206
207 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ESWITCH, HCA_CAP_OPMOD_GET_CUR);
208 if (err)
209 return err;
210 }
211
212 if (MLX5_CAP_GEN(dev, qos)) {
213 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_QOS, HCA_CAP_OPMOD_GET_CUR);
214 if (err)
215 return err;
216 }
217
218 if (MLX5_CAP_GEN(dev, debug))
219 mlx5_core_get_caps_mode(dev, MLX5_CAP_DEBUG, HCA_CAP_OPMOD_GET_CUR);
220
221 if (MLX5_CAP_GEN(dev, pcam_reg))
222 mlx5_get_pcam_reg(dev);
223
224 if (MLX5_CAP_GEN(dev, mcam_reg)) {
225 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
226 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
227 }
228
229 if (MLX5_CAP_GEN(dev, qcam_reg))
230 mlx5_get_qcam_reg(dev);
231
232 if (MLX5_CAP_GEN(dev, device_memory)) {
233 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_DEV_MEM, HCA_CAP_OPMOD_GET_CUR);
234 if (err)
235 return err;
236 }
237
238 if (MLX5_CAP_GEN(dev, event_cap)) {
239 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_DEV_EVENT, HCA_CAP_OPMOD_GET_CUR);
240 if (err)
241 return err;
242 }
243
244 if (MLX5_CAP_GEN(dev, tls_tx) || MLX5_CAP_GEN(dev, tls_rx)) {
245 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_TLS, HCA_CAP_OPMOD_GET_CUR);
246 if (err)
247 return err;
248 }
249
250 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
251 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
252 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, HCA_CAP_OPMOD_GET_CUR);
253 if (err)
254 return err;
255 }
256
257 if (MLX5_CAP_GEN(dev, ipsec_offload)) {
258 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_IPSEC, HCA_CAP_OPMOD_GET_CUR);
259 if (err)
260 return err;
261 }
262
263 if (MLX5_CAP_GEN(dev, crypto)) {
264 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_CRYPTO, HCA_CAP_OPMOD_GET_CUR);
265 if (err)
266 return err;
267 }
268
269 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
270 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD) {
271 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_MACSEC, HCA_CAP_OPMOD_GET_CUR);
272 if (err)
273 return err;
274 }
275
276 if (MLX5_CAP_GEN(dev, adv_virtualization)) {
277 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ADV_VIRTUALIZATION,
278 HCA_CAP_OPMOD_GET_CUR);
279 if (err)
280 return err;
281 }
282
283 return 0;
284 }
285
mlx5_cmd_init_hca(struct mlx5_core_dev * dev,uint32_t * sw_owner_id)286 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
287 {
288 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {};
289 int i;
290
291 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
292
293 if (MLX5_CAP_GEN(dev, sw_owner_id)) {
294 for (i = 0; i < 4; i++)
295 MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
296 sw_owner_id[i]);
297 }
298
299 if (MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) &&
300 dev->priv.sw_vhca_id > 0)
301 MLX5_SET(init_hca_in, in, sw_vhca_id, dev->priv.sw_vhca_id);
302
303 return mlx5_cmd_exec_in(dev, init_hca, in);
304 }
305
mlx5_cmd_teardown_hca(struct mlx5_core_dev * dev)306 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
307 {
308 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
309
310 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
311 return mlx5_cmd_exec_in(dev, teardown_hca, in);
312 }
313
mlx5_cmd_force_teardown_hca(struct mlx5_core_dev * dev)314 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
315 {
316 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
317 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
318 int force_state;
319 int ret;
320
321 if (!MLX5_CAP_GEN(dev, force_teardown)) {
322 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
323 return -EOPNOTSUPP;
324 }
325
326 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
327 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
328
329 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
330 if (ret)
331 return ret;
332
333 force_state = MLX5_GET(teardown_hca_out, out, state);
334 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
335 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
336 return -EIO;
337 }
338
339 return 0;
340 }
341
mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev * dev)342 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
343 {
344 unsigned long end, delay_ms = mlx5_tout_ms(dev, TEARDOWN);
345 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
346 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
347 int state;
348 int ret;
349
350 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
351 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
352 return -EOPNOTSUPP;
353 }
354
355 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
356 MLX5_SET(teardown_hca_in, in, profile,
357 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
358
359 ret = mlx5_cmd_exec_inout(dev, teardown_hca, in, out);
360 if (ret)
361 return ret;
362
363 state = MLX5_GET(teardown_hca_out, out, state);
364 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
365 mlx5_core_warn(dev, "teardown with fast mode failed\n");
366 return -EIO;
367 }
368
369 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
370
371 /* Loop until device state turns to disable */
372 end = jiffies + msecs_to_jiffies(delay_ms);
373 do {
374 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
375 break;
376 if (pci_channel_offline(dev->pdev)) {
377 mlx5_core_err(dev, "PCI channel offline, stop waiting for NIC IFC\n");
378 return -EACCES;
379 }
380
381 cond_resched();
382 } while (!time_after(jiffies, end));
383
384 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
385 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
386 mlx5_get_nic_state(dev), delay_ms);
387 return -EIO;
388 }
389
390 return 0;
391 }
392
393 enum mlxsw_reg_mcc_instruction {
394 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
395 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
396 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
397 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
398 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
399 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
400 };
401
mlx5_reg_mcc_set(struct mlx5_core_dev * dev,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)402 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
403 enum mlxsw_reg_mcc_instruction instr,
404 u16 component_index, u32 update_handle,
405 u32 component_size)
406 {
407 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
408 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
409
410 memset(in, 0, sizeof(in));
411
412 MLX5_SET(mcc_reg, in, instruction, instr);
413 MLX5_SET(mcc_reg, in, component_index, component_index);
414 MLX5_SET(mcc_reg, in, update_handle, update_handle);
415 MLX5_SET(mcc_reg, in, component_size, component_size);
416
417 return mlx5_core_access_reg(dev, in, sizeof(in), out,
418 sizeof(out), MLX5_REG_MCC, 0, 1);
419 }
420
mlx5_reg_mcc_query(struct mlx5_core_dev * dev,u32 * update_handle,u8 * error_code,u8 * control_state)421 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
422 u32 *update_handle, u8 *error_code,
423 u8 *control_state)
424 {
425 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
426 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
427 int err;
428
429 memset(in, 0, sizeof(in));
430 memset(out, 0, sizeof(out));
431 MLX5_SET(mcc_reg, in, update_handle, *update_handle);
432
433 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
434 sizeof(out), MLX5_REG_MCC, 0, 0);
435 if (err)
436 goto out;
437
438 *update_handle = MLX5_GET(mcc_reg, out, update_handle);
439 *error_code = MLX5_GET(mcc_reg, out, error_code);
440 *control_state = MLX5_GET(mcc_reg, out, control_state);
441
442 out:
443 return err;
444 }
445
mlx5_reg_mcda_set(struct mlx5_core_dev * dev,u32 update_handle,u32 offset,u16 size,u8 * data)446 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
447 u32 update_handle,
448 u32 offset, u16 size,
449 u8 *data)
450 {
451 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
452 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
453 int i, j, dw_size = size >> 2;
454 __be32 data_element;
455 u32 *in;
456
457 in = kzalloc(in_size, GFP_KERNEL);
458 if (!in)
459 return -ENOMEM;
460
461 MLX5_SET(mcda_reg, in, update_handle, update_handle);
462 MLX5_SET(mcda_reg, in, offset, offset);
463 MLX5_SET(mcda_reg, in, size, size);
464
465 for (i = 0; i < dw_size; i++) {
466 j = i * 4;
467 data_element = htonl(*(u32 *)&data[j]);
468 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
469 }
470
471 err = mlx5_core_access_reg(dev, in, in_size, out,
472 sizeof(out), MLX5_REG_MCDA, 0, 1);
473 kfree(in);
474 return err;
475 }
476
mlx5_reg_mcqi_query(struct mlx5_core_dev * dev,u16 component_index,bool read_pending,u8 info_type,u16 data_size,void * mcqi_data)477 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
478 u16 component_index, bool read_pending,
479 u8 info_type, u16 data_size, void *mcqi_data)
480 {
481 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {};
482 u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {};
483 void *data;
484 int err;
485
486 MLX5_SET(mcqi_reg, in, component_index, component_index);
487 MLX5_SET(mcqi_reg, in, read_pending_component, read_pending);
488 MLX5_SET(mcqi_reg, in, info_type, info_type);
489 MLX5_SET(mcqi_reg, in, data_size, data_size);
490
491 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
492 MLX5_ST_SZ_BYTES(mcqi_reg) + data_size,
493 MLX5_REG_MCQI, 0, 0);
494 if (err)
495 return err;
496
497 data = MLX5_ADDR_OF(mcqi_reg, out, data);
498 memcpy(mcqi_data, data, data_size);
499
500 return 0;
501 }
502
mlx5_reg_mcqi_caps_query(struct mlx5_core_dev * dev,u16 component_index,u32 * max_component_size,u8 * log_mcda_word_size,u16 * mcda_max_write_size)503 static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index,
504 u32 *max_component_size, u8 *log_mcda_word_size,
505 u16 *mcda_max_write_size)
506 {
507 u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {};
508 int err;
509
510 err = mlx5_reg_mcqi_query(dev, component_index, 0,
511 MCQI_INFO_TYPE_CAPABILITIES,
512 MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg);
513 if (err)
514 return err;
515
516 *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size);
517 *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size);
518 *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size);
519
520 return 0;
521 }
522
523 struct mlx5_mlxfw_dev {
524 struct mlxfw_dev mlxfw_dev;
525 struct mlx5_core_dev *mlx5_core_dev;
526 };
527
mlx5_component_query(struct mlxfw_dev * mlxfw_dev,u16 component_index,u32 * p_max_size,u8 * p_align_bits,u16 * p_max_write_size)528 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
529 u16 component_index, u32 *p_max_size,
530 u8 *p_align_bits, u16 *p_max_write_size)
531 {
532 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
533 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
534 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
535
536 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) {
537 mlx5_core_warn(dev, "caps query isn't supported by running FW\n");
538 return -EOPNOTSUPP;
539 }
540
541 return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size,
542 p_align_bits, p_max_write_size);
543 }
544
mlx5_fsm_lock(struct mlxfw_dev * mlxfw_dev,u32 * fwhandle)545 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
546 {
547 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
548 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
549 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
550 u8 control_state, error_code;
551 int err;
552
553 *fwhandle = 0;
554 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
555 if (err)
556 return err;
557
558 if (control_state != MLXFW_FSM_STATE_IDLE)
559 return -EBUSY;
560
561 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
562 0, *fwhandle, 0);
563 }
564
mlx5_fsm_component_update(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index,u32 component_size)565 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
566 u16 component_index, u32 component_size)
567 {
568 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
569 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
570 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
571
572 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
573 component_index, fwhandle, component_size);
574 }
575
mlx5_fsm_block_download(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u8 * data,u16 size,u32 offset)576 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
577 u8 *data, u16 size, u32 offset)
578 {
579 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
580 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
581 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
582
583 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
584 }
585
mlx5_fsm_component_verify(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index)586 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
587 u16 component_index)
588 {
589 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
590 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
591 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
592
593 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
594 component_index, fwhandle, 0);
595 }
596
mlx5_fsm_activate(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)597 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
598 {
599 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
600 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
601 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
602
603 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
604 fwhandle, 0);
605 }
606
mlx5_fsm_query_state(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,enum mlxfw_fsm_state * fsm_state,enum mlxfw_fsm_state_err * fsm_state_err)607 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
608 enum mlxfw_fsm_state *fsm_state,
609 enum mlxfw_fsm_state_err *fsm_state_err)
610 {
611 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
612 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
613 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
614 u8 control_state, error_code;
615 int err;
616
617 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
618 if (err)
619 return err;
620
621 *fsm_state = control_state;
622 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
623 MLXFW_FSM_STATE_ERR_MAX);
624 return 0;
625 }
626
mlx5_fsm_cancel(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)627 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
628 {
629 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
630 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
631 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
632
633 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
634 }
635
mlx5_fsm_release(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)636 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
637 {
638 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
639 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
640 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
641
642 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
643 fwhandle, 0);
644 }
645
mlx5_fsm_reactivate(struct mlxfw_dev * mlxfw_dev,u8 * status)646 static int mlx5_fsm_reactivate(struct mlxfw_dev *mlxfw_dev, u8 *status)
647 {
648 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
649 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
650 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
651 u32 out[MLX5_ST_SZ_DW(mirc_reg)];
652 u32 in[MLX5_ST_SZ_DW(mirc_reg)];
653 unsigned long exp_time;
654 int err;
655
656 exp_time = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, FSM_REACTIVATE));
657
658 if (!MLX5_CAP_MCAM_REG2(dev, mirc))
659 return -EOPNOTSUPP;
660
661 memset(in, 0, sizeof(in));
662
663 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
664 sizeof(out), MLX5_REG_MIRC, 0, 1);
665 if (err)
666 return err;
667
668 do {
669 memset(out, 0, sizeof(out));
670 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
671 sizeof(out), MLX5_REG_MIRC, 0, 0);
672 if (err)
673 return err;
674
675 *status = MLX5_GET(mirc_reg, out, status_code);
676 if (*status != MLXFW_FSM_REACTIVATE_STATUS_BUSY)
677 return 0;
678
679 msleep(20);
680 } while (time_before(jiffies, exp_time));
681
682 return 0;
683 }
684
685 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
686 .component_query = mlx5_component_query,
687 .fsm_lock = mlx5_fsm_lock,
688 .fsm_component_update = mlx5_fsm_component_update,
689 .fsm_block_download = mlx5_fsm_block_download,
690 .fsm_component_verify = mlx5_fsm_component_verify,
691 .fsm_activate = mlx5_fsm_activate,
692 .fsm_reactivate = mlx5_fsm_reactivate,
693 .fsm_query_state = mlx5_fsm_query_state,
694 .fsm_cancel = mlx5_fsm_cancel,
695 .fsm_release = mlx5_fsm_release
696 };
697
mlx5_firmware_flash(struct mlx5_core_dev * dev,const struct firmware * firmware,struct netlink_ext_ack * extack)698 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
699 const struct firmware *firmware,
700 struct netlink_ext_ack *extack)
701 {
702 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
703 .mlxfw_dev = {
704 .ops = &mlx5_mlxfw_dev_ops,
705 .psid = dev->board_id,
706 .psid_size = strlen(dev->board_id),
707 .devlink = priv_to_devlink(dev),
708 },
709 .mlx5_core_dev = dev
710 };
711
712 if (!MLX5_CAP_GEN(dev, mcam_reg) ||
713 !MLX5_CAP_MCAM_REG(dev, mcqi) ||
714 !MLX5_CAP_MCAM_REG(dev, mcc) ||
715 !MLX5_CAP_MCAM_REG(dev, mcda)) {
716 pr_info("%s flashing isn't supported by the running FW\n", __func__);
717 return -EOPNOTSUPP;
718 }
719
720 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev,
721 firmware, extack);
722 }
723
mlx5_reg_mcqi_version_query(struct mlx5_core_dev * dev,u16 component_index,bool read_pending,u32 * mcqi_version_out)724 static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev,
725 u16 component_index, bool read_pending,
726 u32 *mcqi_version_out)
727 {
728 return mlx5_reg_mcqi_query(dev, component_index, read_pending,
729 MCQI_INFO_TYPE_VERSION,
730 MLX5_ST_SZ_BYTES(mcqi_version),
731 mcqi_version_out);
732 }
733
mlx5_reg_mcqs_query(struct mlx5_core_dev * dev,u32 * out,u16 component_index)734 static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out,
735 u16 component_index)
736 {
737 u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg);
738 u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {};
739 int err;
740
741 memset(out, 0, out_sz);
742
743 MLX5_SET(mcqs_reg, in, component_index, component_index);
744
745 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
746 out_sz, MLX5_REG_MCQS, 0, 0);
747 return err;
748 }
749
750 /* scans component index sequentially, to find the boot img index */
mlx5_get_boot_img_component_index(struct mlx5_core_dev * dev)751 static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev)
752 {
753 u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {};
754 u16 identifier, component_idx = 0;
755 bool quit;
756 int err;
757
758 do {
759 err = mlx5_reg_mcqs_query(dev, out, component_idx);
760 if (err)
761 return err;
762
763 identifier = MLX5_GET(mcqs_reg, out, identifier);
764 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag);
765 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG;
766 } while (!quit && ++component_idx);
767
768 if (identifier != MCQS_IDENTIFIER_BOOT_IMG) {
769 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n",
770 component_idx);
771 return -EOPNOTSUPP;
772 }
773
774 return component_idx;
775 }
776
777 static int
mlx5_fw_image_pending(struct mlx5_core_dev * dev,int component_index,bool * pending_version_exists)778 mlx5_fw_image_pending(struct mlx5_core_dev *dev,
779 int component_index,
780 bool *pending_version_exists)
781 {
782 u32 out[MLX5_ST_SZ_DW(mcqs_reg)];
783 u8 component_update_state;
784 int err;
785
786 err = mlx5_reg_mcqs_query(dev, out, component_index);
787 if (err)
788 return err;
789
790 component_update_state = MLX5_GET(mcqs_reg, out, component_update_state);
791
792 if (component_update_state == MCQS_UPDATE_STATE_IDLE) {
793 *pending_version_exists = false;
794 } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) {
795 *pending_version_exists = true;
796 } else {
797 mlx5_core_warn(dev,
798 "mcqs: can't read pending fw version while fw state is %d\n",
799 component_update_state);
800 return -ENODATA;
801 }
802 return 0;
803 }
804
mlx5_fw_version_query(struct mlx5_core_dev * dev,u32 * running_ver,u32 * pending_ver)805 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
806 u32 *running_ver, u32 *pending_ver)
807 {
808 u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {};
809 bool pending_version_exists;
810 int component_index;
811 int err;
812
813 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) ||
814 !MLX5_CAP_MCAM_REG(dev, mcqs)) {
815 mlx5_core_warn(dev, "fw query isn't supported by the FW\n");
816 return -EOPNOTSUPP;
817 }
818
819 component_index = mlx5_get_boot_img_component_index(dev);
820 if (component_index < 0)
821 return component_index;
822
823 err = mlx5_reg_mcqi_version_query(dev, component_index,
824 MCQI_FW_RUNNING_VERSION,
825 reg_mcqi_version);
826 if (err)
827 return err;
828
829 *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
830
831 err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists);
832 if (err)
833 return err;
834
835 if (!pending_version_exists) {
836 *pending_ver = 0;
837 return 0;
838 }
839
840 err = mlx5_reg_mcqi_version_query(dev, component_index,
841 MCQI_FW_STORED_VERSION,
842 reg_mcqi_version);
843 if (err)
844 return err;
845
846 *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
847
848 return 0;
849 }
850