1 /*******************************************************************************
2 
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2013 Intel Corporation.
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #include "ixgbe.h"
30 #include "ixgbe_type.h"
31 #include "ixgbe_dcb.h"
32 #include "ixgbe_dcb_82599.h"
33 
34 /**
35  * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
36  * @hw: pointer to hardware structure
37  * @refill: refill credits index by traffic class
38  * @max: max credits index by traffic class
39  * @bwg_id: bandwidth grouping indexed by traffic class
40  * @prio_type: priority type indexed by traffic class
41  *
42  * Configure Rx Packet Arbiter and credits for each traffic class.
43  */
44 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
45 				      u16 *refill,
46 				      u16 *max,
47 				      u8 *bwg_id,
48 				      u8 *prio_type,
49 				      u8 *prio_tc)
50 {
51 	u32    reg           = 0;
52 	u32    credit_refill = 0;
53 	u32    credit_max    = 0;
54 	u8     i             = 0;
55 
56 	/*
57 	 * Disable the arbiter before changing parameters
58 	 * (always enable recycle mode; WSP)
59 	 */
60 	reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
61 	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
62 
63 	/* Map all traffic classes to their UP */
64 	reg = 0;
65 	for (i = 0; i < MAX_USER_PRIORITY; i++)
66 		reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
67 	IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
68 
69 	/* Configure traffic class credits and priority */
70 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
71 		credit_refill = refill[i];
72 		credit_max    = max[i];
73 		reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
74 
75 		reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
76 
77 		if (prio_type[i] == prio_link)
78 			reg |= IXGBE_RTRPT4C_LSP;
79 
80 		IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
81 	}
82 
83 	/*
84 	 * Configure Rx packet plane (recycle mode; WSP) and
85 	 * enable arbiter
86 	 */
87 	reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
88 	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
89 
90 	return 0;
91 }
92 
93 /**
94  * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
95  * @hw: pointer to hardware structure
96  * @refill: refill credits index by traffic class
97  * @max: max credits index by traffic class
98  * @bwg_id: bandwidth grouping indexed by traffic class
99  * @prio_type: priority type indexed by traffic class
100  *
101  * Configure Tx Descriptor Arbiter and credits for each traffic class.
102  */
103 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
104 					   u16 *refill,
105 					   u16 *max,
106 					   u8 *bwg_id,
107 					   u8 *prio_type)
108 {
109 	u32    reg, max_credits;
110 	u8     i;
111 
112 	/* Clear the per-Tx queue credits; we use per-TC instead */
113 	for (i = 0; i < 128; i++) {
114 		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
115 		IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
116 	}
117 
118 	/* Configure traffic class credits and priority */
119 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
120 		max_credits = max[i];
121 		reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
122 		reg |= refill[i];
123 		reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
124 
125 		if (prio_type[i] == prio_group)
126 			reg |= IXGBE_RTTDT2C_GSP;
127 
128 		if (prio_type[i] == prio_link)
129 			reg |= IXGBE_RTTDT2C_LSP;
130 
131 		IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
132 	}
133 
134 	/*
135 	 * Configure Tx descriptor plane (recycle mode; WSP) and
136 	 * enable arbiter
137 	 */
138 	reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
139 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
140 
141 	return 0;
142 }
143 
144 /**
145  * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
146  * @hw: pointer to hardware structure
147  * @refill: refill credits index by traffic class
148  * @max: max credits index by traffic class
149  * @bwg_id: bandwidth grouping indexed by traffic class
150  * @prio_type: priority type indexed by traffic class
151  *
152  * Configure Tx Packet Arbiter and credits for each traffic class.
153  */
154 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
155 					   u16 *refill,
156 					   u16 *max,
157 					   u8 *bwg_id,
158 					   u8 *prio_type,
159 					   u8 *prio_tc)
160 {
161 	u32 reg;
162 	u8 i;
163 
164 	/*
165 	 * Disable the arbiter before changing parameters
166 	 * (always enable recycle mode; SP; arb delay)
167 	 */
168 	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
169 	      (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
170 	      IXGBE_RTTPCS_ARBDIS;
171 	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
172 
173 	/* Map all traffic classes to their UP */
174 	reg = 0;
175 	for (i = 0; i < MAX_USER_PRIORITY; i++)
176 		reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
177 	IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
178 
179 	/* Configure traffic class credits and priority */
180 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
181 		reg = refill[i];
182 		reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
183 		reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
184 
185 		if (prio_type[i] == prio_group)
186 			reg |= IXGBE_RTTPT2C_GSP;
187 
188 		if (prio_type[i] == prio_link)
189 			reg |= IXGBE_RTTPT2C_LSP;
190 
191 		IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
192 	}
193 
194 	/*
195 	 * Configure Tx packet plane (recycle mode; SP; arb delay) and
196 	 * enable arbiter
197 	 */
198 	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
199 	      (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
200 	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
201 
202 	return 0;
203 }
204 
205 /**
206  * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
207  * @hw: pointer to hardware structure
208  * @pfc_en: enabled pfc bitmask
209  * @prio_tc: priority to tc assignments indexed by priority
210  *
211  * Configure Priority Flow Control (PFC) for each traffic class.
212  */
213 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
214 {
215 	u32 i, j, fcrtl, reg;
216 	u8 max_tc = 0;
217 
218 	/* Enable Transmit Priority Flow Control */
219 	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
220 
221 	/* Enable Receive Priority Flow Control */
222 	reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
223 	reg |= IXGBE_MFLCN_DPF;
224 
225 	/*
226 	 * X540 supports per TC Rx priority flow control.  So
227 	 * clear all TCs and only enable those that should be
228 	 * enabled.
229 	 */
230 	reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
231 
232 	if (hw->mac.type == ixgbe_mac_X540)
233 		reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
234 
235 	if (pfc_en)
236 		reg |= IXGBE_MFLCN_RPFCE;
237 
238 	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
239 
240 	for (i = 0; i < MAX_USER_PRIORITY; i++) {
241 		if (prio_tc[i] > max_tc)
242 			max_tc = prio_tc[i];
243 	}
244 
245 
246 	/* Configure PFC Tx thresholds per TC */
247 	for (i = 0; i <= max_tc; i++) {
248 		int enabled = 0;
249 
250 		for (j = 0; j < MAX_USER_PRIORITY; j++) {
251 			if ((prio_tc[j] == i) && (pfc_en & (1 << j))) {
252 				enabled = 1;
253 				break;
254 			}
255 		}
256 
257 		if (enabled) {
258 			reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
259 			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
260 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
261 		} else {
262 			reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
263 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
264 		}
265 
266 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
267 	}
268 
269 	for (; i < MAX_TRAFFIC_CLASS; i++) {
270 		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
271 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
272 	}
273 
274 	/* Configure pause time (2 TCs per register) */
275 	reg = hw->fc.pause_time * 0x00010001;
276 	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
277 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
278 
279 	/* Configure flow control refresh threshold value */
280 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
281 
282 	return 0;
283 }
284 
285 /**
286  * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
287  * @hw: pointer to hardware structure
288  *
289  * Configure queue statistics registers, all queues belonging to same traffic
290  * class uses a single set of queue statistics counters.
291  */
292 static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
293 {
294 	u32 reg = 0;
295 	u8  i   = 0;
296 
297 	/*
298 	 * Receive Queues stats setting
299 	 * 32 RQSMR registers, each configuring 4 queues.
300 	 * Set all 16 queues of each TC to the same stat
301 	 * with TC 'n' going to stat 'n'.
302 	 */
303 	for (i = 0; i < 32; i++) {
304 		reg = 0x01010101 * (i / 4);
305 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
306 	}
307 	/*
308 	 * Transmit Queues stats setting
309 	 * 32 TQSM registers, each controlling 4 queues.
310 	 * Set all queues of each TC to the same stat
311 	 * with TC 'n' going to stat 'n'.
312 	 * Tx queues are allocated non-uniformly to TCs:
313 	 * 32, 32, 16, 16, 8, 8, 8, 8.
314 	 */
315 	for (i = 0; i < 32; i++) {
316 		if (i < 8)
317 			reg = 0x00000000;
318 		else if (i < 16)
319 			reg = 0x01010101;
320 		else if (i < 20)
321 			reg = 0x02020202;
322 		else if (i < 24)
323 			reg = 0x03030303;
324 		else if (i < 26)
325 			reg = 0x04040404;
326 		else if (i < 28)
327 			reg = 0x05050505;
328 		else if (i < 30)
329 			reg = 0x06060606;
330 		else
331 			reg = 0x07070707;
332 		IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
333 	}
334 
335 	return 0;
336 }
337 
338 /**
339  * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
340  * @hw: pointer to hardware structure
341  * @refill: refill credits index by traffic class
342  * @max: max credits index by traffic class
343  * @bwg_id: bandwidth grouping indexed by traffic class
344  * @prio_type: priority type indexed by traffic class
345  * @pfc_en: enabled pfc bitmask
346  *
347  * Configure dcb settings and enable dcb mode.
348  */
349 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
350 			      u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
351 {
352 	ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
353 					  prio_type, prio_tc);
354 	ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
355 					       bwg_id, prio_type);
356 	ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
357 					       bwg_id, prio_type, prio_tc);
358 	ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
359 	ixgbe_dcb_config_tc_stats_82599(hw);
360 
361 	return 0;
362 }
363 
364