1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include "ixgbe.h" 29 #include "ixgbe_type.h" 30 #include "ixgbe_dcb.h" 31 #include "ixgbe_dcb_82599.h" 32 33 /** 34 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter 35 * @hw: pointer to hardware structure 36 * @refill: refill credits index by traffic class 37 * @max: max credits index by traffic class 38 * @bwg_id: bandwidth grouping indexed by traffic class 39 * @prio_type: priority type indexed by traffic class 40 * 41 * Configure Rx Packet Arbiter and credits for each traffic class. 42 */ 43 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, 44 u16 *refill, 45 u16 *max, 46 u8 *bwg_id, 47 u8 *prio_type, 48 u8 *prio_tc) 49 { 50 u32 reg = 0; 51 u32 credit_refill = 0; 52 u32 credit_max = 0; 53 u8 i = 0; 54 55 /* 56 * Disable the arbiter before changing parameters 57 * (always enable recycle mode; WSP) 58 */ 59 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; 60 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 61 62 /* Map all traffic classes to their UP */ 63 reg = 0; 64 for (i = 0; i < MAX_USER_PRIORITY; i++) 65 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 66 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 67 68 /* Configure traffic class credits and priority */ 69 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 70 credit_refill = refill[i]; 71 credit_max = max[i]; 72 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); 73 74 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; 75 76 if (prio_type[i] == prio_link) 77 reg |= IXGBE_RTRPT4C_LSP; 78 79 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); 80 } 81 82 /* 83 * Configure Rx packet plane (recycle mode; WSP) and 84 * enable arbiter 85 */ 86 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; 87 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 88 89 return 0; 90 } 91 92 /** 93 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter 94 * @hw: pointer to hardware structure 95 * @refill: refill credits index by traffic class 96 * @max: max credits index by traffic class 97 * @bwg_id: bandwidth grouping indexed by traffic class 98 * @prio_type: priority type indexed by traffic class 99 * 100 * Configure Tx Descriptor Arbiter and credits for each traffic class. 101 */ 102 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 103 u16 *refill, 104 u16 *max, 105 u8 *bwg_id, 106 u8 *prio_type) 107 { 108 u32 reg, max_credits; 109 u8 i; 110 111 /* Clear the per-Tx queue credits; we use per-TC instead */ 112 for (i = 0; i < 128; i++) { 113 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 114 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); 115 } 116 117 /* Configure traffic class credits and priority */ 118 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 119 max_credits = max[i]; 120 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; 121 reg |= refill[i]; 122 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT; 123 124 if (prio_type[i] == prio_group) 125 reg |= IXGBE_RTTDT2C_GSP; 126 127 if (prio_type[i] == prio_link) 128 reg |= IXGBE_RTTDT2C_LSP; 129 130 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); 131 } 132 133 /* 134 * Configure Tx descriptor plane (recycle mode; WSP) and 135 * enable arbiter 136 */ 137 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; 138 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); 139 140 return 0; 141 } 142 143 /** 144 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter 145 * @hw: pointer to hardware structure 146 * @refill: refill credits index by traffic class 147 * @max: max credits index by traffic class 148 * @bwg_id: bandwidth grouping indexed by traffic class 149 * @prio_type: priority type indexed by traffic class 150 * 151 * Configure Tx Packet Arbiter and credits for each traffic class. 152 */ 153 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, 154 u16 *refill, 155 u16 *max, 156 u8 *bwg_id, 157 u8 *prio_type, 158 u8 *prio_tc) 159 { 160 u32 reg; 161 u8 i; 162 163 /* 164 * Disable the arbiter before changing parameters 165 * (always enable recycle mode; SP; arb delay) 166 */ 167 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 168 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) | 169 IXGBE_RTTPCS_ARBDIS; 170 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 171 172 /* Map all traffic classes to their UP */ 173 reg = 0; 174 for (i = 0; i < MAX_USER_PRIORITY; i++) 175 reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); 176 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); 177 178 /* Configure traffic class credits and priority */ 179 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 180 reg = refill[i]; 181 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT; 182 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT; 183 184 if (prio_type[i] == prio_group) 185 reg |= IXGBE_RTTPT2C_GSP; 186 187 if (prio_type[i] == prio_link) 188 reg |= IXGBE_RTTPT2C_LSP; 189 190 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); 191 } 192 193 /* 194 * Configure Tx packet plane (recycle mode; SP; arb delay) and 195 * enable arbiter 196 */ 197 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 198 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT); 199 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 200 201 return 0; 202 } 203 204 /** 205 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control 206 * @hw: pointer to hardware structure 207 * @pfc_en: enabled pfc bitmask 208 * @prio_tc: priority to tc assignments indexed by priority 209 * 210 * Configure Priority Flow Control (PFC) for each traffic class. 211 */ 212 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 213 { 214 u32 i, j, reg; 215 u8 max_tc = 0; 216 217 for (i = 0; i < MAX_USER_PRIORITY; i++) 218 if (prio_tc[i] > max_tc) 219 max_tc = prio_tc[i]; 220 221 /* Configure PFC Tx thresholds per TC */ 222 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 223 int enabled = 0; 224 225 if (i > max_tc) { 226 reg = 0; 227 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg); 228 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); 229 continue; 230 } 231 232 for (j = 0; j < MAX_USER_PRIORITY; j++) { 233 if ((prio_tc[j] == i) && (pfc_en & (1 << j))) { 234 enabled = 1; 235 break; 236 } 237 } 238 239 reg = hw->fc.low_water << 10; 240 241 if (enabled) 242 reg |= IXGBE_FCRTL_XONE; 243 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg); 244 245 reg = hw->fc.high_water[i] << 10; 246 if (enabled) 247 reg |= IXGBE_FCRTH_FCEN; 248 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); 249 } 250 251 if (pfc_en) { 252 /* Configure pause time (2 TCs per register) */ 253 reg = hw->fc.pause_time | (hw->fc.pause_time << 16); 254 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 255 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 256 257 /* Configure flow control refresh threshold value */ 258 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 259 260 261 reg = IXGBE_FCCFG_TFCE_PRIORITY; 262 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg); 263 /* 264 * Enable Receive PFC 265 * 82599 will always honor XOFF frames we receive when 266 * we are in PFC mode however X540 only honors enabled 267 * traffic classes. 268 */ 269 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 270 reg &= ~IXGBE_MFLCN_RFCE; 271 reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF; 272 273 if (hw->mac.type == ixgbe_mac_X540) { 274 reg &= ~IXGBE_MFLCN_RPFCE_MASK; 275 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; 276 } 277 278 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); 279 280 } else { 281 /* X540 devices have a RX bit that should be cleared 282 * if PFC is disabled on all TCs but PFC features is 283 * enabled. 284 */ 285 if (hw->mac.type == ixgbe_mac_X540) { 286 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 287 reg &= ~IXGBE_MFLCN_RPFCE_MASK; 288 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); 289 } 290 291 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 292 hw->mac.ops.fc_enable(hw, i); 293 } 294 295 return 0; 296 } 297 298 /** 299 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics 300 * @hw: pointer to hardware structure 301 * 302 * Configure queue statistics registers, all queues belonging to same traffic 303 * class uses a single set of queue statistics counters. 304 */ 305 static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw) 306 { 307 u32 reg = 0; 308 u8 i = 0; 309 310 /* 311 * Receive Queues stats setting 312 * 32 RQSMR registers, each configuring 4 queues. 313 * Set all 16 queues of each TC to the same stat 314 * with TC 'n' going to stat 'n'. 315 */ 316 for (i = 0; i < 32; i++) { 317 reg = 0x01010101 * (i / 4); 318 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 319 } 320 /* 321 * Transmit Queues stats setting 322 * 32 TQSM registers, each controlling 4 queues. 323 * Set all queues of each TC to the same stat 324 * with TC 'n' going to stat 'n'. 325 * Tx queues are allocated non-uniformly to TCs: 326 * 32, 32, 16, 16, 8, 8, 8, 8. 327 */ 328 for (i = 0; i < 32; i++) { 329 if (i < 8) 330 reg = 0x00000000; 331 else if (i < 16) 332 reg = 0x01010101; 333 else if (i < 20) 334 reg = 0x02020202; 335 else if (i < 24) 336 reg = 0x03030303; 337 else if (i < 26) 338 reg = 0x04040404; 339 else if (i < 28) 340 reg = 0x05050505; 341 else if (i < 30) 342 reg = 0x06060606; 343 else 344 reg = 0x07070707; 345 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); 346 } 347 348 return 0; 349 } 350 351 /** 352 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB 353 * @hw: pointer to hardware structure 354 * @refill: refill credits index by traffic class 355 * @max: max credits index by traffic class 356 * @bwg_id: bandwidth grouping indexed by traffic class 357 * @prio_type: priority type indexed by traffic class 358 * @pfc_en: enabled pfc bitmask 359 * 360 * Configure dcb settings and enable dcb mode. 361 */ 362 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 363 u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) 364 { 365 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 366 prio_type, prio_tc); 367 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 368 bwg_id, prio_type); 369 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 370 bwg_id, prio_type, prio_tc); 371 ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); 372 ixgbe_dcb_config_tc_stats_82599(hw); 373 374 return 0; 375 } 376 377