1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include "ixgbe.h" 29 #include "ixgbe_type.h" 30 #include "ixgbe_dcb.h" 31 #include "ixgbe_dcb_82599.h" 32 33 /** 34 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter 35 * @hw: pointer to hardware structure 36 * @refill: refill credits index by traffic class 37 * @max: max credits index by traffic class 38 * @bwg_id: bandwidth grouping indexed by traffic class 39 * @prio_type: priority type indexed by traffic class 40 * 41 * Configure Rx Packet Arbiter and credits for each traffic class. 42 */ 43 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, 44 u16 *refill, 45 u16 *max, 46 u8 *bwg_id, 47 u8 *prio_type, 48 u8 *prio_tc) 49 { 50 u32 reg = 0; 51 u32 credit_refill = 0; 52 u32 credit_max = 0; 53 u8 i = 0; 54 55 /* 56 * Disable the arbiter before changing parameters 57 * (always enable recycle mode; WSP) 58 */ 59 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; 60 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 61 62 /* Map all traffic classes to their UP */ 63 reg = 0; 64 for (i = 0; i < MAX_USER_PRIORITY; i++) 65 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 66 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 67 68 /* Configure traffic class credits and priority */ 69 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 70 credit_refill = refill[i]; 71 credit_max = max[i]; 72 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); 73 74 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; 75 76 if (prio_type[i] == prio_link) 77 reg |= IXGBE_RTRPT4C_LSP; 78 79 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); 80 } 81 82 /* 83 * Configure Rx packet plane (recycle mode; WSP) and 84 * enable arbiter 85 */ 86 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; 87 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 88 89 return 0; 90 } 91 92 /** 93 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter 94 * @hw: pointer to hardware structure 95 * @refill: refill credits index by traffic class 96 * @max: max credits index by traffic class 97 * @bwg_id: bandwidth grouping indexed by traffic class 98 * @prio_type: priority type indexed by traffic class 99 * 100 * Configure Tx Descriptor Arbiter and credits for each traffic class. 101 */ 102 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 103 u16 *refill, 104 u16 *max, 105 u8 *bwg_id, 106 u8 *prio_type) 107 { 108 u32 reg, max_credits; 109 u8 i; 110 111 /* Clear the per-Tx queue credits; we use per-TC instead */ 112 for (i = 0; i < 128; i++) { 113 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 114 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); 115 } 116 117 /* Configure traffic class credits and priority */ 118 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 119 max_credits = max[i]; 120 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; 121 reg |= refill[i]; 122 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT; 123 124 if (prio_type[i] == prio_group) 125 reg |= IXGBE_RTTDT2C_GSP; 126 127 if (prio_type[i] == prio_link) 128 reg |= IXGBE_RTTDT2C_LSP; 129 130 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); 131 } 132 133 /* 134 * Configure Tx descriptor plane (recycle mode; WSP) and 135 * enable arbiter 136 */ 137 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; 138 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); 139 140 return 0; 141 } 142 143 /** 144 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter 145 * @hw: pointer to hardware structure 146 * @refill: refill credits index by traffic class 147 * @max: max credits index by traffic class 148 * @bwg_id: bandwidth grouping indexed by traffic class 149 * @prio_type: priority type indexed by traffic class 150 * 151 * Configure Tx Packet Arbiter and credits for each traffic class. 152 */ 153 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, 154 u16 *refill, 155 u16 *max, 156 u8 *bwg_id, 157 u8 *prio_type, 158 u8 *prio_tc) 159 { 160 u32 reg; 161 u8 i; 162 163 /* 164 * Disable the arbiter before changing parameters 165 * (always enable recycle mode; SP; arb delay) 166 */ 167 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 168 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) | 169 IXGBE_RTTPCS_ARBDIS; 170 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 171 172 /* Map all traffic classes to their UP */ 173 reg = 0; 174 for (i = 0; i < MAX_USER_PRIORITY; i++) 175 reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); 176 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); 177 178 /* Configure traffic class credits and priority */ 179 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 180 reg = refill[i]; 181 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT; 182 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT; 183 184 if (prio_type[i] == prio_group) 185 reg |= IXGBE_RTTPT2C_GSP; 186 187 if (prio_type[i] == prio_link) 188 reg |= IXGBE_RTTPT2C_LSP; 189 190 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); 191 } 192 193 /* 194 * Configure Tx packet plane (recycle mode; SP; arb delay) and 195 * enable arbiter 196 */ 197 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 198 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT); 199 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 200 201 return 0; 202 } 203 204 /** 205 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control 206 * @hw: pointer to hardware structure 207 * @pfc_en: enabled pfc bitmask 208 * @prio_tc: priority to tc assignments indexed by priority 209 * 210 * Configure Priority Flow Control (PFC) for each traffic class. 211 */ 212 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 213 { 214 u32 i, j, fcrtl, reg; 215 u8 max_tc = 0; 216 217 /* Enable Transmit Priority Flow Control */ 218 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY); 219 220 /* Enable Receive Priority Flow Control */ 221 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 222 reg |= IXGBE_MFLCN_DPF; 223 224 /* 225 * X540 supports per TC Rx priority flow control. So 226 * clear all TCs and only enable those that should be 227 * enabled. 228 */ 229 reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 230 231 if (hw->mac.type == ixgbe_mac_X540) 232 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; 233 234 if (pfc_en) 235 reg |= IXGBE_MFLCN_RPFCE; 236 237 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); 238 239 for (i = 0; i < MAX_USER_PRIORITY; i++) { 240 if (prio_tc[i] > max_tc) 241 max_tc = prio_tc[i]; 242 } 243 244 fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE; 245 246 /* Configure PFC Tx thresholds per TC */ 247 for (i = 0; i <= max_tc; i++) { 248 int enabled = 0; 249 250 for (j = 0; j < MAX_USER_PRIORITY; j++) { 251 if ((prio_tc[j] == i) && (pfc_en & (1 << j))) { 252 enabled = 1; 253 break; 254 } 255 } 256 257 if (enabled) { 258 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 259 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 260 } else { 261 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 262 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 263 } 264 265 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); 266 } 267 268 for (; i < MAX_TRAFFIC_CLASS; i++) { 269 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 270 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0); 271 } 272 273 /* Configure pause time (2 TCs per register) */ 274 reg = hw->fc.pause_time * 0x00010001; 275 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 276 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 277 278 /* Configure flow control refresh threshold value */ 279 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 280 281 return 0; 282 } 283 284 /** 285 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics 286 * @hw: pointer to hardware structure 287 * 288 * Configure queue statistics registers, all queues belonging to same traffic 289 * class uses a single set of queue statistics counters. 290 */ 291 static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw) 292 { 293 u32 reg = 0; 294 u8 i = 0; 295 296 /* 297 * Receive Queues stats setting 298 * 32 RQSMR registers, each configuring 4 queues. 299 * Set all 16 queues of each TC to the same stat 300 * with TC 'n' going to stat 'n'. 301 */ 302 for (i = 0; i < 32; i++) { 303 reg = 0x01010101 * (i / 4); 304 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 305 } 306 /* 307 * Transmit Queues stats setting 308 * 32 TQSM registers, each controlling 4 queues. 309 * Set all queues of each TC to the same stat 310 * with TC 'n' going to stat 'n'. 311 * Tx queues are allocated non-uniformly to TCs: 312 * 32, 32, 16, 16, 8, 8, 8, 8. 313 */ 314 for (i = 0; i < 32; i++) { 315 if (i < 8) 316 reg = 0x00000000; 317 else if (i < 16) 318 reg = 0x01010101; 319 else if (i < 20) 320 reg = 0x02020202; 321 else if (i < 24) 322 reg = 0x03030303; 323 else if (i < 26) 324 reg = 0x04040404; 325 else if (i < 28) 326 reg = 0x05050505; 327 else if (i < 30) 328 reg = 0x06060606; 329 else 330 reg = 0x07070707; 331 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); 332 } 333 334 return 0; 335 } 336 337 /** 338 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB 339 * @hw: pointer to hardware structure 340 * @refill: refill credits index by traffic class 341 * @max: max credits index by traffic class 342 * @bwg_id: bandwidth grouping indexed by traffic class 343 * @prio_type: priority type indexed by traffic class 344 * @pfc_en: enabled pfc bitmask 345 * 346 * Configure dcb settings and enable dcb mode. 347 */ 348 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 349 u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) 350 { 351 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 352 prio_type, prio_tc); 353 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 354 bwg_id, prio_type); 355 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 356 bwg_id, prio_type, prio_tc); 357 ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); 358 ixgbe_dcb_config_tc_stats_82599(hw); 359 360 return 0; 361 } 362 363