1dee1ad47SJeff Kirsher /******************************************************************************* 2dee1ad47SJeff Kirsher 3dee1ad47SJeff Kirsher Intel 10 Gigabit PCI Express Linux driver 4434c5e39SDon Skidmore Copyright(c) 1999 - 2013 Intel Corporation. 5dee1ad47SJeff Kirsher 6dee1ad47SJeff Kirsher This program is free software; you can redistribute it and/or modify it 7dee1ad47SJeff Kirsher under the terms and conditions of the GNU General Public License, 8dee1ad47SJeff Kirsher version 2, as published by the Free Software Foundation. 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 11dee1ad47SJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12dee1ad47SJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13dee1ad47SJeff Kirsher more details. 14dee1ad47SJeff Kirsher 15dee1ad47SJeff Kirsher You should have received a copy of the GNU General Public License along with 16dee1ad47SJeff Kirsher this program; if not, write to the Free Software Foundation, Inc., 17dee1ad47SJeff Kirsher 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18dee1ad47SJeff Kirsher 19dee1ad47SJeff Kirsher The full GNU General Public License is included in this distribution in 20dee1ad47SJeff Kirsher the file called "COPYING". 21dee1ad47SJeff Kirsher 22dee1ad47SJeff Kirsher Contact Information: 23b89aae71SJacob Keller Linux NICS <linux.nics@intel.com> 24dee1ad47SJeff Kirsher e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25dee1ad47SJeff Kirsher Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26dee1ad47SJeff Kirsher 27dee1ad47SJeff Kirsher *******************************************************************************/ 28dee1ad47SJeff Kirsher 29dee1ad47SJeff Kirsher #include "ixgbe.h" 30dee1ad47SJeff Kirsher #include "ixgbe_type.h" 31dee1ad47SJeff Kirsher #include "ixgbe_dcb.h" 32dee1ad47SJeff Kirsher #include "ixgbe_dcb_82599.h" 33dee1ad47SJeff Kirsher 34dee1ad47SJeff Kirsher /** 35dee1ad47SJeff Kirsher * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter 36dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 37dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 38dee1ad47SJeff Kirsher * @max: max credits index by traffic class 39dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 40dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 41dee1ad47SJeff Kirsher * 42dee1ad47SJeff Kirsher * Configure Rx Packet Arbiter and credits for each traffic class. 43dee1ad47SJeff Kirsher */ 44dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, 45dee1ad47SJeff Kirsher u16 *refill, 46dee1ad47SJeff Kirsher u16 *max, 47dee1ad47SJeff Kirsher u8 *bwg_id, 48dee1ad47SJeff Kirsher u8 *prio_type, 49dee1ad47SJeff Kirsher u8 *prio_tc) 50dee1ad47SJeff Kirsher { 51dee1ad47SJeff Kirsher u32 reg = 0; 52dee1ad47SJeff Kirsher u32 credit_refill = 0; 53dee1ad47SJeff Kirsher u32 credit_max = 0; 54dee1ad47SJeff Kirsher u8 i = 0; 55dee1ad47SJeff Kirsher 56dee1ad47SJeff Kirsher /* 57dee1ad47SJeff Kirsher * Disable the arbiter before changing parameters 58dee1ad47SJeff Kirsher * (always enable recycle mode; WSP) 59dee1ad47SJeff Kirsher */ 60dee1ad47SJeff Kirsher reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; 61dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 62dee1ad47SJeff Kirsher 6332701dc2SJohn Fastabend /* Map all traffic classes to their UP */ 64dee1ad47SJeff Kirsher reg = 0; 6532701dc2SJohn Fastabend for (i = 0; i < MAX_USER_PRIORITY; i++) 66dee1ad47SJeff Kirsher reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 67dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 68dee1ad47SJeff Kirsher 69dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 70dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 71dee1ad47SJeff Kirsher credit_refill = refill[i]; 72dee1ad47SJeff Kirsher credit_max = max[i]; 73dee1ad47SJeff Kirsher reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); 74dee1ad47SJeff Kirsher 75dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; 76dee1ad47SJeff Kirsher 77dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 78dee1ad47SJeff Kirsher reg |= IXGBE_RTRPT4C_LSP; 79dee1ad47SJeff Kirsher 80dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); 81dee1ad47SJeff Kirsher } 82dee1ad47SJeff Kirsher 83dee1ad47SJeff Kirsher /* 84dee1ad47SJeff Kirsher * Configure Rx packet plane (recycle mode; WSP) and 85dee1ad47SJeff Kirsher * enable arbiter 86dee1ad47SJeff Kirsher */ 87dee1ad47SJeff Kirsher reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; 88dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 89dee1ad47SJeff Kirsher 90dee1ad47SJeff Kirsher return 0; 91dee1ad47SJeff Kirsher } 92dee1ad47SJeff Kirsher 93dee1ad47SJeff Kirsher /** 94dee1ad47SJeff Kirsher * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter 95dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 96dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 97dee1ad47SJeff Kirsher * @max: max credits index by traffic class 98dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 99dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 100dee1ad47SJeff Kirsher * 101dee1ad47SJeff Kirsher * Configure Tx Descriptor Arbiter and credits for each traffic class. 102dee1ad47SJeff Kirsher */ 103dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 104dee1ad47SJeff Kirsher u16 *refill, 105dee1ad47SJeff Kirsher u16 *max, 106dee1ad47SJeff Kirsher u8 *bwg_id, 107dee1ad47SJeff Kirsher u8 *prio_type) 108dee1ad47SJeff Kirsher { 109dee1ad47SJeff Kirsher u32 reg, max_credits; 110dee1ad47SJeff Kirsher u8 i; 111dee1ad47SJeff Kirsher 112dee1ad47SJeff Kirsher /* Clear the per-Tx queue credits; we use per-TC instead */ 113dee1ad47SJeff Kirsher for (i = 0; i < 128; i++) { 114dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 115dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); 116dee1ad47SJeff Kirsher } 117dee1ad47SJeff Kirsher 118dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 119dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 120dee1ad47SJeff Kirsher max_credits = max[i]; 121dee1ad47SJeff Kirsher reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; 122dee1ad47SJeff Kirsher reg |= refill[i]; 123dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT; 124dee1ad47SJeff Kirsher 125dee1ad47SJeff Kirsher if (prio_type[i] == prio_group) 126dee1ad47SJeff Kirsher reg |= IXGBE_RTTDT2C_GSP; 127dee1ad47SJeff Kirsher 128dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 129dee1ad47SJeff Kirsher reg |= IXGBE_RTTDT2C_LSP; 130dee1ad47SJeff Kirsher 131dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); 132dee1ad47SJeff Kirsher } 133dee1ad47SJeff Kirsher 134dee1ad47SJeff Kirsher /* 135dee1ad47SJeff Kirsher * Configure Tx descriptor plane (recycle mode; WSP) and 136dee1ad47SJeff Kirsher * enable arbiter 137dee1ad47SJeff Kirsher */ 138dee1ad47SJeff Kirsher reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; 139dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); 140dee1ad47SJeff Kirsher 141dee1ad47SJeff Kirsher return 0; 142dee1ad47SJeff Kirsher } 143dee1ad47SJeff Kirsher 144dee1ad47SJeff Kirsher /** 145dee1ad47SJeff Kirsher * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter 146dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 147dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 148dee1ad47SJeff Kirsher * @max: max credits index by traffic class 149dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 150dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 151dee1ad47SJeff Kirsher * 152dee1ad47SJeff Kirsher * Configure Tx Packet Arbiter and credits for each traffic class. 153dee1ad47SJeff Kirsher */ 154dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, 155dee1ad47SJeff Kirsher u16 *refill, 156dee1ad47SJeff Kirsher u16 *max, 157dee1ad47SJeff Kirsher u8 *bwg_id, 158dee1ad47SJeff Kirsher u8 *prio_type, 159dee1ad47SJeff Kirsher u8 *prio_tc) 160dee1ad47SJeff Kirsher { 161dee1ad47SJeff Kirsher u32 reg; 162dee1ad47SJeff Kirsher u8 i; 163dee1ad47SJeff Kirsher 164dee1ad47SJeff Kirsher /* 165dee1ad47SJeff Kirsher * Disable the arbiter before changing parameters 166dee1ad47SJeff Kirsher * (always enable recycle mode; SP; arb delay) 167dee1ad47SJeff Kirsher */ 168dee1ad47SJeff Kirsher reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 169dee1ad47SJeff Kirsher (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) | 170dee1ad47SJeff Kirsher IXGBE_RTTPCS_ARBDIS; 171dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 172dee1ad47SJeff Kirsher 17332701dc2SJohn Fastabend /* Map all traffic classes to their UP */ 174dee1ad47SJeff Kirsher reg = 0; 17532701dc2SJohn Fastabend for (i = 0; i < MAX_USER_PRIORITY; i++) 176dee1ad47SJeff Kirsher reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); 177dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); 178dee1ad47SJeff Kirsher 179dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 180dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 181dee1ad47SJeff Kirsher reg = refill[i]; 182dee1ad47SJeff Kirsher reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT; 183dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT; 184dee1ad47SJeff Kirsher 185dee1ad47SJeff Kirsher if (prio_type[i] == prio_group) 186dee1ad47SJeff Kirsher reg |= IXGBE_RTTPT2C_GSP; 187dee1ad47SJeff Kirsher 188dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 189dee1ad47SJeff Kirsher reg |= IXGBE_RTTPT2C_LSP; 190dee1ad47SJeff Kirsher 191dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); 192dee1ad47SJeff Kirsher } 193dee1ad47SJeff Kirsher 194dee1ad47SJeff Kirsher /* 195dee1ad47SJeff Kirsher * Configure Tx packet plane (recycle mode; SP; arb delay) and 196dee1ad47SJeff Kirsher * enable arbiter 197dee1ad47SJeff Kirsher */ 198dee1ad47SJeff Kirsher reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 199dee1ad47SJeff Kirsher (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT); 200dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 201dee1ad47SJeff Kirsher 202dee1ad47SJeff Kirsher return 0; 203dee1ad47SJeff Kirsher } 204dee1ad47SJeff Kirsher 205dee1ad47SJeff Kirsher /** 206dee1ad47SJeff Kirsher * ixgbe_dcb_config_pfc_82599 - Configure priority flow control 207dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 208dee1ad47SJeff Kirsher * @pfc_en: enabled pfc bitmask 20932701dc2SJohn Fastabend * @prio_tc: priority to tc assignments indexed by priority 210dee1ad47SJeff Kirsher * 211dee1ad47SJeff Kirsher * Configure Priority Flow Control (PFC) for each traffic class. 212dee1ad47SJeff Kirsher */ 21332701dc2SJohn Fastabend s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 214dee1ad47SJeff Kirsher { 215943561d3SAlexander Duyck u32 i, j, fcrtl, reg; 21632701dc2SJohn Fastabend u8 max_tc = 0; 21732701dc2SJohn Fastabend 218943561d3SAlexander Duyck /* Enable Transmit Priority Flow Control */ 219943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY); 220943561d3SAlexander Duyck 221943561d3SAlexander Duyck /* Enable Receive Priority Flow Control */ 222943561d3SAlexander Duyck reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 223943561d3SAlexander Duyck reg |= IXGBE_MFLCN_DPF; 224943561d3SAlexander Duyck 225943561d3SAlexander Duyck /* 226943561d3SAlexander Duyck * X540 supports per TC Rx priority flow control. So 227943561d3SAlexander Duyck * clear all TCs and only enable those that should be 228943561d3SAlexander Duyck * enabled. 229943561d3SAlexander Duyck */ 230943561d3SAlexander Duyck reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 231943561d3SAlexander Duyck 232943561d3SAlexander Duyck if (hw->mac.type == ixgbe_mac_X540) 233943561d3SAlexander Duyck reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; 234943561d3SAlexander Duyck 235943561d3SAlexander Duyck if (pfc_en) 236943561d3SAlexander Duyck reg |= IXGBE_MFLCN_RPFCE; 237943561d3SAlexander Duyck 238943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); 239943561d3SAlexander Duyck 240943561d3SAlexander Duyck for (i = 0; i < MAX_USER_PRIORITY; i++) { 24132701dc2SJohn Fastabend if (prio_tc[i] > max_tc) 24232701dc2SJohn Fastabend max_tc = prio_tc[i]; 243943561d3SAlexander Duyck } 244943561d3SAlexander Duyck 245dee1ad47SJeff Kirsher 246dee1ad47SJeff Kirsher /* Configure PFC Tx thresholds per TC */ 247943561d3SAlexander Duyck for (i = 0; i <= max_tc; i++) { 24832701dc2SJohn Fastabend int enabled = 0; 24932701dc2SJohn Fastabend 25032701dc2SJohn Fastabend for (j = 0; j < MAX_USER_PRIORITY; j++) { 25132701dc2SJohn Fastabend if ((prio_tc[j] == i) && (pfc_en & (1 << j))) { 25232701dc2SJohn Fastabend enabled = 1; 25332701dc2SJohn Fastabend break; 25432701dc2SJohn Fastabend } 25532701dc2SJohn Fastabend } 256dee1ad47SJeff Kirsher 257943561d3SAlexander Duyck if (enabled) { 258943561d3SAlexander Duyck reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 259e5776620SJacob Keller fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 260943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 261943561d3SAlexander Duyck } else { 262bc1fc64fSMark Rustad /* In order to prevent Tx hangs when the internal Tx 263bc1fc64fSMark Rustad * switch is enabled we must set the high water mark 264bc1fc64fSMark Rustad * to the Rx packet buffer size - 24KB. This allows 265bc1fc64fSMark Rustad * the Tx switch to function even under heavy Rx 266bc1fc64fSMark Rustad * workloads. 267bc1fc64fSMark Rustad */ 268bc1fc64fSMark Rustad reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 269943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 270943561d3SAlexander Duyck } 271dee1ad47SJeff Kirsher 272dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); 273dee1ad47SJeff Kirsher } 274dee1ad47SJeff Kirsher 275943561d3SAlexander Duyck for (; i < MAX_TRAFFIC_CLASS; i++) { 276943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 277943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0); 278943561d3SAlexander Duyck } 279943561d3SAlexander Duyck 280dee1ad47SJeff Kirsher /* Configure pause time (2 TCs per register) */ 281943561d3SAlexander Duyck reg = hw->fc.pause_time * 0x00010001; 282dee1ad47SJeff Kirsher for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 283dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 284dee1ad47SJeff Kirsher 285dee1ad47SJeff Kirsher /* Configure flow control refresh threshold value */ 286dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 287dee1ad47SJeff Kirsher 288dee1ad47SJeff Kirsher return 0; 289dee1ad47SJeff Kirsher } 290dee1ad47SJeff Kirsher 291dee1ad47SJeff Kirsher /** 292dee1ad47SJeff Kirsher * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics 293dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 294dee1ad47SJeff Kirsher * 295dee1ad47SJeff Kirsher * Configure queue statistics registers, all queues belonging to same traffic 296dee1ad47SJeff Kirsher * class uses a single set of queue statistics counters. 297dee1ad47SJeff Kirsher */ 298dee1ad47SJeff Kirsher static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw) 299dee1ad47SJeff Kirsher { 300dee1ad47SJeff Kirsher u32 reg = 0; 301dee1ad47SJeff Kirsher u8 i = 0; 302dee1ad47SJeff Kirsher 303dee1ad47SJeff Kirsher /* 304dee1ad47SJeff Kirsher * Receive Queues stats setting 305dee1ad47SJeff Kirsher * 32 RQSMR registers, each configuring 4 queues. 306dee1ad47SJeff Kirsher * Set all 16 queues of each TC to the same stat 307dee1ad47SJeff Kirsher * with TC 'n' going to stat 'n'. 308dee1ad47SJeff Kirsher */ 309dee1ad47SJeff Kirsher for (i = 0; i < 32; i++) { 310dee1ad47SJeff Kirsher reg = 0x01010101 * (i / 4); 311dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 312dee1ad47SJeff Kirsher } 313dee1ad47SJeff Kirsher /* 314dee1ad47SJeff Kirsher * Transmit Queues stats setting 315dee1ad47SJeff Kirsher * 32 TQSM registers, each controlling 4 queues. 316dee1ad47SJeff Kirsher * Set all queues of each TC to the same stat 317dee1ad47SJeff Kirsher * with TC 'n' going to stat 'n'. 318dee1ad47SJeff Kirsher * Tx queues are allocated non-uniformly to TCs: 319dee1ad47SJeff Kirsher * 32, 32, 16, 16, 8, 8, 8, 8. 320dee1ad47SJeff Kirsher */ 321dee1ad47SJeff Kirsher for (i = 0; i < 32; i++) { 322dee1ad47SJeff Kirsher if (i < 8) 323dee1ad47SJeff Kirsher reg = 0x00000000; 324dee1ad47SJeff Kirsher else if (i < 16) 325dee1ad47SJeff Kirsher reg = 0x01010101; 326dee1ad47SJeff Kirsher else if (i < 20) 327dee1ad47SJeff Kirsher reg = 0x02020202; 328dee1ad47SJeff Kirsher else if (i < 24) 329dee1ad47SJeff Kirsher reg = 0x03030303; 330dee1ad47SJeff Kirsher else if (i < 26) 331dee1ad47SJeff Kirsher reg = 0x04040404; 332dee1ad47SJeff Kirsher else if (i < 28) 333dee1ad47SJeff Kirsher reg = 0x05050505; 334dee1ad47SJeff Kirsher else if (i < 30) 335dee1ad47SJeff Kirsher reg = 0x06060606; 336dee1ad47SJeff Kirsher else 337dee1ad47SJeff Kirsher reg = 0x07070707; 338dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); 339dee1ad47SJeff Kirsher } 340dee1ad47SJeff Kirsher 341dee1ad47SJeff Kirsher return 0; 342dee1ad47SJeff Kirsher } 343dee1ad47SJeff Kirsher 344dee1ad47SJeff Kirsher /** 345dee1ad47SJeff Kirsher * ixgbe_dcb_hw_config_82599 - Configure and enable DCB 346dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 347dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 348dee1ad47SJeff Kirsher * @max: max credits index by traffic class 349dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 350dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 351dee1ad47SJeff Kirsher * @pfc_en: enabled pfc bitmask 352dee1ad47SJeff Kirsher * 353dee1ad47SJeff Kirsher * Configure dcb settings and enable dcb mode. 354dee1ad47SJeff Kirsher */ 355dee1ad47SJeff Kirsher s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 356dee1ad47SJeff Kirsher u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) 357dee1ad47SJeff Kirsher { 358dee1ad47SJeff Kirsher ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 359dee1ad47SJeff Kirsher prio_type, prio_tc); 360dee1ad47SJeff Kirsher ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 361dee1ad47SJeff Kirsher bwg_id, prio_type); 362dee1ad47SJeff Kirsher ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 363dee1ad47SJeff Kirsher bwg_id, prio_type, prio_tc); 36432701dc2SJohn Fastabend ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); 365dee1ad47SJeff Kirsher ixgbe_dcb_config_tc_stats_82599(hw); 366dee1ad47SJeff Kirsher 367dee1ad47SJeff Kirsher return 0; 368dee1ad47SJeff Kirsher } 369dee1ad47SJeff Kirsher 370