1dee1ad47SJeff Kirsher /******************************************************************************* 2dee1ad47SJeff Kirsher 3dee1ad47SJeff Kirsher Intel 10 Gigabit PCI Express Linux driver 494971820SDon Skidmore Copyright(c) 1999 - 2012 Intel Corporation. 5dee1ad47SJeff Kirsher 6dee1ad47SJeff Kirsher This program is free software; you can redistribute it and/or modify it 7dee1ad47SJeff Kirsher under the terms and conditions of the GNU General Public License, 8dee1ad47SJeff Kirsher version 2, as published by the Free Software Foundation. 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 11dee1ad47SJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12dee1ad47SJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13dee1ad47SJeff Kirsher more details. 14dee1ad47SJeff Kirsher 15dee1ad47SJeff Kirsher You should have received a copy of the GNU General Public License along with 16dee1ad47SJeff Kirsher this program; if not, write to the Free Software Foundation, Inc., 17dee1ad47SJeff Kirsher 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18dee1ad47SJeff Kirsher 19dee1ad47SJeff Kirsher The full GNU General Public License is included in this distribution in 20dee1ad47SJeff Kirsher the file called "COPYING". 21dee1ad47SJeff Kirsher 22dee1ad47SJeff Kirsher Contact Information: 23dee1ad47SJeff Kirsher e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24dee1ad47SJeff Kirsher Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25dee1ad47SJeff Kirsher 26dee1ad47SJeff Kirsher *******************************************************************************/ 27dee1ad47SJeff Kirsher 28dee1ad47SJeff Kirsher #include "ixgbe.h" 29dee1ad47SJeff Kirsher #include "ixgbe_type.h" 30dee1ad47SJeff Kirsher #include "ixgbe_dcb.h" 31dee1ad47SJeff Kirsher #include "ixgbe_dcb_82599.h" 32dee1ad47SJeff Kirsher 33dee1ad47SJeff Kirsher /** 34dee1ad47SJeff Kirsher * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter 35dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 36dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 37dee1ad47SJeff Kirsher * @max: max credits index by traffic class 38dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 39dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 40dee1ad47SJeff Kirsher * 41dee1ad47SJeff Kirsher * Configure Rx Packet Arbiter and credits for each traffic class. 42dee1ad47SJeff Kirsher */ 43dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, 44dee1ad47SJeff Kirsher u16 *refill, 45dee1ad47SJeff Kirsher u16 *max, 46dee1ad47SJeff Kirsher u8 *bwg_id, 47dee1ad47SJeff Kirsher u8 *prio_type, 48dee1ad47SJeff Kirsher u8 *prio_tc) 49dee1ad47SJeff Kirsher { 50dee1ad47SJeff Kirsher u32 reg = 0; 51dee1ad47SJeff Kirsher u32 credit_refill = 0; 52dee1ad47SJeff Kirsher u32 credit_max = 0; 53dee1ad47SJeff Kirsher u8 i = 0; 54dee1ad47SJeff Kirsher 55dee1ad47SJeff Kirsher /* 56dee1ad47SJeff Kirsher * Disable the arbiter before changing parameters 57dee1ad47SJeff Kirsher * (always enable recycle mode; WSP) 58dee1ad47SJeff Kirsher */ 59dee1ad47SJeff Kirsher reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; 60dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 61dee1ad47SJeff Kirsher 6232701dc2SJohn Fastabend /* Map all traffic classes to their UP */ 63dee1ad47SJeff Kirsher reg = 0; 6432701dc2SJohn Fastabend for (i = 0; i < MAX_USER_PRIORITY; i++) 65dee1ad47SJeff Kirsher reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 66dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 67dee1ad47SJeff Kirsher 68dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 69dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 70dee1ad47SJeff Kirsher credit_refill = refill[i]; 71dee1ad47SJeff Kirsher credit_max = max[i]; 72dee1ad47SJeff Kirsher reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); 73dee1ad47SJeff Kirsher 74dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; 75dee1ad47SJeff Kirsher 76dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 77dee1ad47SJeff Kirsher reg |= IXGBE_RTRPT4C_LSP; 78dee1ad47SJeff Kirsher 79dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); 80dee1ad47SJeff Kirsher } 81dee1ad47SJeff Kirsher 82dee1ad47SJeff Kirsher /* 83dee1ad47SJeff Kirsher * Configure Rx packet plane (recycle mode; WSP) and 84dee1ad47SJeff Kirsher * enable arbiter 85dee1ad47SJeff Kirsher */ 86dee1ad47SJeff Kirsher reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; 87dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 88dee1ad47SJeff Kirsher 89dee1ad47SJeff Kirsher return 0; 90dee1ad47SJeff Kirsher } 91dee1ad47SJeff Kirsher 92dee1ad47SJeff Kirsher /** 93dee1ad47SJeff Kirsher * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter 94dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 95dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 96dee1ad47SJeff Kirsher * @max: max credits index by traffic class 97dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 98dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 99dee1ad47SJeff Kirsher * 100dee1ad47SJeff Kirsher * Configure Tx Descriptor Arbiter and credits for each traffic class. 101dee1ad47SJeff Kirsher */ 102dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 103dee1ad47SJeff Kirsher u16 *refill, 104dee1ad47SJeff Kirsher u16 *max, 105dee1ad47SJeff Kirsher u8 *bwg_id, 106dee1ad47SJeff Kirsher u8 *prio_type) 107dee1ad47SJeff Kirsher { 108dee1ad47SJeff Kirsher u32 reg, max_credits; 109dee1ad47SJeff Kirsher u8 i; 110dee1ad47SJeff Kirsher 111dee1ad47SJeff Kirsher /* Clear the per-Tx queue credits; we use per-TC instead */ 112dee1ad47SJeff Kirsher for (i = 0; i < 128; i++) { 113dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 114dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); 115dee1ad47SJeff Kirsher } 116dee1ad47SJeff Kirsher 117dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 118dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 119dee1ad47SJeff Kirsher max_credits = max[i]; 120dee1ad47SJeff Kirsher reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; 121dee1ad47SJeff Kirsher reg |= refill[i]; 122dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT; 123dee1ad47SJeff Kirsher 124dee1ad47SJeff Kirsher if (prio_type[i] == prio_group) 125dee1ad47SJeff Kirsher reg |= IXGBE_RTTDT2C_GSP; 126dee1ad47SJeff Kirsher 127dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 128dee1ad47SJeff Kirsher reg |= IXGBE_RTTDT2C_LSP; 129dee1ad47SJeff Kirsher 130dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); 131dee1ad47SJeff Kirsher } 132dee1ad47SJeff Kirsher 133dee1ad47SJeff Kirsher /* 134dee1ad47SJeff Kirsher * Configure Tx descriptor plane (recycle mode; WSP) and 135dee1ad47SJeff Kirsher * enable arbiter 136dee1ad47SJeff Kirsher */ 137dee1ad47SJeff Kirsher reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; 138dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); 139dee1ad47SJeff Kirsher 140dee1ad47SJeff Kirsher return 0; 141dee1ad47SJeff Kirsher } 142dee1ad47SJeff Kirsher 143dee1ad47SJeff Kirsher /** 144dee1ad47SJeff Kirsher * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter 145dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 146dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 147dee1ad47SJeff Kirsher * @max: max credits index by traffic class 148dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 149dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 150dee1ad47SJeff Kirsher * 151dee1ad47SJeff Kirsher * Configure Tx Packet Arbiter and credits for each traffic class. 152dee1ad47SJeff Kirsher */ 153dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, 154dee1ad47SJeff Kirsher u16 *refill, 155dee1ad47SJeff Kirsher u16 *max, 156dee1ad47SJeff Kirsher u8 *bwg_id, 157dee1ad47SJeff Kirsher u8 *prio_type, 158dee1ad47SJeff Kirsher u8 *prio_tc) 159dee1ad47SJeff Kirsher { 160dee1ad47SJeff Kirsher u32 reg; 161dee1ad47SJeff Kirsher u8 i; 162dee1ad47SJeff Kirsher 163dee1ad47SJeff Kirsher /* 164dee1ad47SJeff Kirsher * Disable the arbiter before changing parameters 165dee1ad47SJeff Kirsher * (always enable recycle mode; SP; arb delay) 166dee1ad47SJeff Kirsher */ 167dee1ad47SJeff Kirsher reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 168dee1ad47SJeff Kirsher (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) | 169dee1ad47SJeff Kirsher IXGBE_RTTPCS_ARBDIS; 170dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 171dee1ad47SJeff Kirsher 17232701dc2SJohn Fastabend /* Map all traffic classes to their UP */ 173dee1ad47SJeff Kirsher reg = 0; 17432701dc2SJohn Fastabend for (i = 0; i < MAX_USER_PRIORITY; i++) 175dee1ad47SJeff Kirsher reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); 176dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); 177dee1ad47SJeff Kirsher 178dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 179dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 180dee1ad47SJeff Kirsher reg = refill[i]; 181dee1ad47SJeff Kirsher reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT; 182dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT; 183dee1ad47SJeff Kirsher 184dee1ad47SJeff Kirsher if (prio_type[i] == prio_group) 185dee1ad47SJeff Kirsher reg |= IXGBE_RTTPT2C_GSP; 186dee1ad47SJeff Kirsher 187dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 188dee1ad47SJeff Kirsher reg |= IXGBE_RTTPT2C_LSP; 189dee1ad47SJeff Kirsher 190dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); 191dee1ad47SJeff Kirsher } 192dee1ad47SJeff Kirsher 193dee1ad47SJeff Kirsher /* 194dee1ad47SJeff Kirsher * Configure Tx packet plane (recycle mode; SP; arb delay) and 195dee1ad47SJeff Kirsher * enable arbiter 196dee1ad47SJeff Kirsher */ 197dee1ad47SJeff Kirsher reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 198dee1ad47SJeff Kirsher (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT); 199dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 200dee1ad47SJeff Kirsher 201dee1ad47SJeff Kirsher return 0; 202dee1ad47SJeff Kirsher } 203dee1ad47SJeff Kirsher 204dee1ad47SJeff Kirsher /** 205dee1ad47SJeff Kirsher * ixgbe_dcb_config_pfc_82599 - Configure priority flow control 206dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 207dee1ad47SJeff Kirsher * @pfc_en: enabled pfc bitmask 20832701dc2SJohn Fastabend * @prio_tc: priority to tc assignments indexed by priority 209dee1ad47SJeff Kirsher * 210dee1ad47SJeff Kirsher * Configure Priority Flow Control (PFC) for each traffic class. 211dee1ad47SJeff Kirsher */ 21232701dc2SJohn Fastabend s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 213dee1ad47SJeff Kirsher { 214943561d3SAlexander Duyck u32 i, j, fcrtl, reg; 21532701dc2SJohn Fastabend u8 max_tc = 0; 21632701dc2SJohn Fastabend 217943561d3SAlexander Duyck /* Enable Transmit Priority Flow Control */ 218943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY); 219943561d3SAlexander Duyck 220943561d3SAlexander Duyck /* Enable Receive Priority Flow Control */ 221943561d3SAlexander Duyck reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 222943561d3SAlexander Duyck reg |= IXGBE_MFLCN_DPF; 223943561d3SAlexander Duyck 224943561d3SAlexander Duyck /* 225943561d3SAlexander Duyck * X540 supports per TC Rx priority flow control. So 226943561d3SAlexander Duyck * clear all TCs and only enable those that should be 227943561d3SAlexander Duyck * enabled. 228943561d3SAlexander Duyck */ 229943561d3SAlexander Duyck reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 230943561d3SAlexander Duyck 231943561d3SAlexander Duyck if (hw->mac.type == ixgbe_mac_X540) 232943561d3SAlexander Duyck reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; 233943561d3SAlexander Duyck 234943561d3SAlexander Duyck if (pfc_en) 235943561d3SAlexander Duyck reg |= IXGBE_MFLCN_RPFCE; 236943561d3SAlexander Duyck 237943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); 238943561d3SAlexander Duyck 239943561d3SAlexander Duyck for (i = 0; i < MAX_USER_PRIORITY; i++) { 24032701dc2SJohn Fastabend if (prio_tc[i] > max_tc) 24132701dc2SJohn Fastabend max_tc = prio_tc[i]; 242943561d3SAlexander Duyck } 243943561d3SAlexander Duyck 244943561d3SAlexander Duyck fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE; 245dee1ad47SJeff Kirsher 246dee1ad47SJeff Kirsher /* Configure PFC Tx thresholds per TC */ 247943561d3SAlexander Duyck for (i = 0; i <= max_tc; i++) { 24832701dc2SJohn Fastabend int enabled = 0; 24932701dc2SJohn Fastabend 25032701dc2SJohn Fastabend for (j = 0; j < MAX_USER_PRIORITY; j++) { 25132701dc2SJohn Fastabend if ((prio_tc[j] == i) && (pfc_en & (1 << j))) { 25232701dc2SJohn Fastabend enabled = 1; 25332701dc2SJohn Fastabend break; 25432701dc2SJohn Fastabend } 25532701dc2SJohn Fastabend } 256dee1ad47SJeff Kirsher 257943561d3SAlexander Duyck if (enabled) { 258943561d3SAlexander Duyck reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 259943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 260943561d3SAlexander Duyck } else { 261943561d3SAlexander Duyck reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 262943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 263943561d3SAlexander Duyck } 264dee1ad47SJeff Kirsher 265dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); 266dee1ad47SJeff Kirsher } 267dee1ad47SJeff Kirsher 268943561d3SAlexander Duyck for (; i < MAX_TRAFFIC_CLASS; i++) { 269943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 270943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0); 271943561d3SAlexander Duyck } 272943561d3SAlexander Duyck 273dee1ad47SJeff Kirsher /* Configure pause time (2 TCs per register) */ 274943561d3SAlexander Duyck reg = hw->fc.pause_time * 0x00010001; 275dee1ad47SJeff Kirsher for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 276dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 277dee1ad47SJeff Kirsher 278dee1ad47SJeff Kirsher /* Configure flow control refresh threshold value */ 279dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 280dee1ad47SJeff Kirsher 281dee1ad47SJeff Kirsher return 0; 282dee1ad47SJeff Kirsher } 283dee1ad47SJeff Kirsher 284dee1ad47SJeff Kirsher /** 285dee1ad47SJeff Kirsher * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics 286dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 287dee1ad47SJeff Kirsher * 288dee1ad47SJeff Kirsher * Configure queue statistics registers, all queues belonging to same traffic 289dee1ad47SJeff Kirsher * class uses a single set of queue statistics counters. 290dee1ad47SJeff Kirsher */ 291dee1ad47SJeff Kirsher static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw) 292dee1ad47SJeff Kirsher { 293dee1ad47SJeff Kirsher u32 reg = 0; 294dee1ad47SJeff Kirsher u8 i = 0; 295dee1ad47SJeff Kirsher 296dee1ad47SJeff Kirsher /* 297dee1ad47SJeff Kirsher * Receive Queues stats setting 298dee1ad47SJeff Kirsher * 32 RQSMR registers, each configuring 4 queues. 299dee1ad47SJeff Kirsher * Set all 16 queues of each TC to the same stat 300dee1ad47SJeff Kirsher * with TC 'n' going to stat 'n'. 301dee1ad47SJeff Kirsher */ 302dee1ad47SJeff Kirsher for (i = 0; i < 32; i++) { 303dee1ad47SJeff Kirsher reg = 0x01010101 * (i / 4); 304dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 305dee1ad47SJeff Kirsher } 306dee1ad47SJeff Kirsher /* 307dee1ad47SJeff Kirsher * Transmit Queues stats setting 308dee1ad47SJeff Kirsher * 32 TQSM registers, each controlling 4 queues. 309dee1ad47SJeff Kirsher * Set all queues of each TC to the same stat 310dee1ad47SJeff Kirsher * with TC 'n' going to stat 'n'. 311dee1ad47SJeff Kirsher * Tx queues are allocated non-uniformly to TCs: 312dee1ad47SJeff Kirsher * 32, 32, 16, 16, 8, 8, 8, 8. 313dee1ad47SJeff Kirsher */ 314dee1ad47SJeff Kirsher for (i = 0; i < 32; i++) { 315dee1ad47SJeff Kirsher if (i < 8) 316dee1ad47SJeff Kirsher reg = 0x00000000; 317dee1ad47SJeff Kirsher else if (i < 16) 318dee1ad47SJeff Kirsher reg = 0x01010101; 319dee1ad47SJeff Kirsher else if (i < 20) 320dee1ad47SJeff Kirsher reg = 0x02020202; 321dee1ad47SJeff Kirsher else if (i < 24) 322dee1ad47SJeff Kirsher reg = 0x03030303; 323dee1ad47SJeff Kirsher else if (i < 26) 324dee1ad47SJeff Kirsher reg = 0x04040404; 325dee1ad47SJeff Kirsher else if (i < 28) 326dee1ad47SJeff Kirsher reg = 0x05050505; 327dee1ad47SJeff Kirsher else if (i < 30) 328dee1ad47SJeff Kirsher reg = 0x06060606; 329dee1ad47SJeff Kirsher else 330dee1ad47SJeff Kirsher reg = 0x07070707; 331dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); 332dee1ad47SJeff Kirsher } 333dee1ad47SJeff Kirsher 334dee1ad47SJeff Kirsher return 0; 335dee1ad47SJeff Kirsher } 336dee1ad47SJeff Kirsher 337dee1ad47SJeff Kirsher /** 338dee1ad47SJeff Kirsher * ixgbe_dcb_hw_config_82599 - Configure and enable DCB 339dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 340dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 341dee1ad47SJeff Kirsher * @max: max credits index by traffic class 342dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 343dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 344dee1ad47SJeff Kirsher * @pfc_en: enabled pfc bitmask 345dee1ad47SJeff Kirsher * 346dee1ad47SJeff Kirsher * Configure dcb settings and enable dcb mode. 347dee1ad47SJeff Kirsher */ 348dee1ad47SJeff Kirsher s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 349dee1ad47SJeff Kirsher u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) 350dee1ad47SJeff Kirsher { 351dee1ad47SJeff Kirsher ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 352dee1ad47SJeff Kirsher prio_type, prio_tc); 353dee1ad47SJeff Kirsher ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 354dee1ad47SJeff Kirsher bwg_id, prio_type); 355dee1ad47SJeff Kirsher ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 356dee1ad47SJeff Kirsher bwg_id, prio_type, prio_tc); 35732701dc2SJohn Fastabend ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); 358dee1ad47SJeff Kirsher ixgbe_dcb_config_tc_stats_82599(hw); 359dee1ad47SJeff Kirsher 360dee1ad47SJeff Kirsher return 0; 361dee1ad47SJeff Kirsher } 362dee1ad47SJeff Kirsher 363