1dee1ad47SJeff Kirsher /******************************************************************************* 2dee1ad47SJeff Kirsher 3dee1ad47SJeff Kirsher Intel 10 Gigabit PCI Express Linux driver 4434c5e39SDon Skidmore Copyright(c) 1999 - 2013 Intel Corporation. 5dee1ad47SJeff Kirsher 6dee1ad47SJeff Kirsher This program is free software; you can redistribute it and/or modify it 7dee1ad47SJeff Kirsher under the terms and conditions of the GNU General Public License, 8dee1ad47SJeff Kirsher version 2, as published by the Free Software Foundation. 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 11dee1ad47SJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12dee1ad47SJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13dee1ad47SJeff Kirsher more details. 14dee1ad47SJeff Kirsher 15dee1ad47SJeff Kirsher You should have received a copy of the GNU General Public License along with 16dee1ad47SJeff Kirsher this program; if not, write to the Free Software Foundation, Inc., 17dee1ad47SJeff Kirsher 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18dee1ad47SJeff Kirsher 19dee1ad47SJeff Kirsher The full GNU General Public License is included in this distribution in 20dee1ad47SJeff Kirsher the file called "COPYING". 21dee1ad47SJeff Kirsher 22dee1ad47SJeff Kirsher Contact Information: 23b89aae71SJacob Keller Linux NICS <linux.nics@intel.com> 24dee1ad47SJeff Kirsher e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25dee1ad47SJeff Kirsher Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26dee1ad47SJeff Kirsher 27dee1ad47SJeff Kirsher *******************************************************************************/ 28dee1ad47SJeff Kirsher 29dee1ad47SJeff Kirsher #include "ixgbe.h" 30dee1ad47SJeff Kirsher #include "ixgbe_type.h" 31dee1ad47SJeff Kirsher #include "ixgbe_dcb.h" 32dee1ad47SJeff Kirsher #include "ixgbe_dcb_82599.h" 33dee1ad47SJeff Kirsher 34dee1ad47SJeff Kirsher /** 35dee1ad47SJeff Kirsher * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter 36dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 37dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 38dee1ad47SJeff Kirsher * @max: max credits index by traffic class 39dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 40dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 415ba643c6STony Nguyen * @prio_tc: priority to tc assignments indexed by priority 42dee1ad47SJeff Kirsher * 43dee1ad47SJeff Kirsher * Configure Rx Packet Arbiter and credits for each traffic class. 44dee1ad47SJeff Kirsher */ 45dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, 46dee1ad47SJeff Kirsher u16 *refill, 47dee1ad47SJeff Kirsher u16 *max, 48dee1ad47SJeff Kirsher u8 *bwg_id, 49dee1ad47SJeff Kirsher u8 *prio_type, 50dee1ad47SJeff Kirsher u8 *prio_tc) 51dee1ad47SJeff Kirsher { 52dee1ad47SJeff Kirsher u32 reg = 0; 53dee1ad47SJeff Kirsher u32 credit_refill = 0; 54dee1ad47SJeff Kirsher u32 credit_max = 0; 55dee1ad47SJeff Kirsher u8 i = 0; 56dee1ad47SJeff Kirsher 57dee1ad47SJeff Kirsher /* 58dee1ad47SJeff Kirsher * Disable the arbiter before changing parameters 59dee1ad47SJeff Kirsher * (always enable recycle mode; WSP) 60dee1ad47SJeff Kirsher */ 61dee1ad47SJeff Kirsher reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; 62dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 63dee1ad47SJeff Kirsher 6432701dc2SJohn Fastabend /* Map all traffic classes to their UP */ 65dee1ad47SJeff Kirsher reg = 0; 6632701dc2SJohn Fastabend for (i = 0; i < MAX_USER_PRIORITY; i++) 67dee1ad47SJeff Kirsher reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 68dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 69dee1ad47SJeff Kirsher 70dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 71dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 72dee1ad47SJeff Kirsher credit_refill = refill[i]; 73dee1ad47SJeff Kirsher credit_max = max[i]; 74dee1ad47SJeff Kirsher reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); 75dee1ad47SJeff Kirsher 76dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; 77dee1ad47SJeff Kirsher 78dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 79dee1ad47SJeff Kirsher reg |= IXGBE_RTRPT4C_LSP; 80dee1ad47SJeff Kirsher 81dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); 82dee1ad47SJeff Kirsher } 83dee1ad47SJeff Kirsher 84dee1ad47SJeff Kirsher /* 85dee1ad47SJeff Kirsher * Configure Rx packet plane (recycle mode; WSP) and 86dee1ad47SJeff Kirsher * enable arbiter 87dee1ad47SJeff Kirsher */ 88dee1ad47SJeff Kirsher reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; 89dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 90dee1ad47SJeff Kirsher 91dee1ad47SJeff Kirsher return 0; 92dee1ad47SJeff Kirsher } 93dee1ad47SJeff Kirsher 94dee1ad47SJeff Kirsher /** 95dee1ad47SJeff Kirsher * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter 96dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 97dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 98dee1ad47SJeff Kirsher * @max: max credits index by traffic class 99dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 100dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 101dee1ad47SJeff Kirsher * 102dee1ad47SJeff Kirsher * Configure Tx Descriptor Arbiter and credits for each traffic class. 103dee1ad47SJeff Kirsher */ 104dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 105dee1ad47SJeff Kirsher u16 *refill, 106dee1ad47SJeff Kirsher u16 *max, 107dee1ad47SJeff Kirsher u8 *bwg_id, 108dee1ad47SJeff Kirsher u8 *prio_type) 109dee1ad47SJeff Kirsher { 110dee1ad47SJeff Kirsher u32 reg, max_credits; 111dee1ad47SJeff Kirsher u8 i; 112dee1ad47SJeff Kirsher 113dee1ad47SJeff Kirsher /* Clear the per-Tx queue credits; we use per-TC instead */ 114dee1ad47SJeff Kirsher for (i = 0; i < 128; i++) { 115dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 116dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); 117dee1ad47SJeff Kirsher } 118dee1ad47SJeff Kirsher 119dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 120dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 121dee1ad47SJeff Kirsher max_credits = max[i]; 122dee1ad47SJeff Kirsher reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; 123dee1ad47SJeff Kirsher reg |= refill[i]; 124dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT; 125dee1ad47SJeff Kirsher 126dee1ad47SJeff Kirsher if (prio_type[i] == prio_group) 127dee1ad47SJeff Kirsher reg |= IXGBE_RTTDT2C_GSP; 128dee1ad47SJeff Kirsher 129dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 130dee1ad47SJeff Kirsher reg |= IXGBE_RTTDT2C_LSP; 131dee1ad47SJeff Kirsher 132dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); 133dee1ad47SJeff Kirsher } 134dee1ad47SJeff Kirsher 135dee1ad47SJeff Kirsher /* 136dee1ad47SJeff Kirsher * Configure Tx descriptor plane (recycle mode; WSP) and 137dee1ad47SJeff Kirsher * enable arbiter 138dee1ad47SJeff Kirsher */ 139dee1ad47SJeff Kirsher reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; 140dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); 141dee1ad47SJeff Kirsher 142dee1ad47SJeff Kirsher return 0; 143dee1ad47SJeff Kirsher } 144dee1ad47SJeff Kirsher 145dee1ad47SJeff Kirsher /** 146dee1ad47SJeff Kirsher * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter 147dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 148dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 149dee1ad47SJeff Kirsher * @max: max credits index by traffic class 150dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 151dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 1525ba643c6STony Nguyen * @prio_tc: priority to tc assignments indexed by priority 153dee1ad47SJeff Kirsher * 154dee1ad47SJeff Kirsher * Configure Tx Packet Arbiter and credits for each traffic class. 155dee1ad47SJeff Kirsher */ 156dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, 157dee1ad47SJeff Kirsher u16 *refill, 158dee1ad47SJeff Kirsher u16 *max, 159dee1ad47SJeff Kirsher u8 *bwg_id, 160dee1ad47SJeff Kirsher u8 *prio_type, 161dee1ad47SJeff Kirsher u8 *prio_tc) 162dee1ad47SJeff Kirsher { 163dee1ad47SJeff Kirsher u32 reg; 164dee1ad47SJeff Kirsher u8 i; 165dee1ad47SJeff Kirsher 166dee1ad47SJeff Kirsher /* 167dee1ad47SJeff Kirsher * Disable the arbiter before changing parameters 168dee1ad47SJeff Kirsher * (always enable recycle mode; SP; arb delay) 169dee1ad47SJeff Kirsher */ 170dee1ad47SJeff Kirsher reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 171dee1ad47SJeff Kirsher (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) | 172dee1ad47SJeff Kirsher IXGBE_RTTPCS_ARBDIS; 173dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 174dee1ad47SJeff Kirsher 17532701dc2SJohn Fastabend /* Map all traffic classes to their UP */ 176dee1ad47SJeff Kirsher reg = 0; 17732701dc2SJohn Fastabend for (i = 0; i < MAX_USER_PRIORITY; i++) 178dee1ad47SJeff Kirsher reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); 179dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); 180dee1ad47SJeff Kirsher 181dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 182dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 183dee1ad47SJeff Kirsher reg = refill[i]; 184dee1ad47SJeff Kirsher reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT; 185dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT; 186dee1ad47SJeff Kirsher 187dee1ad47SJeff Kirsher if (prio_type[i] == prio_group) 188dee1ad47SJeff Kirsher reg |= IXGBE_RTTPT2C_GSP; 189dee1ad47SJeff Kirsher 190dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 191dee1ad47SJeff Kirsher reg |= IXGBE_RTTPT2C_LSP; 192dee1ad47SJeff Kirsher 193dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); 194dee1ad47SJeff Kirsher } 195dee1ad47SJeff Kirsher 196dee1ad47SJeff Kirsher /* 197dee1ad47SJeff Kirsher * Configure Tx packet plane (recycle mode; SP; arb delay) and 198dee1ad47SJeff Kirsher * enable arbiter 199dee1ad47SJeff Kirsher */ 200dee1ad47SJeff Kirsher reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | 201dee1ad47SJeff Kirsher (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT); 202dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); 203dee1ad47SJeff Kirsher 204dee1ad47SJeff Kirsher return 0; 205dee1ad47SJeff Kirsher } 206dee1ad47SJeff Kirsher 207dee1ad47SJeff Kirsher /** 208dee1ad47SJeff Kirsher * ixgbe_dcb_config_pfc_82599 - Configure priority flow control 209dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 210dee1ad47SJeff Kirsher * @pfc_en: enabled pfc bitmask 21132701dc2SJohn Fastabend * @prio_tc: priority to tc assignments indexed by priority 212dee1ad47SJeff Kirsher * 213dee1ad47SJeff Kirsher * Configure Priority Flow Control (PFC) for each traffic class. 214dee1ad47SJeff Kirsher */ 21532701dc2SJohn Fastabend s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 216dee1ad47SJeff Kirsher { 217943561d3SAlexander Duyck u32 i, j, fcrtl, reg; 21832701dc2SJohn Fastabend u8 max_tc = 0; 21932701dc2SJohn Fastabend 220943561d3SAlexander Duyck /* Enable Transmit Priority Flow Control */ 221943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY); 222943561d3SAlexander Duyck 223943561d3SAlexander Duyck /* Enable Receive Priority Flow Control */ 224943561d3SAlexander Duyck reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 225943561d3SAlexander Duyck reg |= IXGBE_MFLCN_DPF; 226943561d3SAlexander Duyck 227943561d3SAlexander Duyck /* 228cb78cf12SVasu Dev * X540 & X550 supports per TC Rx priority flow control. 229cb78cf12SVasu Dev * So clear all TCs and only enable those that should be 230943561d3SAlexander Duyck * enabled. 231943561d3SAlexander Duyck */ 232943561d3SAlexander Duyck reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 233943561d3SAlexander Duyck 234cb78cf12SVasu Dev if (hw->mac.type >= ixgbe_mac_X540) 235943561d3SAlexander Duyck reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; 236943561d3SAlexander Duyck 237943561d3SAlexander Duyck if (pfc_en) 238943561d3SAlexander Duyck reg |= IXGBE_MFLCN_RPFCE; 239943561d3SAlexander Duyck 240943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); 241943561d3SAlexander Duyck 242943561d3SAlexander Duyck for (i = 0; i < MAX_USER_PRIORITY; i++) { 24332701dc2SJohn Fastabend if (prio_tc[i] > max_tc) 24432701dc2SJohn Fastabend max_tc = prio_tc[i]; 245943561d3SAlexander Duyck } 246943561d3SAlexander Duyck 247dee1ad47SJeff Kirsher 248dee1ad47SJeff Kirsher /* Configure PFC Tx thresholds per TC */ 249943561d3SAlexander Duyck for (i = 0; i <= max_tc; i++) { 25032701dc2SJohn Fastabend int enabled = 0; 25132701dc2SJohn Fastabend 25232701dc2SJohn Fastabend for (j = 0; j < MAX_USER_PRIORITY; j++) { 253b4f47a48SJacob Keller if ((prio_tc[j] == i) && (pfc_en & BIT(j))) { 25432701dc2SJohn Fastabend enabled = 1; 25532701dc2SJohn Fastabend break; 25632701dc2SJohn Fastabend } 25732701dc2SJohn Fastabend } 258dee1ad47SJeff Kirsher 259943561d3SAlexander Duyck if (enabled) { 260943561d3SAlexander Duyck reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 261e5776620SJacob Keller fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 262943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 263943561d3SAlexander Duyck } else { 264bc1fc64fSMark Rustad /* In order to prevent Tx hangs when the internal Tx 265bc1fc64fSMark Rustad * switch is enabled we must set the high water mark 266bc1fc64fSMark Rustad * to the Rx packet buffer size - 24KB. This allows 267bc1fc64fSMark Rustad * the Tx switch to function even under heavy Rx 268bc1fc64fSMark Rustad * workloads. 269bc1fc64fSMark Rustad */ 270bc1fc64fSMark Rustad reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 271943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 272943561d3SAlexander Duyck } 273dee1ad47SJeff Kirsher 274dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); 275dee1ad47SJeff Kirsher } 276dee1ad47SJeff Kirsher 277943561d3SAlexander Duyck for (; i < MAX_TRAFFIC_CLASS; i++) { 278943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 279943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0); 280943561d3SAlexander Duyck } 281943561d3SAlexander Duyck 282dee1ad47SJeff Kirsher /* Configure pause time (2 TCs per register) */ 283943561d3SAlexander Duyck reg = hw->fc.pause_time * 0x00010001; 284dee1ad47SJeff Kirsher for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 285dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 286dee1ad47SJeff Kirsher 287dee1ad47SJeff Kirsher /* Configure flow control refresh threshold value */ 288dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 289dee1ad47SJeff Kirsher 290dee1ad47SJeff Kirsher return 0; 291dee1ad47SJeff Kirsher } 292dee1ad47SJeff Kirsher 293dee1ad47SJeff Kirsher /** 294dee1ad47SJeff Kirsher * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics 295dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 296dee1ad47SJeff Kirsher * 297dee1ad47SJeff Kirsher * Configure queue statistics registers, all queues belonging to same traffic 298dee1ad47SJeff Kirsher * class uses a single set of queue statistics counters. 299dee1ad47SJeff Kirsher */ 300dee1ad47SJeff Kirsher static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw) 301dee1ad47SJeff Kirsher { 302dee1ad47SJeff Kirsher u32 reg = 0; 303dee1ad47SJeff Kirsher u8 i = 0; 304dee1ad47SJeff Kirsher 305dee1ad47SJeff Kirsher /* 306dee1ad47SJeff Kirsher * Receive Queues stats setting 307dee1ad47SJeff Kirsher * 32 RQSMR registers, each configuring 4 queues. 308dee1ad47SJeff Kirsher * Set all 16 queues of each TC to the same stat 309dee1ad47SJeff Kirsher * with TC 'n' going to stat 'n'. 310dee1ad47SJeff Kirsher */ 311dee1ad47SJeff Kirsher for (i = 0; i < 32; i++) { 312dee1ad47SJeff Kirsher reg = 0x01010101 * (i / 4); 313dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 314dee1ad47SJeff Kirsher } 315dee1ad47SJeff Kirsher /* 316dee1ad47SJeff Kirsher * Transmit Queues stats setting 317dee1ad47SJeff Kirsher * 32 TQSM registers, each controlling 4 queues. 318dee1ad47SJeff Kirsher * Set all queues of each TC to the same stat 319dee1ad47SJeff Kirsher * with TC 'n' going to stat 'n'. 320dee1ad47SJeff Kirsher * Tx queues are allocated non-uniformly to TCs: 321dee1ad47SJeff Kirsher * 32, 32, 16, 16, 8, 8, 8, 8. 322dee1ad47SJeff Kirsher */ 323dee1ad47SJeff Kirsher for (i = 0; i < 32; i++) { 324dee1ad47SJeff Kirsher if (i < 8) 325dee1ad47SJeff Kirsher reg = 0x00000000; 326dee1ad47SJeff Kirsher else if (i < 16) 327dee1ad47SJeff Kirsher reg = 0x01010101; 328dee1ad47SJeff Kirsher else if (i < 20) 329dee1ad47SJeff Kirsher reg = 0x02020202; 330dee1ad47SJeff Kirsher else if (i < 24) 331dee1ad47SJeff Kirsher reg = 0x03030303; 332dee1ad47SJeff Kirsher else if (i < 26) 333dee1ad47SJeff Kirsher reg = 0x04040404; 334dee1ad47SJeff Kirsher else if (i < 28) 335dee1ad47SJeff Kirsher reg = 0x05050505; 336dee1ad47SJeff Kirsher else if (i < 30) 337dee1ad47SJeff Kirsher reg = 0x06060606; 338dee1ad47SJeff Kirsher else 339dee1ad47SJeff Kirsher reg = 0x07070707; 340dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); 341dee1ad47SJeff Kirsher } 342dee1ad47SJeff Kirsher 343dee1ad47SJeff Kirsher return 0; 344dee1ad47SJeff Kirsher } 345dee1ad47SJeff Kirsher 346dee1ad47SJeff Kirsher /** 347dee1ad47SJeff Kirsher * ixgbe_dcb_hw_config_82599 - Configure and enable DCB 348dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 3495ba643c6STony Nguyen * @pfc_en: enabled pfc bitmask 350dee1ad47SJeff Kirsher * @refill: refill credits index by traffic class 351dee1ad47SJeff Kirsher * @max: max credits index by traffic class 352dee1ad47SJeff Kirsher * @bwg_id: bandwidth grouping indexed by traffic class 353dee1ad47SJeff Kirsher * @prio_type: priority type indexed by traffic class 3545ba643c6STony Nguyen * @prio_tc: priority to tc assignments indexed by priority 355dee1ad47SJeff Kirsher * 356dee1ad47SJeff Kirsher * Configure dcb settings and enable dcb mode. 357dee1ad47SJeff Kirsher */ 358dee1ad47SJeff Kirsher s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 359dee1ad47SJeff Kirsher u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) 360dee1ad47SJeff Kirsher { 361dee1ad47SJeff Kirsher ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 362dee1ad47SJeff Kirsher prio_type, prio_tc); 363dee1ad47SJeff Kirsher ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 364dee1ad47SJeff Kirsher bwg_id, prio_type); 365dee1ad47SJeff Kirsher ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 366dee1ad47SJeff Kirsher bwg_id, prio_type, prio_tc); 36732701dc2SJohn Fastabend ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); 368dee1ad47SJeff Kirsher ixgbe_dcb_config_tc_stats_82599(hw); 369dee1ad47SJeff Kirsher 370dee1ad47SJeff Kirsher return 0; 371dee1ad47SJeff Kirsher } 372dee1ad47SJeff Kirsher 373