1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* Linux PRO/1000 Ethernet Driver main header file */ 25 26 #ifndef _IGB_H_ 27 #define _IGB_H_ 28 29 #include "e1000_mac.h" 30 #include "e1000_82575.h" 31 32 #include <linux/timecounter.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <linux/bitops.h> 36 #include <linux/if_vlan.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/pci.h> 40 #include <linux/mdio.h> 41 42 struct igb_adapter; 43 44 #define E1000_PCS_CFG_IGN_SD 1 45 46 /* Interrupt defines */ 47 #define IGB_START_ITR 648 /* ~6000 ints/sec */ 48 #define IGB_4K_ITR 980 49 #define IGB_20K_ITR 196 50 #define IGB_70K_ITR 56 51 52 /* TX/RX descriptor defines */ 53 #define IGB_DEFAULT_TXD 256 54 #define IGB_DEFAULT_TX_WORK 128 55 #define IGB_MIN_TXD 80 56 #define IGB_MAX_TXD 4096 57 58 #define IGB_DEFAULT_RXD 256 59 #define IGB_MIN_RXD 80 60 #define IGB_MAX_RXD 4096 61 62 #define IGB_DEFAULT_ITR 3 /* dynamic */ 63 #define IGB_MAX_ITR_USECS 10000 64 #define IGB_MIN_ITR_USECS 10 65 #define NON_Q_VECTORS 1 66 #define MAX_Q_VECTORS 8 67 #define MAX_MSIX_ENTRIES 10 68 69 /* Transmit and receive queues */ 70 #define IGB_MAX_RX_QUEUES 8 71 #define IGB_MAX_RX_QUEUES_82575 4 72 #define IGB_MAX_RX_QUEUES_I211 2 73 #define IGB_MAX_TX_QUEUES 8 74 #define IGB_MAX_VF_MC_ENTRIES 30 75 #define IGB_MAX_VF_FUNCTIONS 8 76 #define IGB_MAX_VFTA_ENTRIES 128 77 #define IGB_82576_VF_DEV_ID 0x10CA 78 #define IGB_I350_VF_DEV_ID 0x1520 79 80 /* NVM version defines */ 81 #define IGB_MAJOR_MASK 0xF000 82 #define IGB_MINOR_MASK 0x0FF0 83 #define IGB_BUILD_MASK 0x000F 84 #define IGB_COMB_VER_MASK 0x00FF 85 #define IGB_MAJOR_SHIFT 12 86 #define IGB_MINOR_SHIFT 4 87 #define IGB_COMB_VER_SHFT 8 88 #define IGB_NVM_VER_INVALID 0xFFFF 89 #define IGB_ETRACK_SHIFT 16 90 #define NVM_ETRACK_WORD 0x0042 91 #define NVM_COMB_VER_OFF 0x0083 92 #define NVM_COMB_VER_PTR 0x003d 93 94 struct vf_data_storage { 95 unsigned char vf_mac_addresses[ETH_ALEN]; 96 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 97 u16 num_vf_mc_hashes; 98 u32 flags; 99 unsigned long last_nack; 100 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 101 u16 pf_qos; 102 u16 tx_rate; 103 bool spoofchk_enabled; 104 }; 105 106 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 107 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 108 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 109 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 110 111 /* RX descriptor control thresholds. 112 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 113 * descriptors available in its onboard memory. 114 * Setting this to 0 disables RX descriptor prefetch. 115 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 116 * available in host memory. 117 * If PTHRESH is 0, this should also be 0. 118 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 119 * descriptors until either it has this many to write back, or the 120 * ITR timer expires. 121 */ 122 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) 123 #define IGB_RX_HTHRESH 8 124 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 125 #define IGB_TX_HTHRESH 1 126 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 127 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4) 128 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 129 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16) 130 131 /* this is the size past which hardware will drop packets when setting LPE=0 */ 132 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 133 134 /* Supported Rx Buffer Sizes */ 135 #define IGB_RXBUFFER_256 256 136 #define IGB_RXBUFFER_2048 2048 137 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 138 #define IGB_RX_BUFSZ IGB_RXBUFFER_2048 139 140 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 141 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 142 143 #define AUTO_ALL_MODES 0 144 #define IGB_EEPROM_APME 0x0400 145 146 #ifndef IGB_MASTER_SLAVE 147 /* Switch to override PHY master/slave setting */ 148 #define IGB_MASTER_SLAVE e1000_ms_hw_default 149 #endif 150 151 #define IGB_MNG_VLAN_NONE -1 152 153 enum igb_tx_flags { 154 /* cmd_type flags */ 155 IGB_TX_FLAGS_VLAN = 0x01, 156 IGB_TX_FLAGS_TSO = 0x02, 157 IGB_TX_FLAGS_TSTAMP = 0x04, 158 159 /* olinfo flags */ 160 IGB_TX_FLAGS_IPV4 = 0x10, 161 IGB_TX_FLAGS_CSUM = 0x20, 162 }; 163 164 /* VLAN info */ 165 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 166 #define IGB_TX_FLAGS_VLAN_SHIFT 16 167 168 /* The largest size we can write to the descriptor is 65535. In order to 169 * maintain a power of two alignment we have to limit ourselves to 32K. 170 */ 171 #define IGB_MAX_TXD_PWR 15 172 #define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR) 173 174 /* Tx Descriptors needed, worst case */ 175 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) 176 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 177 178 /* EEPROM byte offsets */ 179 #define IGB_SFF_8472_SWAP 0x5C 180 #define IGB_SFF_8472_COMP 0x5E 181 182 /* Bitmasks */ 183 #define IGB_SFF_ADDRESSING_MODE 0x4 184 #define IGB_SFF_8472_UNSUP 0x00 185 186 /* wrapper around a pointer to a socket buffer, 187 * so a DMA handle can be stored along with the buffer 188 */ 189 struct igb_tx_buffer { 190 union e1000_adv_tx_desc *next_to_watch; 191 unsigned long time_stamp; 192 struct sk_buff *skb; 193 unsigned int bytecount; 194 u16 gso_segs; 195 __be16 protocol; 196 197 DEFINE_DMA_UNMAP_ADDR(dma); 198 DEFINE_DMA_UNMAP_LEN(len); 199 u32 tx_flags; 200 }; 201 202 struct igb_rx_buffer { 203 dma_addr_t dma; 204 struct page *page; 205 unsigned int page_offset; 206 }; 207 208 struct igb_tx_queue_stats { 209 u64 packets; 210 u64 bytes; 211 u64 restart_queue; 212 u64 restart_queue2; 213 }; 214 215 struct igb_rx_queue_stats { 216 u64 packets; 217 u64 bytes; 218 u64 drops; 219 u64 csum_err; 220 u64 alloc_failed; 221 }; 222 223 struct igb_ring_container { 224 struct igb_ring *ring; /* pointer to linked list of rings */ 225 unsigned int total_bytes; /* total bytes processed this int */ 226 unsigned int total_packets; /* total packets processed this int */ 227 u16 work_limit; /* total work allowed per interrupt */ 228 u8 count; /* total number of rings in vector */ 229 u8 itr; /* current ITR setting for ring */ 230 }; 231 232 struct igb_ring { 233 struct igb_q_vector *q_vector; /* backlink to q_vector */ 234 struct net_device *netdev; /* back pointer to net_device */ 235 struct device *dev; /* device pointer for dma mapping */ 236 union { /* array of buffer info structs */ 237 struct igb_tx_buffer *tx_buffer_info; 238 struct igb_rx_buffer *rx_buffer_info; 239 }; 240 void *desc; /* descriptor ring memory */ 241 unsigned long flags; /* ring specific flags */ 242 void __iomem *tail; /* pointer to ring tail register */ 243 dma_addr_t dma; /* phys address of the ring */ 244 unsigned int size; /* length of desc. ring in bytes */ 245 246 u16 count; /* number of desc. in the ring */ 247 u8 queue_index; /* logical index of the ring*/ 248 u8 reg_idx; /* physical index of the ring */ 249 250 /* everything past this point are written often */ 251 u16 next_to_clean; 252 u16 next_to_use; 253 u16 next_to_alloc; 254 255 union { 256 /* TX */ 257 struct { 258 struct igb_tx_queue_stats tx_stats; 259 struct u64_stats_sync tx_syncp; 260 struct u64_stats_sync tx_syncp2; 261 }; 262 /* RX */ 263 struct { 264 struct sk_buff *skb; 265 struct igb_rx_queue_stats rx_stats; 266 struct u64_stats_sync rx_syncp; 267 }; 268 }; 269 } ____cacheline_internodealigned_in_smp; 270 271 struct igb_q_vector { 272 struct igb_adapter *adapter; /* backlink */ 273 int cpu; /* CPU for DCA */ 274 u32 eims_value; /* EIMS mask value */ 275 276 u16 itr_val; 277 u8 set_itr; 278 void __iomem *itr_register; 279 280 struct igb_ring_container rx, tx; 281 282 struct napi_struct napi; 283 struct rcu_head rcu; /* to avoid race with update stats on free */ 284 char name[IFNAMSIZ + 9]; 285 286 /* for dynamic allocation of rings associated with this q_vector */ 287 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; 288 }; 289 290 enum e1000_ring_flags_t { 291 IGB_RING_FLAG_RX_SCTP_CSUM, 292 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 293 IGB_RING_FLAG_TX_CTX_IDX, 294 IGB_RING_FLAG_TX_DETECT_HANG 295 }; 296 297 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 298 299 #define IGB_RX_DESC(R, i) \ 300 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 301 #define IGB_TX_DESC(R, i) \ 302 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 303 #define IGB_TX_CTXTDESC(R, i) \ 304 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 305 306 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 307 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 308 const u32 stat_err_bits) 309 { 310 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 311 } 312 313 /* igb_desc_unused - calculate if we have unused descriptors */ 314 static inline int igb_desc_unused(struct igb_ring *ring) 315 { 316 if (ring->next_to_clean > ring->next_to_use) 317 return ring->next_to_clean - ring->next_to_use - 1; 318 319 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 320 } 321 322 #ifdef CONFIG_IGB_HWMON 323 324 #define IGB_HWMON_TYPE_LOC 0 325 #define IGB_HWMON_TYPE_TEMP 1 326 #define IGB_HWMON_TYPE_CAUTION 2 327 #define IGB_HWMON_TYPE_MAX 3 328 329 struct hwmon_attr { 330 struct device_attribute dev_attr; 331 struct e1000_hw *hw; 332 struct e1000_thermal_diode_data *sensor; 333 char name[12]; 334 }; 335 336 struct hwmon_buff { 337 struct attribute_group group; 338 const struct attribute_group *groups[2]; 339 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1]; 340 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4]; 341 unsigned int n_hwmon; 342 }; 343 #endif 344 345 #define IGB_N_EXTTS 2 346 #define IGB_N_PEROUT 2 347 #define IGB_N_SDP 4 348 #define IGB_RETA_SIZE 128 349 350 /* board specific private data structure */ 351 struct igb_adapter { 352 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 353 354 struct net_device *netdev; 355 356 unsigned long state; 357 unsigned int flags; 358 359 unsigned int num_q_vectors; 360 struct msix_entry msix_entries[MAX_MSIX_ENTRIES]; 361 362 /* Interrupt Throttle Rate */ 363 u32 rx_itr_setting; 364 u32 tx_itr_setting; 365 u16 tx_itr; 366 u16 rx_itr; 367 368 /* TX */ 369 u16 tx_work_limit; 370 u32 tx_timeout_count; 371 int num_tx_queues; 372 struct igb_ring *tx_ring[16]; 373 374 /* RX */ 375 int num_rx_queues; 376 struct igb_ring *rx_ring[16]; 377 378 u32 max_frame_size; 379 u32 min_frame_size; 380 381 struct timer_list watchdog_timer; 382 struct timer_list phy_info_timer; 383 384 u16 mng_vlan_id; 385 u32 bd_number; 386 u32 wol; 387 u32 en_mng_pt; 388 u16 link_speed; 389 u16 link_duplex; 390 391 u8 __iomem *io_addr; /* Mainly for iounmap use */ 392 393 struct work_struct reset_task; 394 struct work_struct watchdog_task; 395 bool fc_autoneg; 396 u8 tx_timeout_factor; 397 struct timer_list blink_timer; 398 unsigned long led_status; 399 400 /* OS defined structs */ 401 struct pci_dev *pdev; 402 403 spinlock_t stats64_lock; 404 struct rtnl_link_stats64 stats64; 405 406 /* structs defined in e1000_hw.h */ 407 struct e1000_hw hw; 408 struct e1000_hw_stats stats; 409 struct e1000_phy_info phy_info; 410 411 u32 test_icr; 412 struct igb_ring test_tx_ring; 413 struct igb_ring test_rx_ring; 414 415 int msg_enable; 416 417 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 418 u32 eims_enable_mask; 419 u32 eims_other; 420 421 /* to not mess up cache alignment, always add to the bottom */ 422 u16 tx_ring_count; 423 u16 rx_ring_count; 424 unsigned int vfs_allocated_count; 425 struct vf_data_storage *vf_data; 426 int vf_rate_link_speed; 427 u32 rss_queues; 428 u32 wvbr; 429 u32 *shadow_vfta; 430 431 struct ptp_clock *ptp_clock; 432 struct ptp_clock_info ptp_caps; 433 struct delayed_work ptp_overflow_work; 434 struct work_struct ptp_tx_work; 435 struct sk_buff *ptp_tx_skb; 436 struct hwtstamp_config tstamp_config; 437 unsigned long ptp_tx_start; 438 unsigned long last_rx_ptp_check; 439 unsigned long last_rx_timestamp; 440 spinlock_t tmreg_lock; 441 struct cyclecounter cc; 442 struct timecounter tc; 443 u32 tx_hwtstamp_timeouts; 444 u32 rx_hwtstamp_cleared; 445 446 struct ptp_pin_desc sdp_config[IGB_N_SDP]; 447 struct { 448 struct timespec64 start; 449 struct timespec64 period; 450 } perout[IGB_N_PEROUT]; 451 452 char fw_version[32]; 453 #ifdef CONFIG_IGB_HWMON 454 struct hwmon_buff *igb_hwmon_buff; 455 bool ets; 456 #endif 457 struct i2c_algo_bit_data i2c_algo; 458 struct i2c_adapter i2c_adap; 459 struct i2c_client *i2c_client; 460 u32 rss_indir_tbl_init; 461 u8 rss_indir_tbl[IGB_RETA_SIZE]; 462 463 unsigned long link_check_timeout; 464 int copper_tries; 465 struct e1000_info ei; 466 u16 eee_advert; 467 }; 468 469 #define IGB_FLAG_HAS_MSI (1 << 0) 470 #define IGB_FLAG_DCA_ENABLED (1 << 1) 471 #define IGB_FLAG_QUAD_PORT_A (1 << 2) 472 #define IGB_FLAG_QUEUE_PAIRS (1 << 3) 473 #define IGB_FLAG_DMAC (1 << 4) 474 #define IGB_FLAG_PTP (1 << 5) 475 #define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6) 476 #define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7) 477 #define IGB_FLAG_WOL_SUPPORTED (1 << 8) 478 #define IGB_FLAG_NEED_LINK_UPDATE (1 << 9) 479 #define IGB_FLAG_MEDIA_RESET (1 << 10) 480 #define IGB_FLAG_MAS_CAPABLE (1 << 11) 481 #define IGB_FLAG_MAS_ENABLE (1 << 12) 482 #define IGB_FLAG_HAS_MSIX (1 << 13) 483 #define IGB_FLAG_EEE (1 << 14) 484 485 /* Media Auto Sense */ 486 #define IGB_MAS_ENABLE_0 0X0001 487 #define IGB_MAS_ENABLE_1 0X0002 488 #define IGB_MAS_ENABLE_2 0X0004 489 #define IGB_MAS_ENABLE_3 0X0008 490 491 /* DMA Coalescing defines */ 492 #define IGB_MIN_TXPBSIZE 20408 493 #define IGB_TX_BUF_4096 4096 494 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 495 496 #define IGB_82576_TSYNC_SHIFT 19 497 #define IGB_TS_HDR_LEN 16 498 enum e1000_state_t { 499 __IGB_TESTING, 500 __IGB_RESETTING, 501 __IGB_DOWN, 502 __IGB_PTP_TX_IN_PROGRESS, 503 }; 504 505 enum igb_boards { 506 board_82575, 507 }; 508 509 extern char igb_driver_name[]; 510 extern char igb_driver_version[]; 511 512 int igb_up(struct igb_adapter *); 513 void igb_down(struct igb_adapter *); 514 void igb_reinit_locked(struct igb_adapter *); 515 void igb_reset(struct igb_adapter *); 516 int igb_reinit_queues(struct igb_adapter *); 517 void igb_write_rss_indir_tbl(struct igb_adapter *); 518 int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 519 int igb_setup_tx_resources(struct igb_ring *); 520 int igb_setup_rx_resources(struct igb_ring *); 521 void igb_free_tx_resources(struct igb_ring *); 522 void igb_free_rx_resources(struct igb_ring *); 523 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 524 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 525 void igb_setup_tctl(struct igb_adapter *); 526 void igb_setup_rctl(struct igb_adapter *); 527 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 528 void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *); 529 void igb_alloc_rx_buffers(struct igb_ring *, u16); 530 void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 531 bool igb_has_link(struct igb_adapter *adapter); 532 void igb_set_ethtool_ops(struct net_device *); 533 void igb_power_up_link(struct igb_adapter *); 534 void igb_set_fw_version(struct igb_adapter *); 535 void igb_ptp_init(struct igb_adapter *adapter); 536 void igb_ptp_stop(struct igb_adapter *adapter); 537 void igb_ptp_reset(struct igb_adapter *adapter); 538 void igb_ptp_rx_hang(struct igb_adapter *adapter); 539 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb); 540 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va, 541 struct sk_buff *skb); 542 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 543 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 544 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32); 545 #ifdef CONFIG_IGB_HWMON 546 void igb_sysfs_exit(struct igb_adapter *adapter); 547 int igb_sysfs_init(struct igb_adapter *adapter); 548 #endif 549 static inline s32 igb_reset_phy(struct e1000_hw *hw) 550 { 551 if (hw->phy.ops.reset) 552 return hw->phy.ops.reset(hw); 553 554 return 0; 555 } 556 557 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 558 { 559 if (hw->phy.ops.read_reg) 560 return hw->phy.ops.read_reg(hw, offset, data); 561 562 return 0; 563 } 564 565 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 566 { 567 if (hw->phy.ops.write_reg) 568 return hw->phy.ops.write_reg(hw, offset, data); 569 570 return 0; 571 } 572 573 static inline s32 igb_get_phy_info(struct e1000_hw *hw) 574 { 575 if (hw->phy.ops.get_phy_info) 576 return hw->phy.ops.get_phy_info(hw); 577 578 return 0; 579 } 580 581 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 582 { 583 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 584 } 585 586 #endif /* _IGB_H_ */ 587