1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 29 /* Linux PRO/1000 Ethernet Driver main header file */ 30 31 #ifndef _IGB_H_ 32 #define _IGB_H_ 33 34 #include "e1000_mac.h" 35 #include "e1000_82575.h" 36 37 #include <linux/clocksource.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/ptp_clock_kernel.h> 40 #include <linux/bitops.h> 41 #include <linux/if_vlan.h> 42 #include <linux/i2c.h> 43 #include <linux/i2c-algo-bit.h> 44 45 struct igb_adapter; 46 47 #define E1000_PCS_CFG_IGN_SD 1 48 49 /* Interrupt defines */ 50 #define IGB_START_ITR 648 /* ~6000 ints/sec */ 51 #define IGB_4K_ITR 980 52 #define IGB_20K_ITR 196 53 #define IGB_70K_ITR 56 54 55 /* TX/RX descriptor defines */ 56 #define IGB_DEFAULT_TXD 256 57 #define IGB_DEFAULT_TX_WORK 128 58 #define IGB_MIN_TXD 80 59 #define IGB_MAX_TXD 4096 60 61 #define IGB_DEFAULT_RXD 256 62 #define IGB_MIN_RXD 80 63 #define IGB_MAX_RXD 4096 64 65 #define IGB_DEFAULT_ITR 3 /* dynamic */ 66 #define IGB_MAX_ITR_USECS 10000 67 #define IGB_MIN_ITR_USECS 10 68 #define NON_Q_VECTORS 1 69 #define MAX_Q_VECTORS 8 70 71 /* Transmit and receive queues */ 72 #define IGB_MAX_RX_QUEUES 8 73 #define IGB_MAX_RX_QUEUES_82575 4 74 #define IGB_MAX_RX_QUEUES_I211 2 75 #define IGB_MAX_TX_QUEUES 8 76 #define IGB_MAX_VF_MC_ENTRIES 30 77 #define IGB_MAX_VF_FUNCTIONS 8 78 #define IGB_MAX_VFTA_ENTRIES 128 79 #define IGB_82576_VF_DEV_ID 0x10CA 80 #define IGB_I350_VF_DEV_ID 0x1520 81 82 /* NVM version defines */ 83 #define IGB_MAJOR_MASK 0xF000 84 #define IGB_MINOR_MASK 0x0FF0 85 #define IGB_BUILD_MASK 0x000F 86 #define IGB_COMB_VER_MASK 0x00FF 87 #define IGB_MAJOR_SHIFT 12 88 #define IGB_MINOR_SHIFT 4 89 #define IGB_COMB_VER_SHFT 8 90 #define IGB_NVM_VER_INVALID 0xFFFF 91 #define IGB_ETRACK_SHIFT 16 92 #define NVM_ETRACK_WORD 0x0042 93 #define NVM_COMB_VER_OFF 0x0083 94 #define NVM_COMB_VER_PTR 0x003d 95 96 struct vf_data_storage { 97 unsigned char vf_mac_addresses[ETH_ALEN]; 98 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 99 u16 num_vf_mc_hashes; 100 u16 vlans_enabled; 101 u32 flags; 102 unsigned long last_nack; 103 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 104 u16 pf_qos; 105 u16 tx_rate; 106 }; 107 108 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 109 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 110 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 111 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 112 113 /* RX descriptor control thresholds. 114 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 115 * descriptors available in its onboard memory. 116 * Setting this to 0 disables RX descriptor prefetch. 117 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 118 * available in host memory. 119 * If PTHRESH is 0, this should also be 0. 120 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 121 * descriptors until either it has this many to write back, or the 122 * ITR timer expires. 123 */ 124 #define IGB_RX_PTHRESH 8 125 #define IGB_RX_HTHRESH 8 126 #define IGB_TX_PTHRESH 8 127 #define IGB_TX_HTHRESH 1 128 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 129 adapter->msix_entries) ? 1 : 4) 130 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 131 adapter->msix_entries) ? 1 : 16) 132 133 /* this is the size past which hardware will drop packets when setting LPE=0 */ 134 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 135 136 /* Supported Rx Buffer Sizes */ 137 #define IGB_RXBUFFER_256 256 138 #define IGB_RXBUFFER_2048 2048 139 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 140 #define IGB_RX_BUFSZ IGB_RXBUFFER_2048 141 142 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 143 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 144 145 #define AUTO_ALL_MODES 0 146 #define IGB_EEPROM_APME 0x0400 147 148 #ifndef IGB_MASTER_SLAVE 149 /* Switch to override PHY master/slave setting */ 150 #define IGB_MASTER_SLAVE e1000_ms_hw_default 151 #endif 152 153 #define IGB_MNG_VLAN_NONE -1 154 155 enum igb_tx_flags { 156 /* cmd_type flags */ 157 IGB_TX_FLAGS_VLAN = 0x01, 158 IGB_TX_FLAGS_TSO = 0x02, 159 IGB_TX_FLAGS_TSTAMP = 0x04, 160 161 /* olinfo flags */ 162 IGB_TX_FLAGS_IPV4 = 0x10, 163 IGB_TX_FLAGS_CSUM = 0x20, 164 }; 165 166 /* VLAN info */ 167 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 168 #define IGB_TX_FLAGS_VLAN_SHIFT 16 169 170 /* 171 * The largest size we can write to the descriptor is 65535. In order to 172 * maintain a power of two alignment we have to limit ourselves to 32K. 173 */ 174 #define IGB_MAX_TXD_PWR 15 175 #define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR) 176 177 /* Tx Descriptors needed, worst case */ 178 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) 179 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 180 181 /* wrapper around a pointer to a socket buffer, 182 * so a DMA handle can be stored along with the buffer */ 183 struct igb_tx_buffer { 184 union e1000_adv_tx_desc *next_to_watch; 185 unsigned long time_stamp; 186 struct sk_buff *skb; 187 unsigned int bytecount; 188 u16 gso_segs; 189 __be16 protocol; 190 DEFINE_DMA_UNMAP_ADDR(dma); 191 DEFINE_DMA_UNMAP_LEN(len); 192 u32 tx_flags; 193 }; 194 195 struct igb_rx_buffer { 196 dma_addr_t dma; 197 struct page *page; 198 unsigned int page_offset; 199 }; 200 201 struct igb_tx_queue_stats { 202 u64 packets; 203 u64 bytes; 204 u64 restart_queue; 205 u64 restart_queue2; 206 }; 207 208 struct igb_rx_queue_stats { 209 u64 packets; 210 u64 bytes; 211 u64 drops; 212 u64 csum_err; 213 u64 alloc_failed; 214 }; 215 216 struct igb_ring_container { 217 struct igb_ring *ring; /* pointer to linked list of rings */ 218 unsigned int total_bytes; /* total bytes processed this int */ 219 unsigned int total_packets; /* total packets processed this int */ 220 u16 work_limit; /* total work allowed per interrupt */ 221 u8 count; /* total number of rings in vector */ 222 u8 itr; /* current ITR setting for ring */ 223 }; 224 225 struct igb_ring { 226 struct igb_q_vector *q_vector; /* backlink to q_vector */ 227 struct net_device *netdev; /* back pointer to net_device */ 228 struct device *dev; /* device pointer for dma mapping */ 229 union { /* array of buffer info structs */ 230 struct igb_tx_buffer *tx_buffer_info; 231 struct igb_rx_buffer *rx_buffer_info; 232 }; 233 unsigned long last_rx_timestamp; 234 void *desc; /* descriptor ring memory */ 235 unsigned long flags; /* ring specific flags */ 236 void __iomem *tail; /* pointer to ring tail register */ 237 dma_addr_t dma; /* phys address of the ring */ 238 unsigned int size; /* length of desc. ring in bytes */ 239 240 u16 count; /* number of desc. in the ring */ 241 u8 queue_index; /* logical index of the ring*/ 242 u8 reg_idx; /* physical index of the ring */ 243 244 /* everything past this point are written often */ 245 u16 next_to_clean; 246 u16 next_to_use; 247 u16 next_to_alloc; 248 249 union { 250 /* TX */ 251 struct { 252 struct igb_tx_queue_stats tx_stats; 253 struct u64_stats_sync tx_syncp; 254 struct u64_stats_sync tx_syncp2; 255 }; 256 /* RX */ 257 struct { 258 struct sk_buff *skb; 259 struct igb_rx_queue_stats rx_stats; 260 struct u64_stats_sync rx_syncp; 261 }; 262 }; 263 } ____cacheline_internodealigned_in_smp; 264 265 struct igb_q_vector { 266 struct igb_adapter *adapter; /* backlink */ 267 int cpu; /* CPU for DCA */ 268 u32 eims_value; /* EIMS mask value */ 269 270 u16 itr_val; 271 u8 set_itr; 272 void __iomem *itr_register; 273 274 struct igb_ring_container rx, tx; 275 276 struct napi_struct napi; 277 struct rcu_head rcu; /* to avoid race with update stats on free */ 278 char name[IFNAMSIZ + 9]; 279 280 /* for dynamic allocation of rings associated with this q_vector */ 281 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; 282 }; 283 284 enum e1000_ring_flags_t { 285 IGB_RING_FLAG_RX_SCTP_CSUM, 286 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 287 IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, 288 IGB_RING_FLAG_TX_CTX_IDX, 289 IGB_RING_FLAG_TX_DETECT_HANG 290 }; 291 292 #define ring_uses_build_skb(ring) \ 293 test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 294 #define set_ring_build_skb_enabled(ring) \ 295 set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 296 #define clear_ring_build_skb_enabled(ring) \ 297 clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 298 299 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 300 301 #define IGB_RX_DESC(R, i) \ 302 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 303 #define IGB_TX_DESC(R, i) \ 304 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 305 #define IGB_TX_CTXTDESC(R, i) \ 306 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 307 308 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 309 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 310 const u32 stat_err_bits) 311 { 312 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 313 } 314 315 /* igb_desc_unused - calculate if we have unused descriptors */ 316 static inline int igb_desc_unused(struct igb_ring *ring) 317 { 318 if (ring->next_to_clean > ring->next_to_use) 319 return ring->next_to_clean - ring->next_to_use - 1; 320 321 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 322 } 323 324 struct igb_i2c_client_list { 325 struct i2c_client *client; 326 struct igb_i2c_client_list *next; 327 }; 328 329 #ifdef CONFIG_IGB_HWMON 330 331 #define IGB_HWMON_TYPE_LOC 0 332 #define IGB_HWMON_TYPE_TEMP 1 333 #define IGB_HWMON_TYPE_CAUTION 2 334 #define IGB_HWMON_TYPE_MAX 3 335 336 struct hwmon_attr { 337 struct device_attribute dev_attr; 338 struct e1000_hw *hw; 339 struct e1000_thermal_diode_data *sensor; 340 char name[12]; 341 }; 342 343 struct hwmon_buff { 344 struct device *device; 345 struct hwmon_attr *hwmon_list; 346 unsigned int n_hwmon; 347 }; 348 #endif 349 350 /* board specific private data structure */ 351 struct igb_adapter { 352 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 353 354 struct net_device *netdev; 355 356 unsigned long state; 357 unsigned int flags; 358 359 unsigned int num_q_vectors; 360 struct msix_entry *msix_entries; 361 362 /* Interrupt Throttle Rate */ 363 u32 rx_itr_setting; 364 u32 tx_itr_setting; 365 u16 tx_itr; 366 u16 rx_itr; 367 368 /* TX */ 369 u16 tx_work_limit; 370 u32 tx_timeout_count; 371 int num_tx_queues; 372 struct igb_ring *tx_ring[16]; 373 374 /* RX */ 375 int num_rx_queues; 376 struct igb_ring *rx_ring[16]; 377 378 u32 max_frame_size; 379 u32 min_frame_size; 380 381 struct timer_list watchdog_timer; 382 struct timer_list phy_info_timer; 383 384 u16 mng_vlan_id; 385 u32 bd_number; 386 u32 wol; 387 u32 en_mng_pt; 388 u16 link_speed; 389 u16 link_duplex; 390 391 struct work_struct reset_task; 392 struct work_struct watchdog_task; 393 bool fc_autoneg; 394 u8 tx_timeout_factor; 395 struct timer_list blink_timer; 396 unsigned long led_status; 397 398 /* OS defined structs */ 399 struct pci_dev *pdev; 400 401 spinlock_t stats64_lock; 402 struct rtnl_link_stats64 stats64; 403 404 /* structs defined in e1000_hw.h */ 405 struct e1000_hw hw; 406 struct e1000_hw_stats stats; 407 struct e1000_phy_info phy_info; 408 struct e1000_phy_stats phy_stats; 409 410 u32 test_icr; 411 struct igb_ring test_tx_ring; 412 struct igb_ring test_rx_ring; 413 414 int msg_enable; 415 416 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 417 u32 eims_enable_mask; 418 u32 eims_other; 419 420 /* to not mess up cache alignment, always add to the bottom */ 421 u16 tx_ring_count; 422 u16 rx_ring_count; 423 unsigned int vfs_allocated_count; 424 struct vf_data_storage *vf_data; 425 int vf_rate_link_speed; 426 u32 rss_queues; 427 u32 wvbr; 428 u32 *shadow_vfta; 429 430 struct ptp_clock *ptp_clock; 431 struct ptp_clock_info ptp_caps; 432 struct delayed_work ptp_overflow_work; 433 struct work_struct ptp_tx_work; 434 struct sk_buff *ptp_tx_skb; 435 unsigned long ptp_tx_start; 436 unsigned long last_rx_ptp_check; 437 spinlock_t tmreg_lock; 438 struct cyclecounter cc; 439 struct timecounter tc; 440 u32 tx_hwtstamp_timeouts; 441 u32 rx_hwtstamp_cleared; 442 443 char fw_version[32]; 444 #ifdef CONFIG_IGB_HWMON 445 struct hwmon_buff igb_hwmon_buff; 446 bool ets; 447 #endif 448 struct i2c_algo_bit_data i2c_algo; 449 struct i2c_adapter i2c_adap; 450 struct i2c_client *i2c_client; 451 }; 452 453 #define IGB_FLAG_HAS_MSI (1 << 0) 454 #define IGB_FLAG_DCA_ENABLED (1 << 1) 455 #define IGB_FLAG_QUAD_PORT_A (1 << 2) 456 #define IGB_FLAG_QUEUE_PAIRS (1 << 3) 457 #define IGB_FLAG_DMAC (1 << 4) 458 #define IGB_FLAG_PTP (1 << 5) 459 #define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6) 460 #define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7) 461 #define IGB_FLAG_WOL_SUPPORTED (1 << 8) 462 463 /* DMA Coalescing defines */ 464 #define IGB_MIN_TXPBSIZE 20408 465 #define IGB_TX_BUF_4096 4096 466 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 467 468 #define IGB_82576_TSYNC_SHIFT 19 469 #define IGB_TS_HDR_LEN 16 470 enum e1000_state_t { 471 __IGB_TESTING, 472 __IGB_RESETTING, 473 __IGB_DOWN 474 }; 475 476 enum igb_boards { 477 board_82575, 478 }; 479 480 extern char igb_driver_name[]; 481 extern char igb_driver_version[]; 482 483 extern int igb_up(struct igb_adapter *); 484 extern void igb_down(struct igb_adapter *); 485 extern void igb_reinit_locked(struct igb_adapter *); 486 extern void igb_reset(struct igb_adapter *); 487 extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 488 extern int igb_setup_tx_resources(struct igb_ring *); 489 extern int igb_setup_rx_resources(struct igb_ring *); 490 extern void igb_free_tx_resources(struct igb_ring *); 491 extern void igb_free_rx_resources(struct igb_ring *); 492 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 493 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 494 extern void igb_setup_tctl(struct igb_adapter *); 495 extern void igb_setup_rctl(struct igb_adapter *); 496 extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 497 extern void igb_unmap_and_free_tx_resource(struct igb_ring *, 498 struct igb_tx_buffer *); 499 extern void igb_alloc_rx_buffers(struct igb_ring *, u16); 500 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 501 extern bool igb_has_link(struct igb_adapter *adapter); 502 extern void igb_set_ethtool_ops(struct net_device *); 503 extern void igb_power_up_link(struct igb_adapter *); 504 extern void igb_set_fw_version(struct igb_adapter *); 505 extern void igb_ptp_init(struct igb_adapter *adapter); 506 extern void igb_ptp_stop(struct igb_adapter *adapter); 507 extern void igb_ptp_reset(struct igb_adapter *adapter); 508 extern void igb_ptp_tx_work(struct work_struct *work); 509 extern void igb_ptp_rx_hang(struct igb_adapter *adapter); 510 extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 511 extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 512 struct sk_buff *skb); 513 extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, 514 unsigned char *va, 515 struct sk_buff *skb); 516 static inline void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector, 517 union e1000_adv_rx_desc *rx_desc, 518 struct sk_buff *skb) 519 { 520 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 521 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 522 igb_ptp_rx_rgtstamp(q_vector, skb); 523 } 524 525 extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev, 526 struct ifreq *ifr, int cmd); 527 #ifdef CONFIG_IGB_HWMON 528 extern void igb_sysfs_exit(struct igb_adapter *adapter); 529 extern int igb_sysfs_init(struct igb_adapter *adapter); 530 #endif 531 static inline s32 igb_reset_phy(struct e1000_hw *hw) 532 { 533 if (hw->phy.ops.reset) 534 return hw->phy.ops.reset(hw); 535 536 return 0; 537 } 538 539 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 540 { 541 if (hw->phy.ops.read_reg) 542 return hw->phy.ops.read_reg(hw, offset, data); 543 544 return 0; 545 } 546 547 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 548 { 549 if (hw->phy.ops.write_reg) 550 return hw->phy.ops.write_reg(hw, offset, data); 551 552 return 0; 553 } 554 555 static inline s32 igb_get_phy_info(struct e1000_hw *hw) 556 { 557 if (hw->phy.ops.get_phy_info) 558 return hw->phy.ops.get_phy_info(hw); 559 560 return 0; 561 } 562 563 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 564 { 565 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 566 } 567 568 #endif /* _IGB_H_ */ 569