1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* Linux PRO/1000 Ethernet Driver main header file */ 25 26 #ifndef _IGB_H_ 27 #define _IGB_H_ 28 29 #include "e1000_mac.h" 30 #include "e1000_82575.h" 31 32 #include <linux/timecounter.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <linux/bitops.h> 36 #include <linux/if_vlan.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/pci.h> 40 #include <linux/mdio.h> 41 42 struct igb_adapter; 43 44 #define E1000_PCS_CFG_IGN_SD 1 45 46 /* Interrupt defines */ 47 #define IGB_START_ITR 648 /* ~6000 ints/sec */ 48 #define IGB_4K_ITR 980 49 #define IGB_20K_ITR 196 50 #define IGB_70K_ITR 56 51 52 /* TX/RX descriptor defines */ 53 #define IGB_DEFAULT_TXD 256 54 #define IGB_DEFAULT_TX_WORK 128 55 #define IGB_MIN_TXD 80 56 #define IGB_MAX_TXD 4096 57 58 #define IGB_DEFAULT_RXD 256 59 #define IGB_MIN_RXD 80 60 #define IGB_MAX_RXD 4096 61 62 #define IGB_DEFAULT_ITR 3 /* dynamic */ 63 #define IGB_MAX_ITR_USECS 10000 64 #define IGB_MIN_ITR_USECS 10 65 #define NON_Q_VECTORS 1 66 #define MAX_Q_VECTORS 8 67 #define MAX_MSIX_ENTRIES 10 68 69 /* Transmit and receive queues */ 70 #define IGB_MAX_RX_QUEUES 8 71 #define IGB_MAX_RX_QUEUES_82575 4 72 #define IGB_MAX_RX_QUEUES_I211 2 73 #define IGB_MAX_TX_QUEUES 8 74 #define IGB_MAX_VF_MC_ENTRIES 30 75 #define IGB_MAX_VF_FUNCTIONS 8 76 #define IGB_MAX_VFTA_ENTRIES 128 77 #define IGB_82576_VF_DEV_ID 0x10CA 78 #define IGB_I350_VF_DEV_ID 0x1520 79 80 /* NVM version defines */ 81 #define IGB_MAJOR_MASK 0xF000 82 #define IGB_MINOR_MASK 0x0FF0 83 #define IGB_BUILD_MASK 0x000F 84 #define IGB_COMB_VER_MASK 0x00FF 85 #define IGB_MAJOR_SHIFT 12 86 #define IGB_MINOR_SHIFT 4 87 #define IGB_COMB_VER_SHFT 8 88 #define IGB_NVM_VER_INVALID 0xFFFF 89 #define IGB_ETRACK_SHIFT 16 90 #define NVM_ETRACK_WORD 0x0042 91 #define NVM_COMB_VER_OFF 0x0083 92 #define NVM_COMB_VER_PTR 0x003d 93 94 /* Transmit and receive latency (for PTP timestamps) */ 95 #define IGB_I210_TX_LATENCY_10 9542 96 #define IGB_I210_TX_LATENCY_100 1024 97 #define IGB_I210_TX_LATENCY_1000 178 98 #define IGB_I210_RX_LATENCY_10 20662 99 #define IGB_I210_RX_LATENCY_100 2213 100 #define IGB_I210_RX_LATENCY_1000 448 101 102 struct vf_data_storage { 103 unsigned char vf_mac_addresses[ETH_ALEN]; 104 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 105 u16 num_vf_mc_hashes; 106 u32 flags; 107 unsigned long last_nack; 108 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 109 u16 pf_qos; 110 u16 tx_rate; 111 bool spoofchk_enabled; 112 }; 113 114 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 115 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 116 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 117 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 118 119 /* RX descriptor control thresholds. 120 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 121 * descriptors available in its onboard memory. 122 * Setting this to 0 disables RX descriptor prefetch. 123 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 124 * available in host memory. 125 * If PTHRESH is 0, this should also be 0. 126 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 127 * descriptors until either it has this many to write back, or the 128 * ITR timer expires. 129 */ 130 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) 131 #define IGB_RX_HTHRESH 8 132 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 133 #define IGB_TX_HTHRESH 1 134 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 135 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4) 136 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 137 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16) 138 139 /* this is the size past which hardware will drop packets when setting LPE=0 */ 140 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 141 142 /* Supported Rx Buffer Sizes */ 143 #define IGB_RXBUFFER_256 256 144 #define IGB_RXBUFFER_2048 2048 145 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 146 #define IGB_RX_BUFSZ IGB_RXBUFFER_2048 147 148 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 149 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 150 151 #define IGB_RX_DMA_ATTR \ 152 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 153 154 #define AUTO_ALL_MODES 0 155 #define IGB_EEPROM_APME 0x0400 156 157 #ifndef IGB_MASTER_SLAVE 158 /* Switch to override PHY master/slave setting */ 159 #define IGB_MASTER_SLAVE e1000_ms_hw_default 160 #endif 161 162 #define IGB_MNG_VLAN_NONE -1 163 164 enum igb_tx_flags { 165 /* cmd_type flags */ 166 IGB_TX_FLAGS_VLAN = 0x01, 167 IGB_TX_FLAGS_TSO = 0x02, 168 IGB_TX_FLAGS_TSTAMP = 0x04, 169 170 /* olinfo flags */ 171 IGB_TX_FLAGS_IPV4 = 0x10, 172 IGB_TX_FLAGS_CSUM = 0x20, 173 }; 174 175 /* VLAN info */ 176 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 177 #define IGB_TX_FLAGS_VLAN_SHIFT 16 178 179 /* The largest size we can write to the descriptor is 65535. In order to 180 * maintain a power of two alignment we have to limit ourselves to 32K. 181 */ 182 #define IGB_MAX_TXD_PWR 15 183 #define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR) 184 185 /* Tx Descriptors needed, worst case */ 186 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) 187 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 188 189 /* EEPROM byte offsets */ 190 #define IGB_SFF_8472_SWAP 0x5C 191 #define IGB_SFF_8472_COMP 0x5E 192 193 /* Bitmasks */ 194 #define IGB_SFF_ADDRESSING_MODE 0x4 195 #define IGB_SFF_8472_UNSUP 0x00 196 197 /* wrapper around a pointer to a socket buffer, 198 * so a DMA handle can be stored along with the buffer 199 */ 200 struct igb_tx_buffer { 201 union e1000_adv_tx_desc *next_to_watch; 202 unsigned long time_stamp; 203 struct sk_buff *skb; 204 unsigned int bytecount; 205 u16 gso_segs; 206 __be16 protocol; 207 208 DEFINE_DMA_UNMAP_ADDR(dma); 209 DEFINE_DMA_UNMAP_LEN(len); 210 u32 tx_flags; 211 }; 212 213 struct igb_rx_buffer { 214 dma_addr_t dma; 215 struct page *page; 216 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 217 __u32 page_offset; 218 #else 219 __u16 page_offset; 220 #endif 221 __u16 pagecnt_bias; 222 }; 223 224 struct igb_tx_queue_stats { 225 u64 packets; 226 u64 bytes; 227 u64 restart_queue; 228 u64 restart_queue2; 229 }; 230 231 struct igb_rx_queue_stats { 232 u64 packets; 233 u64 bytes; 234 u64 drops; 235 u64 csum_err; 236 u64 alloc_failed; 237 }; 238 239 struct igb_ring_container { 240 struct igb_ring *ring; /* pointer to linked list of rings */ 241 unsigned int total_bytes; /* total bytes processed this int */ 242 unsigned int total_packets; /* total packets processed this int */ 243 u16 work_limit; /* total work allowed per interrupt */ 244 u8 count; /* total number of rings in vector */ 245 u8 itr; /* current ITR setting for ring */ 246 }; 247 248 struct igb_ring { 249 struct igb_q_vector *q_vector; /* backlink to q_vector */ 250 struct net_device *netdev; /* back pointer to net_device */ 251 struct device *dev; /* device pointer for dma mapping */ 252 union { /* array of buffer info structs */ 253 struct igb_tx_buffer *tx_buffer_info; 254 struct igb_rx_buffer *rx_buffer_info; 255 }; 256 void *desc; /* descriptor ring memory */ 257 unsigned long flags; /* ring specific flags */ 258 void __iomem *tail; /* pointer to ring tail register */ 259 dma_addr_t dma; /* phys address of the ring */ 260 unsigned int size; /* length of desc. ring in bytes */ 261 262 u16 count; /* number of desc. in the ring */ 263 u8 queue_index; /* logical index of the ring*/ 264 u8 reg_idx; /* physical index of the ring */ 265 266 /* everything past this point are written often */ 267 u16 next_to_clean; 268 u16 next_to_use; 269 u16 next_to_alloc; 270 271 union { 272 /* TX */ 273 struct { 274 struct igb_tx_queue_stats tx_stats; 275 struct u64_stats_sync tx_syncp; 276 struct u64_stats_sync tx_syncp2; 277 }; 278 /* RX */ 279 struct { 280 struct sk_buff *skb; 281 struct igb_rx_queue_stats rx_stats; 282 struct u64_stats_sync rx_syncp; 283 }; 284 }; 285 } ____cacheline_internodealigned_in_smp; 286 287 struct igb_q_vector { 288 struct igb_adapter *adapter; /* backlink */ 289 int cpu; /* CPU for DCA */ 290 u32 eims_value; /* EIMS mask value */ 291 292 u16 itr_val; 293 u8 set_itr; 294 void __iomem *itr_register; 295 296 struct igb_ring_container rx, tx; 297 298 struct napi_struct napi; 299 struct rcu_head rcu; /* to avoid race with update stats on free */ 300 char name[IFNAMSIZ + 9]; 301 302 /* for dynamic allocation of rings associated with this q_vector */ 303 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; 304 }; 305 306 enum e1000_ring_flags_t { 307 IGB_RING_FLAG_RX_SCTP_CSUM, 308 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 309 IGB_RING_FLAG_TX_CTX_IDX, 310 IGB_RING_FLAG_TX_DETECT_HANG 311 }; 312 313 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 314 315 #define IGB_RX_DESC(R, i) \ 316 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 317 #define IGB_TX_DESC(R, i) \ 318 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 319 #define IGB_TX_CTXTDESC(R, i) \ 320 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 321 322 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 323 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 324 const u32 stat_err_bits) 325 { 326 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 327 } 328 329 /* igb_desc_unused - calculate if we have unused descriptors */ 330 static inline int igb_desc_unused(struct igb_ring *ring) 331 { 332 if (ring->next_to_clean > ring->next_to_use) 333 return ring->next_to_clean - ring->next_to_use - 1; 334 335 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 336 } 337 338 #ifdef CONFIG_IGB_HWMON 339 340 #define IGB_HWMON_TYPE_LOC 0 341 #define IGB_HWMON_TYPE_TEMP 1 342 #define IGB_HWMON_TYPE_CAUTION 2 343 #define IGB_HWMON_TYPE_MAX 3 344 345 struct hwmon_attr { 346 struct device_attribute dev_attr; 347 struct e1000_hw *hw; 348 struct e1000_thermal_diode_data *sensor; 349 char name[12]; 350 }; 351 352 struct hwmon_buff { 353 struct attribute_group group; 354 const struct attribute_group *groups[2]; 355 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1]; 356 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4]; 357 unsigned int n_hwmon; 358 }; 359 #endif 360 361 /* The number of L2 ether-type filter registers, Index 3 is reserved 362 * for PTP 1588 timestamp 363 */ 364 #define MAX_ETYPE_FILTER (4 - 1) 365 /* ETQF filter list: one static filter per filter consumer. This is 366 * to avoid filter collisions later. Add new filters here!! 367 * 368 * Current filters: Filter 3 369 */ 370 #define IGB_ETQF_FILTER_1588 3 371 372 #define IGB_N_EXTTS 2 373 #define IGB_N_PEROUT 2 374 #define IGB_N_SDP 4 375 #define IGB_RETA_SIZE 128 376 377 enum igb_filter_match_flags { 378 IGB_FILTER_FLAG_ETHER_TYPE = 0x1, 379 IGB_FILTER_FLAG_VLAN_TCI = 0x2, 380 }; 381 382 #define IGB_MAX_RXNFC_FILTERS 16 383 384 /* RX network flow classification data structure */ 385 struct igb_nfc_input { 386 /* Byte layout in order, all values with MSB first: 387 * match_flags - 1 byte 388 * etype - 2 bytes 389 * vlan_tci - 2 bytes 390 */ 391 u8 match_flags; 392 __be16 etype; 393 __be16 vlan_tci; 394 }; 395 396 struct igb_nfc_filter { 397 struct hlist_node nfc_node; 398 struct igb_nfc_input filter; 399 u16 etype_reg_index; 400 u16 sw_idx; 401 u16 action; 402 }; 403 404 /* board specific private data structure */ 405 struct igb_adapter { 406 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 407 408 struct net_device *netdev; 409 410 unsigned long state; 411 unsigned int flags; 412 413 unsigned int num_q_vectors; 414 struct msix_entry msix_entries[MAX_MSIX_ENTRIES]; 415 416 /* Interrupt Throttle Rate */ 417 u32 rx_itr_setting; 418 u32 tx_itr_setting; 419 u16 tx_itr; 420 u16 rx_itr; 421 422 /* TX */ 423 u16 tx_work_limit; 424 u32 tx_timeout_count; 425 int num_tx_queues; 426 struct igb_ring *tx_ring[16]; 427 428 /* RX */ 429 int num_rx_queues; 430 struct igb_ring *rx_ring[16]; 431 432 u32 max_frame_size; 433 u32 min_frame_size; 434 435 struct timer_list watchdog_timer; 436 struct timer_list phy_info_timer; 437 438 u16 mng_vlan_id; 439 u32 bd_number; 440 u32 wol; 441 u32 en_mng_pt; 442 u16 link_speed; 443 u16 link_duplex; 444 445 u8 __iomem *io_addr; /* Mainly for iounmap use */ 446 447 struct work_struct reset_task; 448 struct work_struct watchdog_task; 449 bool fc_autoneg; 450 u8 tx_timeout_factor; 451 struct timer_list blink_timer; 452 unsigned long led_status; 453 454 /* OS defined structs */ 455 struct pci_dev *pdev; 456 457 spinlock_t stats64_lock; 458 struct rtnl_link_stats64 stats64; 459 460 /* structs defined in e1000_hw.h */ 461 struct e1000_hw hw; 462 struct e1000_hw_stats stats; 463 struct e1000_phy_info phy_info; 464 465 u32 test_icr; 466 struct igb_ring test_tx_ring; 467 struct igb_ring test_rx_ring; 468 469 int msg_enable; 470 471 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 472 u32 eims_enable_mask; 473 u32 eims_other; 474 475 /* to not mess up cache alignment, always add to the bottom */ 476 u16 tx_ring_count; 477 u16 rx_ring_count; 478 unsigned int vfs_allocated_count; 479 struct vf_data_storage *vf_data; 480 int vf_rate_link_speed; 481 u32 rss_queues; 482 u32 wvbr; 483 u32 *shadow_vfta; 484 485 struct ptp_clock *ptp_clock; 486 struct ptp_clock_info ptp_caps; 487 struct delayed_work ptp_overflow_work; 488 struct work_struct ptp_tx_work; 489 struct sk_buff *ptp_tx_skb; 490 struct hwtstamp_config tstamp_config; 491 unsigned long ptp_tx_start; 492 unsigned long last_rx_ptp_check; 493 unsigned long last_rx_timestamp; 494 unsigned int ptp_flags; 495 spinlock_t tmreg_lock; 496 struct cyclecounter cc; 497 struct timecounter tc; 498 u32 tx_hwtstamp_timeouts; 499 u32 rx_hwtstamp_cleared; 500 bool pps_sys_wrap_on; 501 502 struct ptp_pin_desc sdp_config[IGB_N_SDP]; 503 struct { 504 struct timespec64 start; 505 struct timespec64 period; 506 } perout[IGB_N_PEROUT]; 507 508 char fw_version[32]; 509 #ifdef CONFIG_IGB_HWMON 510 struct hwmon_buff *igb_hwmon_buff; 511 bool ets; 512 #endif 513 struct i2c_algo_bit_data i2c_algo; 514 struct i2c_adapter i2c_adap; 515 struct i2c_client *i2c_client; 516 u32 rss_indir_tbl_init; 517 u8 rss_indir_tbl[IGB_RETA_SIZE]; 518 519 unsigned long link_check_timeout; 520 int copper_tries; 521 struct e1000_info ei; 522 u16 eee_advert; 523 524 /* RX network flow classification support */ 525 struct hlist_head nfc_filter_list; 526 unsigned int nfc_filter_count; 527 /* lock for RX network flow classification filter */ 528 spinlock_t nfc_lock; 529 bool etype_bitmap[MAX_ETYPE_FILTER]; 530 }; 531 532 /* flags controlling PTP/1588 function */ 533 #define IGB_PTP_ENABLED BIT(0) 534 #define IGB_PTP_OVERFLOW_CHECK BIT(1) 535 536 #define IGB_FLAG_HAS_MSI BIT(0) 537 #define IGB_FLAG_DCA_ENABLED BIT(1) 538 #define IGB_FLAG_QUAD_PORT_A BIT(2) 539 #define IGB_FLAG_QUEUE_PAIRS BIT(3) 540 #define IGB_FLAG_DMAC BIT(4) 541 #define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 542 #define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 543 #define IGB_FLAG_WOL_SUPPORTED BIT(8) 544 #define IGB_FLAG_NEED_LINK_UPDATE BIT(9) 545 #define IGB_FLAG_MEDIA_RESET BIT(10) 546 #define IGB_FLAG_MAS_CAPABLE BIT(11) 547 #define IGB_FLAG_MAS_ENABLE BIT(12) 548 #define IGB_FLAG_HAS_MSIX BIT(13) 549 #define IGB_FLAG_EEE BIT(14) 550 #define IGB_FLAG_VLAN_PROMISC BIT(15) 551 552 /* Media Auto Sense */ 553 #define IGB_MAS_ENABLE_0 0X0001 554 #define IGB_MAS_ENABLE_1 0X0002 555 #define IGB_MAS_ENABLE_2 0X0004 556 #define IGB_MAS_ENABLE_3 0X0008 557 558 /* DMA Coalescing defines */ 559 #define IGB_MIN_TXPBSIZE 20408 560 #define IGB_TX_BUF_4096 4096 561 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 562 563 #define IGB_82576_TSYNC_SHIFT 19 564 #define IGB_TS_HDR_LEN 16 565 enum e1000_state_t { 566 __IGB_TESTING, 567 __IGB_RESETTING, 568 __IGB_DOWN, 569 __IGB_PTP_TX_IN_PROGRESS, 570 }; 571 572 enum igb_boards { 573 board_82575, 574 }; 575 576 extern char igb_driver_name[]; 577 extern char igb_driver_version[]; 578 579 int igb_open(struct net_device *netdev); 580 int igb_close(struct net_device *netdev); 581 int igb_up(struct igb_adapter *); 582 void igb_down(struct igb_adapter *); 583 void igb_reinit_locked(struct igb_adapter *); 584 void igb_reset(struct igb_adapter *); 585 int igb_reinit_queues(struct igb_adapter *); 586 void igb_write_rss_indir_tbl(struct igb_adapter *); 587 int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 588 int igb_setup_tx_resources(struct igb_ring *); 589 int igb_setup_rx_resources(struct igb_ring *); 590 void igb_free_tx_resources(struct igb_ring *); 591 void igb_free_rx_resources(struct igb_ring *); 592 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 593 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 594 void igb_setup_tctl(struct igb_adapter *); 595 void igb_setup_rctl(struct igb_adapter *); 596 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 597 void igb_alloc_rx_buffers(struct igb_ring *, u16); 598 void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 599 bool igb_has_link(struct igb_adapter *adapter); 600 void igb_set_ethtool_ops(struct net_device *); 601 void igb_power_up_link(struct igb_adapter *); 602 void igb_set_fw_version(struct igb_adapter *); 603 void igb_ptp_init(struct igb_adapter *adapter); 604 void igb_ptp_stop(struct igb_adapter *adapter); 605 void igb_ptp_reset(struct igb_adapter *adapter); 606 void igb_ptp_suspend(struct igb_adapter *adapter); 607 void igb_ptp_rx_hang(struct igb_adapter *adapter); 608 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb); 609 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va, 610 struct sk_buff *skb); 611 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 612 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 613 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32); 614 #ifdef CONFIG_IGB_HWMON 615 void igb_sysfs_exit(struct igb_adapter *adapter); 616 int igb_sysfs_init(struct igb_adapter *adapter); 617 #endif 618 static inline s32 igb_reset_phy(struct e1000_hw *hw) 619 { 620 if (hw->phy.ops.reset) 621 return hw->phy.ops.reset(hw); 622 623 return 0; 624 } 625 626 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 627 { 628 if (hw->phy.ops.read_reg) 629 return hw->phy.ops.read_reg(hw, offset, data); 630 631 return 0; 632 } 633 634 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 635 { 636 if (hw->phy.ops.write_reg) 637 return hw->phy.ops.write_reg(hw, offset, data); 638 639 return 0; 640 } 641 642 static inline s32 igb_get_phy_info(struct e1000_hw *hw) 643 { 644 if (hw->phy.ops.get_phy_info) 645 return hw->phy.ops.get_phy_info(hw); 646 647 return 0; 648 } 649 650 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 651 { 652 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 653 } 654 655 int igb_add_filter(struct igb_adapter *adapter, 656 struct igb_nfc_filter *input); 657 int igb_erase_filter(struct igb_adapter *adapter, 658 struct igb_nfc_filter *input); 659 660 #endif /* _IGB_H_ */ 661