1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 /* Linux PRO/1000 Ethernet Driver main header file */ 5 6 #ifndef _IGB_H_ 7 #define _IGB_H_ 8 9 #include "e1000_mac.h" 10 #include "e1000_82575.h" 11 12 #include <linux/timecounter.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/ptp_clock_kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/if_vlan.h> 17 #include <linux/i2c.h> 18 #include <linux/i2c-algo-bit.h> 19 #include <linux/pci.h> 20 #include <linux/mdio.h> 21 22 #include <net/xdp.h> 23 24 struct igb_adapter; 25 26 #define E1000_PCS_CFG_IGN_SD 1 27 28 /* Interrupt defines */ 29 #define IGB_START_ITR 648 /* ~6000 ints/sec */ 30 #define IGB_4K_ITR 980 31 #define IGB_20K_ITR 196 32 #define IGB_70K_ITR 56 33 34 /* TX/RX descriptor defines */ 35 #define IGB_DEFAULT_TXD 256 36 #define IGB_DEFAULT_TX_WORK 128 37 #define IGB_MIN_TXD 80 38 #define IGB_MAX_TXD 4096 39 40 #define IGB_DEFAULT_RXD 256 41 #define IGB_MIN_RXD 80 42 #define IGB_MAX_RXD 4096 43 44 #define IGB_DEFAULT_ITR 3 /* dynamic */ 45 #define IGB_MAX_ITR_USECS 10000 46 #define IGB_MIN_ITR_USECS 10 47 #define NON_Q_VECTORS 1 48 #define MAX_Q_VECTORS 8 49 #define MAX_MSIX_ENTRIES 10 50 51 /* Transmit and receive queues */ 52 #define IGB_MAX_RX_QUEUES 8 53 #define IGB_MAX_RX_QUEUES_82575 4 54 #define IGB_MAX_RX_QUEUES_I211 2 55 #define IGB_MAX_TX_QUEUES 8 56 #define IGB_MAX_VF_MC_ENTRIES 30 57 #define IGB_MAX_VF_FUNCTIONS 8 58 #define IGB_MAX_VFTA_ENTRIES 128 59 #define IGB_82576_VF_DEV_ID 0x10CA 60 #define IGB_I350_VF_DEV_ID 0x1520 61 62 /* NVM version defines */ 63 #define IGB_MAJOR_MASK 0xF000 64 #define IGB_MINOR_MASK 0x0FF0 65 #define IGB_BUILD_MASK 0x000F 66 #define IGB_COMB_VER_MASK 0x00FF 67 #define IGB_MAJOR_SHIFT 12 68 #define IGB_MINOR_SHIFT 4 69 #define IGB_COMB_VER_SHFT 8 70 #define IGB_NVM_VER_INVALID 0xFFFF 71 #define IGB_ETRACK_SHIFT 16 72 #define NVM_ETRACK_WORD 0x0042 73 #define NVM_COMB_VER_OFF 0x0083 74 #define NVM_COMB_VER_PTR 0x003d 75 76 /* Transmit and receive latency (for PTP timestamps) */ 77 #define IGB_I210_TX_LATENCY_10 9542 78 #define IGB_I210_TX_LATENCY_100 1024 79 #define IGB_I210_TX_LATENCY_1000 178 80 #define IGB_I210_RX_LATENCY_10 20662 81 #define IGB_I210_RX_LATENCY_100 2213 82 #define IGB_I210_RX_LATENCY_1000 448 83 84 /* XDP */ 85 #define IGB_XDP_PASS 0 86 #define IGB_XDP_CONSUMED BIT(0) 87 #define IGB_XDP_TX BIT(1) 88 #define IGB_XDP_REDIR BIT(2) 89 90 struct vf_data_storage { 91 unsigned char vf_mac_addresses[ETH_ALEN]; 92 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 93 u16 num_vf_mc_hashes; 94 u32 flags; 95 unsigned long last_nack; 96 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 97 u16 pf_qos; 98 u16 tx_rate; 99 bool spoofchk_enabled; 100 bool trusted; 101 }; 102 103 /* Number of unicast MAC filters reserved for the PF in the RAR registers */ 104 #define IGB_PF_MAC_FILTERS_RESERVED 3 105 106 struct vf_mac_filter { 107 struct list_head l; 108 int vf; 109 bool free; 110 u8 vf_mac[ETH_ALEN]; 111 }; 112 113 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 114 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 115 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 116 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 117 118 /* RX descriptor control thresholds. 119 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 120 * descriptors available in its onboard memory. 121 * Setting this to 0 disables RX descriptor prefetch. 122 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 123 * available in host memory. 124 * If PTHRESH is 0, this should also be 0. 125 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 126 * descriptors until either it has this many to write back, or the 127 * ITR timer expires. 128 */ 129 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) 130 #define IGB_RX_HTHRESH 8 131 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 132 #define IGB_TX_HTHRESH 1 133 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 134 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4) 135 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 136 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16) 137 138 /* this is the size past which hardware will drop packets when setting LPE=0 */ 139 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 140 141 /* Supported Rx Buffer Sizes */ 142 #define IGB_RXBUFFER_256 256 143 #define IGB_RXBUFFER_1536 1536 144 #define IGB_RXBUFFER_2048 2048 145 #define IGB_RXBUFFER_3072 3072 146 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 147 #define IGB_TS_HDR_LEN 16 148 149 /* Attempt to maximize the headroom available for incoming frames. We 150 * use a 2K buffer for receives and need 1536/1534 to store the data for 151 * the frame. This leaves us with 512 bytes of room. From that we need 152 * to deduct the space needed for the shared info and the padding needed 153 * to IP align the frame. 154 * 155 * Note: For cache line sizes 256 or larger this value is going to end 156 * up negative. In these cases we should fall back to the 3K 157 * buffers. 158 */ 159 #if (PAGE_SIZE < 8192) 160 #define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_1536 - NET_IP_ALIGN) 161 #define IGB_2K_TOO_SMALL_WITH_PADDING \ 162 ((NET_SKB_PAD + IGB_TS_HDR_LEN + IGB_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048)) 163 164 static inline int igb_compute_pad(int rx_buf_len) 165 { 166 int page_size, pad_size; 167 168 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 169 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 170 171 return pad_size; 172 } 173 174 static inline int igb_skb_pad(void) 175 { 176 int rx_buf_len; 177 178 /* If a 2K buffer cannot handle a standard Ethernet frame then 179 * optimize padding for a 3K buffer instead of a 1.5K buffer. 180 * 181 * For a 3K buffer we need to add enough padding to allow for 182 * tailroom due to NET_IP_ALIGN possibly shifting us out of 183 * cache-line alignment. 184 */ 185 if (IGB_2K_TOO_SMALL_WITH_PADDING) 186 rx_buf_len = IGB_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); 187 else 188 rx_buf_len = IGB_RXBUFFER_1536; 189 190 /* if needed make room for NET_IP_ALIGN */ 191 rx_buf_len -= NET_IP_ALIGN; 192 193 return igb_compute_pad(rx_buf_len); 194 } 195 196 #define IGB_SKB_PAD igb_skb_pad() 197 #else 198 #define IGB_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 199 #endif 200 201 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 202 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 203 204 #define IGB_RX_DMA_ATTR \ 205 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 206 207 #define AUTO_ALL_MODES 0 208 #define IGB_EEPROM_APME 0x0400 209 210 #ifndef IGB_MASTER_SLAVE 211 /* Switch to override PHY master/slave setting */ 212 #define IGB_MASTER_SLAVE e1000_ms_hw_default 213 #endif 214 215 #define IGB_MNG_VLAN_NONE -1 216 217 enum igb_tx_flags { 218 /* cmd_type flags */ 219 IGB_TX_FLAGS_VLAN = 0x01, 220 IGB_TX_FLAGS_TSO = 0x02, 221 IGB_TX_FLAGS_TSTAMP = 0x04, 222 223 /* olinfo flags */ 224 IGB_TX_FLAGS_IPV4 = 0x10, 225 IGB_TX_FLAGS_CSUM = 0x20, 226 }; 227 228 /* VLAN info */ 229 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 230 #define IGB_TX_FLAGS_VLAN_SHIFT 16 231 232 /* The largest size we can write to the descriptor is 65535. In order to 233 * maintain a power of two alignment we have to limit ourselves to 32K. 234 */ 235 #define IGB_MAX_TXD_PWR 15 236 #define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR) 237 238 /* Tx Descriptors needed, worst case */ 239 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) 240 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 241 242 /* EEPROM byte offsets */ 243 #define IGB_SFF_8472_SWAP 0x5C 244 #define IGB_SFF_8472_COMP 0x5E 245 246 /* Bitmasks */ 247 #define IGB_SFF_ADDRESSING_MODE 0x4 248 #define IGB_SFF_8472_UNSUP 0x00 249 250 enum igb_tx_buf_type { 251 IGB_TYPE_SKB = 0, 252 IGB_TYPE_XDP, 253 }; 254 255 /* wrapper around a pointer to a socket buffer, 256 * so a DMA handle can be stored along with the buffer 257 */ 258 struct igb_tx_buffer { 259 union e1000_adv_tx_desc *next_to_watch; 260 unsigned long time_stamp; 261 enum igb_tx_buf_type type; 262 union { 263 struct sk_buff *skb; 264 struct xdp_frame *xdpf; 265 }; 266 unsigned int bytecount; 267 u16 gso_segs; 268 __be16 protocol; 269 270 DEFINE_DMA_UNMAP_ADDR(dma); 271 DEFINE_DMA_UNMAP_LEN(len); 272 u32 tx_flags; 273 }; 274 275 struct igb_rx_buffer { 276 dma_addr_t dma; 277 struct page *page; 278 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 279 __u32 page_offset; 280 #else 281 __u16 page_offset; 282 #endif 283 __u16 pagecnt_bias; 284 }; 285 286 struct igb_tx_queue_stats { 287 u64 packets; 288 u64 bytes; 289 u64 restart_queue; 290 u64 restart_queue2; 291 }; 292 293 struct igb_rx_queue_stats { 294 u64 packets; 295 u64 bytes; 296 u64 drops; 297 u64 csum_err; 298 u64 alloc_failed; 299 }; 300 301 struct igb_ring_container { 302 struct igb_ring *ring; /* pointer to linked list of rings */ 303 unsigned int total_bytes; /* total bytes processed this int */ 304 unsigned int total_packets; /* total packets processed this int */ 305 u16 work_limit; /* total work allowed per interrupt */ 306 u8 count; /* total number of rings in vector */ 307 u8 itr; /* current ITR setting for ring */ 308 }; 309 310 struct igb_ring { 311 struct igb_q_vector *q_vector; /* backlink to q_vector */ 312 struct net_device *netdev; /* back pointer to net_device */ 313 struct bpf_prog *xdp_prog; 314 struct device *dev; /* device pointer for dma mapping */ 315 union { /* array of buffer info structs */ 316 struct igb_tx_buffer *tx_buffer_info; 317 struct igb_rx_buffer *rx_buffer_info; 318 }; 319 void *desc; /* descriptor ring memory */ 320 unsigned long flags; /* ring specific flags */ 321 void __iomem *tail; /* pointer to ring tail register */ 322 dma_addr_t dma; /* phys address of the ring */ 323 unsigned int size; /* length of desc. ring in bytes */ 324 325 u16 count; /* number of desc. in the ring */ 326 u8 queue_index; /* logical index of the ring*/ 327 u8 reg_idx; /* physical index of the ring */ 328 bool launchtime_enable; /* true if LaunchTime is enabled */ 329 bool cbs_enable; /* indicates if CBS is enabled */ 330 s32 idleslope; /* idleSlope in kbps */ 331 s32 sendslope; /* sendSlope in kbps */ 332 s32 hicredit; /* hiCredit in bytes */ 333 s32 locredit; /* loCredit in bytes */ 334 335 /* everything past this point are written often */ 336 u16 next_to_clean; 337 u16 next_to_use; 338 u16 next_to_alloc; 339 340 union { 341 /* TX */ 342 struct { 343 struct igb_tx_queue_stats tx_stats; 344 struct u64_stats_sync tx_syncp; 345 struct u64_stats_sync tx_syncp2; 346 }; 347 /* RX */ 348 struct { 349 struct sk_buff *skb; 350 struct igb_rx_queue_stats rx_stats; 351 struct u64_stats_sync rx_syncp; 352 }; 353 }; 354 struct xdp_rxq_info xdp_rxq; 355 } ____cacheline_internodealigned_in_smp; 356 357 struct igb_q_vector { 358 struct igb_adapter *adapter; /* backlink */ 359 int cpu; /* CPU for DCA */ 360 u32 eims_value; /* EIMS mask value */ 361 362 u16 itr_val; 363 u8 set_itr; 364 void __iomem *itr_register; 365 366 struct igb_ring_container rx, tx; 367 368 struct napi_struct napi; 369 struct rcu_head rcu; /* to avoid race with update stats on free */ 370 char name[IFNAMSIZ + 9]; 371 372 /* for dynamic allocation of rings associated with this q_vector */ 373 struct igb_ring ring[] ____cacheline_internodealigned_in_smp; 374 }; 375 376 enum e1000_ring_flags_t { 377 IGB_RING_FLAG_RX_3K_BUFFER, 378 IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, 379 IGB_RING_FLAG_RX_SCTP_CSUM, 380 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 381 IGB_RING_FLAG_TX_CTX_IDX, 382 IGB_RING_FLAG_TX_DETECT_HANG 383 }; 384 385 #define ring_uses_large_buffer(ring) \ 386 test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 387 #define set_ring_uses_large_buffer(ring) \ 388 set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 389 #define clear_ring_uses_large_buffer(ring) \ 390 clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 391 392 #define ring_uses_build_skb(ring) \ 393 test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 394 #define set_ring_build_skb_enabled(ring) \ 395 set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 396 #define clear_ring_build_skb_enabled(ring) \ 397 clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 398 399 static inline unsigned int igb_rx_bufsz(struct igb_ring *ring) 400 { 401 #if (PAGE_SIZE < 8192) 402 if (ring_uses_large_buffer(ring)) 403 return IGB_RXBUFFER_3072; 404 405 if (ring_uses_build_skb(ring)) 406 return IGB_MAX_FRAME_BUILD_SKB; 407 #endif 408 return IGB_RXBUFFER_2048; 409 } 410 411 static inline unsigned int igb_rx_pg_order(struct igb_ring *ring) 412 { 413 #if (PAGE_SIZE < 8192) 414 if (ring_uses_large_buffer(ring)) 415 return 1; 416 #endif 417 return 0; 418 } 419 420 #define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring)) 421 422 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 423 424 #define IGB_RX_DESC(R, i) \ 425 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 426 #define IGB_TX_DESC(R, i) \ 427 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 428 #define IGB_TX_CTXTDESC(R, i) \ 429 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 430 431 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 432 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 433 const u32 stat_err_bits) 434 { 435 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 436 } 437 438 /* igb_desc_unused - calculate if we have unused descriptors */ 439 static inline int igb_desc_unused(struct igb_ring *ring) 440 { 441 if (ring->next_to_clean > ring->next_to_use) 442 return ring->next_to_clean - ring->next_to_use - 1; 443 444 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 445 } 446 447 #ifdef CONFIG_IGB_HWMON 448 449 #define IGB_HWMON_TYPE_LOC 0 450 #define IGB_HWMON_TYPE_TEMP 1 451 #define IGB_HWMON_TYPE_CAUTION 2 452 #define IGB_HWMON_TYPE_MAX 3 453 454 struct hwmon_attr { 455 struct device_attribute dev_attr; 456 struct e1000_hw *hw; 457 struct e1000_thermal_diode_data *sensor; 458 char name[12]; 459 }; 460 461 struct hwmon_buff { 462 struct attribute_group group; 463 const struct attribute_group *groups[2]; 464 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1]; 465 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4]; 466 unsigned int n_hwmon; 467 }; 468 #endif 469 470 /* The number of L2 ether-type filter registers, Index 3 is reserved 471 * for PTP 1588 timestamp 472 */ 473 #define MAX_ETYPE_FILTER (4 - 1) 474 /* ETQF filter list: one static filter per filter consumer. This is 475 * to avoid filter collisions later. Add new filters here!! 476 * 477 * Current filters: Filter 3 478 */ 479 #define IGB_ETQF_FILTER_1588 3 480 481 #define IGB_N_EXTTS 2 482 #define IGB_N_PEROUT 2 483 #define IGB_N_SDP 4 484 #define IGB_RETA_SIZE 128 485 486 enum igb_filter_match_flags { 487 IGB_FILTER_FLAG_ETHER_TYPE = 0x1, 488 IGB_FILTER_FLAG_VLAN_TCI = 0x2, 489 IGB_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 490 IGB_FILTER_FLAG_DST_MAC_ADDR = 0x8, 491 }; 492 493 #define IGB_MAX_RXNFC_FILTERS 16 494 495 /* RX network flow classification data structure */ 496 struct igb_nfc_input { 497 /* Byte layout in order, all values with MSB first: 498 * match_flags - 1 byte 499 * etype - 2 bytes 500 * vlan_tci - 2 bytes 501 */ 502 u8 match_flags; 503 __be16 etype; 504 __be16 vlan_tci; 505 u8 src_addr[ETH_ALEN]; 506 u8 dst_addr[ETH_ALEN]; 507 }; 508 509 struct igb_nfc_filter { 510 struct hlist_node nfc_node; 511 struct igb_nfc_input filter; 512 unsigned long cookie; 513 u16 etype_reg_index; 514 u16 sw_idx; 515 u16 action; 516 }; 517 518 struct igb_mac_addr { 519 u8 addr[ETH_ALEN]; 520 u8 queue; 521 u8 state; /* bitmask */ 522 }; 523 524 #define IGB_MAC_STATE_DEFAULT 0x1 525 #define IGB_MAC_STATE_IN_USE 0x2 526 #define IGB_MAC_STATE_SRC_ADDR 0x4 527 #define IGB_MAC_STATE_QUEUE_STEERING 0x8 528 529 /* board specific private data structure */ 530 struct igb_adapter { 531 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 532 533 struct net_device *netdev; 534 struct bpf_prog *xdp_prog; 535 536 unsigned long state; 537 unsigned int flags; 538 539 unsigned int num_q_vectors; 540 struct msix_entry msix_entries[MAX_MSIX_ENTRIES]; 541 542 /* Interrupt Throttle Rate */ 543 u32 rx_itr_setting; 544 u32 tx_itr_setting; 545 u16 tx_itr; 546 u16 rx_itr; 547 548 /* TX */ 549 u16 tx_work_limit; 550 u32 tx_timeout_count; 551 int num_tx_queues; 552 struct igb_ring *tx_ring[16]; 553 554 /* RX */ 555 int num_rx_queues; 556 struct igb_ring *rx_ring[16]; 557 558 u32 max_frame_size; 559 u32 min_frame_size; 560 561 struct timer_list watchdog_timer; 562 struct timer_list phy_info_timer; 563 564 u16 mng_vlan_id; 565 u32 bd_number; 566 u32 wol; 567 u32 en_mng_pt; 568 u16 link_speed; 569 u16 link_duplex; 570 571 u8 __iomem *io_addr; /* Mainly for iounmap use */ 572 573 struct work_struct reset_task; 574 struct work_struct watchdog_task; 575 bool fc_autoneg; 576 u8 tx_timeout_factor; 577 struct timer_list blink_timer; 578 unsigned long led_status; 579 580 /* OS defined structs */ 581 struct pci_dev *pdev; 582 583 spinlock_t stats64_lock; 584 struct rtnl_link_stats64 stats64; 585 586 /* structs defined in e1000_hw.h */ 587 struct e1000_hw hw; 588 struct e1000_hw_stats stats; 589 struct e1000_phy_info phy_info; 590 591 u32 test_icr; 592 struct igb_ring test_tx_ring; 593 struct igb_ring test_rx_ring; 594 595 int msg_enable; 596 597 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 598 u32 eims_enable_mask; 599 u32 eims_other; 600 601 /* to not mess up cache alignment, always add to the bottom */ 602 u16 tx_ring_count; 603 u16 rx_ring_count; 604 unsigned int vfs_allocated_count; 605 struct vf_data_storage *vf_data; 606 int vf_rate_link_speed; 607 u32 rss_queues; 608 u32 wvbr; 609 u32 *shadow_vfta; 610 611 struct ptp_clock *ptp_clock; 612 struct ptp_clock_info ptp_caps; 613 struct delayed_work ptp_overflow_work; 614 struct work_struct ptp_tx_work; 615 struct sk_buff *ptp_tx_skb; 616 struct hwtstamp_config tstamp_config; 617 unsigned long ptp_tx_start; 618 unsigned long last_rx_ptp_check; 619 unsigned long last_rx_timestamp; 620 unsigned int ptp_flags; 621 spinlock_t tmreg_lock; 622 struct cyclecounter cc; 623 struct timecounter tc; 624 u32 tx_hwtstamp_timeouts; 625 u32 tx_hwtstamp_skipped; 626 u32 rx_hwtstamp_cleared; 627 bool pps_sys_wrap_on; 628 629 struct ptp_pin_desc sdp_config[IGB_N_SDP]; 630 struct { 631 struct timespec64 start; 632 struct timespec64 period; 633 } perout[IGB_N_PEROUT]; 634 635 char fw_version[32]; 636 #ifdef CONFIG_IGB_HWMON 637 struct hwmon_buff *igb_hwmon_buff; 638 bool ets; 639 #endif 640 struct i2c_algo_bit_data i2c_algo; 641 struct i2c_adapter i2c_adap; 642 struct i2c_client *i2c_client; 643 u32 rss_indir_tbl_init; 644 u8 rss_indir_tbl[IGB_RETA_SIZE]; 645 646 unsigned long link_check_timeout; 647 int copper_tries; 648 struct e1000_info ei; 649 u16 eee_advert; 650 651 /* RX network flow classification support */ 652 struct hlist_head nfc_filter_list; 653 struct hlist_head cls_flower_list; 654 unsigned int nfc_filter_count; 655 /* lock for RX network flow classification filter */ 656 spinlock_t nfc_lock; 657 bool etype_bitmap[MAX_ETYPE_FILTER]; 658 659 struct igb_mac_addr *mac_table; 660 struct vf_mac_filter vf_macs; 661 struct vf_mac_filter *vf_mac_list; 662 }; 663 664 /* flags controlling PTP/1588 function */ 665 #define IGB_PTP_ENABLED BIT(0) 666 #define IGB_PTP_OVERFLOW_CHECK BIT(1) 667 668 #define IGB_FLAG_HAS_MSI BIT(0) 669 #define IGB_FLAG_DCA_ENABLED BIT(1) 670 #define IGB_FLAG_QUAD_PORT_A BIT(2) 671 #define IGB_FLAG_QUEUE_PAIRS BIT(3) 672 #define IGB_FLAG_DMAC BIT(4) 673 #define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 674 #define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 675 #define IGB_FLAG_WOL_SUPPORTED BIT(8) 676 #define IGB_FLAG_NEED_LINK_UPDATE BIT(9) 677 #define IGB_FLAG_MEDIA_RESET BIT(10) 678 #define IGB_FLAG_MAS_CAPABLE BIT(11) 679 #define IGB_FLAG_MAS_ENABLE BIT(12) 680 #define IGB_FLAG_HAS_MSIX BIT(13) 681 #define IGB_FLAG_EEE BIT(14) 682 #define IGB_FLAG_VLAN_PROMISC BIT(15) 683 #define IGB_FLAG_RX_LEGACY BIT(16) 684 #define IGB_FLAG_FQTSS BIT(17) 685 686 /* Media Auto Sense */ 687 #define IGB_MAS_ENABLE_0 0X0001 688 #define IGB_MAS_ENABLE_1 0X0002 689 #define IGB_MAS_ENABLE_2 0X0004 690 #define IGB_MAS_ENABLE_3 0X0008 691 692 /* DMA Coalescing defines */ 693 #define IGB_MIN_TXPBSIZE 20408 694 #define IGB_TX_BUF_4096 4096 695 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 696 697 #define IGB_82576_TSYNC_SHIFT 19 698 enum e1000_state_t { 699 __IGB_TESTING, 700 __IGB_RESETTING, 701 __IGB_DOWN, 702 __IGB_PTP_TX_IN_PROGRESS, 703 }; 704 705 enum igb_boards { 706 board_82575, 707 }; 708 709 extern char igb_driver_name[]; 710 711 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 712 struct igb_ring *ring, 713 struct xdp_frame *xdpf); 714 int igb_open(struct net_device *netdev); 715 int igb_close(struct net_device *netdev); 716 int igb_up(struct igb_adapter *); 717 void igb_down(struct igb_adapter *); 718 void igb_reinit_locked(struct igb_adapter *); 719 void igb_reset(struct igb_adapter *); 720 int igb_reinit_queues(struct igb_adapter *); 721 void igb_write_rss_indir_tbl(struct igb_adapter *); 722 int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 723 int igb_setup_tx_resources(struct igb_ring *); 724 int igb_setup_rx_resources(struct igb_ring *); 725 void igb_free_tx_resources(struct igb_ring *); 726 void igb_free_rx_resources(struct igb_ring *); 727 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 728 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 729 void igb_setup_tctl(struct igb_adapter *); 730 void igb_setup_rctl(struct igb_adapter *); 731 void igb_setup_srrctl(struct igb_adapter *, struct igb_ring *); 732 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 733 void igb_alloc_rx_buffers(struct igb_ring *, u16); 734 void igb_update_stats(struct igb_adapter *); 735 bool igb_has_link(struct igb_adapter *adapter); 736 void igb_set_ethtool_ops(struct net_device *); 737 void igb_power_up_link(struct igb_adapter *); 738 void igb_set_fw_version(struct igb_adapter *); 739 void igb_ptp_init(struct igb_adapter *adapter); 740 void igb_ptp_stop(struct igb_adapter *adapter); 741 void igb_ptp_reset(struct igb_adapter *adapter); 742 void igb_ptp_suspend(struct igb_adapter *adapter); 743 void igb_ptp_rx_hang(struct igb_adapter *adapter); 744 void igb_ptp_tx_hang(struct igb_adapter *adapter); 745 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb); 746 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, 747 struct sk_buff *skb); 748 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 749 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 750 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32); 751 unsigned int igb_get_max_rss_queues(struct igb_adapter *); 752 #ifdef CONFIG_IGB_HWMON 753 void igb_sysfs_exit(struct igb_adapter *adapter); 754 int igb_sysfs_init(struct igb_adapter *adapter); 755 #endif 756 static inline s32 igb_reset_phy(struct e1000_hw *hw) 757 { 758 if (hw->phy.ops.reset) 759 return hw->phy.ops.reset(hw); 760 761 return 0; 762 } 763 764 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 765 { 766 if (hw->phy.ops.read_reg) 767 return hw->phy.ops.read_reg(hw, offset, data); 768 769 return 0; 770 } 771 772 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 773 { 774 if (hw->phy.ops.write_reg) 775 return hw->phy.ops.write_reg(hw, offset, data); 776 777 return 0; 778 } 779 780 static inline s32 igb_get_phy_info(struct e1000_hw *hw) 781 { 782 if (hw->phy.ops.get_phy_info) 783 return hw->phy.ops.get_phy_info(hw); 784 785 return 0; 786 } 787 788 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 789 { 790 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 791 } 792 793 int igb_add_filter(struct igb_adapter *adapter, 794 struct igb_nfc_filter *input); 795 int igb_erase_filter(struct igb_adapter *adapter, 796 struct igb_nfc_filter *input); 797 798 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 799 const u8 *addr, u8 queue, u8 flags); 800 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 801 const u8 *addr, u8 queue, u8 flags); 802 803 #endif /* _IGB_H_ */ 804