1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* Linux PRO/1000 Ethernet Driver main header file */ 25 26 #ifndef _IGB_H_ 27 #define _IGB_H_ 28 29 #include "e1000_mac.h" 30 #include "e1000_82575.h" 31 32 #include <linux/timecounter.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <linux/bitops.h> 36 #include <linux/if_vlan.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/pci.h> 40 #include <linux/mdio.h> 41 42 struct igb_adapter; 43 44 #define E1000_PCS_CFG_IGN_SD 1 45 46 /* Interrupt defines */ 47 #define IGB_START_ITR 648 /* ~6000 ints/sec */ 48 #define IGB_4K_ITR 980 49 #define IGB_20K_ITR 196 50 #define IGB_70K_ITR 56 51 52 /* TX/RX descriptor defines */ 53 #define IGB_DEFAULT_TXD 256 54 #define IGB_DEFAULT_TX_WORK 128 55 #define IGB_MIN_TXD 80 56 #define IGB_MAX_TXD 4096 57 58 #define IGB_DEFAULT_RXD 256 59 #define IGB_MIN_RXD 80 60 #define IGB_MAX_RXD 4096 61 62 #define IGB_DEFAULT_ITR 3 /* dynamic */ 63 #define IGB_MAX_ITR_USECS 10000 64 #define IGB_MIN_ITR_USECS 10 65 #define NON_Q_VECTORS 1 66 #define MAX_Q_VECTORS 8 67 #define MAX_MSIX_ENTRIES 10 68 69 /* Transmit and receive queues */ 70 #define IGB_MAX_RX_QUEUES 8 71 #define IGB_MAX_RX_QUEUES_82575 4 72 #define IGB_MAX_RX_QUEUES_I211 2 73 #define IGB_MAX_TX_QUEUES 8 74 #define IGB_MAX_VF_MC_ENTRIES 30 75 #define IGB_MAX_VF_FUNCTIONS 8 76 #define IGB_MAX_VFTA_ENTRIES 128 77 #define IGB_82576_VF_DEV_ID 0x10CA 78 #define IGB_I350_VF_DEV_ID 0x1520 79 80 /* NVM version defines */ 81 #define IGB_MAJOR_MASK 0xF000 82 #define IGB_MINOR_MASK 0x0FF0 83 #define IGB_BUILD_MASK 0x000F 84 #define IGB_COMB_VER_MASK 0x00FF 85 #define IGB_MAJOR_SHIFT 12 86 #define IGB_MINOR_SHIFT 4 87 #define IGB_COMB_VER_SHFT 8 88 #define IGB_NVM_VER_INVALID 0xFFFF 89 #define IGB_ETRACK_SHIFT 16 90 #define NVM_ETRACK_WORD 0x0042 91 #define NVM_COMB_VER_OFF 0x0083 92 #define NVM_COMB_VER_PTR 0x003d 93 94 /* Transmit and receive latency (for PTP timestamps) */ 95 #define IGB_I210_TX_LATENCY_10 9542 96 #define IGB_I210_TX_LATENCY_100 1024 97 #define IGB_I210_TX_LATENCY_1000 178 98 #define IGB_I210_RX_LATENCY_10 20662 99 #define IGB_I210_RX_LATENCY_100 2213 100 #define IGB_I210_RX_LATENCY_1000 448 101 102 struct vf_data_storage { 103 unsigned char vf_mac_addresses[ETH_ALEN]; 104 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 105 u16 num_vf_mc_hashes; 106 u32 flags; 107 unsigned long last_nack; 108 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 109 u16 pf_qos; 110 u16 tx_rate; 111 bool spoofchk_enabled; 112 }; 113 114 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 115 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 116 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 117 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 118 119 /* RX descriptor control thresholds. 120 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 121 * descriptors available in its onboard memory. 122 * Setting this to 0 disables RX descriptor prefetch. 123 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 124 * available in host memory. 125 * If PTHRESH is 0, this should also be 0. 126 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 127 * descriptors until either it has this many to write back, or the 128 * ITR timer expires. 129 */ 130 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) 131 #define IGB_RX_HTHRESH 8 132 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 133 #define IGB_TX_HTHRESH 1 134 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 135 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4) 136 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 137 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16) 138 139 /* this is the size past which hardware will drop packets when setting LPE=0 */ 140 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 141 142 /* Supported Rx Buffer Sizes */ 143 #define IGB_RXBUFFER_256 256 144 #define IGB_RXBUFFER_2048 2048 145 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 146 #define IGB_RX_BUFSZ IGB_RXBUFFER_2048 147 148 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 149 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 150 151 #define AUTO_ALL_MODES 0 152 #define IGB_EEPROM_APME 0x0400 153 154 #ifndef IGB_MASTER_SLAVE 155 /* Switch to override PHY master/slave setting */ 156 #define IGB_MASTER_SLAVE e1000_ms_hw_default 157 #endif 158 159 #define IGB_MNG_VLAN_NONE -1 160 161 enum igb_tx_flags { 162 /* cmd_type flags */ 163 IGB_TX_FLAGS_VLAN = 0x01, 164 IGB_TX_FLAGS_TSO = 0x02, 165 IGB_TX_FLAGS_TSTAMP = 0x04, 166 167 /* olinfo flags */ 168 IGB_TX_FLAGS_IPV4 = 0x10, 169 IGB_TX_FLAGS_CSUM = 0x20, 170 }; 171 172 /* VLAN info */ 173 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 174 #define IGB_TX_FLAGS_VLAN_SHIFT 16 175 176 /* The largest size we can write to the descriptor is 65535. In order to 177 * maintain a power of two alignment we have to limit ourselves to 32K. 178 */ 179 #define IGB_MAX_TXD_PWR 15 180 #define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR) 181 182 /* Tx Descriptors needed, worst case */ 183 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) 184 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 185 186 /* EEPROM byte offsets */ 187 #define IGB_SFF_8472_SWAP 0x5C 188 #define IGB_SFF_8472_COMP 0x5E 189 190 /* Bitmasks */ 191 #define IGB_SFF_ADDRESSING_MODE 0x4 192 #define IGB_SFF_8472_UNSUP 0x00 193 194 /* wrapper around a pointer to a socket buffer, 195 * so a DMA handle can be stored along with the buffer 196 */ 197 struct igb_tx_buffer { 198 union e1000_adv_tx_desc *next_to_watch; 199 unsigned long time_stamp; 200 struct sk_buff *skb; 201 unsigned int bytecount; 202 u16 gso_segs; 203 __be16 protocol; 204 205 DEFINE_DMA_UNMAP_ADDR(dma); 206 DEFINE_DMA_UNMAP_LEN(len); 207 u32 tx_flags; 208 }; 209 210 struct igb_rx_buffer { 211 dma_addr_t dma; 212 struct page *page; 213 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 214 __u32 page_offset; 215 #else 216 __u16 page_offset; 217 #endif 218 __u16 pagecnt_bias; 219 }; 220 221 struct igb_tx_queue_stats { 222 u64 packets; 223 u64 bytes; 224 u64 restart_queue; 225 u64 restart_queue2; 226 }; 227 228 struct igb_rx_queue_stats { 229 u64 packets; 230 u64 bytes; 231 u64 drops; 232 u64 csum_err; 233 u64 alloc_failed; 234 }; 235 236 struct igb_ring_container { 237 struct igb_ring *ring; /* pointer to linked list of rings */ 238 unsigned int total_bytes; /* total bytes processed this int */ 239 unsigned int total_packets; /* total packets processed this int */ 240 u16 work_limit; /* total work allowed per interrupt */ 241 u8 count; /* total number of rings in vector */ 242 u8 itr; /* current ITR setting for ring */ 243 }; 244 245 struct igb_ring { 246 struct igb_q_vector *q_vector; /* backlink to q_vector */ 247 struct net_device *netdev; /* back pointer to net_device */ 248 struct device *dev; /* device pointer for dma mapping */ 249 union { /* array of buffer info structs */ 250 struct igb_tx_buffer *tx_buffer_info; 251 struct igb_rx_buffer *rx_buffer_info; 252 }; 253 void *desc; /* descriptor ring memory */ 254 unsigned long flags; /* ring specific flags */ 255 void __iomem *tail; /* pointer to ring tail register */ 256 dma_addr_t dma; /* phys address of the ring */ 257 unsigned int size; /* length of desc. ring in bytes */ 258 259 u16 count; /* number of desc. in the ring */ 260 u8 queue_index; /* logical index of the ring*/ 261 u8 reg_idx; /* physical index of the ring */ 262 263 /* everything past this point are written often */ 264 u16 next_to_clean; 265 u16 next_to_use; 266 u16 next_to_alloc; 267 268 union { 269 /* TX */ 270 struct { 271 struct igb_tx_queue_stats tx_stats; 272 struct u64_stats_sync tx_syncp; 273 struct u64_stats_sync tx_syncp2; 274 }; 275 /* RX */ 276 struct { 277 struct sk_buff *skb; 278 struct igb_rx_queue_stats rx_stats; 279 struct u64_stats_sync rx_syncp; 280 }; 281 }; 282 } ____cacheline_internodealigned_in_smp; 283 284 struct igb_q_vector { 285 struct igb_adapter *adapter; /* backlink */ 286 int cpu; /* CPU for DCA */ 287 u32 eims_value; /* EIMS mask value */ 288 289 u16 itr_val; 290 u8 set_itr; 291 void __iomem *itr_register; 292 293 struct igb_ring_container rx, tx; 294 295 struct napi_struct napi; 296 struct rcu_head rcu; /* to avoid race with update stats on free */ 297 char name[IFNAMSIZ + 9]; 298 299 /* for dynamic allocation of rings associated with this q_vector */ 300 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; 301 }; 302 303 enum e1000_ring_flags_t { 304 IGB_RING_FLAG_RX_SCTP_CSUM, 305 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 306 IGB_RING_FLAG_TX_CTX_IDX, 307 IGB_RING_FLAG_TX_DETECT_HANG 308 }; 309 310 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 311 312 #define IGB_RX_DESC(R, i) \ 313 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 314 #define IGB_TX_DESC(R, i) \ 315 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 316 #define IGB_TX_CTXTDESC(R, i) \ 317 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 318 319 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 320 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 321 const u32 stat_err_bits) 322 { 323 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 324 } 325 326 /* igb_desc_unused - calculate if we have unused descriptors */ 327 static inline int igb_desc_unused(struct igb_ring *ring) 328 { 329 if (ring->next_to_clean > ring->next_to_use) 330 return ring->next_to_clean - ring->next_to_use - 1; 331 332 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 333 } 334 335 #ifdef CONFIG_IGB_HWMON 336 337 #define IGB_HWMON_TYPE_LOC 0 338 #define IGB_HWMON_TYPE_TEMP 1 339 #define IGB_HWMON_TYPE_CAUTION 2 340 #define IGB_HWMON_TYPE_MAX 3 341 342 struct hwmon_attr { 343 struct device_attribute dev_attr; 344 struct e1000_hw *hw; 345 struct e1000_thermal_diode_data *sensor; 346 char name[12]; 347 }; 348 349 struct hwmon_buff { 350 struct attribute_group group; 351 const struct attribute_group *groups[2]; 352 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1]; 353 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4]; 354 unsigned int n_hwmon; 355 }; 356 #endif 357 358 /* The number of L2 ether-type filter registers, Index 3 is reserved 359 * for PTP 1588 timestamp 360 */ 361 #define MAX_ETYPE_FILTER (4 - 1) 362 /* ETQF filter list: one static filter per filter consumer. This is 363 * to avoid filter collisions later. Add new filters here!! 364 * 365 * Current filters: Filter 3 366 */ 367 #define IGB_ETQF_FILTER_1588 3 368 369 #define IGB_N_EXTTS 2 370 #define IGB_N_PEROUT 2 371 #define IGB_N_SDP 4 372 #define IGB_RETA_SIZE 128 373 374 enum igb_filter_match_flags { 375 IGB_FILTER_FLAG_ETHER_TYPE = 0x1, 376 IGB_FILTER_FLAG_VLAN_TCI = 0x2, 377 }; 378 379 #define IGB_MAX_RXNFC_FILTERS 16 380 381 /* RX network flow classification data structure */ 382 struct igb_nfc_input { 383 /* Byte layout in order, all values with MSB first: 384 * match_flags - 1 byte 385 * etype - 2 bytes 386 * vlan_tci - 2 bytes 387 */ 388 u8 match_flags; 389 __be16 etype; 390 __be16 vlan_tci; 391 }; 392 393 struct igb_nfc_filter { 394 struct hlist_node nfc_node; 395 struct igb_nfc_input filter; 396 u16 etype_reg_index; 397 u16 sw_idx; 398 u16 action; 399 }; 400 401 /* board specific private data structure */ 402 struct igb_adapter { 403 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 404 405 struct net_device *netdev; 406 407 unsigned long state; 408 unsigned int flags; 409 410 unsigned int num_q_vectors; 411 struct msix_entry msix_entries[MAX_MSIX_ENTRIES]; 412 413 /* Interrupt Throttle Rate */ 414 u32 rx_itr_setting; 415 u32 tx_itr_setting; 416 u16 tx_itr; 417 u16 rx_itr; 418 419 /* TX */ 420 u16 tx_work_limit; 421 u32 tx_timeout_count; 422 int num_tx_queues; 423 struct igb_ring *tx_ring[16]; 424 425 /* RX */ 426 int num_rx_queues; 427 struct igb_ring *rx_ring[16]; 428 429 u32 max_frame_size; 430 u32 min_frame_size; 431 432 struct timer_list watchdog_timer; 433 struct timer_list phy_info_timer; 434 435 u16 mng_vlan_id; 436 u32 bd_number; 437 u32 wol; 438 u32 en_mng_pt; 439 u16 link_speed; 440 u16 link_duplex; 441 442 u8 __iomem *io_addr; /* Mainly for iounmap use */ 443 444 struct work_struct reset_task; 445 struct work_struct watchdog_task; 446 bool fc_autoneg; 447 u8 tx_timeout_factor; 448 struct timer_list blink_timer; 449 unsigned long led_status; 450 451 /* OS defined structs */ 452 struct pci_dev *pdev; 453 454 spinlock_t stats64_lock; 455 struct rtnl_link_stats64 stats64; 456 457 /* structs defined in e1000_hw.h */ 458 struct e1000_hw hw; 459 struct e1000_hw_stats stats; 460 struct e1000_phy_info phy_info; 461 462 u32 test_icr; 463 struct igb_ring test_tx_ring; 464 struct igb_ring test_rx_ring; 465 466 int msg_enable; 467 468 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 469 u32 eims_enable_mask; 470 u32 eims_other; 471 472 /* to not mess up cache alignment, always add to the bottom */ 473 u16 tx_ring_count; 474 u16 rx_ring_count; 475 unsigned int vfs_allocated_count; 476 struct vf_data_storage *vf_data; 477 int vf_rate_link_speed; 478 u32 rss_queues; 479 u32 wvbr; 480 u32 *shadow_vfta; 481 482 struct ptp_clock *ptp_clock; 483 struct ptp_clock_info ptp_caps; 484 struct delayed_work ptp_overflow_work; 485 struct work_struct ptp_tx_work; 486 struct sk_buff *ptp_tx_skb; 487 struct hwtstamp_config tstamp_config; 488 unsigned long ptp_tx_start; 489 unsigned long last_rx_ptp_check; 490 unsigned long last_rx_timestamp; 491 unsigned int ptp_flags; 492 spinlock_t tmreg_lock; 493 struct cyclecounter cc; 494 struct timecounter tc; 495 u32 tx_hwtstamp_timeouts; 496 u32 rx_hwtstamp_cleared; 497 bool pps_sys_wrap_on; 498 499 struct ptp_pin_desc sdp_config[IGB_N_SDP]; 500 struct { 501 struct timespec64 start; 502 struct timespec64 period; 503 } perout[IGB_N_PEROUT]; 504 505 char fw_version[32]; 506 #ifdef CONFIG_IGB_HWMON 507 struct hwmon_buff *igb_hwmon_buff; 508 bool ets; 509 #endif 510 struct i2c_algo_bit_data i2c_algo; 511 struct i2c_adapter i2c_adap; 512 struct i2c_client *i2c_client; 513 u32 rss_indir_tbl_init; 514 u8 rss_indir_tbl[IGB_RETA_SIZE]; 515 516 unsigned long link_check_timeout; 517 int copper_tries; 518 struct e1000_info ei; 519 u16 eee_advert; 520 521 /* RX network flow classification support */ 522 struct hlist_head nfc_filter_list; 523 unsigned int nfc_filter_count; 524 /* lock for RX network flow classification filter */ 525 spinlock_t nfc_lock; 526 bool etype_bitmap[MAX_ETYPE_FILTER]; 527 }; 528 529 /* flags controlling PTP/1588 function */ 530 #define IGB_PTP_ENABLED BIT(0) 531 #define IGB_PTP_OVERFLOW_CHECK BIT(1) 532 533 #define IGB_FLAG_HAS_MSI BIT(0) 534 #define IGB_FLAG_DCA_ENABLED BIT(1) 535 #define IGB_FLAG_QUAD_PORT_A BIT(2) 536 #define IGB_FLAG_QUEUE_PAIRS BIT(3) 537 #define IGB_FLAG_DMAC BIT(4) 538 #define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 539 #define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 540 #define IGB_FLAG_WOL_SUPPORTED BIT(8) 541 #define IGB_FLAG_NEED_LINK_UPDATE BIT(9) 542 #define IGB_FLAG_MEDIA_RESET BIT(10) 543 #define IGB_FLAG_MAS_CAPABLE BIT(11) 544 #define IGB_FLAG_MAS_ENABLE BIT(12) 545 #define IGB_FLAG_HAS_MSIX BIT(13) 546 #define IGB_FLAG_EEE BIT(14) 547 #define IGB_FLAG_VLAN_PROMISC BIT(15) 548 549 /* Media Auto Sense */ 550 #define IGB_MAS_ENABLE_0 0X0001 551 #define IGB_MAS_ENABLE_1 0X0002 552 #define IGB_MAS_ENABLE_2 0X0004 553 #define IGB_MAS_ENABLE_3 0X0008 554 555 /* DMA Coalescing defines */ 556 #define IGB_MIN_TXPBSIZE 20408 557 #define IGB_TX_BUF_4096 4096 558 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 559 560 #define IGB_82576_TSYNC_SHIFT 19 561 #define IGB_TS_HDR_LEN 16 562 enum e1000_state_t { 563 __IGB_TESTING, 564 __IGB_RESETTING, 565 __IGB_DOWN, 566 __IGB_PTP_TX_IN_PROGRESS, 567 }; 568 569 enum igb_boards { 570 board_82575, 571 }; 572 573 extern char igb_driver_name[]; 574 extern char igb_driver_version[]; 575 576 int igb_open(struct net_device *netdev); 577 int igb_close(struct net_device *netdev); 578 int igb_up(struct igb_adapter *); 579 void igb_down(struct igb_adapter *); 580 void igb_reinit_locked(struct igb_adapter *); 581 void igb_reset(struct igb_adapter *); 582 int igb_reinit_queues(struct igb_adapter *); 583 void igb_write_rss_indir_tbl(struct igb_adapter *); 584 int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 585 int igb_setup_tx_resources(struct igb_ring *); 586 int igb_setup_rx_resources(struct igb_ring *); 587 void igb_free_tx_resources(struct igb_ring *); 588 void igb_free_rx_resources(struct igb_ring *); 589 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 590 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 591 void igb_setup_tctl(struct igb_adapter *); 592 void igb_setup_rctl(struct igb_adapter *); 593 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 594 void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *); 595 void igb_alloc_rx_buffers(struct igb_ring *, u16); 596 void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 597 bool igb_has_link(struct igb_adapter *adapter); 598 void igb_set_ethtool_ops(struct net_device *); 599 void igb_power_up_link(struct igb_adapter *); 600 void igb_set_fw_version(struct igb_adapter *); 601 void igb_ptp_init(struct igb_adapter *adapter); 602 void igb_ptp_stop(struct igb_adapter *adapter); 603 void igb_ptp_reset(struct igb_adapter *adapter); 604 void igb_ptp_suspend(struct igb_adapter *adapter); 605 void igb_ptp_rx_hang(struct igb_adapter *adapter); 606 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb); 607 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va, 608 struct sk_buff *skb); 609 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 610 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 611 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32); 612 #ifdef CONFIG_IGB_HWMON 613 void igb_sysfs_exit(struct igb_adapter *adapter); 614 int igb_sysfs_init(struct igb_adapter *adapter); 615 #endif 616 static inline s32 igb_reset_phy(struct e1000_hw *hw) 617 { 618 if (hw->phy.ops.reset) 619 return hw->phy.ops.reset(hw); 620 621 return 0; 622 } 623 624 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 625 { 626 if (hw->phy.ops.read_reg) 627 return hw->phy.ops.read_reg(hw, offset, data); 628 629 return 0; 630 } 631 632 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 633 { 634 if (hw->phy.ops.write_reg) 635 return hw->phy.ops.write_reg(hw, offset, data); 636 637 return 0; 638 } 639 640 static inline s32 igb_get_phy_info(struct e1000_hw *hw) 641 { 642 if (hw->phy.ops.get_phy_info) 643 return hw->phy.ops.get_phy_info(hw); 644 645 return 0; 646 } 647 648 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 649 { 650 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 651 } 652 653 int igb_add_filter(struct igb_adapter *adapter, 654 struct igb_nfc_filter *input); 655 int igb_erase_filter(struct igb_adapter *adapter, 656 struct igb_nfc_filter *input); 657 658 #endif /* _IGB_H_ */ 659