1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* Linux PRO/1000 Ethernet Driver main header file */ 25 26 #ifndef _IGB_H_ 27 #define _IGB_H_ 28 29 #include "e1000_mac.h" 30 #include "e1000_82575.h" 31 32 #include <linux/timecounter.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <linux/bitops.h> 36 #include <linux/if_vlan.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/pci.h> 40 #include <linux/mdio.h> 41 42 struct igb_adapter; 43 44 #define E1000_PCS_CFG_IGN_SD 1 45 46 /* Interrupt defines */ 47 #define IGB_START_ITR 648 /* ~6000 ints/sec */ 48 #define IGB_4K_ITR 980 49 #define IGB_20K_ITR 196 50 #define IGB_70K_ITR 56 51 52 /* TX/RX descriptor defines */ 53 #define IGB_DEFAULT_TXD 256 54 #define IGB_DEFAULT_TX_WORK 128 55 #define IGB_MIN_TXD 80 56 #define IGB_MAX_TXD 4096 57 58 #define IGB_DEFAULT_RXD 256 59 #define IGB_MIN_RXD 80 60 #define IGB_MAX_RXD 4096 61 62 #define IGB_DEFAULT_ITR 3 /* dynamic */ 63 #define IGB_MAX_ITR_USECS 10000 64 #define IGB_MIN_ITR_USECS 10 65 #define NON_Q_VECTORS 1 66 #define MAX_Q_VECTORS 8 67 #define MAX_MSIX_ENTRIES 10 68 69 /* Transmit and receive queues */ 70 #define IGB_MAX_RX_QUEUES 8 71 #define IGB_MAX_RX_QUEUES_82575 4 72 #define IGB_MAX_RX_QUEUES_I211 2 73 #define IGB_MAX_TX_QUEUES 8 74 #define IGB_MAX_VF_MC_ENTRIES 30 75 #define IGB_MAX_VF_FUNCTIONS 8 76 #define IGB_MAX_VFTA_ENTRIES 128 77 #define IGB_82576_VF_DEV_ID 0x10CA 78 #define IGB_I350_VF_DEV_ID 0x1520 79 80 /* NVM version defines */ 81 #define IGB_MAJOR_MASK 0xF000 82 #define IGB_MINOR_MASK 0x0FF0 83 #define IGB_BUILD_MASK 0x000F 84 #define IGB_COMB_VER_MASK 0x00FF 85 #define IGB_MAJOR_SHIFT 12 86 #define IGB_MINOR_SHIFT 4 87 #define IGB_COMB_VER_SHFT 8 88 #define IGB_NVM_VER_INVALID 0xFFFF 89 #define IGB_ETRACK_SHIFT 16 90 #define NVM_ETRACK_WORD 0x0042 91 #define NVM_COMB_VER_OFF 0x0083 92 #define NVM_COMB_VER_PTR 0x003d 93 94 /* Transmit and receive latency (for PTP timestamps) */ 95 #define IGB_I210_TX_LATENCY_10 9542 96 #define IGB_I210_TX_LATENCY_100 1024 97 #define IGB_I210_TX_LATENCY_1000 178 98 #define IGB_I210_RX_LATENCY_10 20662 99 #define IGB_I210_RX_LATENCY_100 2213 100 #define IGB_I210_RX_LATENCY_1000 448 101 102 struct vf_data_storage { 103 unsigned char vf_mac_addresses[ETH_ALEN]; 104 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 105 u16 num_vf_mc_hashes; 106 u32 flags; 107 unsigned long last_nack; 108 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 109 u16 pf_qos; 110 u16 tx_rate; 111 bool spoofchk_enabled; 112 }; 113 114 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 115 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 116 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 117 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 118 119 /* RX descriptor control thresholds. 120 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 121 * descriptors available in its onboard memory. 122 * Setting this to 0 disables RX descriptor prefetch. 123 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 124 * available in host memory. 125 * If PTHRESH is 0, this should also be 0. 126 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 127 * descriptors until either it has this many to write back, or the 128 * ITR timer expires. 129 */ 130 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) 131 #define IGB_RX_HTHRESH 8 132 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 133 #define IGB_TX_HTHRESH 1 134 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 135 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4) 136 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 137 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16) 138 139 /* this is the size past which hardware will drop packets when setting LPE=0 */ 140 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 141 142 /* Supported Rx Buffer Sizes */ 143 #define IGB_RXBUFFER_256 256 144 #define IGB_RXBUFFER_2048 2048 145 #define IGB_RXBUFFER_3072 3072 146 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 147 #define IGB_TS_HDR_LEN 16 148 149 #define IGB_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 150 #if (PAGE_SIZE < 8192) 151 #define IGB_MAX_FRAME_BUILD_SKB \ 152 (SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048) - IGB_SKB_PAD - IGB_TS_HDR_LEN) 153 #else 154 #define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_2048 - IGB_TS_HDR_LEN) 155 #endif 156 157 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 158 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 159 160 #define IGB_RX_DMA_ATTR \ 161 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 162 163 #define AUTO_ALL_MODES 0 164 #define IGB_EEPROM_APME 0x0400 165 166 #ifndef IGB_MASTER_SLAVE 167 /* Switch to override PHY master/slave setting */ 168 #define IGB_MASTER_SLAVE e1000_ms_hw_default 169 #endif 170 171 #define IGB_MNG_VLAN_NONE -1 172 173 enum igb_tx_flags { 174 /* cmd_type flags */ 175 IGB_TX_FLAGS_VLAN = 0x01, 176 IGB_TX_FLAGS_TSO = 0x02, 177 IGB_TX_FLAGS_TSTAMP = 0x04, 178 179 /* olinfo flags */ 180 IGB_TX_FLAGS_IPV4 = 0x10, 181 IGB_TX_FLAGS_CSUM = 0x20, 182 }; 183 184 /* VLAN info */ 185 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 186 #define IGB_TX_FLAGS_VLAN_SHIFT 16 187 188 /* The largest size we can write to the descriptor is 65535. In order to 189 * maintain a power of two alignment we have to limit ourselves to 32K. 190 */ 191 #define IGB_MAX_TXD_PWR 15 192 #define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR) 193 194 /* Tx Descriptors needed, worst case */ 195 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) 196 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 197 198 /* EEPROM byte offsets */ 199 #define IGB_SFF_8472_SWAP 0x5C 200 #define IGB_SFF_8472_COMP 0x5E 201 202 /* Bitmasks */ 203 #define IGB_SFF_ADDRESSING_MODE 0x4 204 #define IGB_SFF_8472_UNSUP 0x00 205 206 /* wrapper around a pointer to a socket buffer, 207 * so a DMA handle can be stored along with the buffer 208 */ 209 struct igb_tx_buffer { 210 union e1000_adv_tx_desc *next_to_watch; 211 unsigned long time_stamp; 212 struct sk_buff *skb; 213 unsigned int bytecount; 214 u16 gso_segs; 215 __be16 protocol; 216 217 DEFINE_DMA_UNMAP_ADDR(dma); 218 DEFINE_DMA_UNMAP_LEN(len); 219 u32 tx_flags; 220 }; 221 222 struct igb_rx_buffer { 223 dma_addr_t dma; 224 struct page *page; 225 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 226 __u32 page_offset; 227 #else 228 __u16 page_offset; 229 #endif 230 __u16 pagecnt_bias; 231 }; 232 233 struct igb_tx_queue_stats { 234 u64 packets; 235 u64 bytes; 236 u64 restart_queue; 237 u64 restart_queue2; 238 }; 239 240 struct igb_rx_queue_stats { 241 u64 packets; 242 u64 bytes; 243 u64 drops; 244 u64 csum_err; 245 u64 alloc_failed; 246 }; 247 248 struct igb_ring_container { 249 struct igb_ring *ring; /* pointer to linked list of rings */ 250 unsigned int total_bytes; /* total bytes processed this int */ 251 unsigned int total_packets; /* total packets processed this int */ 252 u16 work_limit; /* total work allowed per interrupt */ 253 u8 count; /* total number of rings in vector */ 254 u8 itr; /* current ITR setting for ring */ 255 }; 256 257 struct igb_ring { 258 struct igb_q_vector *q_vector; /* backlink to q_vector */ 259 struct net_device *netdev; /* back pointer to net_device */ 260 struct device *dev; /* device pointer for dma mapping */ 261 union { /* array of buffer info structs */ 262 struct igb_tx_buffer *tx_buffer_info; 263 struct igb_rx_buffer *rx_buffer_info; 264 }; 265 void *desc; /* descriptor ring memory */ 266 unsigned long flags; /* ring specific flags */ 267 void __iomem *tail; /* pointer to ring tail register */ 268 dma_addr_t dma; /* phys address of the ring */ 269 unsigned int size; /* length of desc. ring in bytes */ 270 271 u16 count; /* number of desc. in the ring */ 272 u8 queue_index; /* logical index of the ring*/ 273 u8 reg_idx; /* physical index of the ring */ 274 275 /* everything past this point are written often */ 276 u16 next_to_clean; 277 u16 next_to_use; 278 u16 next_to_alloc; 279 280 union { 281 /* TX */ 282 struct { 283 struct igb_tx_queue_stats tx_stats; 284 struct u64_stats_sync tx_syncp; 285 struct u64_stats_sync tx_syncp2; 286 }; 287 /* RX */ 288 struct { 289 struct sk_buff *skb; 290 struct igb_rx_queue_stats rx_stats; 291 struct u64_stats_sync rx_syncp; 292 }; 293 }; 294 } ____cacheline_internodealigned_in_smp; 295 296 struct igb_q_vector { 297 struct igb_adapter *adapter; /* backlink */ 298 int cpu; /* CPU for DCA */ 299 u32 eims_value; /* EIMS mask value */ 300 301 u16 itr_val; 302 u8 set_itr; 303 void __iomem *itr_register; 304 305 struct igb_ring_container rx, tx; 306 307 struct napi_struct napi; 308 struct rcu_head rcu; /* to avoid race with update stats on free */ 309 char name[IFNAMSIZ + 9]; 310 311 /* for dynamic allocation of rings associated with this q_vector */ 312 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; 313 }; 314 315 enum e1000_ring_flags_t { 316 IGB_RING_FLAG_RX_3K_BUFFER, 317 IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, 318 IGB_RING_FLAG_RX_SCTP_CSUM, 319 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 320 IGB_RING_FLAG_TX_CTX_IDX, 321 IGB_RING_FLAG_TX_DETECT_HANG 322 }; 323 324 #define ring_uses_large_buffer(ring) \ 325 test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 326 #define set_ring_uses_large_buffer(ring) \ 327 set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 328 #define clear_ring_uses_large_buffer(ring) \ 329 clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 330 331 #define ring_uses_build_skb(ring) \ 332 test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 333 #define set_ring_build_skb_enabled(ring) \ 334 set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 335 #define clear_ring_build_skb_enabled(ring) \ 336 clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 337 338 static inline unsigned int igb_rx_bufsz(struct igb_ring *ring) 339 { 340 #if (PAGE_SIZE < 8192) 341 if (ring_uses_large_buffer(ring)) 342 return IGB_RXBUFFER_3072; 343 344 if (ring_uses_build_skb(ring)) 345 return IGB_MAX_FRAME_BUILD_SKB + IGB_TS_HDR_LEN; 346 #endif 347 return IGB_RXBUFFER_2048; 348 } 349 350 static inline unsigned int igb_rx_pg_order(struct igb_ring *ring) 351 { 352 #if (PAGE_SIZE < 8192) 353 if (ring_uses_large_buffer(ring)) 354 return 1; 355 #endif 356 return 0; 357 } 358 359 #define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring)) 360 361 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 362 363 #define IGB_RX_DESC(R, i) \ 364 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 365 #define IGB_TX_DESC(R, i) \ 366 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 367 #define IGB_TX_CTXTDESC(R, i) \ 368 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 369 370 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 371 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 372 const u32 stat_err_bits) 373 { 374 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 375 } 376 377 /* igb_desc_unused - calculate if we have unused descriptors */ 378 static inline int igb_desc_unused(struct igb_ring *ring) 379 { 380 if (ring->next_to_clean > ring->next_to_use) 381 return ring->next_to_clean - ring->next_to_use - 1; 382 383 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 384 } 385 386 #ifdef CONFIG_IGB_HWMON 387 388 #define IGB_HWMON_TYPE_LOC 0 389 #define IGB_HWMON_TYPE_TEMP 1 390 #define IGB_HWMON_TYPE_CAUTION 2 391 #define IGB_HWMON_TYPE_MAX 3 392 393 struct hwmon_attr { 394 struct device_attribute dev_attr; 395 struct e1000_hw *hw; 396 struct e1000_thermal_diode_data *sensor; 397 char name[12]; 398 }; 399 400 struct hwmon_buff { 401 struct attribute_group group; 402 const struct attribute_group *groups[2]; 403 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1]; 404 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4]; 405 unsigned int n_hwmon; 406 }; 407 #endif 408 409 /* The number of L2 ether-type filter registers, Index 3 is reserved 410 * for PTP 1588 timestamp 411 */ 412 #define MAX_ETYPE_FILTER (4 - 1) 413 /* ETQF filter list: one static filter per filter consumer. This is 414 * to avoid filter collisions later. Add new filters here!! 415 * 416 * Current filters: Filter 3 417 */ 418 #define IGB_ETQF_FILTER_1588 3 419 420 #define IGB_N_EXTTS 2 421 #define IGB_N_PEROUT 2 422 #define IGB_N_SDP 4 423 #define IGB_RETA_SIZE 128 424 425 enum igb_filter_match_flags { 426 IGB_FILTER_FLAG_ETHER_TYPE = 0x1, 427 IGB_FILTER_FLAG_VLAN_TCI = 0x2, 428 }; 429 430 #define IGB_MAX_RXNFC_FILTERS 16 431 432 /* RX network flow classification data structure */ 433 struct igb_nfc_input { 434 /* Byte layout in order, all values with MSB first: 435 * match_flags - 1 byte 436 * etype - 2 bytes 437 * vlan_tci - 2 bytes 438 */ 439 u8 match_flags; 440 __be16 etype; 441 __be16 vlan_tci; 442 }; 443 444 struct igb_nfc_filter { 445 struct hlist_node nfc_node; 446 struct igb_nfc_input filter; 447 u16 etype_reg_index; 448 u16 sw_idx; 449 u16 action; 450 }; 451 452 /* board specific private data structure */ 453 struct igb_adapter { 454 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 455 456 struct net_device *netdev; 457 458 unsigned long state; 459 unsigned int flags; 460 461 unsigned int num_q_vectors; 462 struct msix_entry msix_entries[MAX_MSIX_ENTRIES]; 463 464 /* Interrupt Throttle Rate */ 465 u32 rx_itr_setting; 466 u32 tx_itr_setting; 467 u16 tx_itr; 468 u16 rx_itr; 469 470 /* TX */ 471 u16 tx_work_limit; 472 u32 tx_timeout_count; 473 int num_tx_queues; 474 struct igb_ring *tx_ring[16]; 475 476 /* RX */ 477 int num_rx_queues; 478 struct igb_ring *rx_ring[16]; 479 480 u32 max_frame_size; 481 u32 min_frame_size; 482 483 struct timer_list watchdog_timer; 484 struct timer_list phy_info_timer; 485 486 u16 mng_vlan_id; 487 u32 bd_number; 488 u32 wol; 489 u32 en_mng_pt; 490 u16 link_speed; 491 u16 link_duplex; 492 493 u8 __iomem *io_addr; /* Mainly for iounmap use */ 494 495 struct work_struct reset_task; 496 struct work_struct watchdog_task; 497 bool fc_autoneg; 498 u8 tx_timeout_factor; 499 struct timer_list blink_timer; 500 unsigned long led_status; 501 502 /* OS defined structs */ 503 struct pci_dev *pdev; 504 505 spinlock_t stats64_lock; 506 struct rtnl_link_stats64 stats64; 507 508 /* structs defined in e1000_hw.h */ 509 struct e1000_hw hw; 510 struct e1000_hw_stats stats; 511 struct e1000_phy_info phy_info; 512 513 u32 test_icr; 514 struct igb_ring test_tx_ring; 515 struct igb_ring test_rx_ring; 516 517 int msg_enable; 518 519 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 520 u32 eims_enable_mask; 521 u32 eims_other; 522 523 /* to not mess up cache alignment, always add to the bottom */ 524 u16 tx_ring_count; 525 u16 rx_ring_count; 526 unsigned int vfs_allocated_count; 527 struct vf_data_storage *vf_data; 528 int vf_rate_link_speed; 529 u32 rss_queues; 530 u32 wvbr; 531 u32 *shadow_vfta; 532 533 struct ptp_clock *ptp_clock; 534 struct ptp_clock_info ptp_caps; 535 struct delayed_work ptp_overflow_work; 536 struct work_struct ptp_tx_work; 537 struct sk_buff *ptp_tx_skb; 538 struct hwtstamp_config tstamp_config; 539 unsigned long ptp_tx_start; 540 unsigned long last_rx_ptp_check; 541 unsigned long last_rx_timestamp; 542 unsigned int ptp_flags; 543 spinlock_t tmreg_lock; 544 struct cyclecounter cc; 545 struct timecounter tc; 546 u32 tx_hwtstamp_timeouts; 547 u32 rx_hwtstamp_cleared; 548 bool pps_sys_wrap_on; 549 550 struct ptp_pin_desc sdp_config[IGB_N_SDP]; 551 struct { 552 struct timespec64 start; 553 struct timespec64 period; 554 } perout[IGB_N_PEROUT]; 555 556 char fw_version[32]; 557 #ifdef CONFIG_IGB_HWMON 558 struct hwmon_buff *igb_hwmon_buff; 559 bool ets; 560 #endif 561 struct i2c_algo_bit_data i2c_algo; 562 struct i2c_adapter i2c_adap; 563 struct i2c_client *i2c_client; 564 u32 rss_indir_tbl_init; 565 u8 rss_indir_tbl[IGB_RETA_SIZE]; 566 567 unsigned long link_check_timeout; 568 int copper_tries; 569 struct e1000_info ei; 570 u16 eee_advert; 571 572 /* RX network flow classification support */ 573 struct hlist_head nfc_filter_list; 574 unsigned int nfc_filter_count; 575 /* lock for RX network flow classification filter */ 576 spinlock_t nfc_lock; 577 bool etype_bitmap[MAX_ETYPE_FILTER]; 578 }; 579 580 /* flags controlling PTP/1588 function */ 581 #define IGB_PTP_ENABLED BIT(0) 582 #define IGB_PTP_OVERFLOW_CHECK BIT(1) 583 584 #define IGB_FLAG_HAS_MSI BIT(0) 585 #define IGB_FLAG_DCA_ENABLED BIT(1) 586 #define IGB_FLAG_QUAD_PORT_A BIT(2) 587 #define IGB_FLAG_QUEUE_PAIRS BIT(3) 588 #define IGB_FLAG_DMAC BIT(4) 589 #define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 590 #define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 591 #define IGB_FLAG_WOL_SUPPORTED BIT(8) 592 #define IGB_FLAG_NEED_LINK_UPDATE BIT(9) 593 #define IGB_FLAG_MEDIA_RESET BIT(10) 594 #define IGB_FLAG_MAS_CAPABLE BIT(11) 595 #define IGB_FLAG_MAS_ENABLE BIT(12) 596 #define IGB_FLAG_HAS_MSIX BIT(13) 597 #define IGB_FLAG_EEE BIT(14) 598 #define IGB_FLAG_VLAN_PROMISC BIT(15) 599 #define IGB_FLAG_RX_LEGACY BIT(16) 600 601 /* Media Auto Sense */ 602 #define IGB_MAS_ENABLE_0 0X0001 603 #define IGB_MAS_ENABLE_1 0X0002 604 #define IGB_MAS_ENABLE_2 0X0004 605 #define IGB_MAS_ENABLE_3 0X0008 606 607 /* DMA Coalescing defines */ 608 #define IGB_MIN_TXPBSIZE 20408 609 #define IGB_TX_BUF_4096 4096 610 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 611 612 #define IGB_82576_TSYNC_SHIFT 19 613 enum e1000_state_t { 614 __IGB_TESTING, 615 __IGB_RESETTING, 616 __IGB_DOWN, 617 __IGB_PTP_TX_IN_PROGRESS, 618 }; 619 620 enum igb_boards { 621 board_82575, 622 }; 623 624 extern char igb_driver_name[]; 625 extern char igb_driver_version[]; 626 627 int igb_open(struct net_device *netdev); 628 int igb_close(struct net_device *netdev); 629 int igb_up(struct igb_adapter *); 630 void igb_down(struct igb_adapter *); 631 void igb_reinit_locked(struct igb_adapter *); 632 void igb_reset(struct igb_adapter *); 633 int igb_reinit_queues(struct igb_adapter *); 634 void igb_write_rss_indir_tbl(struct igb_adapter *); 635 int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 636 int igb_setup_tx_resources(struct igb_ring *); 637 int igb_setup_rx_resources(struct igb_ring *); 638 void igb_free_tx_resources(struct igb_ring *); 639 void igb_free_rx_resources(struct igb_ring *); 640 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 641 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 642 void igb_setup_tctl(struct igb_adapter *); 643 void igb_setup_rctl(struct igb_adapter *); 644 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 645 void igb_alloc_rx_buffers(struct igb_ring *, u16); 646 void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 647 bool igb_has_link(struct igb_adapter *adapter); 648 void igb_set_ethtool_ops(struct net_device *); 649 void igb_power_up_link(struct igb_adapter *); 650 void igb_set_fw_version(struct igb_adapter *); 651 void igb_ptp_init(struct igb_adapter *adapter); 652 void igb_ptp_stop(struct igb_adapter *adapter); 653 void igb_ptp_reset(struct igb_adapter *adapter); 654 void igb_ptp_suspend(struct igb_adapter *adapter); 655 void igb_ptp_rx_hang(struct igb_adapter *adapter); 656 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb); 657 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, 658 struct sk_buff *skb); 659 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 660 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 661 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32); 662 #ifdef CONFIG_IGB_HWMON 663 void igb_sysfs_exit(struct igb_adapter *adapter); 664 int igb_sysfs_init(struct igb_adapter *adapter); 665 #endif 666 static inline s32 igb_reset_phy(struct e1000_hw *hw) 667 { 668 if (hw->phy.ops.reset) 669 return hw->phy.ops.reset(hw); 670 671 return 0; 672 } 673 674 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 675 { 676 if (hw->phy.ops.read_reg) 677 return hw->phy.ops.read_reg(hw, offset, data); 678 679 return 0; 680 } 681 682 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 683 { 684 if (hw->phy.ops.write_reg) 685 return hw->phy.ops.write_reg(hw, offset, data); 686 687 return 0; 688 } 689 690 static inline s32 igb_get_phy_info(struct e1000_hw *hw) 691 { 692 if (hw->phy.ops.get_phy_info) 693 return hw->phy.ops.get_phy_info(hw); 694 695 return 0; 696 } 697 698 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 699 { 700 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 701 } 702 703 int igb_add_filter(struct igb_adapter *adapter, 704 struct igb_nfc_filter *input); 705 int igb_erase_filter(struct igb_adapter *adapter, 706 struct igb_nfc_filter *input); 707 708 #endif /* _IGB_H_ */ 709