1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #ifndef _E1000_HW_H_ 23 #define _E1000_HW_H_ 24 25 #include "regs.h" 26 #include "defines.h" 27 28 struct e1000_hw; 29 30 #define E1000_DEV_ID_82571EB_COPPER 0x105E 31 #define E1000_DEV_ID_82571EB_FIBER 0x105F 32 #define E1000_DEV_ID_82571EB_SERDES 0x1060 33 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 34 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 35 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 36 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 37 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 38 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 39 #define E1000_DEV_ID_82572EI_COPPER 0x107D 40 #define E1000_DEV_ID_82572EI_FIBER 0x107E 41 #define E1000_DEV_ID_82572EI_SERDES 0x107F 42 #define E1000_DEV_ID_82572EI 0x10B9 43 #define E1000_DEV_ID_82573E 0x108B 44 #define E1000_DEV_ID_82573E_IAMT 0x108C 45 #define E1000_DEV_ID_82573L 0x109A 46 #define E1000_DEV_ID_82574L 0x10D3 47 #define E1000_DEV_ID_82574LA 0x10F6 48 #define E1000_DEV_ID_82583V 0x150C 49 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 50 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 51 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 52 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 53 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 54 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 55 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 56 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 57 #define E1000_DEV_ID_ICH8_IFE 0x104C 58 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 59 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 60 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 61 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 62 #define E1000_DEV_ID_ICH9_BM 0x10E5 63 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 64 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 65 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 66 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 67 #define E1000_DEV_ID_ICH9_IFE 0x10C0 68 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 69 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 70 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 71 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 72 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 73 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 74 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 75 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 76 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 77 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 78 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 79 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 80 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 81 #define E1000_DEV_ID_PCH2_LV_V 0x1503 82 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 83 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 84 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 85 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 86 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 87 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 88 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 89 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 90 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */ 91 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */ 92 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */ 93 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */ 94 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */ 95 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 96 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 97 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 98 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 99 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 100 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 101 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 102 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 103 104 #define E1000_REVISION_4 4 105 106 #define E1000_FUNC_1 1 107 108 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 109 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 110 111 enum e1000_mac_type { 112 e1000_82571, 113 e1000_82572, 114 e1000_82573, 115 e1000_82574, 116 e1000_82583, 117 e1000_80003es2lan, 118 e1000_ich8lan, 119 e1000_ich9lan, 120 e1000_ich10lan, 121 e1000_pchlan, 122 e1000_pch2lan, 123 e1000_pch_lpt, 124 e1000_pch_spt, 125 e1000_pch_cnp, 126 }; 127 128 enum e1000_media_type { 129 e1000_media_type_unknown = 0, 130 e1000_media_type_copper = 1, 131 e1000_media_type_fiber = 2, 132 e1000_media_type_internal_serdes = 3, 133 e1000_num_media_types 134 }; 135 136 enum e1000_nvm_type { 137 e1000_nvm_unknown = 0, 138 e1000_nvm_none, 139 e1000_nvm_eeprom_spi, 140 e1000_nvm_flash_hw, 141 e1000_nvm_flash_sw 142 }; 143 144 enum e1000_nvm_override { 145 e1000_nvm_override_none = 0, 146 e1000_nvm_override_spi_small, 147 e1000_nvm_override_spi_large 148 }; 149 150 enum e1000_phy_type { 151 e1000_phy_unknown = 0, 152 e1000_phy_none, 153 e1000_phy_m88, 154 e1000_phy_igp, 155 e1000_phy_igp_2, 156 e1000_phy_gg82563, 157 e1000_phy_igp_3, 158 e1000_phy_ife, 159 e1000_phy_bm, 160 e1000_phy_82578, 161 e1000_phy_82577, 162 e1000_phy_82579, 163 e1000_phy_i217, 164 }; 165 166 enum e1000_bus_width { 167 e1000_bus_width_unknown = 0, 168 e1000_bus_width_pcie_x1, 169 e1000_bus_width_pcie_x2, 170 e1000_bus_width_pcie_x4 = 4, 171 e1000_bus_width_pcie_x8 = 8, 172 e1000_bus_width_32, 173 e1000_bus_width_64, 174 e1000_bus_width_reserved 175 }; 176 177 enum e1000_1000t_rx_status { 178 e1000_1000t_rx_status_not_ok = 0, 179 e1000_1000t_rx_status_ok, 180 e1000_1000t_rx_status_undefined = 0xFF 181 }; 182 183 enum e1000_rev_polarity { 184 e1000_rev_polarity_normal = 0, 185 e1000_rev_polarity_reversed, 186 e1000_rev_polarity_undefined = 0xFF 187 }; 188 189 enum e1000_fc_mode { 190 e1000_fc_none = 0, 191 e1000_fc_rx_pause, 192 e1000_fc_tx_pause, 193 e1000_fc_full, 194 e1000_fc_default = 0xFF 195 }; 196 197 enum e1000_ms_type { 198 e1000_ms_hw_default = 0, 199 e1000_ms_force_master, 200 e1000_ms_force_slave, 201 e1000_ms_auto 202 }; 203 204 enum e1000_smart_speed { 205 e1000_smart_speed_default = 0, 206 e1000_smart_speed_on, 207 e1000_smart_speed_off 208 }; 209 210 enum e1000_serdes_link_state { 211 e1000_serdes_link_down = 0, 212 e1000_serdes_link_autoneg_progress, 213 e1000_serdes_link_autoneg_complete, 214 e1000_serdes_link_forced_up 215 }; 216 217 /* Receive Descriptor - Extended */ 218 union e1000_rx_desc_extended { 219 struct { 220 __le64 buffer_addr; 221 __le64 reserved; 222 } read; 223 struct { 224 struct { 225 __le32 mrq; /* Multiple Rx Queues */ 226 union { 227 __le32 rss; /* RSS Hash */ 228 struct { 229 __le16 ip_id; /* IP id */ 230 __le16 csum; /* Packet Checksum */ 231 } csum_ip; 232 } hi_dword; 233 } lower; 234 struct { 235 __le32 status_error; /* ext status/error */ 236 __le16 length; 237 __le16 vlan; /* VLAN tag */ 238 } upper; 239 } wb; /* writeback */ 240 }; 241 242 #define MAX_PS_BUFFERS 4 243 244 /* Number of packet split data buffers (not including the header buffer) */ 245 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 246 247 /* Receive Descriptor - Packet Split */ 248 union e1000_rx_desc_packet_split { 249 struct { 250 /* one buffer for protocol header(s), three data buffers */ 251 __le64 buffer_addr[MAX_PS_BUFFERS]; 252 } read; 253 struct { 254 struct { 255 __le32 mrq; /* Multiple Rx Queues */ 256 union { 257 __le32 rss; /* RSS Hash */ 258 struct { 259 __le16 ip_id; /* IP id */ 260 __le16 csum; /* Packet Checksum */ 261 } csum_ip; 262 } hi_dword; 263 } lower; 264 struct { 265 __le32 status_error; /* ext status/error */ 266 __le16 length0; /* length of buffer 0 */ 267 __le16 vlan; /* VLAN tag */ 268 } middle; 269 struct { 270 __le16 header_status; 271 /* length of buffers 1-3 */ 272 __le16 length[PS_PAGE_BUFFERS]; 273 } upper; 274 __le64 reserved; 275 } wb; /* writeback */ 276 }; 277 278 /* Transmit Descriptor */ 279 struct e1000_tx_desc { 280 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 281 union { 282 __le32 data; 283 struct { 284 __le16 length; /* Data buffer length */ 285 u8 cso; /* Checksum offset */ 286 u8 cmd; /* Descriptor control */ 287 } flags; 288 } lower; 289 union { 290 __le32 data; 291 struct { 292 u8 status; /* Descriptor status */ 293 u8 css; /* Checksum start */ 294 __le16 special; 295 } fields; 296 } upper; 297 }; 298 299 /* Offload Context Descriptor */ 300 struct e1000_context_desc { 301 union { 302 __le32 ip_config; 303 struct { 304 u8 ipcss; /* IP checksum start */ 305 u8 ipcso; /* IP checksum offset */ 306 __le16 ipcse; /* IP checksum end */ 307 } ip_fields; 308 } lower_setup; 309 union { 310 __le32 tcp_config; 311 struct { 312 u8 tucss; /* TCP checksum start */ 313 u8 tucso; /* TCP checksum offset */ 314 __le16 tucse; /* TCP checksum end */ 315 } tcp_fields; 316 } upper_setup; 317 __le32 cmd_and_length; 318 union { 319 __le32 data; 320 struct { 321 u8 status; /* Descriptor status */ 322 u8 hdr_len; /* Header length */ 323 __le16 mss; /* Maximum segment size */ 324 } fields; 325 } tcp_seg_setup; 326 }; 327 328 /* Offload data descriptor */ 329 struct e1000_data_desc { 330 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 331 union { 332 __le32 data; 333 struct { 334 __le16 length; /* Data buffer length */ 335 u8 typ_len_ext; 336 u8 cmd; 337 } flags; 338 } lower; 339 union { 340 __le32 data; 341 struct { 342 u8 status; /* Descriptor status */ 343 u8 popts; /* Packet Options */ 344 __le16 special; 345 } fields; 346 } upper; 347 }; 348 349 /* Statistics counters collected by the MAC */ 350 struct e1000_hw_stats { 351 u64 crcerrs; 352 u64 algnerrc; 353 u64 symerrs; 354 u64 rxerrc; 355 u64 mpc; 356 u64 scc; 357 u64 ecol; 358 u64 mcc; 359 u64 latecol; 360 u64 colc; 361 u64 dc; 362 u64 tncrs; 363 u64 sec; 364 u64 cexterr; 365 u64 rlec; 366 u64 xonrxc; 367 u64 xontxc; 368 u64 xoffrxc; 369 u64 xofftxc; 370 u64 fcruc; 371 u64 prc64; 372 u64 prc127; 373 u64 prc255; 374 u64 prc511; 375 u64 prc1023; 376 u64 prc1522; 377 u64 gprc; 378 u64 bprc; 379 u64 mprc; 380 u64 gptc; 381 u64 gorc; 382 u64 gotc; 383 u64 rnbc; 384 u64 ruc; 385 u64 rfc; 386 u64 roc; 387 u64 rjc; 388 u64 mgprc; 389 u64 mgpdc; 390 u64 mgptc; 391 u64 tor; 392 u64 tot; 393 u64 tpr; 394 u64 tpt; 395 u64 ptc64; 396 u64 ptc127; 397 u64 ptc255; 398 u64 ptc511; 399 u64 ptc1023; 400 u64 ptc1522; 401 u64 mptc; 402 u64 bptc; 403 u64 tsctc; 404 u64 tsctfc; 405 u64 iac; 406 u64 icrxptc; 407 u64 icrxatc; 408 u64 ictxptc; 409 u64 ictxatc; 410 u64 ictxqec; 411 u64 ictxqmtc; 412 u64 icrxdmtc; 413 u64 icrxoc; 414 }; 415 416 struct e1000_phy_stats { 417 u32 idle_errors; 418 u32 receive_errors; 419 }; 420 421 struct e1000_host_mng_dhcp_cookie { 422 u32 signature; 423 u8 status; 424 u8 reserved0; 425 u16 vlan_id; 426 u32 reserved1; 427 u16 reserved2; 428 u8 reserved3; 429 u8 checksum; 430 }; 431 432 /* Host Interface "Rev 1" */ 433 struct e1000_host_command_header { 434 u8 command_id; 435 u8 command_length; 436 u8 command_options; 437 u8 checksum; 438 }; 439 440 #define E1000_HI_MAX_DATA_LENGTH 252 441 struct e1000_host_command_info { 442 struct e1000_host_command_header command_header; 443 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 444 }; 445 446 /* Host Interface "Rev 2" */ 447 struct e1000_host_mng_command_header { 448 u8 command_id; 449 u8 checksum; 450 u16 reserved1; 451 u16 reserved2; 452 u16 command_length; 453 }; 454 455 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 456 struct e1000_host_mng_command_info { 457 struct e1000_host_mng_command_header command_header; 458 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 459 }; 460 461 #include "mac.h" 462 #include "phy.h" 463 #include "nvm.h" 464 #include "manage.h" 465 466 /* Function pointers for the MAC. */ 467 struct e1000_mac_operations { 468 s32 (*id_led_init)(struct e1000_hw *); 469 s32 (*blink_led)(struct e1000_hw *); 470 bool (*check_mng_mode)(struct e1000_hw *); 471 s32 (*check_for_link)(struct e1000_hw *); 472 s32 (*cleanup_led)(struct e1000_hw *); 473 void (*clear_hw_cntrs)(struct e1000_hw *); 474 void (*clear_vfta)(struct e1000_hw *); 475 s32 (*get_bus_info)(struct e1000_hw *); 476 void (*set_lan_id)(struct e1000_hw *); 477 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 478 s32 (*led_on)(struct e1000_hw *); 479 s32 (*led_off)(struct e1000_hw *); 480 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 481 s32 (*reset_hw)(struct e1000_hw *); 482 s32 (*init_hw)(struct e1000_hw *); 483 s32 (*setup_link)(struct e1000_hw *); 484 s32 (*setup_physical_interface)(struct e1000_hw *); 485 s32 (*setup_led)(struct e1000_hw *); 486 void (*write_vfta)(struct e1000_hw *, u32, u32); 487 void (*config_collision_dist)(struct e1000_hw *); 488 int (*rar_set)(struct e1000_hw *, u8 *, u32); 489 s32 (*read_mac_addr)(struct e1000_hw *); 490 u32 (*rar_get_count)(struct e1000_hw *); 491 }; 492 493 /* When to use various PHY register access functions: 494 * 495 * Func Caller 496 * Function Does Does When to use 497 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 498 * X_reg L,P,A n/a for simple PHY reg accesses 499 * X_reg_locked P,A L for multiple accesses of different regs 500 * on different pages 501 * X_reg_page A L,P for multiple accesses of different regs 502 * on the same page 503 * 504 * Where X=[read|write], L=locking, P=sets page, A=register access 505 * 506 */ 507 struct e1000_phy_operations { 508 s32 (*acquire)(struct e1000_hw *); 509 s32 (*cfg_on_link_up)(struct e1000_hw *); 510 s32 (*check_polarity)(struct e1000_hw *); 511 s32 (*check_reset_block)(struct e1000_hw *); 512 s32 (*commit)(struct e1000_hw *); 513 s32 (*force_speed_duplex)(struct e1000_hw *); 514 s32 (*get_cfg_done)(struct e1000_hw *hw); 515 s32 (*get_cable_length)(struct e1000_hw *); 516 s32 (*get_info)(struct e1000_hw *); 517 s32 (*set_page)(struct e1000_hw *, u16); 518 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 519 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 520 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 521 void (*release)(struct e1000_hw *); 522 s32 (*reset)(struct e1000_hw *); 523 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 524 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 525 s32 (*write_reg)(struct e1000_hw *, u32, u16); 526 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 527 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 528 void (*power_up)(struct e1000_hw *); 529 void (*power_down)(struct e1000_hw *); 530 }; 531 532 /* Function pointers for the NVM. */ 533 struct e1000_nvm_operations { 534 s32 (*acquire)(struct e1000_hw *); 535 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 536 void (*release)(struct e1000_hw *); 537 void (*reload)(struct e1000_hw *); 538 s32 (*update)(struct e1000_hw *); 539 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 540 s32 (*validate)(struct e1000_hw *); 541 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 542 }; 543 544 struct e1000_mac_info { 545 struct e1000_mac_operations ops; 546 u8 addr[ETH_ALEN]; 547 u8 perm_addr[ETH_ALEN]; 548 549 enum e1000_mac_type type; 550 551 u32 collision_delta; 552 u32 ledctl_default; 553 u32 ledctl_mode1; 554 u32 ledctl_mode2; 555 u32 mc_filter_type; 556 u32 tx_packet_delta; 557 u32 txcw; 558 559 u16 current_ifs_val; 560 u16 ifs_max_val; 561 u16 ifs_min_val; 562 u16 ifs_ratio; 563 u16 ifs_step_size; 564 u16 mta_reg_count; 565 566 /* Maximum size of the MTA register table in all supported adapters */ 567 #define MAX_MTA_REG 128 568 u32 mta_shadow[MAX_MTA_REG]; 569 u16 rar_entry_count; 570 571 u8 forced_speed_duplex; 572 573 bool adaptive_ifs; 574 bool has_fwsm; 575 bool arc_subsystem_valid; 576 bool autoneg; 577 bool autoneg_failed; 578 bool get_link_status; 579 bool in_ifs_mode; 580 bool serdes_has_link; 581 bool tx_pkt_filtering; 582 enum e1000_serdes_link_state serdes_link_state; 583 }; 584 585 struct e1000_phy_info { 586 struct e1000_phy_operations ops; 587 588 enum e1000_phy_type type; 589 590 enum e1000_1000t_rx_status local_rx; 591 enum e1000_1000t_rx_status remote_rx; 592 enum e1000_ms_type ms_type; 593 enum e1000_ms_type original_ms_type; 594 enum e1000_rev_polarity cable_polarity; 595 enum e1000_smart_speed smart_speed; 596 597 u32 addr; 598 u32 id; 599 u32 reset_delay_us; /* in usec */ 600 u32 revision; 601 602 enum e1000_media_type media_type; 603 604 u16 autoneg_advertised; 605 u16 autoneg_mask; 606 u16 cable_length; 607 u16 max_cable_length; 608 u16 min_cable_length; 609 610 u8 mdix; 611 612 bool disable_polarity_correction; 613 bool is_mdix; 614 bool polarity_correction; 615 bool speed_downgraded; 616 bool autoneg_wait_to_complete; 617 }; 618 619 struct e1000_nvm_info { 620 struct e1000_nvm_operations ops; 621 622 enum e1000_nvm_type type; 623 enum e1000_nvm_override override; 624 625 u32 flash_bank_size; 626 u32 flash_base_addr; 627 628 u16 word_size; 629 u16 delay_usec; 630 u16 address_bits; 631 u16 opcode_bits; 632 u16 page_size; 633 }; 634 635 struct e1000_bus_info { 636 enum e1000_bus_width width; 637 638 u16 func; 639 }; 640 641 struct e1000_fc_info { 642 u32 high_water; /* Flow control high-water mark */ 643 u32 low_water; /* Flow control low-water mark */ 644 u16 pause_time; /* Flow control pause timer */ 645 u16 refresh_time; /* Flow control refresh timer */ 646 bool send_xon; /* Flow control send XON */ 647 bool strict_ieee; /* Strict IEEE mode */ 648 enum e1000_fc_mode current_mode; /* FC mode in effect */ 649 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 650 }; 651 652 struct e1000_dev_spec_82571 { 653 bool laa_is_present; 654 u32 smb_counter; 655 }; 656 657 struct e1000_dev_spec_80003es2lan { 658 bool mdic_wa_enable; 659 }; 660 661 struct e1000_shadow_ram { 662 u16 value; 663 bool modified; 664 }; 665 666 #define E1000_ICH8_SHADOW_RAM_WORDS 2048 667 668 /* I218 PHY Ultra Low Power (ULP) states */ 669 enum e1000_ulp_state { 670 e1000_ulp_state_unknown, 671 e1000_ulp_state_off, 672 e1000_ulp_state_on, 673 }; 674 675 struct e1000_dev_spec_ich8lan { 676 bool kmrn_lock_loss_workaround_enabled; 677 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 678 bool nvm_k1_enabled; 679 bool eee_disable; 680 u16 eee_lp_ability; 681 enum e1000_ulp_state ulp_state; 682 }; 683 684 struct e1000_hw { 685 struct e1000_adapter *adapter; 686 687 void __iomem *hw_addr; 688 void __iomem *flash_address; 689 690 struct e1000_mac_info mac; 691 struct e1000_fc_info fc; 692 struct e1000_phy_info phy; 693 struct e1000_nvm_info nvm; 694 struct e1000_bus_info bus; 695 struct e1000_host_mng_dhcp_cookie mng_cookie; 696 697 union { 698 struct e1000_dev_spec_82571 e82571; 699 struct e1000_dev_spec_80003es2lan e80003es2lan; 700 struct e1000_dev_spec_ich8lan ich8lan; 701 } dev_spec; 702 }; 703 704 #include "82571.h" 705 #include "80003es2lan.h" 706 #include "ich8lan.h" 707 708 #endif 709