1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #ifndef _E1000_HW_H_ 23 #define _E1000_HW_H_ 24 25 #include "regs.h" 26 #include "defines.h" 27 28 struct e1000_hw; 29 30 #define E1000_DEV_ID_82571EB_COPPER 0x105E 31 #define E1000_DEV_ID_82571EB_FIBER 0x105F 32 #define E1000_DEV_ID_82571EB_SERDES 0x1060 33 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 34 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 35 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 36 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 37 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 38 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 39 #define E1000_DEV_ID_82572EI_COPPER 0x107D 40 #define E1000_DEV_ID_82572EI_FIBER 0x107E 41 #define E1000_DEV_ID_82572EI_SERDES 0x107F 42 #define E1000_DEV_ID_82572EI 0x10B9 43 #define E1000_DEV_ID_82573E 0x108B 44 #define E1000_DEV_ID_82573E_IAMT 0x108C 45 #define E1000_DEV_ID_82573L 0x109A 46 #define E1000_DEV_ID_82574L 0x10D3 47 #define E1000_DEV_ID_82574LA 0x10F6 48 #define E1000_DEV_ID_82583V 0x150C 49 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 50 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 51 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 52 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 53 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 54 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 55 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 56 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 57 #define E1000_DEV_ID_ICH8_IFE 0x104C 58 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 59 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 60 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 61 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 62 #define E1000_DEV_ID_ICH9_BM 0x10E5 63 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 64 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 65 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 66 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 67 #define E1000_DEV_ID_ICH9_IFE 0x10C0 68 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 69 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 70 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 71 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 72 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 73 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 74 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 75 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 76 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 77 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 78 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 79 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 80 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 81 #define E1000_DEV_ID_PCH2_LV_V 0x1503 82 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 83 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 84 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 85 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 86 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 87 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 88 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 89 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 90 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */ 91 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */ 92 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */ 93 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */ 94 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */ 95 96 #define E1000_REVISION_4 4 97 98 #define E1000_FUNC_1 1 99 100 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 101 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 102 103 enum e1000_mac_type { 104 e1000_82571, 105 e1000_82572, 106 e1000_82573, 107 e1000_82574, 108 e1000_82583, 109 e1000_80003es2lan, 110 e1000_ich8lan, 111 e1000_ich9lan, 112 e1000_ich10lan, 113 e1000_pchlan, 114 e1000_pch2lan, 115 e1000_pch_lpt, 116 e1000_pch_spt, 117 }; 118 119 enum e1000_media_type { 120 e1000_media_type_unknown = 0, 121 e1000_media_type_copper = 1, 122 e1000_media_type_fiber = 2, 123 e1000_media_type_internal_serdes = 3, 124 e1000_num_media_types 125 }; 126 127 enum e1000_nvm_type { 128 e1000_nvm_unknown = 0, 129 e1000_nvm_none, 130 e1000_nvm_eeprom_spi, 131 e1000_nvm_flash_hw, 132 e1000_nvm_flash_sw 133 }; 134 135 enum e1000_nvm_override { 136 e1000_nvm_override_none = 0, 137 e1000_nvm_override_spi_small, 138 e1000_nvm_override_spi_large 139 }; 140 141 enum e1000_phy_type { 142 e1000_phy_unknown = 0, 143 e1000_phy_none, 144 e1000_phy_m88, 145 e1000_phy_igp, 146 e1000_phy_igp_2, 147 e1000_phy_gg82563, 148 e1000_phy_igp_3, 149 e1000_phy_ife, 150 e1000_phy_bm, 151 e1000_phy_82578, 152 e1000_phy_82577, 153 e1000_phy_82579, 154 e1000_phy_i217, 155 }; 156 157 enum e1000_bus_width { 158 e1000_bus_width_unknown = 0, 159 e1000_bus_width_pcie_x1, 160 e1000_bus_width_pcie_x2, 161 e1000_bus_width_pcie_x4 = 4, 162 e1000_bus_width_pcie_x8 = 8, 163 e1000_bus_width_32, 164 e1000_bus_width_64, 165 e1000_bus_width_reserved 166 }; 167 168 enum e1000_1000t_rx_status { 169 e1000_1000t_rx_status_not_ok = 0, 170 e1000_1000t_rx_status_ok, 171 e1000_1000t_rx_status_undefined = 0xFF 172 }; 173 174 enum e1000_rev_polarity { 175 e1000_rev_polarity_normal = 0, 176 e1000_rev_polarity_reversed, 177 e1000_rev_polarity_undefined = 0xFF 178 }; 179 180 enum e1000_fc_mode { 181 e1000_fc_none = 0, 182 e1000_fc_rx_pause, 183 e1000_fc_tx_pause, 184 e1000_fc_full, 185 e1000_fc_default = 0xFF 186 }; 187 188 enum e1000_ms_type { 189 e1000_ms_hw_default = 0, 190 e1000_ms_force_master, 191 e1000_ms_force_slave, 192 e1000_ms_auto 193 }; 194 195 enum e1000_smart_speed { 196 e1000_smart_speed_default = 0, 197 e1000_smart_speed_on, 198 e1000_smart_speed_off 199 }; 200 201 enum e1000_serdes_link_state { 202 e1000_serdes_link_down = 0, 203 e1000_serdes_link_autoneg_progress, 204 e1000_serdes_link_autoneg_complete, 205 e1000_serdes_link_forced_up 206 }; 207 208 /* Receive Descriptor - Extended */ 209 union e1000_rx_desc_extended { 210 struct { 211 __le64 buffer_addr; 212 __le64 reserved; 213 } read; 214 struct { 215 struct { 216 __le32 mrq; /* Multiple Rx Queues */ 217 union { 218 __le32 rss; /* RSS Hash */ 219 struct { 220 __le16 ip_id; /* IP id */ 221 __le16 csum; /* Packet Checksum */ 222 } csum_ip; 223 } hi_dword; 224 } lower; 225 struct { 226 __le32 status_error; /* ext status/error */ 227 __le16 length; 228 __le16 vlan; /* VLAN tag */ 229 } upper; 230 } wb; /* writeback */ 231 }; 232 233 #define MAX_PS_BUFFERS 4 234 235 /* Number of packet split data buffers (not including the header buffer) */ 236 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 237 238 /* Receive Descriptor - Packet Split */ 239 union e1000_rx_desc_packet_split { 240 struct { 241 /* one buffer for protocol header(s), three data buffers */ 242 __le64 buffer_addr[MAX_PS_BUFFERS]; 243 } read; 244 struct { 245 struct { 246 __le32 mrq; /* Multiple Rx Queues */ 247 union { 248 __le32 rss; /* RSS Hash */ 249 struct { 250 __le16 ip_id; /* IP id */ 251 __le16 csum; /* Packet Checksum */ 252 } csum_ip; 253 } hi_dword; 254 } lower; 255 struct { 256 __le32 status_error; /* ext status/error */ 257 __le16 length0; /* length of buffer 0 */ 258 __le16 vlan; /* VLAN tag */ 259 } middle; 260 struct { 261 __le16 header_status; 262 /* length of buffers 1-3 */ 263 __le16 length[PS_PAGE_BUFFERS]; 264 } upper; 265 __le64 reserved; 266 } wb; /* writeback */ 267 }; 268 269 /* Transmit Descriptor */ 270 struct e1000_tx_desc { 271 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 272 union { 273 __le32 data; 274 struct { 275 __le16 length; /* Data buffer length */ 276 u8 cso; /* Checksum offset */ 277 u8 cmd; /* Descriptor control */ 278 } flags; 279 } lower; 280 union { 281 __le32 data; 282 struct { 283 u8 status; /* Descriptor status */ 284 u8 css; /* Checksum start */ 285 __le16 special; 286 } fields; 287 } upper; 288 }; 289 290 /* Offload Context Descriptor */ 291 struct e1000_context_desc { 292 union { 293 __le32 ip_config; 294 struct { 295 u8 ipcss; /* IP checksum start */ 296 u8 ipcso; /* IP checksum offset */ 297 __le16 ipcse; /* IP checksum end */ 298 } ip_fields; 299 } lower_setup; 300 union { 301 __le32 tcp_config; 302 struct { 303 u8 tucss; /* TCP checksum start */ 304 u8 tucso; /* TCP checksum offset */ 305 __le16 tucse; /* TCP checksum end */ 306 } tcp_fields; 307 } upper_setup; 308 __le32 cmd_and_length; 309 union { 310 __le32 data; 311 struct { 312 u8 status; /* Descriptor status */ 313 u8 hdr_len; /* Header length */ 314 __le16 mss; /* Maximum segment size */ 315 } fields; 316 } tcp_seg_setup; 317 }; 318 319 /* Offload data descriptor */ 320 struct e1000_data_desc { 321 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 322 union { 323 __le32 data; 324 struct { 325 __le16 length; /* Data buffer length */ 326 u8 typ_len_ext; 327 u8 cmd; 328 } flags; 329 } lower; 330 union { 331 __le32 data; 332 struct { 333 u8 status; /* Descriptor status */ 334 u8 popts; /* Packet Options */ 335 __le16 special; 336 } fields; 337 } upper; 338 }; 339 340 /* Statistics counters collected by the MAC */ 341 struct e1000_hw_stats { 342 u64 crcerrs; 343 u64 algnerrc; 344 u64 symerrs; 345 u64 rxerrc; 346 u64 mpc; 347 u64 scc; 348 u64 ecol; 349 u64 mcc; 350 u64 latecol; 351 u64 colc; 352 u64 dc; 353 u64 tncrs; 354 u64 sec; 355 u64 cexterr; 356 u64 rlec; 357 u64 xonrxc; 358 u64 xontxc; 359 u64 xoffrxc; 360 u64 xofftxc; 361 u64 fcruc; 362 u64 prc64; 363 u64 prc127; 364 u64 prc255; 365 u64 prc511; 366 u64 prc1023; 367 u64 prc1522; 368 u64 gprc; 369 u64 bprc; 370 u64 mprc; 371 u64 gptc; 372 u64 gorc; 373 u64 gotc; 374 u64 rnbc; 375 u64 ruc; 376 u64 rfc; 377 u64 roc; 378 u64 rjc; 379 u64 mgprc; 380 u64 mgpdc; 381 u64 mgptc; 382 u64 tor; 383 u64 tot; 384 u64 tpr; 385 u64 tpt; 386 u64 ptc64; 387 u64 ptc127; 388 u64 ptc255; 389 u64 ptc511; 390 u64 ptc1023; 391 u64 ptc1522; 392 u64 mptc; 393 u64 bptc; 394 u64 tsctc; 395 u64 tsctfc; 396 u64 iac; 397 u64 icrxptc; 398 u64 icrxatc; 399 u64 ictxptc; 400 u64 ictxatc; 401 u64 ictxqec; 402 u64 ictxqmtc; 403 u64 icrxdmtc; 404 u64 icrxoc; 405 }; 406 407 struct e1000_phy_stats { 408 u32 idle_errors; 409 u32 receive_errors; 410 }; 411 412 struct e1000_host_mng_dhcp_cookie { 413 u32 signature; 414 u8 status; 415 u8 reserved0; 416 u16 vlan_id; 417 u32 reserved1; 418 u16 reserved2; 419 u8 reserved3; 420 u8 checksum; 421 }; 422 423 /* Host Interface "Rev 1" */ 424 struct e1000_host_command_header { 425 u8 command_id; 426 u8 command_length; 427 u8 command_options; 428 u8 checksum; 429 }; 430 431 #define E1000_HI_MAX_DATA_LENGTH 252 432 struct e1000_host_command_info { 433 struct e1000_host_command_header command_header; 434 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 435 }; 436 437 /* Host Interface "Rev 2" */ 438 struct e1000_host_mng_command_header { 439 u8 command_id; 440 u8 checksum; 441 u16 reserved1; 442 u16 reserved2; 443 u16 command_length; 444 }; 445 446 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 447 struct e1000_host_mng_command_info { 448 struct e1000_host_mng_command_header command_header; 449 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 450 }; 451 452 #include "mac.h" 453 #include "phy.h" 454 #include "nvm.h" 455 #include "manage.h" 456 457 /* Function pointers for the MAC. */ 458 struct e1000_mac_operations { 459 s32 (*id_led_init)(struct e1000_hw *); 460 s32 (*blink_led)(struct e1000_hw *); 461 bool (*check_mng_mode)(struct e1000_hw *); 462 s32 (*check_for_link)(struct e1000_hw *); 463 s32 (*cleanup_led)(struct e1000_hw *); 464 void (*clear_hw_cntrs)(struct e1000_hw *); 465 void (*clear_vfta)(struct e1000_hw *); 466 s32 (*get_bus_info)(struct e1000_hw *); 467 void (*set_lan_id)(struct e1000_hw *); 468 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 469 s32 (*led_on)(struct e1000_hw *); 470 s32 (*led_off)(struct e1000_hw *); 471 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 472 s32 (*reset_hw)(struct e1000_hw *); 473 s32 (*init_hw)(struct e1000_hw *); 474 s32 (*setup_link)(struct e1000_hw *); 475 s32 (*setup_physical_interface)(struct e1000_hw *); 476 s32 (*setup_led)(struct e1000_hw *); 477 void (*write_vfta)(struct e1000_hw *, u32, u32); 478 void (*config_collision_dist)(struct e1000_hw *); 479 int (*rar_set)(struct e1000_hw *, u8 *, u32); 480 s32 (*read_mac_addr)(struct e1000_hw *); 481 u32 (*rar_get_count)(struct e1000_hw *); 482 }; 483 484 /* When to use various PHY register access functions: 485 * 486 * Func Caller 487 * Function Does Does When to use 488 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 489 * X_reg L,P,A n/a for simple PHY reg accesses 490 * X_reg_locked P,A L for multiple accesses of different regs 491 * on different pages 492 * X_reg_page A L,P for multiple accesses of different regs 493 * on the same page 494 * 495 * Where X=[read|write], L=locking, P=sets page, A=register access 496 * 497 */ 498 struct e1000_phy_operations { 499 s32 (*acquire)(struct e1000_hw *); 500 s32 (*cfg_on_link_up)(struct e1000_hw *); 501 s32 (*check_polarity)(struct e1000_hw *); 502 s32 (*check_reset_block)(struct e1000_hw *); 503 s32 (*commit)(struct e1000_hw *); 504 s32 (*force_speed_duplex)(struct e1000_hw *); 505 s32 (*get_cfg_done)(struct e1000_hw *hw); 506 s32 (*get_cable_length)(struct e1000_hw *); 507 s32 (*get_info)(struct e1000_hw *); 508 s32 (*set_page)(struct e1000_hw *, u16); 509 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 510 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 511 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 512 void (*release)(struct e1000_hw *); 513 s32 (*reset)(struct e1000_hw *); 514 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 515 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 516 s32 (*write_reg)(struct e1000_hw *, u32, u16); 517 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 518 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 519 void (*power_up)(struct e1000_hw *); 520 void (*power_down)(struct e1000_hw *); 521 }; 522 523 /* Function pointers for the NVM. */ 524 struct e1000_nvm_operations { 525 s32 (*acquire)(struct e1000_hw *); 526 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 527 void (*release)(struct e1000_hw *); 528 void (*reload)(struct e1000_hw *); 529 s32 (*update)(struct e1000_hw *); 530 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 531 s32 (*validate)(struct e1000_hw *); 532 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 533 }; 534 535 struct e1000_mac_info { 536 struct e1000_mac_operations ops; 537 u8 addr[ETH_ALEN]; 538 u8 perm_addr[ETH_ALEN]; 539 540 enum e1000_mac_type type; 541 542 u32 collision_delta; 543 u32 ledctl_default; 544 u32 ledctl_mode1; 545 u32 ledctl_mode2; 546 u32 mc_filter_type; 547 u32 tx_packet_delta; 548 u32 txcw; 549 550 u16 current_ifs_val; 551 u16 ifs_max_val; 552 u16 ifs_min_val; 553 u16 ifs_ratio; 554 u16 ifs_step_size; 555 u16 mta_reg_count; 556 557 /* Maximum size of the MTA register table in all supported adapters */ 558 #define MAX_MTA_REG 128 559 u32 mta_shadow[MAX_MTA_REG]; 560 u16 rar_entry_count; 561 562 u8 forced_speed_duplex; 563 564 bool adaptive_ifs; 565 bool has_fwsm; 566 bool arc_subsystem_valid; 567 bool autoneg; 568 bool autoneg_failed; 569 bool get_link_status; 570 bool in_ifs_mode; 571 bool serdes_has_link; 572 bool tx_pkt_filtering; 573 enum e1000_serdes_link_state serdes_link_state; 574 }; 575 576 struct e1000_phy_info { 577 struct e1000_phy_operations ops; 578 579 enum e1000_phy_type type; 580 581 enum e1000_1000t_rx_status local_rx; 582 enum e1000_1000t_rx_status remote_rx; 583 enum e1000_ms_type ms_type; 584 enum e1000_ms_type original_ms_type; 585 enum e1000_rev_polarity cable_polarity; 586 enum e1000_smart_speed smart_speed; 587 588 u32 addr; 589 u32 id; 590 u32 reset_delay_us; /* in usec */ 591 u32 revision; 592 593 enum e1000_media_type media_type; 594 595 u16 autoneg_advertised; 596 u16 autoneg_mask; 597 u16 cable_length; 598 u16 max_cable_length; 599 u16 min_cable_length; 600 601 u8 mdix; 602 603 bool disable_polarity_correction; 604 bool is_mdix; 605 bool polarity_correction; 606 bool speed_downgraded; 607 bool autoneg_wait_to_complete; 608 }; 609 610 struct e1000_nvm_info { 611 struct e1000_nvm_operations ops; 612 613 enum e1000_nvm_type type; 614 enum e1000_nvm_override override; 615 616 u32 flash_bank_size; 617 u32 flash_base_addr; 618 619 u16 word_size; 620 u16 delay_usec; 621 u16 address_bits; 622 u16 opcode_bits; 623 u16 page_size; 624 }; 625 626 struct e1000_bus_info { 627 enum e1000_bus_width width; 628 629 u16 func; 630 }; 631 632 struct e1000_fc_info { 633 u32 high_water; /* Flow control high-water mark */ 634 u32 low_water; /* Flow control low-water mark */ 635 u16 pause_time; /* Flow control pause timer */ 636 u16 refresh_time; /* Flow control refresh timer */ 637 bool send_xon; /* Flow control send XON */ 638 bool strict_ieee; /* Strict IEEE mode */ 639 enum e1000_fc_mode current_mode; /* FC mode in effect */ 640 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 641 }; 642 643 struct e1000_dev_spec_82571 { 644 bool laa_is_present; 645 u32 smb_counter; 646 }; 647 648 struct e1000_dev_spec_80003es2lan { 649 bool mdic_wa_enable; 650 }; 651 652 struct e1000_shadow_ram { 653 u16 value; 654 bool modified; 655 }; 656 657 #define E1000_ICH8_SHADOW_RAM_WORDS 2048 658 659 /* I218 PHY Ultra Low Power (ULP) states */ 660 enum e1000_ulp_state { 661 e1000_ulp_state_unknown, 662 e1000_ulp_state_off, 663 e1000_ulp_state_on, 664 }; 665 666 struct e1000_dev_spec_ich8lan { 667 bool kmrn_lock_loss_workaround_enabled; 668 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 669 bool nvm_k1_enabled; 670 bool eee_disable; 671 u16 eee_lp_ability; 672 enum e1000_ulp_state ulp_state; 673 }; 674 675 struct e1000_hw { 676 struct e1000_adapter *adapter; 677 678 void __iomem *hw_addr; 679 void __iomem *flash_address; 680 681 struct e1000_mac_info mac; 682 struct e1000_fc_info fc; 683 struct e1000_phy_info phy; 684 struct e1000_nvm_info nvm; 685 struct e1000_bus_info bus; 686 struct e1000_host_mng_dhcp_cookie mng_cookie; 687 688 union { 689 struct e1000_dev_spec_82571 e82571; 690 struct e1000_dev_spec_80003es2lan e80003es2lan; 691 struct e1000_dev_spec_ich8lan ich8lan; 692 } dev_spec; 693 }; 694 695 #include "82571.h" 696 #include "80003es2lan.h" 697 #include "ich8lan.h" 698 699 #endif 700