1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _E1000_HW_H_ 5 #define _E1000_HW_H_ 6 7 #include "regs.h" 8 #include "defines.h" 9 10 struct e1000_hw; 11 12 #define E1000_DEV_ID_82571EB_COPPER 0x105E 13 #define E1000_DEV_ID_82571EB_FIBER 0x105F 14 #define E1000_DEV_ID_82571EB_SERDES 0x1060 15 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 16 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 17 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 19 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 20 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 21 #define E1000_DEV_ID_82572EI_COPPER 0x107D 22 #define E1000_DEV_ID_82572EI_FIBER 0x107E 23 #define E1000_DEV_ID_82572EI_SERDES 0x107F 24 #define E1000_DEV_ID_82572EI 0x10B9 25 #define E1000_DEV_ID_82573E 0x108B 26 #define E1000_DEV_ID_82573E_IAMT 0x108C 27 #define E1000_DEV_ID_82573L 0x109A 28 #define E1000_DEV_ID_82574L 0x10D3 29 #define E1000_DEV_ID_82574LA 0x10F6 30 #define E1000_DEV_ID_82583V 0x150C 31 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 32 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 33 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 34 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 35 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 36 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 37 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 38 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 39 #define E1000_DEV_ID_ICH8_IFE 0x104C 40 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 41 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 42 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 43 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 44 #define E1000_DEV_ID_ICH9_BM 0x10E5 45 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 46 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 47 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 48 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 49 #define E1000_DEV_ID_ICH9_IFE 0x10C0 50 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 51 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 52 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 53 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 54 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 55 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 56 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 57 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 58 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 59 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 60 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 61 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 62 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 63 #define E1000_DEV_ID_PCH2_LV_V 0x1503 64 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 65 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 66 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 67 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 68 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 69 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 70 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 71 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 72 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */ 73 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */ 74 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */ 75 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */ 76 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */ 77 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 78 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 79 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 80 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 81 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 82 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 83 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 84 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 85 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 86 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 87 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 88 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 89 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 90 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 91 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 92 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 93 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 94 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 95 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 96 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 97 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 98 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 99 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 100 101 #define E1000_REVISION_4 4 102 103 #define E1000_FUNC_1 1 104 105 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 106 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 107 108 enum e1000_mac_type { 109 e1000_82571, 110 e1000_82572, 111 e1000_82573, 112 e1000_82574, 113 e1000_82583, 114 e1000_80003es2lan, 115 e1000_ich8lan, 116 e1000_ich9lan, 117 e1000_ich10lan, 118 e1000_pchlan, 119 e1000_pch2lan, 120 e1000_pch_lpt, 121 e1000_pch_spt, 122 e1000_pch_cnp, 123 e1000_pch_tgp, 124 }; 125 126 enum e1000_media_type { 127 e1000_media_type_unknown = 0, 128 e1000_media_type_copper = 1, 129 e1000_media_type_fiber = 2, 130 e1000_media_type_internal_serdes = 3, 131 e1000_num_media_types 132 }; 133 134 enum e1000_nvm_type { 135 e1000_nvm_unknown = 0, 136 e1000_nvm_none, 137 e1000_nvm_eeprom_spi, 138 e1000_nvm_flash_hw, 139 e1000_nvm_flash_sw 140 }; 141 142 enum e1000_nvm_override { 143 e1000_nvm_override_none = 0, 144 e1000_nvm_override_spi_small, 145 e1000_nvm_override_spi_large 146 }; 147 148 enum e1000_phy_type { 149 e1000_phy_unknown = 0, 150 e1000_phy_none, 151 e1000_phy_m88, 152 e1000_phy_igp, 153 e1000_phy_igp_2, 154 e1000_phy_gg82563, 155 e1000_phy_igp_3, 156 e1000_phy_ife, 157 e1000_phy_bm, 158 e1000_phy_82578, 159 e1000_phy_82577, 160 e1000_phy_82579, 161 e1000_phy_i217, 162 }; 163 164 enum e1000_bus_width { 165 e1000_bus_width_unknown = 0, 166 e1000_bus_width_pcie_x1, 167 e1000_bus_width_pcie_x2, 168 e1000_bus_width_pcie_x4 = 4, 169 e1000_bus_width_pcie_x8 = 8, 170 e1000_bus_width_32, 171 e1000_bus_width_64, 172 e1000_bus_width_reserved 173 }; 174 175 enum e1000_1000t_rx_status { 176 e1000_1000t_rx_status_not_ok = 0, 177 e1000_1000t_rx_status_ok, 178 e1000_1000t_rx_status_undefined = 0xFF 179 }; 180 181 enum e1000_rev_polarity { 182 e1000_rev_polarity_normal = 0, 183 e1000_rev_polarity_reversed, 184 e1000_rev_polarity_undefined = 0xFF 185 }; 186 187 enum e1000_fc_mode { 188 e1000_fc_none = 0, 189 e1000_fc_rx_pause, 190 e1000_fc_tx_pause, 191 e1000_fc_full, 192 e1000_fc_default = 0xFF 193 }; 194 195 enum e1000_ms_type { 196 e1000_ms_hw_default = 0, 197 e1000_ms_force_master, 198 e1000_ms_force_slave, 199 e1000_ms_auto 200 }; 201 202 enum e1000_smart_speed { 203 e1000_smart_speed_default = 0, 204 e1000_smart_speed_on, 205 e1000_smart_speed_off 206 }; 207 208 enum e1000_serdes_link_state { 209 e1000_serdes_link_down = 0, 210 e1000_serdes_link_autoneg_progress, 211 e1000_serdes_link_autoneg_complete, 212 e1000_serdes_link_forced_up 213 }; 214 215 /* Receive Descriptor - Extended */ 216 union e1000_rx_desc_extended { 217 struct { 218 __le64 buffer_addr; 219 __le64 reserved; 220 } read; 221 struct { 222 struct { 223 __le32 mrq; /* Multiple Rx Queues */ 224 union { 225 __le32 rss; /* RSS Hash */ 226 struct { 227 __le16 ip_id; /* IP id */ 228 __le16 csum; /* Packet Checksum */ 229 } csum_ip; 230 } hi_dword; 231 } lower; 232 struct { 233 __le32 status_error; /* ext status/error */ 234 __le16 length; 235 __le16 vlan; /* VLAN tag */ 236 } upper; 237 } wb; /* writeback */ 238 }; 239 240 #define MAX_PS_BUFFERS 4 241 242 /* Number of packet split data buffers (not including the header buffer) */ 243 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 244 245 /* Receive Descriptor - Packet Split */ 246 union e1000_rx_desc_packet_split { 247 struct { 248 /* one buffer for protocol header(s), three data buffers */ 249 __le64 buffer_addr[MAX_PS_BUFFERS]; 250 } read; 251 struct { 252 struct { 253 __le32 mrq; /* Multiple Rx Queues */ 254 union { 255 __le32 rss; /* RSS Hash */ 256 struct { 257 __le16 ip_id; /* IP id */ 258 __le16 csum; /* Packet Checksum */ 259 } csum_ip; 260 } hi_dword; 261 } lower; 262 struct { 263 __le32 status_error; /* ext status/error */ 264 __le16 length0; /* length of buffer 0 */ 265 __le16 vlan; /* VLAN tag */ 266 } middle; 267 struct { 268 __le16 header_status; 269 /* length of buffers 1-3 */ 270 __le16 length[PS_PAGE_BUFFERS]; 271 } upper; 272 __le64 reserved; 273 } wb; /* writeback */ 274 }; 275 276 /* Transmit Descriptor */ 277 struct e1000_tx_desc { 278 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 279 union { 280 __le32 data; 281 struct { 282 __le16 length; /* Data buffer length */ 283 u8 cso; /* Checksum offset */ 284 u8 cmd; /* Descriptor control */ 285 } flags; 286 } lower; 287 union { 288 __le32 data; 289 struct { 290 u8 status; /* Descriptor status */ 291 u8 css; /* Checksum start */ 292 __le16 special; 293 } fields; 294 } upper; 295 }; 296 297 /* Offload Context Descriptor */ 298 struct e1000_context_desc { 299 union { 300 __le32 ip_config; 301 struct { 302 u8 ipcss; /* IP checksum start */ 303 u8 ipcso; /* IP checksum offset */ 304 __le16 ipcse; /* IP checksum end */ 305 } ip_fields; 306 } lower_setup; 307 union { 308 __le32 tcp_config; 309 struct { 310 u8 tucss; /* TCP checksum start */ 311 u8 tucso; /* TCP checksum offset */ 312 __le16 tucse; /* TCP checksum end */ 313 } tcp_fields; 314 } upper_setup; 315 __le32 cmd_and_length; 316 union { 317 __le32 data; 318 struct { 319 u8 status; /* Descriptor status */ 320 u8 hdr_len; /* Header length */ 321 __le16 mss; /* Maximum segment size */ 322 } fields; 323 } tcp_seg_setup; 324 }; 325 326 /* Offload data descriptor */ 327 struct e1000_data_desc { 328 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 329 union { 330 __le32 data; 331 struct { 332 __le16 length; /* Data buffer length */ 333 u8 typ_len_ext; 334 u8 cmd; 335 } flags; 336 } lower; 337 union { 338 __le32 data; 339 struct { 340 u8 status; /* Descriptor status */ 341 u8 popts; /* Packet Options */ 342 __le16 special; 343 } fields; 344 } upper; 345 }; 346 347 /* Statistics counters collected by the MAC */ 348 struct e1000_hw_stats { 349 u64 crcerrs; 350 u64 algnerrc; 351 u64 symerrs; 352 u64 rxerrc; 353 u64 mpc; 354 u64 scc; 355 u64 ecol; 356 u64 mcc; 357 u64 latecol; 358 u64 colc; 359 u64 dc; 360 u64 tncrs; 361 u64 sec; 362 u64 cexterr; 363 u64 rlec; 364 u64 xonrxc; 365 u64 xontxc; 366 u64 xoffrxc; 367 u64 xofftxc; 368 u64 fcruc; 369 u64 prc64; 370 u64 prc127; 371 u64 prc255; 372 u64 prc511; 373 u64 prc1023; 374 u64 prc1522; 375 u64 gprc; 376 u64 bprc; 377 u64 mprc; 378 u64 gptc; 379 u64 gorc; 380 u64 gotc; 381 u64 rnbc; 382 u64 ruc; 383 u64 rfc; 384 u64 roc; 385 u64 rjc; 386 u64 mgprc; 387 u64 mgpdc; 388 u64 mgptc; 389 u64 tor; 390 u64 tot; 391 u64 tpr; 392 u64 tpt; 393 u64 ptc64; 394 u64 ptc127; 395 u64 ptc255; 396 u64 ptc511; 397 u64 ptc1023; 398 u64 ptc1522; 399 u64 mptc; 400 u64 bptc; 401 u64 tsctc; 402 u64 tsctfc; 403 u64 iac; 404 u64 icrxptc; 405 u64 icrxatc; 406 u64 ictxptc; 407 u64 ictxatc; 408 u64 ictxqec; 409 u64 ictxqmtc; 410 u64 icrxdmtc; 411 u64 icrxoc; 412 }; 413 414 struct e1000_phy_stats { 415 u32 idle_errors; 416 u32 receive_errors; 417 }; 418 419 struct e1000_host_mng_dhcp_cookie { 420 u32 signature; 421 u8 status; 422 u8 reserved0; 423 u16 vlan_id; 424 u32 reserved1; 425 u16 reserved2; 426 u8 reserved3; 427 u8 checksum; 428 }; 429 430 /* Host Interface "Rev 1" */ 431 struct e1000_host_command_header { 432 u8 command_id; 433 u8 command_length; 434 u8 command_options; 435 u8 checksum; 436 }; 437 438 #define E1000_HI_MAX_DATA_LENGTH 252 439 struct e1000_host_command_info { 440 struct e1000_host_command_header command_header; 441 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 442 }; 443 444 /* Host Interface "Rev 2" */ 445 struct e1000_host_mng_command_header { 446 u8 command_id; 447 u8 checksum; 448 u16 reserved1; 449 u16 reserved2; 450 u16 command_length; 451 }; 452 453 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 454 struct e1000_host_mng_command_info { 455 struct e1000_host_mng_command_header command_header; 456 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 457 }; 458 459 #include "mac.h" 460 #include "phy.h" 461 #include "nvm.h" 462 #include "manage.h" 463 464 /* Function pointers for the MAC. */ 465 struct e1000_mac_operations { 466 s32 (*id_led_init)(struct e1000_hw *); 467 s32 (*blink_led)(struct e1000_hw *); 468 bool (*check_mng_mode)(struct e1000_hw *); 469 s32 (*check_for_link)(struct e1000_hw *); 470 s32 (*cleanup_led)(struct e1000_hw *); 471 void (*clear_hw_cntrs)(struct e1000_hw *); 472 void (*clear_vfta)(struct e1000_hw *); 473 s32 (*get_bus_info)(struct e1000_hw *); 474 void (*set_lan_id)(struct e1000_hw *); 475 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 476 s32 (*led_on)(struct e1000_hw *); 477 s32 (*led_off)(struct e1000_hw *); 478 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 479 s32 (*reset_hw)(struct e1000_hw *); 480 s32 (*init_hw)(struct e1000_hw *); 481 s32 (*setup_link)(struct e1000_hw *); 482 s32 (*setup_physical_interface)(struct e1000_hw *); 483 s32 (*setup_led)(struct e1000_hw *); 484 void (*write_vfta)(struct e1000_hw *, u32, u32); 485 void (*config_collision_dist)(struct e1000_hw *); 486 int (*rar_set)(struct e1000_hw *, u8 *, u32); 487 s32 (*read_mac_addr)(struct e1000_hw *); 488 u32 (*rar_get_count)(struct e1000_hw *); 489 }; 490 491 /* When to use various PHY register access functions: 492 * 493 * Func Caller 494 * Function Does Does When to use 495 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 496 * X_reg L,P,A n/a for simple PHY reg accesses 497 * X_reg_locked P,A L for multiple accesses of different regs 498 * on different pages 499 * X_reg_page A L,P for multiple accesses of different regs 500 * on the same page 501 * 502 * Where X=[read|write], L=locking, P=sets page, A=register access 503 * 504 */ 505 struct e1000_phy_operations { 506 s32 (*acquire)(struct e1000_hw *); 507 s32 (*cfg_on_link_up)(struct e1000_hw *); 508 s32 (*check_polarity)(struct e1000_hw *); 509 s32 (*check_reset_block)(struct e1000_hw *); 510 s32 (*commit)(struct e1000_hw *); 511 s32 (*force_speed_duplex)(struct e1000_hw *); 512 s32 (*get_cfg_done)(struct e1000_hw *hw); 513 s32 (*get_cable_length)(struct e1000_hw *); 514 s32 (*get_info)(struct e1000_hw *); 515 s32 (*set_page)(struct e1000_hw *, u16); 516 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 517 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 518 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 519 void (*release)(struct e1000_hw *); 520 s32 (*reset)(struct e1000_hw *); 521 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 522 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 523 s32 (*write_reg)(struct e1000_hw *, u32, u16); 524 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 525 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 526 void (*power_up)(struct e1000_hw *); 527 void (*power_down)(struct e1000_hw *); 528 }; 529 530 /* Function pointers for the NVM. */ 531 struct e1000_nvm_operations { 532 s32 (*acquire)(struct e1000_hw *); 533 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 534 void (*release)(struct e1000_hw *); 535 void (*reload)(struct e1000_hw *); 536 s32 (*update)(struct e1000_hw *); 537 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 538 s32 (*validate)(struct e1000_hw *); 539 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 540 }; 541 542 struct e1000_mac_info { 543 struct e1000_mac_operations ops; 544 u8 addr[ETH_ALEN]; 545 u8 perm_addr[ETH_ALEN]; 546 547 enum e1000_mac_type type; 548 549 u32 collision_delta; 550 u32 ledctl_default; 551 u32 ledctl_mode1; 552 u32 ledctl_mode2; 553 u32 mc_filter_type; 554 u32 tx_packet_delta; 555 u32 txcw; 556 557 u16 current_ifs_val; 558 u16 ifs_max_val; 559 u16 ifs_min_val; 560 u16 ifs_ratio; 561 u16 ifs_step_size; 562 u16 mta_reg_count; 563 564 /* Maximum size of the MTA register table in all supported adapters */ 565 #define MAX_MTA_REG 128 566 u32 mta_shadow[MAX_MTA_REG]; 567 u16 rar_entry_count; 568 569 u8 forced_speed_duplex; 570 571 bool adaptive_ifs; 572 bool has_fwsm; 573 bool arc_subsystem_valid; 574 bool autoneg; 575 bool autoneg_failed; 576 bool get_link_status; 577 bool in_ifs_mode; 578 bool serdes_has_link; 579 bool tx_pkt_filtering; 580 enum e1000_serdes_link_state serdes_link_state; 581 }; 582 583 struct e1000_phy_info { 584 struct e1000_phy_operations ops; 585 586 enum e1000_phy_type type; 587 588 enum e1000_1000t_rx_status local_rx; 589 enum e1000_1000t_rx_status remote_rx; 590 enum e1000_ms_type ms_type; 591 enum e1000_ms_type original_ms_type; 592 enum e1000_rev_polarity cable_polarity; 593 enum e1000_smart_speed smart_speed; 594 595 u32 addr; 596 u32 id; 597 u32 reset_delay_us; /* in usec */ 598 u32 revision; 599 600 enum e1000_media_type media_type; 601 602 u16 autoneg_advertised; 603 u16 autoneg_mask; 604 u16 cable_length; 605 u16 max_cable_length; 606 u16 min_cable_length; 607 608 u8 mdix; 609 610 bool disable_polarity_correction; 611 bool is_mdix; 612 bool polarity_correction; 613 bool speed_downgraded; 614 bool autoneg_wait_to_complete; 615 }; 616 617 struct e1000_nvm_info { 618 struct e1000_nvm_operations ops; 619 620 enum e1000_nvm_type type; 621 enum e1000_nvm_override override; 622 623 u32 flash_bank_size; 624 u32 flash_base_addr; 625 626 u16 word_size; 627 u16 delay_usec; 628 u16 address_bits; 629 u16 opcode_bits; 630 u16 page_size; 631 }; 632 633 struct e1000_bus_info { 634 enum e1000_bus_width width; 635 636 u16 func; 637 }; 638 639 struct e1000_fc_info { 640 u32 high_water; /* Flow control high-water mark */ 641 u32 low_water; /* Flow control low-water mark */ 642 u16 pause_time; /* Flow control pause timer */ 643 u16 refresh_time; /* Flow control refresh timer */ 644 bool send_xon; /* Flow control send XON */ 645 bool strict_ieee; /* Strict IEEE mode */ 646 enum e1000_fc_mode current_mode; /* FC mode in effect */ 647 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 648 }; 649 650 struct e1000_dev_spec_82571 { 651 bool laa_is_present; 652 u32 smb_counter; 653 }; 654 655 struct e1000_dev_spec_80003es2lan { 656 bool mdic_wa_enable; 657 }; 658 659 struct e1000_shadow_ram { 660 u16 value; 661 bool modified; 662 }; 663 664 #define E1000_ICH8_SHADOW_RAM_WORDS 2048 665 666 /* I218 PHY Ultra Low Power (ULP) states */ 667 enum e1000_ulp_state { 668 e1000_ulp_state_unknown, 669 e1000_ulp_state_off, 670 e1000_ulp_state_on, 671 }; 672 673 struct e1000_dev_spec_ich8lan { 674 bool kmrn_lock_loss_workaround_enabled; 675 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 676 bool nvm_k1_enabled; 677 bool eee_disable; 678 u16 eee_lp_ability; 679 enum e1000_ulp_state ulp_state; 680 }; 681 682 struct e1000_hw { 683 struct e1000_adapter *adapter; 684 685 void __iomem *hw_addr; 686 void __iomem *flash_address; 687 688 struct e1000_mac_info mac; 689 struct e1000_fc_info fc; 690 struct e1000_phy_info phy; 691 struct e1000_nvm_info nvm; 692 struct e1000_bus_info bus; 693 struct e1000_host_mng_dhcp_cookie mng_cookie; 694 695 union { 696 struct e1000_dev_spec_82571 e82571; 697 struct e1000_dev_spec_80003es2lan e80003es2lan; 698 struct e1000_dev_spec_ich8lan ich8lan; 699 } dev_spec; 700 }; 701 702 #include "82571.h" 703 #include "80003es2lan.h" 704 #include "ich8lan.h" 705 706 #endif 707