1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #ifndef _E1000E_HW_H_
5 #define _E1000E_HW_H_
6 
7 #include "regs.h"
8 #include "defines.h"
9 
10 struct e1000_hw;
11 
12 #define E1000_DEV_ID_82571EB_COPPER		0x105E
13 #define E1000_DEV_ID_82571EB_FIBER		0x105F
14 #define E1000_DEV_ID_82571EB_SERDES		0x1060
15 #define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
16 #define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
17 #define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
19 #define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
20 #define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
21 #define E1000_DEV_ID_82572EI_COPPER		0x107D
22 #define E1000_DEV_ID_82572EI_FIBER		0x107E
23 #define E1000_DEV_ID_82572EI_SERDES		0x107F
24 #define E1000_DEV_ID_82572EI			0x10B9
25 #define E1000_DEV_ID_82573E			0x108B
26 #define E1000_DEV_ID_82573E_IAMT		0x108C
27 #define E1000_DEV_ID_82573L			0x109A
28 #define E1000_DEV_ID_82574L			0x10D3
29 #define E1000_DEV_ID_82574LA			0x10F6
30 #define E1000_DEV_ID_82583V			0x150C
31 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
32 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
33 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
34 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
35 #define E1000_DEV_ID_ICH8_82567V_3		0x1501
36 #define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
37 #define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
38 #define E1000_DEV_ID_ICH8_IGP_C			0x104B
39 #define E1000_DEV_ID_ICH8_IFE			0x104C
40 #define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
41 #define E1000_DEV_ID_ICH8_IFE_G			0x10C5
42 #define E1000_DEV_ID_ICH8_IGP_M			0x104D
43 #define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
44 #define E1000_DEV_ID_ICH9_BM			0x10E5
45 #define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
46 #define E1000_DEV_ID_ICH9_IGP_M			0x10BF
47 #define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
48 #define E1000_DEV_ID_ICH9_IGP_C			0x294C
49 #define E1000_DEV_ID_ICH9_IFE			0x10C0
50 #define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
51 #define E1000_DEV_ID_ICH9_IFE_G			0x10C2
52 #define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
53 #define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
54 #define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
55 #define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
56 #define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
57 #define E1000_DEV_ID_ICH10_D_BM_V		0x1525
58 #define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
59 #define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
60 #define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
61 #define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
62 #define E1000_DEV_ID_PCH2_LV_LM			0x1502
63 #define E1000_DEV_ID_PCH2_LV_V			0x1503
64 #define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
65 #define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
66 #define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
67 #define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559
68 #define E1000_DEV_ID_PCH_I218_LM2		0x15A0
69 #define E1000_DEV_ID_PCH_I218_V2		0x15A1
70 #define E1000_DEV_ID_PCH_I218_LM3		0x15A2	/* Wildcat Point PCH */
71 #define E1000_DEV_ID_PCH_I218_V3		0x15A3	/* Wildcat Point PCH */
72 #define E1000_DEV_ID_PCH_SPT_I219_LM		0x156F	/* SPT PCH */
73 #define E1000_DEV_ID_PCH_SPT_I219_V		0x1570	/* SPT PCH */
74 #define E1000_DEV_ID_PCH_SPT_I219_LM2		0x15B7	/* SPT-H PCH */
75 #define E1000_DEV_ID_PCH_SPT_I219_V2		0x15B8	/* SPT-H PCH */
76 #define E1000_DEV_ID_PCH_LBG_I219_LM3		0x15B9	/* LBG PCH */
77 #define E1000_DEV_ID_PCH_SPT_I219_LM4		0x15D7
78 #define E1000_DEV_ID_PCH_SPT_I219_V4		0x15D8
79 #define E1000_DEV_ID_PCH_SPT_I219_LM5		0x15E3
80 #define E1000_DEV_ID_PCH_SPT_I219_V5		0x15D6
81 #define E1000_DEV_ID_PCH_CNP_I219_LM6		0x15BD
82 #define E1000_DEV_ID_PCH_CNP_I219_V6		0x15BE
83 #define E1000_DEV_ID_PCH_CNP_I219_LM7		0x15BB
84 #define E1000_DEV_ID_PCH_CNP_I219_V7		0x15BC
85 #define E1000_DEV_ID_PCH_ICP_I219_LM8		0x15DF
86 #define E1000_DEV_ID_PCH_ICP_I219_V8		0x15E0
87 #define E1000_DEV_ID_PCH_ICP_I219_LM9		0x15E1
88 #define E1000_DEV_ID_PCH_ICP_I219_V9		0x15E2
89 #define E1000_DEV_ID_PCH_CMP_I219_LM10		0x0D4E
90 #define E1000_DEV_ID_PCH_CMP_I219_V10		0x0D4F
91 #define E1000_DEV_ID_PCH_CMP_I219_LM11		0x0D4C
92 #define E1000_DEV_ID_PCH_CMP_I219_V11		0x0D4D
93 #define E1000_DEV_ID_PCH_CMP_I219_LM12		0x0D53
94 #define E1000_DEV_ID_PCH_CMP_I219_V12		0x0D55
95 #define E1000_DEV_ID_PCH_TGP_I219_LM13		0x15FB
96 #define E1000_DEV_ID_PCH_TGP_I219_V13		0x15FC
97 #define E1000_DEV_ID_PCH_TGP_I219_LM14		0x15F9
98 #define E1000_DEV_ID_PCH_TGP_I219_V14		0x15FA
99 #define E1000_DEV_ID_PCH_TGP_I219_LM15		0x15F4
100 #define E1000_DEV_ID_PCH_TGP_I219_V15		0x15F5
101 #define E1000_DEV_ID_PCH_RPL_I219_LM23		0x0DC5
102 #define E1000_DEV_ID_PCH_RPL_I219_V23		0x0DC6
103 #define E1000_DEV_ID_PCH_ADP_I219_LM16		0x1A1E
104 #define E1000_DEV_ID_PCH_ADP_I219_V16		0x1A1F
105 #define E1000_DEV_ID_PCH_ADP_I219_LM17		0x1A1C
106 #define E1000_DEV_ID_PCH_ADP_I219_V17		0x1A1D
107 #define E1000_DEV_ID_PCH_RPL_I219_LM22		0x0DC7
108 #define E1000_DEV_ID_PCH_RPL_I219_V22		0x0DC8
109 #define E1000_DEV_ID_PCH_MTP_I219_LM18		0x550A
110 #define E1000_DEV_ID_PCH_MTP_I219_V18		0x550B
111 #define E1000_DEV_ID_PCH_MTP_I219_LM19		0x550C
112 #define E1000_DEV_ID_PCH_MTP_I219_V19		0x550D
113 #define E1000_DEV_ID_PCH_LNP_I219_LM20		0x550E
114 #define E1000_DEV_ID_PCH_LNP_I219_V20		0x550F
115 #define E1000_DEV_ID_PCH_LNP_I219_LM21		0x5510
116 #define E1000_DEV_ID_PCH_LNP_I219_V21		0x5511
117 #define E1000_DEV_ID_PCH_ARL_I219_LM24		0x57A0
118 #define E1000_DEV_ID_PCH_ARL_I219_V24		0x57A1
119 #define E1000_DEV_ID_PCH_PTP_I219_LM25		0x57B3
120 #define E1000_DEV_ID_PCH_PTP_I219_V25		0x57B4
121 #define E1000_DEV_ID_PCH_PTP_I219_LM26		0x57B5
122 #define E1000_DEV_ID_PCH_PTP_I219_V26		0x57B6
123 #define E1000_DEV_ID_PCH_PTP_I219_LM27		0x57B7
124 #define E1000_DEV_ID_PCH_PTP_I219_V27		0x57B8
125 #define E1000_DEV_ID_PCH_NVL_I219_LM29		0x57B9
126 #define E1000_DEV_ID_PCH_NVL_I219_V29		0x57BA
127 
128 #define E1000_REVISION_4	4
129 
130 #define E1000_FUNC_1		1
131 
132 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
133 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
134 
135 enum e1000_mac_type {
136 	e1000_82571,
137 	e1000_82572,
138 	e1000_82573,
139 	e1000_82574,
140 	e1000_82583,
141 	e1000_80003es2lan,
142 	e1000_ich8lan,
143 	e1000_ich9lan,
144 	e1000_ich10lan,
145 	e1000_pchlan,
146 	e1000_pch2lan,
147 	e1000_pch_lpt,
148 	e1000_pch_spt,
149 	e1000_pch_cnp,
150 	e1000_pch_tgp,
151 	e1000_pch_adp,
152 	e1000_pch_mtp,
153 	e1000_pch_lnp,
154 	e1000_pch_ptp,
155 	e1000_pch_nvp,
156 };
157 
158 enum e1000_media_type {
159 	e1000_media_type_unknown = 0,
160 	e1000_media_type_copper = 1,
161 	e1000_media_type_fiber = 2,
162 	e1000_media_type_internal_serdes = 3,
163 	e1000_num_media_types
164 };
165 
166 enum e1000_nvm_type {
167 	e1000_nvm_unknown = 0,
168 	e1000_nvm_none,
169 	e1000_nvm_eeprom_spi,
170 	e1000_nvm_flash_hw,
171 	e1000_nvm_flash_sw
172 };
173 
174 enum e1000_nvm_override {
175 	e1000_nvm_override_none = 0,
176 	e1000_nvm_override_spi_small,
177 	e1000_nvm_override_spi_large
178 };
179 
180 enum e1000_phy_type {
181 	e1000_phy_unknown = 0,
182 	e1000_phy_none,
183 	e1000_phy_m88,
184 	e1000_phy_igp,
185 	e1000_phy_igp_2,
186 	e1000_phy_gg82563,
187 	e1000_phy_igp_3,
188 	e1000_phy_ife,
189 	e1000_phy_bm,
190 	e1000_phy_82578,
191 	e1000_phy_82577,
192 	e1000_phy_82579,
193 	e1000_phy_i217,
194 };
195 
196 enum e1000_bus_width {
197 	e1000_bus_width_unknown = 0,
198 	e1000_bus_width_pcie_x1,
199 	e1000_bus_width_pcie_x2,
200 	e1000_bus_width_pcie_x4 = 4,
201 	e1000_bus_width_pcie_x8 = 8,
202 	e1000_bus_width_32,
203 	e1000_bus_width_64,
204 	e1000_bus_width_reserved
205 };
206 
207 enum e1000_1000t_rx_status {
208 	e1000_1000t_rx_status_not_ok = 0,
209 	e1000_1000t_rx_status_ok,
210 	e1000_1000t_rx_status_undefined = 0xFF
211 };
212 
213 enum e1000_rev_polarity {
214 	e1000_rev_polarity_normal = 0,
215 	e1000_rev_polarity_reversed,
216 	e1000_rev_polarity_undefined = 0xFF
217 };
218 
219 enum e1000_fc_mode {
220 	e1000_fc_none = 0,
221 	e1000_fc_rx_pause,
222 	e1000_fc_tx_pause,
223 	e1000_fc_full,
224 	e1000_fc_default = 0xFF
225 };
226 
227 enum e1000_ms_type {
228 	e1000_ms_hw_default = 0,
229 	e1000_ms_force_master,
230 	e1000_ms_force_slave,
231 	e1000_ms_auto
232 };
233 
234 enum e1000_smart_speed {
235 	e1000_smart_speed_default = 0,
236 	e1000_smart_speed_on,
237 	e1000_smart_speed_off
238 };
239 
240 enum e1000_serdes_link_state {
241 	e1000_serdes_link_down = 0,
242 	e1000_serdes_link_autoneg_progress,
243 	e1000_serdes_link_autoneg_complete,
244 	e1000_serdes_link_forced_up
245 };
246 
247 /* Receive Descriptor - Extended */
248 union e1000_rx_desc_extended {
249 	struct {
250 		__le64 buffer_addr;
251 		__le64 reserved;
252 	} read;
253 	struct {
254 		struct {
255 			__le32 mrq;	      /* Multiple Rx Queues */
256 			union {
257 				__le32 rss;	    /* RSS Hash */
258 				struct {
259 					__le16 ip_id;  /* IP id */
260 					__le16 csum;   /* Packet Checksum */
261 				} csum_ip;
262 			} hi_dword;
263 		} lower;
264 		struct {
265 			__le32 status_error;     /* ext status/error */
266 			__le16 length;
267 			__le16 vlan;	     /* VLAN tag */
268 		} upper;
269 	} wb;  /* writeback */
270 };
271 
272 #define MAX_PS_BUFFERS 4
273 
274 /* Number of packet split data buffers (not including the header buffer) */
275 #define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)
276 
277 /* Receive Descriptor - Packet Split */
278 union e1000_rx_desc_packet_split {
279 	struct {
280 		/* one buffer for protocol header(s), three data buffers */
281 		__le64 buffer_addr[MAX_PS_BUFFERS];
282 	} read;
283 	struct {
284 		struct {
285 			__le32 mrq;	      /* Multiple Rx Queues */
286 			union {
287 				__le32 rss;	      /* RSS Hash */
288 				struct {
289 					__le16 ip_id;    /* IP id */
290 					__le16 csum;     /* Packet Checksum */
291 				} csum_ip;
292 			} hi_dword;
293 		} lower;
294 		struct {
295 			__le32 status_error;     /* ext status/error */
296 			__le16 length0;	  /* length of buffer 0 */
297 			__le16 vlan;	     /* VLAN tag */
298 		} middle;
299 		struct {
300 			__le16 header_status;
301 			/* length of buffers 1-3 */
302 			__le16 length[PS_PAGE_BUFFERS];
303 		} upper;
304 		__le64 reserved;
305 	} wb; /* writeback */
306 };
307 
308 /* Transmit Descriptor */
309 struct e1000_tx_desc {
310 	__le64 buffer_addr;      /* Address of the descriptor's data buffer */
311 	union {
312 		__le32 data;
313 		struct {
314 			__le16 length;    /* Data buffer length */
315 			u8 cso;	/* Checksum offset */
316 			u8 cmd;	/* Descriptor control */
317 		} flags;
318 	} lower;
319 	union {
320 		__le32 data;
321 		struct {
322 			u8 status;     /* Descriptor status */
323 			u8 css;	/* Checksum start */
324 			__le16 special;
325 		} fields;
326 	} upper;
327 };
328 
329 /* Offload Context Descriptor */
330 struct e1000_context_desc {
331 	union {
332 		__le32 ip_config;
333 		struct {
334 			u8 ipcss;      /* IP checksum start */
335 			u8 ipcso;      /* IP checksum offset */
336 			__le16 ipcse;     /* IP checksum end */
337 		} ip_fields;
338 	} lower_setup;
339 	union {
340 		__le32 tcp_config;
341 		struct {
342 			u8 tucss;      /* TCP checksum start */
343 			u8 tucso;      /* TCP checksum offset */
344 			__le16 tucse;     /* TCP checksum end */
345 		} tcp_fields;
346 	} upper_setup;
347 	__le32 cmd_and_length;
348 	union {
349 		__le32 data;
350 		struct {
351 			u8 status;     /* Descriptor status */
352 			u8 hdr_len;    /* Header length */
353 			__le16 mss;       /* Maximum segment size */
354 		} fields;
355 	} tcp_seg_setup;
356 };
357 
358 /* Offload data descriptor */
359 struct e1000_data_desc {
360 	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
361 	union {
362 		__le32 data;
363 		struct {
364 			__le16 length;    /* Data buffer length */
365 			u8 typ_len_ext;
366 			u8 cmd;
367 		} flags;
368 	} lower;
369 	union {
370 		__le32 data;
371 		struct {
372 			u8 status;     /* Descriptor status */
373 			u8 popts;      /* Packet Options */
374 			__le16 special;
375 		} fields;
376 	} upper;
377 };
378 
379 /* Statistics counters collected by the MAC */
380 struct e1000_hw_stats {
381 	u64 crcerrs;
382 	u64 algnerrc;
383 	u64 symerrs;
384 	u64 rxerrc;
385 	u64 mpc;
386 	u64 scc;
387 	u64 ecol;
388 	u64 mcc;
389 	u64 latecol;
390 	u64 colc;
391 	u64 dc;
392 	u64 tncrs;
393 	u64 sec;
394 	u64 cexterr;
395 	u64 rlec;
396 	u64 xonrxc;
397 	u64 xontxc;
398 	u64 xoffrxc;
399 	u64 xofftxc;
400 	u64 fcruc;
401 	u64 prc64;
402 	u64 prc127;
403 	u64 prc255;
404 	u64 prc511;
405 	u64 prc1023;
406 	u64 prc1522;
407 	u64 gprc;
408 	u64 bprc;
409 	u64 mprc;
410 	u64 gptc;
411 	u64 gorc;
412 	u64 gotc;
413 	u64 rnbc;
414 	u64 ruc;
415 	u64 rfc;
416 	u64 roc;
417 	u64 rjc;
418 	u64 mgprc;
419 	u64 mgpdc;
420 	u64 mgptc;
421 	u64 tor;
422 	u64 tot;
423 	u64 tpr;
424 	u64 tpt;
425 	u64 ptc64;
426 	u64 ptc127;
427 	u64 ptc255;
428 	u64 ptc511;
429 	u64 ptc1023;
430 	u64 ptc1522;
431 	u64 mptc;
432 	u64 bptc;
433 	u64 tsctc;
434 	u64 tsctfc;
435 	u64 iac;
436 	u64 icrxptc;
437 	u64 icrxatc;
438 	u64 ictxptc;
439 	u64 ictxatc;
440 	u64 ictxqec;
441 	u64 ictxqmtc;
442 	u64 icrxdmtc;
443 	u64 icrxoc;
444 };
445 
446 struct e1000_phy_stats {
447 	u32 idle_errors;
448 	u32 receive_errors;
449 };
450 
451 struct e1000_host_mng_dhcp_cookie {
452 	u32 signature;
453 	u8 status;
454 	u8 reserved0;
455 	u16 vlan_id;
456 	u32 reserved1;
457 	u16 reserved2;
458 	u8 reserved3;
459 	u8 checksum;
460 };
461 
462 /* Host Interface "Rev 1" */
463 struct e1000_host_command_header {
464 	u8 command_id;
465 	u8 command_length;
466 	u8 command_options;
467 	u8 checksum;
468 };
469 
470 #define E1000_HI_MAX_DATA_LENGTH	252
471 struct e1000_host_command_info {
472 	struct e1000_host_command_header command_header;
473 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
474 };
475 
476 /* Host Interface "Rev 2" */
477 struct e1000_host_mng_command_header {
478 	u8 command_id;
479 	u8 checksum;
480 	u16 reserved1;
481 	u16 reserved2;
482 	u16 command_length;
483 };
484 
485 #define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
486 struct e1000_host_mng_command_info {
487 	struct e1000_host_mng_command_header command_header;
488 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
489 };
490 
491 #include "mac.h"
492 #include "phy.h"
493 #include "nvm.h"
494 #include "manage.h"
495 
496 /* Function pointers for the MAC. */
497 struct e1000_mac_operations {
498 	s32  (*id_led_init)(struct e1000_hw *);
499 	s32  (*blink_led)(struct e1000_hw *);
500 	bool (*check_mng_mode)(struct e1000_hw *);
501 	s32  (*check_for_link)(struct e1000_hw *);
502 	s32  (*cleanup_led)(struct e1000_hw *);
503 	void (*clear_hw_cntrs)(struct e1000_hw *);
504 	void (*clear_vfta)(struct e1000_hw *);
505 	s32  (*get_bus_info)(struct e1000_hw *);
506 	void (*set_lan_id)(struct e1000_hw *);
507 	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
508 	s32  (*led_on)(struct e1000_hw *);
509 	s32  (*led_off)(struct e1000_hw *);
510 	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
511 	s32  (*reset_hw)(struct e1000_hw *);
512 	s32  (*init_hw)(struct e1000_hw *);
513 	s32  (*setup_link)(struct e1000_hw *);
514 	s32  (*setup_physical_interface)(struct e1000_hw *);
515 	s32  (*setup_led)(struct e1000_hw *);
516 	void (*write_vfta)(struct e1000_hw *, u32, u32);
517 	void (*config_collision_dist)(struct e1000_hw *);
518 	int  (*rar_set)(struct e1000_hw *, u8 *, u32);
519 	s32  (*read_mac_addr)(struct e1000_hw *);
520 	u32  (*rar_get_count)(struct e1000_hw *);
521 };
522 
523 /* When to use various PHY register access functions:
524  *
525  *                 Func   Caller
526  *   Function      Does   Does    When to use
527  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
528  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
529  *   X_reg_locked  P,A    L       for multiple accesses of different regs
530  *                                on different pages
531  *   X_reg_page    A      L,P     for multiple accesses of different regs
532  *                                on the same page
533  *
534  * Where X=[read|write], L=locking, P=sets page, A=register access
535  *
536  */
537 struct e1000_phy_operations {
538 	s32  (*acquire)(struct e1000_hw *);
539 	s32  (*cfg_on_link_up)(struct e1000_hw *);
540 	s32  (*check_polarity)(struct e1000_hw *);
541 	s32  (*check_reset_block)(struct e1000_hw *);
542 	s32  (*commit)(struct e1000_hw *);
543 	s32  (*force_speed_duplex)(struct e1000_hw *);
544 	s32  (*get_cfg_done)(struct e1000_hw *hw);
545 	s32  (*get_cable_length)(struct e1000_hw *);
546 	s32  (*get_info)(struct e1000_hw *);
547 	s32  (*set_page)(struct e1000_hw *, u16);
548 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
549 	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
550 	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
551 	void (*release)(struct e1000_hw *);
552 	s32  (*reset)(struct e1000_hw *);
553 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
554 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
555 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
556 	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
557 	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
558 	void (*power_up)(struct e1000_hw *);
559 	void (*power_down)(struct e1000_hw *);
560 };
561 
562 /* Function pointers for the NVM. */
563 struct e1000_nvm_operations {
564 	s32  (*acquire)(struct e1000_hw *);
565 	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
566 	void (*release)(struct e1000_hw *);
567 	void (*reload)(struct e1000_hw *);
568 	s32  (*update)(struct e1000_hw *);
569 	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
570 	s32  (*validate)(struct e1000_hw *);
571 	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
572 };
573 
574 struct e1000_mac_info {
575 	struct e1000_mac_operations ops;
576 	u8 addr[ETH_ALEN];
577 	u8 perm_addr[ETH_ALEN];
578 
579 	enum e1000_mac_type type;
580 
581 	u32 collision_delta;
582 	u32 ledctl_default;
583 	u32 ledctl_mode1;
584 	u32 ledctl_mode2;
585 	u32 mc_filter_type;
586 	u32 tx_packet_delta;
587 	u32 txcw;
588 
589 	u16 current_ifs_val;
590 	u16 ifs_max_val;
591 	u16 ifs_min_val;
592 	u16 ifs_ratio;
593 	u16 ifs_step_size;
594 	u16 mta_reg_count;
595 
596 	/* Maximum size of the MTA register table in all supported adapters */
597 #define MAX_MTA_REG 128
598 	u32 mta_shadow[MAX_MTA_REG];
599 	u16 rar_entry_count;
600 
601 	u8 forced_speed_duplex;
602 
603 	bool adaptive_ifs;
604 	bool has_fwsm;
605 	bool arc_subsystem_valid;
606 	bool autoneg;
607 	bool autoneg_failed;
608 	bool get_link_status;
609 	bool in_ifs_mode;
610 	bool serdes_has_link;
611 	bool tx_pkt_filtering;
612 	enum e1000_serdes_link_state serdes_link_state;
613 };
614 
615 struct e1000_phy_info {
616 	struct e1000_phy_operations ops;
617 
618 	enum e1000_phy_type type;
619 
620 	enum e1000_1000t_rx_status local_rx;
621 	enum e1000_1000t_rx_status remote_rx;
622 	enum e1000_ms_type ms_type;
623 	enum e1000_ms_type original_ms_type;
624 	enum e1000_rev_polarity cable_polarity;
625 	enum e1000_smart_speed smart_speed;
626 
627 	u32 addr;
628 	u32 id;
629 	u32 reset_delay_us;	/* in usec */
630 	u32 revision;
631 
632 	enum e1000_media_type media_type;
633 
634 	u16 autoneg_advertised;
635 	u16 autoneg_mask;
636 	u16 cable_length;
637 	u16 max_cable_length;
638 	u16 min_cable_length;
639 
640 	u8 mdix;
641 
642 	bool disable_polarity_correction;
643 	bool is_mdix;
644 	bool polarity_correction;
645 	bool speed_downgraded;
646 	bool autoneg_wait_to_complete;
647 };
648 
649 struct e1000_nvm_info {
650 	struct e1000_nvm_operations ops;
651 
652 	enum e1000_nvm_type type;
653 	enum e1000_nvm_override override;
654 
655 	u32 flash_bank_size;
656 	u32 flash_base_addr;
657 
658 	u16 word_size;
659 	u16 delay_usec;
660 	u16 address_bits;
661 	u16 opcode_bits;
662 	u16 page_size;
663 };
664 
665 struct e1000_bus_info {
666 	enum e1000_bus_width width;
667 
668 	u16 func;
669 };
670 
671 struct e1000_fc_info {
672 	u32 high_water;          /* Flow control high-water mark */
673 	u32 low_water;           /* Flow control low-water mark */
674 	u16 pause_time;          /* Flow control pause timer */
675 	u16 refresh_time;        /* Flow control refresh timer */
676 	bool send_xon;           /* Flow control send XON */
677 	bool strict_ieee;        /* Strict IEEE mode */
678 	enum e1000_fc_mode current_mode; /* FC mode in effect */
679 	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
680 };
681 
682 struct e1000_dev_spec_82571 {
683 	bool laa_is_present;
684 	u32 smb_counter;
685 };
686 
687 struct e1000_dev_spec_80003es2lan {
688 	bool mdic_wa_enable;
689 };
690 
691 struct e1000_shadow_ram {
692 	u16 value;
693 	bool modified;
694 };
695 
696 #define E1000_ICH8_SHADOW_RAM_WORDS		2048
697 
698 /* I218 PHY Ultra Low Power (ULP) states */
699 enum e1000_ulp_state {
700 	e1000_ulp_state_unknown,
701 	e1000_ulp_state_off,
702 	e1000_ulp_state_on,
703 };
704 
705 struct e1000_dev_spec_ich8lan {
706 	bool kmrn_lock_loss_workaround_enabled;
707 	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
708 	bool nvm_k1_enabled;
709 	bool eee_disable;
710 	u16 eee_lp_ability;
711 	enum e1000_ulp_state ulp_state;
712 };
713 
714 struct e1000_hw {
715 	struct e1000_adapter *adapter;
716 
717 	void __iomem *hw_addr;
718 	void __iomem *flash_address;
719 
720 	struct e1000_mac_info mac;
721 	struct e1000_fc_info fc;
722 	struct e1000_phy_info phy;
723 	struct e1000_nvm_info nvm;
724 	struct e1000_bus_info bus;
725 	struct e1000_host_mng_dhcp_cookie mng_cookie;
726 
727 	union {
728 		struct e1000_dev_spec_82571 e82571;
729 		struct e1000_dev_spec_80003es2lan e80003es2lan;
730 		struct e1000_dev_spec_ich8lan ich8lan;
731 	} dev_spec;
732 };
733 
734 #include "82571.h"
735 #include "80003es2lan.h"
736 #include "ich8lan.h"
737 
738 #endif /* _E1000E_HW_H_ */
739