1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Intel PRO/1000 Linux driver 3 * Copyright(c) 1999 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 * Contact Information: 18 * Linux NICS <linux.nics@intel.com> 19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 21 */ 22 23 #ifndef _E1000_HW_H_ 24 #define _E1000_HW_H_ 25 26 #include "regs.h" 27 #include "defines.h" 28 29 struct e1000_hw; 30 31 #define E1000_DEV_ID_82571EB_COPPER 0x105E 32 #define E1000_DEV_ID_82571EB_FIBER 0x105F 33 #define E1000_DEV_ID_82571EB_SERDES 0x1060 34 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 35 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 36 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 37 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 38 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 39 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 40 #define E1000_DEV_ID_82572EI_COPPER 0x107D 41 #define E1000_DEV_ID_82572EI_FIBER 0x107E 42 #define E1000_DEV_ID_82572EI_SERDES 0x107F 43 #define E1000_DEV_ID_82572EI 0x10B9 44 #define E1000_DEV_ID_82573E 0x108B 45 #define E1000_DEV_ID_82573E_IAMT 0x108C 46 #define E1000_DEV_ID_82573L 0x109A 47 #define E1000_DEV_ID_82574L 0x10D3 48 #define E1000_DEV_ID_82574LA 0x10F6 49 #define E1000_DEV_ID_82583V 0x150C 50 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 51 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 52 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 53 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 54 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 55 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 56 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 57 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 58 #define E1000_DEV_ID_ICH8_IFE 0x104C 59 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 60 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 61 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 62 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 63 #define E1000_DEV_ID_ICH9_BM 0x10E5 64 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 65 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 66 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 67 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 68 #define E1000_DEV_ID_ICH9_IFE 0x10C0 69 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 70 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 71 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 72 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 73 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 74 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 75 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 76 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 77 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 78 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 79 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 80 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 81 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 82 #define E1000_DEV_ID_PCH2_LV_V 0x1503 83 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 84 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 85 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 86 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 87 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 88 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 89 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 90 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 91 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */ 92 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */ 93 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */ 94 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */ 95 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */ 96 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 97 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 98 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 99 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 100 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 101 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 102 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 103 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 104 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 105 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 106 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 107 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 108 109 #define E1000_REVISION_4 4 110 111 #define E1000_FUNC_1 1 112 113 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 114 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 115 116 enum e1000_mac_type { 117 e1000_82571, 118 e1000_82572, 119 e1000_82573, 120 e1000_82574, 121 e1000_82583, 122 e1000_80003es2lan, 123 e1000_ich8lan, 124 e1000_ich9lan, 125 e1000_ich10lan, 126 e1000_pchlan, 127 e1000_pch2lan, 128 e1000_pch_lpt, 129 e1000_pch_spt, 130 e1000_pch_cnp, 131 }; 132 133 enum e1000_media_type { 134 e1000_media_type_unknown = 0, 135 e1000_media_type_copper = 1, 136 e1000_media_type_fiber = 2, 137 e1000_media_type_internal_serdes = 3, 138 e1000_num_media_types 139 }; 140 141 enum e1000_nvm_type { 142 e1000_nvm_unknown = 0, 143 e1000_nvm_none, 144 e1000_nvm_eeprom_spi, 145 e1000_nvm_flash_hw, 146 e1000_nvm_flash_sw 147 }; 148 149 enum e1000_nvm_override { 150 e1000_nvm_override_none = 0, 151 e1000_nvm_override_spi_small, 152 e1000_nvm_override_spi_large 153 }; 154 155 enum e1000_phy_type { 156 e1000_phy_unknown = 0, 157 e1000_phy_none, 158 e1000_phy_m88, 159 e1000_phy_igp, 160 e1000_phy_igp_2, 161 e1000_phy_gg82563, 162 e1000_phy_igp_3, 163 e1000_phy_ife, 164 e1000_phy_bm, 165 e1000_phy_82578, 166 e1000_phy_82577, 167 e1000_phy_82579, 168 e1000_phy_i217, 169 }; 170 171 enum e1000_bus_width { 172 e1000_bus_width_unknown = 0, 173 e1000_bus_width_pcie_x1, 174 e1000_bus_width_pcie_x2, 175 e1000_bus_width_pcie_x4 = 4, 176 e1000_bus_width_pcie_x8 = 8, 177 e1000_bus_width_32, 178 e1000_bus_width_64, 179 e1000_bus_width_reserved 180 }; 181 182 enum e1000_1000t_rx_status { 183 e1000_1000t_rx_status_not_ok = 0, 184 e1000_1000t_rx_status_ok, 185 e1000_1000t_rx_status_undefined = 0xFF 186 }; 187 188 enum e1000_rev_polarity { 189 e1000_rev_polarity_normal = 0, 190 e1000_rev_polarity_reversed, 191 e1000_rev_polarity_undefined = 0xFF 192 }; 193 194 enum e1000_fc_mode { 195 e1000_fc_none = 0, 196 e1000_fc_rx_pause, 197 e1000_fc_tx_pause, 198 e1000_fc_full, 199 e1000_fc_default = 0xFF 200 }; 201 202 enum e1000_ms_type { 203 e1000_ms_hw_default = 0, 204 e1000_ms_force_master, 205 e1000_ms_force_slave, 206 e1000_ms_auto 207 }; 208 209 enum e1000_smart_speed { 210 e1000_smart_speed_default = 0, 211 e1000_smart_speed_on, 212 e1000_smart_speed_off 213 }; 214 215 enum e1000_serdes_link_state { 216 e1000_serdes_link_down = 0, 217 e1000_serdes_link_autoneg_progress, 218 e1000_serdes_link_autoneg_complete, 219 e1000_serdes_link_forced_up 220 }; 221 222 /* Receive Descriptor - Extended */ 223 union e1000_rx_desc_extended { 224 struct { 225 __le64 buffer_addr; 226 __le64 reserved; 227 } read; 228 struct { 229 struct { 230 __le32 mrq; /* Multiple Rx Queues */ 231 union { 232 __le32 rss; /* RSS Hash */ 233 struct { 234 __le16 ip_id; /* IP id */ 235 __le16 csum; /* Packet Checksum */ 236 } csum_ip; 237 } hi_dword; 238 } lower; 239 struct { 240 __le32 status_error; /* ext status/error */ 241 __le16 length; 242 __le16 vlan; /* VLAN tag */ 243 } upper; 244 } wb; /* writeback */ 245 }; 246 247 #define MAX_PS_BUFFERS 4 248 249 /* Number of packet split data buffers (not including the header buffer) */ 250 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 251 252 /* Receive Descriptor - Packet Split */ 253 union e1000_rx_desc_packet_split { 254 struct { 255 /* one buffer for protocol header(s), three data buffers */ 256 __le64 buffer_addr[MAX_PS_BUFFERS]; 257 } read; 258 struct { 259 struct { 260 __le32 mrq; /* Multiple Rx Queues */ 261 union { 262 __le32 rss; /* RSS Hash */ 263 struct { 264 __le16 ip_id; /* IP id */ 265 __le16 csum; /* Packet Checksum */ 266 } csum_ip; 267 } hi_dword; 268 } lower; 269 struct { 270 __le32 status_error; /* ext status/error */ 271 __le16 length0; /* length of buffer 0 */ 272 __le16 vlan; /* VLAN tag */ 273 } middle; 274 struct { 275 __le16 header_status; 276 /* length of buffers 1-3 */ 277 __le16 length[PS_PAGE_BUFFERS]; 278 } upper; 279 __le64 reserved; 280 } wb; /* writeback */ 281 }; 282 283 /* Transmit Descriptor */ 284 struct e1000_tx_desc { 285 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 286 union { 287 __le32 data; 288 struct { 289 __le16 length; /* Data buffer length */ 290 u8 cso; /* Checksum offset */ 291 u8 cmd; /* Descriptor control */ 292 } flags; 293 } lower; 294 union { 295 __le32 data; 296 struct { 297 u8 status; /* Descriptor status */ 298 u8 css; /* Checksum start */ 299 __le16 special; 300 } fields; 301 } upper; 302 }; 303 304 /* Offload Context Descriptor */ 305 struct e1000_context_desc { 306 union { 307 __le32 ip_config; 308 struct { 309 u8 ipcss; /* IP checksum start */ 310 u8 ipcso; /* IP checksum offset */ 311 __le16 ipcse; /* IP checksum end */ 312 } ip_fields; 313 } lower_setup; 314 union { 315 __le32 tcp_config; 316 struct { 317 u8 tucss; /* TCP checksum start */ 318 u8 tucso; /* TCP checksum offset */ 319 __le16 tucse; /* TCP checksum end */ 320 } tcp_fields; 321 } upper_setup; 322 __le32 cmd_and_length; 323 union { 324 __le32 data; 325 struct { 326 u8 status; /* Descriptor status */ 327 u8 hdr_len; /* Header length */ 328 __le16 mss; /* Maximum segment size */ 329 } fields; 330 } tcp_seg_setup; 331 }; 332 333 /* Offload data descriptor */ 334 struct e1000_data_desc { 335 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 336 union { 337 __le32 data; 338 struct { 339 __le16 length; /* Data buffer length */ 340 u8 typ_len_ext; 341 u8 cmd; 342 } flags; 343 } lower; 344 union { 345 __le32 data; 346 struct { 347 u8 status; /* Descriptor status */ 348 u8 popts; /* Packet Options */ 349 __le16 special; 350 } fields; 351 } upper; 352 }; 353 354 /* Statistics counters collected by the MAC */ 355 struct e1000_hw_stats { 356 u64 crcerrs; 357 u64 algnerrc; 358 u64 symerrs; 359 u64 rxerrc; 360 u64 mpc; 361 u64 scc; 362 u64 ecol; 363 u64 mcc; 364 u64 latecol; 365 u64 colc; 366 u64 dc; 367 u64 tncrs; 368 u64 sec; 369 u64 cexterr; 370 u64 rlec; 371 u64 xonrxc; 372 u64 xontxc; 373 u64 xoffrxc; 374 u64 xofftxc; 375 u64 fcruc; 376 u64 prc64; 377 u64 prc127; 378 u64 prc255; 379 u64 prc511; 380 u64 prc1023; 381 u64 prc1522; 382 u64 gprc; 383 u64 bprc; 384 u64 mprc; 385 u64 gptc; 386 u64 gorc; 387 u64 gotc; 388 u64 rnbc; 389 u64 ruc; 390 u64 rfc; 391 u64 roc; 392 u64 rjc; 393 u64 mgprc; 394 u64 mgpdc; 395 u64 mgptc; 396 u64 tor; 397 u64 tot; 398 u64 tpr; 399 u64 tpt; 400 u64 ptc64; 401 u64 ptc127; 402 u64 ptc255; 403 u64 ptc511; 404 u64 ptc1023; 405 u64 ptc1522; 406 u64 mptc; 407 u64 bptc; 408 u64 tsctc; 409 u64 tsctfc; 410 u64 iac; 411 u64 icrxptc; 412 u64 icrxatc; 413 u64 ictxptc; 414 u64 ictxatc; 415 u64 ictxqec; 416 u64 ictxqmtc; 417 u64 icrxdmtc; 418 u64 icrxoc; 419 }; 420 421 struct e1000_phy_stats { 422 u32 idle_errors; 423 u32 receive_errors; 424 }; 425 426 struct e1000_host_mng_dhcp_cookie { 427 u32 signature; 428 u8 status; 429 u8 reserved0; 430 u16 vlan_id; 431 u32 reserved1; 432 u16 reserved2; 433 u8 reserved3; 434 u8 checksum; 435 }; 436 437 /* Host Interface "Rev 1" */ 438 struct e1000_host_command_header { 439 u8 command_id; 440 u8 command_length; 441 u8 command_options; 442 u8 checksum; 443 }; 444 445 #define E1000_HI_MAX_DATA_LENGTH 252 446 struct e1000_host_command_info { 447 struct e1000_host_command_header command_header; 448 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 449 }; 450 451 /* Host Interface "Rev 2" */ 452 struct e1000_host_mng_command_header { 453 u8 command_id; 454 u8 checksum; 455 u16 reserved1; 456 u16 reserved2; 457 u16 command_length; 458 }; 459 460 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 461 struct e1000_host_mng_command_info { 462 struct e1000_host_mng_command_header command_header; 463 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 464 }; 465 466 #include "mac.h" 467 #include "phy.h" 468 #include "nvm.h" 469 #include "manage.h" 470 471 /* Function pointers for the MAC. */ 472 struct e1000_mac_operations { 473 s32 (*id_led_init)(struct e1000_hw *); 474 s32 (*blink_led)(struct e1000_hw *); 475 bool (*check_mng_mode)(struct e1000_hw *); 476 s32 (*check_for_link)(struct e1000_hw *); 477 s32 (*cleanup_led)(struct e1000_hw *); 478 void (*clear_hw_cntrs)(struct e1000_hw *); 479 void (*clear_vfta)(struct e1000_hw *); 480 s32 (*get_bus_info)(struct e1000_hw *); 481 void (*set_lan_id)(struct e1000_hw *); 482 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 483 s32 (*led_on)(struct e1000_hw *); 484 s32 (*led_off)(struct e1000_hw *); 485 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 486 s32 (*reset_hw)(struct e1000_hw *); 487 s32 (*init_hw)(struct e1000_hw *); 488 s32 (*setup_link)(struct e1000_hw *); 489 s32 (*setup_physical_interface)(struct e1000_hw *); 490 s32 (*setup_led)(struct e1000_hw *); 491 void (*write_vfta)(struct e1000_hw *, u32, u32); 492 void (*config_collision_dist)(struct e1000_hw *); 493 int (*rar_set)(struct e1000_hw *, u8 *, u32); 494 s32 (*read_mac_addr)(struct e1000_hw *); 495 u32 (*rar_get_count)(struct e1000_hw *); 496 }; 497 498 /* When to use various PHY register access functions: 499 * 500 * Func Caller 501 * Function Does Does When to use 502 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 503 * X_reg L,P,A n/a for simple PHY reg accesses 504 * X_reg_locked P,A L for multiple accesses of different regs 505 * on different pages 506 * X_reg_page A L,P for multiple accesses of different regs 507 * on the same page 508 * 509 * Where X=[read|write], L=locking, P=sets page, A=register access 510 * 511 */ 512 struct e1000_phy_operations { 513 s32 (*acquire)(struct e1000_hw *); 514 s32 (*cfg_on_link_up)(struct e1000_hw *); 515 s32 (*check_polarity)(struct e1000_hw *); 516 s32 (*check_reset_block)(struct e1000_hw *); 517 s32 (*commit)(struct e1000_hw *); 518 s32 (*force_speed_duplex)(struct e1000_hw *); 519 s32 (*get_cfg_done)(struct e1000_hw *hw); 520 s32 (*get_cable_length)(struct e1000_hw *); 521 s32 (*get_info)(struct e1000_hw *); 522 s32 (*set_page)(struct e1000_hw *, u16); 523 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 524 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 525 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 526 void (*release)(struct e1000_hw *); 527 s32 (*reset)(struct e1000_hw *); 528 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 529 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 530 s32 (*write_reg)(struct e1000_hw *, u32, u16); 531 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 532 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 533 void (*power_up)(struct e1000_hw *); 534 void (*power_down)(struct e1000_hw *); 535 }; 536 537 /* Function pointers for the NVM. */ 538 struct e1000_nvm_operations { 539 s32 (*acquire)(struct e1000_hw *); 540 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 541 void (*release)(struct e1000_hw *); 542 void (*reload)(struct e1000_hw *); 543 s32 (*update)(struct e1000_hw *); 544 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 545 s32 (*validate)(struct e1000_hw *); 546 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 547 }; 548 549 struct e1000_mac_info { 550 struct e1000_mac_operations ops; 551 u8 addr[ETH_ALEN]; 552 u8 perm_addr[ETH_ALEN]; 553 554 enum e1000_mac_type type; 555 556 u32 collision_delta; 557 u32 ledctl_default; 558 u32 ledctl_mode1; 559 u32 ledctl_mode2; 560 u32 mc_filter_type; 561 u32 tx_packet_delta; 562 u32 txcw; 563 564 u16 current_ifs_val; 565 u16 ifs_max_val; 566 u16 ifs_min_val; 567 u16 ifs_ratio; 568 u16 ifs_step_size; 569 u16 mta_reg_count; 570 571 /* Maximum size of the MTA register table in all supported adapters */ 572 #define MAX_MTA_REG 128 573 u32 mta_shadow[MAX_MTA_REG]; 574 u16 rar_entry_count; 575 576 u8 forced_speed_duplex; 577 578 bool adaptive_ifs; 579 bool has_fwsm; 580 bool arc_subsystem_valid; 581 bool autoneg; 582 bool autoneg_failed; 583 bool get_link_status; 584 bool in_ifs_mode; 585 bool serdes_has_link; 586 bool tx_pkt_filtering; 587 enum e1000_serdes_link_state serdes_link_state; 588 }; 589 590 struct e1000_phy_info { 591 struct e1000_phy_operations ops; 592 593 enum e1000_phy_type type; 594 595 enum e1000_1000t_rx_status local_rx; 596 enum e1000_1000t_rx_status remote_rx; 597 enum e1000_ms_type ms_type; 598 enum e1000_ms_type original_ms_type; 599 enum e1000_rev_polarity cable_polarity; 600 enum e1000_smart_speed smart_speed; 601 602 u32 addr; 603 u32 id; 604 u32 reset_delay_us; /* in usec */ 605 u32 revision; 606 607 enum e1000_media_type media_type; 608 609 u16 autoneg_advertised; 610 u16 autoneg_mask; 611 u16 cable_length; 612 u16 max_cable_length; 613 u16 min_cable_length; 614 615 u8 mdix; 616 617 bool disable_polarity_correction; 618 bool is_mdix; 619 bool polarity_correction; 620 bool speed_downgraded; 621 bool autoneg_wait_to_complete; 622 }; 623 624 struct e1000_nvm_info { 625 struct e1000_nvm_operations ops; 626 627 enum e1000_nvm_type type; 628 enum e1000_nvm_override override; 629 630 u32 flash_bank_size; 631 u32 flash_base_addr; 632 633 u16 word_size; 634 u16 delay_usec; 635 u16 address_bits; 636 u16 opcode_bits; 637 u16 page_size; 638 }; 639 640 struct e1000_bus_info { 641 enum e1000_bus_width width; 642 643 u16 func; 644 }; 645 646 struct e1000_fc_info { 647 u32 high_water; /* Flow control high-water mark */ 648 u32 low_water; /* Flow control low-water mark */ 649 u16 pause_time; /* Flow control pause timer */ 650 u16 refresh_time; /* Flow control refresh timer */ 651 bool send_xon; /* Flow control send XON */ 652 bool strict_ieee; /* Strict IEEE mode */ 653 enum e1000_fc_mode current_mode; /* FC mode in effect */ 654 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 655 }; 656 657 struct e1000_dev_spec_82571 { 658 bool laa_is_present; 659 u32 smb_counter; 660 }; 661 662 struct e1000_dev_spec_80003es2lan { 663 bool mdic_wa_enable; 664 }; 665 666 struct e1000_shadow_ram { 667 u16 value; 668 bool modified; 669 }; 670 671 #define E1000_ICH8_SHADOW_RAM_WORDS 2048 672 673 /* I218 PHY Ultra Low Power (ULP) states */ 674 enum e1000_ulp_state { 675 e1000_ulp_state_unknown, 676 e1000_ulp_state_off, 677 e1000_ulp_state_on, 678 }; 679 680 struct e1000_dev_spec_ich8lan { 681 bool kmrn_lock_loss_workaround_enabled; 682 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 683 bool nvm_k1_enabled; 684 bool eee_disable; 685 u16 eee_lp_ability; 686 enum e1000_ulp_state ulp_state; 687 }; 688 689 struct e1000_hw { 690 struct e1000_adapter *adapter; 691 692 void __iomem *hw_addr; 693 void __iomem *flash_address; 694 695 struct e1000_mac_info mac; 696 struct e1000_fc_info fc; 697 struct e1000_phy_info phy; 698 struct e1000_nvm_info nvm; 699 struct e1000_bus_info bus; 700 struct e1000_host_mng_dhcp_cookie mng_cookie; 701 702 union { 703 struct e1000_dev_spec_82571 e82571; 704 struct e1000_dev_spec_80003es2lan e80003es2lan; 705 struct e1000_dev_spec_ich8lan ich8lan; 706 } dev_spec; 707 }; 708 709 #include "82571.h" 710 #include "80003es2lan.h" 711 #include "ich8lan.h" 712 713 #endif 714