1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* Linux PRO/1000 Ethernet Driver main header file */ 30 31 #ifndef _E1000_H_ 32 #define _E1000_H_ 33 34 #include <linux/bitops.h> 35 #include <linux/types.h> 36 #include <linux/timer.h> 37 #include <linux/workqueue.h> 38 #include <linux/io.h> 39 #include <linux/netdevice.h> 40 #include <linux/pci.h> 41 #include <linux/pci-aspm.h> 42 #include <linux/crc32.h> 43 #include <linux/if_vlan.h> 44 #include <linux/clocksource.h> 45 #include <linux/net_tstamp.h> 46 #include <linux/ptp_clock_kernel.h> 47 #include <linux/ptp_classify.h> 48 #include <linux/mii.h> 49 #include <linux/mdio.h> 50 #include "hw.h" 51 52 struct e1000_info; 53 54 #define e_dbg(format, arg...) \ 55 netdev_dbg(hw->adapter->netdev, format, ## arg) 56 #define e_err(format, arg...) \ 57 netdev_err(adapter->netdev, format, ## arg) 58 #define e_info(format, arg...) \ 59 netdev_info(adapter->netdev, format, ## arg) 60 #define e_warn(format, arg...) \ 61 netdev_warn(adapter->netdev, format, ## arg) 62 #define e_notice(format, arg...) \ 63 netdev_notice(adapter->netdev, format, ## arg) 64 65 /* Interrupt modes, as used by the IntMode parameter */ 66 #define E1000E_INT_MODE_LEGACY 0 67 #define E1000E_INT_MODE_MSI 1 68 #define E1000E_INT_MODE_MSIX 2 69 70 /* Tx/Rx descriptor defines */ 71 #define E1000_DEFAULT_TXD 256 72 #define E1000_MAX_TXD 4096 73 #define E1000_MIN_TXD 64 74 75 #define E1000_DEFAULT_RXD 256 76 #define E1000_MAX_RXD 4096 77 #define E1000_MIN_RXD 64 78 79 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 80 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 81 82 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 83 84 /* How many Tx Descriptors do we need to call netif_wake_queue ? */ 85 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 86 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 87 88 #define AUTO_ALL_MODES 0 89 #define E1000_EEPROM_APME 0x0400 90 91 #define E1000_MNG_VLAN_NONE (-1) 92 93 /* Number of packet split data buffers (not including the header buffer) */ 94 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 95 96 #define DEFAULT_JUMBO 9234 97 98 /* Time to wait before putting the device into D3 if there's no link (in ms). */ 99 #define LINK_TIMEOUT 100 100 101 /* Count for polling __E1000_RESET condition every 10-20msec. 102 * Experimentation has shown the reset can take approximately 210msec. 103 */ 104 #define E1000_CHECK_RESET_COUNT 25 105 106 #define DEFAULT_RDTR 0 107 #define DEFAULT_RADV 8 108 #define BURST_RDTR 0x20 109 #define BURST_RADV 0x20 110 111 /* in the case of WTHRESH, it appears at least the 82571/2 hardware 112 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 113 * WTHRESH=4, so a setting of 5 gives the most efficient bus 114 * utilization but to avoid possible Tx stalls, set it to 1 115 */ 116 #define E1000_TXDCTL_DMA_BURST_ENABLE \ 117 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 118 E1000_TXDCTL_COUNT_DESC | \ 119 (1 << 16) | /* wthresh must be +1 more than desired */\ 120 (1 << 8) | /* hthresh */ \ 121 0x1f) /* pthresh */ 122 123 #define E1000_RXDCTL_DMA_BURST_ENABLE \ 124 (0x01000000 | /* set descriptor granularity */ \ 125 (4 << 16) | /* set writeback threshold */ \ 126 (4 << 8) | /* set prefetch threshold */ \ 127 0x20) /* set hthresh */ 128 129 #define E1000_TIDV_FPD (1 << 31) 130 #define E1000_RDTR_FPD (1 << 31) 131 132 enum e1000_boards { 133 board_82571, 134 board_82572, 135 board_82573, 136 board_82574, 137 board_82583, 138 board_80003es2lan, 139 board_ich8lan, 140 board_ich9lan, 141 board_ich10lan, 142 board_pchlan, 143 board_pch2lan, 144 board_pch_lpt, 145 }; 146 147 struct e1000_ps_page { 148 struct page *page; 149 u64 dma; /* must be u64 - written to hw */ 150 }; 151 152 /* wrappers around a pointer to a socket buffer, 153 * so a DMA handle can be stored along with the buffer 154 */ 155 struct e1000_buffer { 156 dma_addr_t dma; 157 struct sk_buff *skb; 158 union { 159 /* Tx */ 160 struct { 161 unsigned long time_stamp; 162 u16 length; 163 u16 next_to_watch; 164 unsigned int segs; 165 unsigned int bytecount; 166 u16 mapped_as_page; 167 }; 168 /* Rx */ 169 struct { 170 /* arrays of page information for packet split */ 171 struct e1000_ps_page *ps_pages; 172 struct page *page; 173 }; 174 }; 175 }; 176 177 struct e1000_ring { 178 struct e1000_adapter *adapter; /* back pointer to adapter */ 179 void *desc; /* pointer to ring memory */ 180 dma_addr_t dma; /* phys address of ring */ 181 unsigned int size; /* length of ring in bytes */ 182 unsigned int count; /* number of desc. in ring */ 183 184 u16 next_to_use; 185 u16 next_to_clean; 186 187 void __iomem *head; 188 void __iomem *tail; 189 190 /* array of buffer information structs */ 191 struct e1000_buffer *buffer_info; 192 193 char name[IFNAMSIZ + 5]; 194 u32 ims_val; 195 u32 itr_val; 196 void __iomem *itr_register; 197 int set_itr; 198 199 struct sk_buff *rx_skb_top; 200 }; 201 202 /* PHY register snapshot values */ 203 struct e1000_phy_regs { 204 u16 bmcr; /* basic mode control register */ 205 u16 bmsr; /* basic mode status register */ 206 u16 advertise; /* auto-negotiation advertisement */ 207 u16 lpa; /* link partner ability register */ 208 u16 expansion; /* auto-negotiation expansion reg */ 209 u16 ctrl1000; /* 1000BASE-T control register */ 210 u16 stat1000; /* 1000BASE-T status register */ 211 u16 estatus; /* extended status register */ 212 }; 213 214 /* board specific private data structure */ 215 struct e1000_adapter { 216 struct timer_list watchdog_timer; 217 struct timer_list phy_info_timer; 218 struct timer_list blink_timer; 219 220 struct work_struct reset_task; 221 struct work_struct watchdog_task; 222 223 const struct e1000_info *ei; 224 225 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 226 u32 bd_number; 227 u32 rx_buffer_len; 228 u16 mng_vlan_id; 229 u16 link_speed; 230 u16 link_duplex; 231 u16 eeprom_vers; 232 233 /* track device up/down/testing state */ 234 unsigned long state; 235 236 /* Interrupt Throttle Rate */ 237 u32 itr; 238 u32 itr_setting; 239 u16 tx_itr; 240 u16 rx_itr; 241 242 /* Tx - one ring per active queue */ 243 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; 244 u32 tx_fifo_limit; 245 246 struct napi_struct napi; 247 248 unsigned int uncorr_errors; /* uncorrectable ECC errors */ 249 unsigned int corr_errors; /* correctable ECC errors */ 250 unsigned int restart_queue; 251 u32 txd_cmd; 252 253 bool detect_tx_hung; 254 bool tx_hang_recheck; 255 u8 tx_timeout_factor; 256 257 u32 tx_int_delay; 258 u32 tx_abs_int_delay; 259 260 unsigned int total_tx_bytes; 261 unsigned int total_tx_packets; 262 unsigned int total_rx_bytes; 263 unsigned int total_rx_packets; 264 265 /* Tx stats */ 266 u64 tpt_old; 267 u64 colc_old; 268 u32 gotc; 269 u64 gotc_old; 270 u32 tx_timeout_count; 271 u32 tx_fifo_head; 272 u32 tx_head_addr; 273 u32 tx_fifo_size; 274 u32 tx_dma_failed; 275 276 /* Rx */ 277 bool (*clean_rx) (struct e1000_ring *ring, int *work_done, 278 int work_to_do) ____cacheline_aligned_in_smp; 279 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count, 280 gfp_t gfp); 281 struct e1000_ring *rx_ring; 282 283 u32 rx_int_delay; 284 u32 rx_abs_int_delay; 285 286 /* Rx stats */ 287 u64 hw_csum_err; 288 u64 hw_csum_good; 289 u64 rx_hdr_split; 290 u32 gorc; 291 u64 gorc_old; 292 u32 alloc_rx_buff_failed; 293 u32 rx_dma_failed; 294 u32 rx_hwtstamp_cleared; 295 296 unsigned int rx_ps_pages; 297 u16 rx_ps_bsize0; 298 u32 max_frame_size; 299 u32 min_frame_size; 300 301 /* OS defined structs */ 302 struct net_device *netdev; 303 struct pci_dev *pdev; 304 305 /* structs defined in e1000_hw.h */ 306 struct e1000_hw hw; 307 308 spinlock_t stats64_lock; /* protects statistics counters */ 309 struct e1000_hw_stats stats; 310 struct e1000_phy_info phy_info; 311 struct e1000_phy_stats phy_stats; 312 313 /* Snapshot of PHY registers */ 314 struct e1000_phy_regs phy_regs; 315 316 struct e1000_ring test_tx_ring; 317 struct e1000_ring test_rx_ring; 318 u32 test_icr; 319 320 u32 msg_enable; 321 unsigned int num_vectors; 322 struct msix_entry *msix_entries; 323 int int_mode; 324 u32 eiac_mask; 325 326 u32 eeprom_wol; 327 u32 wol; 328 u32 pba; 329 u32 max_hw_frame_size; 330 331 bool fc_autoneg; 332 333 unsigned int flags; 334 unsigned int flags2; 335 struct work_struct downshift_task; 336 struct work_struct update_phy_task; 337 struct work_struct print_hang_task; 338 339 bool idle_check; 340 int phy_hang_count; 341 342 u16 tx_ring_count; 343 u16 rx_ring_count; 344 345 struct hwtstamp_config hwtstamp_config; 346 struct delayed_work systim_overflow_work; 347 struct sk_buff *tx_hwtstamp_skb; 348 struct work_struct tx_hwtstamp_work; 349 spinlock_t systim_lock; /* protects SYSTIML/H regsters */ 350 struct cyclecounter cc; 351 struct timecounter tc; 352 struct ptp_clock *ptp_clock; 353 struct ptp_clock_info ptp_clock_info; 354 355 u16 eee_advert; 356 }; 357 358 struct e1000_info { 359 enum e1000_mac_type mac; 360 unsigned int flags; 361 unsigned int flags2; 362 u32 pba; 363 u32 max_hw_frame_size; 364 s32 (*get_variants)(struct e1000_adapter *); 365 const struct e1000_mac_operations *mac_ops; 366 const struct e1000_phy_operations *phy_ops; 367 const struct e1000_nvm_operations *nvm_ops; 368 }; 369 370 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); 371 372 /* The system time is maintained by a 64-bit counter comprised of the 32-bit 373 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore 374 * its resolution) is based on the contents of the TIMINCA register - it 375 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). 376 * For the best accuracy, the incperiod should be as small as possible. The 377 * incvalue is scaled by a factor as large as possible (while still fitting 378 * in bits 23:0) so that relatively small clock corrections can be made. 379 * 380 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of 381 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) 382 * bits to count nanoseconds leaving the rest for fractional nonseconds. 383 */ 384 #define INCVALUE_96MHz 125 385 #define INCVALUE_SHIFT_96MHz 17 386 #define INCPERIOD_SHIFT_96MHz 2 387 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz) 388 389 #define INCVALUE_25MHz 40 390 #define INCVALUE_SHIFT_25MHz 18 391 #define INCPERIOD_25MHz 1 392 393 /* Another drawback of scaling the incvalue by a large factor is the 394 * 64-bit SYSTIM register overflows more quickly. This is dealt with 395 * by simply reading the clock before it overflows. 396 * 397 * Clock ns bits Overflows after 398 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ 399 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs 400 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours 401 */ 402 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) 403 404 /* hardware capability, feature, and workaround flags */ 405 #define FLAG_HAS_AMT (1 << 0) 406 #define FLAG_HAS_FLASH (1 << 1) 407 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2) 408 #define FLAG_HAS_WOL (1 << 3) 409 /* reserved bit4 */ 410 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) 411 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) 412 #define FLAG_HAS_JUMBO_FRAMES (1 << 7) 413 #define FLAG_READ_ONLY_NVM (1 << 8) 414 #define FLAG_IS_ICH (1 << 9) 415 #define FLAG_HAS_MSIX (1 << 10) 416 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) 417 #define FLAG_IS_QUAD_PORT_A (1 << 12) 418 #define FLAG_IS_QUAD_PORT (1 << 13) 419 #define FLAG_HAS_HW_TIMESTAMP (1 << 14) 420 #define FLAG_APME_IN_WUC (1 << 15) 421 #define FLAG_APME_IN_CTRL3 (1 << 16) 422 #define FLAG_APME_CHECK_PORT_B (1 << 17) 423 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) 424 #define FLAG_NO_WAKE_UCAST (1 << 19) 425 #define FLAG_MNG_PT_ENABLED (1 << 20) 426 #define FLAG_RESET_OVERWRITES_LAA (1 << 21) 427 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) 428 #define FLAG_TARC_SET_BIT_ZERO (1 << 23) 429 #define FLAG_RX_NEEDS_RESTART (1 << 24) 430 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) 431 #define FLAG_SMART_POWER_DOWN (1 << 26) 432 #define FLAG_MSI_ENABLED (1 << 27) 433 /* reserved (1 << 28) */ 434 #define FLAG_TSO_FORCE (1 << 29) 435 #define FLAG_RESTART_NOW (1 << 30) 436 #define FLAG_MSI_TEST_FAILED (1 << 31) 437 438 #define FLAG2_CRC_STRIPPING (1 << 0) 439 #define FLAG2_HAS_PHY_WAKEUP (1 << 1) 440 #define FLAG2_IS_DISCARDING (1 << 2) 441 #define FLAG2_DISABLE_ASPM_L1 (1 << 3) 442 #define FLAG2_HAS_PHY_STATS (1 << 4) 443 #define FLAG2_HAS_EEE (1 << 5) 444 #define FLAG2_DMA_BURST (1 << 6) 445 #define FLAG2_DISABLE_ASPM_L0S (1 << 7) 446 #define FLAG2_DISABLE_AIM (1 << 8) 447 #define FLAG2_CHECK_PHY_HANG (1 << 9) 448 #define FLAG2_NO_DISABLE_RX (1 << 10) 449 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) 450 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12) 451 #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13) 452 453 #define E1000_RX_DESC_PS(R, i) \ 454 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 455 #define E1000_RX_DESC_EXT(R, i) \ 456 (&(((union e1000_rx_desc_extended *)((R).desc))[i])) 457 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 458 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 459 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 460 461 enum e1000_state_t { 462 __E1000_TESTING, 463 __E1000_RESETTING, 464 __E1000_ACCESS_SHARED_RESOURCE, 465 __E1000_DOWN 466 }; 467 468 enum latency_range { 469 lowest_latency = 0, 470 low_latency = 1, 471 bulk_latency = 2, 472 latency_invalid = 255 473 }; 474 475 extern char e1000e_driver_name[]; 476 extern const char e1000e_driver_version[]; 477 478 extern void e1000e_check_options(struct e1000_adapter *adapter); 479 extern void e1000e_set_ethtool_ops(struct net_device *netdev); 480 481 extern int e1000e_up(struct e1000_adapter *adapter); 482 extern void e1000e_down(struct e1000_adapter *adapter); 483 extern void e1000e_reinit_locked(struct e1000_adapter *adapter); 484 extern void e1000e_reset(struct e1000_adapter *adapter); 485 extern void e1000e_power_up_phy(struct e1000_adapter *adapter); 486 extern int e1000e_setup_rx_resources(struct e1000_ring *ring); 487 extern int e1000e_setup_tx_resources(struct e1000_ring *ring); 488 extern void e1000e_free_rx_resources(struct e1000_ring *ring); 489 extern void e1000e_free_tx_resources(struct e1000_ring *ring); 490 extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 491 struct rtnl_link_stats64 492 *stats); 493 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 494 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 495 extern void e1000e_get_hw_control(struct e1000_adapter *adapter); 496 extern void e1000e_release_hw_control(struct e1000_adapter *adapter); 497 extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); 498 499 extern unsigned int copybreak; 500 501 extern const struct e1000_info e1000_82571_info; 502 extern const struct e1000_info e1000_82572_info; 503 extern const struct e1000_info e1000_82573_info; 504 extern const struct e1000_info e1000_82574_info; 505 extern const struct e1000_info e1000_82583_info; 506 extern const struct e1000_info e1000_ich8_info; 507 extern const struct e1000_info e1000_ich9_info; 508 extern const struct e1000_info e1000_ich10_info; 509 extern const struct e1000_info e1000_pch_info; 510 extern const struct e1000_info e1000_pch2_info; 511 extern const struct e1000_info e1000_pch_lpt_info; 512 extern const struct e1000_info e1000_es2_info; 513 514 extern void e1000e_ptp_init(struct e1000_adapter *adapter); 515 extern void e1000e_ptp_remove(struct e1000_adapter *adapter); 516 517 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 518 { 519 return hw->phy.ops.reset(hw); 520 } 521 522 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 523 { 524 return hw->phy.ops.read_reg(hw, offset, data); 525 } 526 527 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) 528 { 529 return hw->phy.ops.read_reg_locked(hw, offset, data); 530 } 531 532 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 533 { 534 return hw->phy.ops.write_reg(hw, offset, data); 535 } 536 537 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) 538 { 539 return hw->phy.ops.write_reg_locked(hw, offset, data); 540 } 541 542 extern void e1000e_reload_nvm_generic(struct e1000_hw *hw); 543 544 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 545 { 546 if (hw->mac.ops.read_mac_addr) 547 return hw->mac.ops.read_mac_addr(hw); 548 549 return e1000_read_mac_addr_generic(hw); 550 } 551 552 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 553 { 554 return hw->nvm.ops.validate(hw); 555 } 556 557 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 558 { 559 return hw->nvm.ops.update(hw); 560 } 561 562 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, 563 u16 *data) 564 { 565 return hw->nvm.ops.read(hw, offset, words, data); 566 } 567 568 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, 569 u16 *data) 570 { 571 return hw->nvm.ops.write(hw, offset, words, data); 572 } 573 574 static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 575 { 576 return hw->phy.ops.get_info(hw); 577 } 578 579 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 580 { 581 return readl(hw->hw_addr + reg); 582 } 583 584 #define er32(reg) __er32(hw, E1000_##reg) 585 586 /** 587 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 588 * @hw: pointer to the HW structure 589 * 590 * When updating the MAC CSR registers, the Manageability Engine (ME) could 591 * be accessing the registers at the same time. Normally, this is handled in 592 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 593 * accesses later than it should which could result in the register to have 594 * an incorrect value. Workaround this by checking the FWSM register which 595 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 596 * and try again a number of times. 597 **/ 598 static inline s32 __ew32_prepare(struct e1000_hw *hw) 599 { 600 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 601 602 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 603 udelay(50); 604 605 return i; 606 } 607 608 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 609 { 610 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 611 __ew32_prepare(hw); 612 613 writel(val, hw->hw_addr + reg); 614 } 615 616 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 617 618 #define e1e_flush() er32(STATUS) 619 620 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 621 (__ew32((a), (reg + ((offset) << 2)), (value))) 622 623 #define E1000_READ_REG_ARRAY(a, reg, offset) \ 624 (readl((a)->hw_addr + reg + ((offset) << 2))) 625 626 #endif /* _E1000_H_ */ 627