1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* Linux PRO/1000 Ethernet Driver main header file */ 30 31 #ifndef _E1000_H_ 32 #define _E1000_H_ 33 34 #include <linux/bitops.h> 35 #include <linux/types.h> 36 #include <linux/timer.h> 37 #include <linux/workqueue.h> 38 #include <linux/io.h> 39 #include <linux/netdevice.h> 40 #include <linux/pci.h> 41 #include <linux/pci-aspm.h> 42 #include <linux/crc32.h> 43 #include <linux/if_vlan.h> 44 #include <linux/clocksource.h> 45 #include <linux/net_tstamp.h> 46 #include <linux/ptp_clock_kernel.h> 47 #include <linux/ptp_classify.h> 48 #include "hw.h" 49 50 struct e1000_info; 51 52 #define e_dbg(format, arg...) \ 53 netdev_dbg(hw->adapter->netdev, format, ## arg) 54 #define e_err(format, arg...) \ 55 netdev_err(adapter->netdev, format, ## arg) 56 #define e_info(format, arg...) \ 57 netdev_info(adapter->netdev, format, ## arg) 58 #define e_warn(format, arg...) \ 59 netdev_warn(adapter->netdev, format, ## arg) 60 #define e_notice(format, arg...) \ 61 netdev_notice(adapter->netdev, format, ## arg) 62 63 64 /* Interrupt modes, as used by the IntMode parameter */ 65 #define E1000E_INT_MODE_LEGACY 0 66 #define E1000E_INT_MODE_MSI 1 67 #define E1000E_INT_MODE_MSIX 2 68 69 /* Tx/Rx descriptor defines */ 70 #define E1000_DEFAULT_TXD 256 71 #define E1000_MAX_TXD 4096 72 #define E1000_MIN_TXD 64 73 74 #define E1000_DEFAULT_RXD 256 75 #define E1000_MAX_RXD 4096 76 #define E1000_MIN_RXD 64 77 78 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 79 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 80 81 /* Early Receive defines */ 82 #define E1000_ERT_2048 0x100 83 84 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 85 86 /* How many Tx Descriptors do we need to call netif_wake_queue ? */ 87 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 88 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 89 90 #define AUTO_ALL_MODES 0 91 #define E1000_EEPROM_APME 0x0400 92 93 #define E1000_MNG_VLAN_NONE (-1) 94 95 /* Number of packet split data buffers (not including the header buffer) */ 96 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 97 98 #define DEFAULT_JUMBO 9234 99 100 /* BM/HV Specific Registers */ 101 #define BM_PORT_CTRL_PAGE 769 102 103 #define PHY_UPPER_SHIFT 21 104 #define BM_PHY_REG(page, reg) \ 105 (((reg) & MAX_PHY_REG_ADDRESS) |\ 106 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 107 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 108 109 /* PHY Wakeup Registers and defines */ 110 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 111 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 112 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 113 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 114 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 115 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 116 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 117 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 118 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 119 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 120 121 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 122 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 123 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 124 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 125 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 126 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 127 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 128 129 #define HV_STATS_PAGE 778 130 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */ 131 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 132 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */ 133 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 134 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */ 135 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 136 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */ 137 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 138 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */ 139 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 140 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 141 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 142 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */ 143 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 144 145 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 146 147 /* BM PHY Copper Specific Status */ 148 #define BM_CS_STATUS 17 149 #define BM_CS_STATUS_LINK_UP 0x0400 150 #define BM_CS_STATUS_RESOLVED 0x0800 151 #define BM_CS_STATUS_SPEED_MASK 0xC000 152 #define BM_CS_STATUS_SPEED_1000 0x8000 153 154 /* 82577 Mobile Phy Status Register */ 155 #define HV_M_STATUS 26 156 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 157 #define HV_M_STATUS_SPEED_MASK 0x0300 158 #define HV_M_STATUS_SPEED_1000 0x0200 159 #define HV_M_STATUS_LINK_UP 0x0040 160 161 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 162 #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 163 164 /* Time to wait before putting the device into D3 if there's no link (in ms). */ 165 #define LINK_TIMEOUT 100 166 167 /* Count for polling __E1000_RESET condition every 10-20msec. 168 * Experimentation has shown the reset can take approximately 210msec. 169 */ 170 #define E1000_CHECK_RESET_COUNT 25 171 172 #define DEFAULT_RDTR 0 173 #define DEFAULT_RADV 8 174 #define BURST_RDTR 0x20 175 #define BURST_RADV 0x20 176 177 /* in the case of WTHRESH, it appears at least the 82571/2 hardware 178 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 179 * WTHRESH=4, so a setting of 5 gives the most efficient bus 180 * utilization but to avoid possible Tx stalls, set it to 1 181 */ 182 #define E1000_TXDCTL_DMA_BURST_ENABLE \ 183 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 184 E1000_TXDCTL_COUNT_DESC | \ 185 (1 << 16) | /* wthresh must be +1 more than desired */\ 186 (1 << 8) | /* hthresh */ \ 187 0x1f) /* pthresh */ 188 189 #define E1000_RXDCTL_DMA_BURST_ENABLE \ 190 (0x01000000 | /* set descriptor granularity */ \ 191 (4 << 16) | /* set writeback threshold */ \ 192 (4 << 8) | /* set prefetch threshold */ \ 193 0x20) /* set hthresh */ 194 195 #define E1000_TIDV_FPD (1 << 31) 196 #define E1000_RDTR_FPD (1 << 31) 197 198 enum e1000_boards { 199 board_82571, 200 board_82572, 201 board_82573, 202 board_82574, 203 board_82583, 204 board_80003es2lan, 205 board_ich8lan, 206 board_ich9lan, 207 board_ich10lan, 208 board_pchlan, 209 board_pch2lan, 210 board_pch_lpt, 211 }; 212 213 struct e1000_ps_page { 214 struct page *page; 215 u64 dma; /* must be u64 - written to hw */ 216 }; 217 218 /* wrappers around a pointer to a socket buffer, 219 * so a DMA handle can be stored along with the buffer 220 */ 221 struct e1000_buffer { 222 dma_addr_t dma; 223 struct sk_buff *skb; 224 union { 225 /* Tx */ 226 struct { 227 unsigned long time_stamp; 228 u16 length; 229 u16 next_to_watch; 230 unsigned int segs; 231 unsigned int bytecount; 232 u16 mapped_as_page; 233 }; 234 /* Rx */ 235 struct { 236 /* arrays of page information for packet split */ 237 struct e1000_ps_page *ps_pages; 238 struct page *page; 239 }; 240 }; 241 }; 242 243 struct e1000_ring { 244 struct e1000_adapter *adapter; /* back pointer to adapter */ 245 void *desc; /* pointer to ring memory */ 246 dma_addr_t dma; /* phys address of ring */ 247 unsigned int size; /* length of ring in bytes */ 248 unsigned int count; /* number of desc. in ring */ 249 250 u16 next_to_use; 251 u16 next_to_clean; 252 253 void __iomem *head; 254 void __iomem *tail; 255 256 /* array of buffer information structs */ 257 struct e1000_buffer *buffer_info; 258 259 char name[IFNAMSIZ + 5]; 260 u32 ims_val; 261 u32 itr_val; 262 void __iomem *itr_register; 263 int set_itr; 264 265 struct sk_buff *rx_skb_top; 266 }; 267 268 /* PHY register snapshot values */ 269 struct e1000_phy_regs { 270 u16 bmcr; /* basic mode control register */ 271 u16 bmsr; /* basic mode status register */ 272 u16 advertise; /* auto-negotiation advertisement */ 273 u16 lpa; /* link partner ability register */ 274 u16 expansion; /* auto-negotiation expansion reg */ 275 u16 ctrl1000; /* 1000BASE-T control register */ 276 u16 stat1000; /* 1000BASE-T status register */ 277 u16 estatus; /* extended status register */ 278 }; 279 280 /* board specific private data structure */ 281 struct e1000_adapter { 282 struct timer_list watchdog_timer; 283 struct timer_list phy_info_timer; 284 struct timer_list blink_timer; 285 286 struct work_struct reset_task; 287 struct work_struct watchdog_task; 288 289 const struct e1000_info *ei; 290 291 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 292 u32 bd_number; 293 u32 rx_buffer_len; 294 u16 mng_vlan_id; 295 u16 link_speed; 296 u16 link_duplex; 297 u16 eeprom_vers; 298 299 /* track device up/down/testing state */ 300 unsigned long state; 301 302 /* Interrupt Throttle Rate */ 303 u32 itr; 304 u32 itr_setting; 305 u16 tx_itr; 306 u16 rx_itr; 307 308 /* Tx */ 309 struct e1000_ring *tx_ring /* One per active queue */ 310 ____cacheline_aligned_in_smp; 311 u32 tx_fifo_limit; 312 313 struct napi_struct napi; 314 315 unsigned int uncorr_errors; /* uncorrectable ECC errors */ 316 unsigned int corr_errors; /* correctable ECC errors */ 317 unsigned int restart_queue; 318 u32 txd_cmd; 319 320 bool detect_tx_hung; 321 bool tx_hang_recheck; 322 u8 tx_timeout_factor; 323 324 u32 tx_int_delay; 325 u32 tx_abs_int_delay; 326 327 unsigned int total_tx_bytes; 328 unsigned int total_tx_packets; 329 unsigned int total_rx_bytes; 330 unsigned int total_rx_packets; 331 332 /* Tx stats */ 333 u64 tpt_old; 334 u64 colc_old; 335 u32 gotc; 336 u64 gotc_old; 337 u32 tx_timeout_count; 338 u32 tx_fifo_head; 339 u32 tx_head_addr; 340 u32 tx_fifo_size; 341 u32 tx_dma_failed; 342 343 /* Rx */ 344 bool (*clean_rx) (struct e1000_ring *ring, int *work_done, 345 int work_to_do) ____cacheline_aligned_in_smp; 346 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count, 347 gfp_t gfp); 348 struct e1000_ring *rx_ring; 349 350 u32 rx_int_delay; 351 u32 rx_abs_int_delay; 352 353 /* Rx stats */ 354 u64 hw_csum_err; 355 u64 hw_csum_good; 356 u64 rx_hdr_split; 357 u32 gorc; 358 u64 gorc_old; 359 u32 alloc_rx_buff_failed; 360 u32 rx_dma_failed; 361 u32 rx_hwtstamp_cleared; 362 363 unsigned int rx_ps_pages; 364 u16 rx_ps_bsize0; 365 u32 max_frame_size; 366 u32 min_frame_size; 367 368 /* OS defined structs */ 369 struct net_device *netdev; 370 struct pci_dev *pdev; 371 372 /* structs defined in e1000_hw.h */ 373 struct e1000_hw hw; 374 375 spinlock_t stats64_lock; 376 struct e1000_hw_stats stats; 377 struct e1000_phy_info phy_info; 378 struct e1000_phy_stats phy_stats; 379 380 /* Snapshot of PHY registers */ 381 struct e1000_phy_regs phy_regs; 382 383 struct e1000_ring test_tx_ring; 384 struct e1000_ring test_rx_ring; 385 u32 test_icr; 386 387 u32 msg_enable; 388 unsigned int num_vectors; 389 struct msix_entry *msix_entries; 390 int int_mode; 391 u32 eiac_mask; 392 393 u32 eeprom_wol; 394 u32 wol; 395 u32 pba; 396 u32 max_hw_frame_size; 397 398 bool fc_autoneg; 399 400 unsigned int flags; 401 unsigned int flags2; 402 struct work_struct downshift_task; 403 struct work_struct update_phy_task; 404 struct work_struct print_hang_task; 405 406 bool idle_check; 407 int phy_hang_count; 408 409 u16 tx_ring_count; 410 u16 rx_ring_count; 411 412 struct hwtstamp_config hwtstamp_config; 413 struct delayed_work systim_overflow_work; 414 struct sk_buff *tx_hwtstamp_skb; 415 struct work_struct tx_hwtstamp_work; 416 spinlock_t systim_lock; /* protects SYSTIML/H regsters */ 417 struct cyclecounter cc; 418 struct timecounter tc; 419 struct ptp_clock *ptp_clock; 420 struct ptp_clock_info ptp_clock_info; 421 }; 422 423 struct e1000_info { 424 enum e1000_mac_type mac; 425 unsigned int flags; 426 unsigned int flags2; 427 u32 pba; 428 u32 max_hw_frame_size; 429 s32 (*get_variants)(struct e1000_adapter *); 430 const struct e1000_mac_operations *mac_ops; 431 const struct e1000_phy_operations *phy_ops; 432 const struct e1000_nvm_operations *nvm_ops; 433 }; 434 435 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); 436 437 /* The system time is maintained by a 64-bit counter comprised of the 32-bit 438 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore 439 * its resolution) is based on the contents of the TIMINCA register - it 440 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). 441 * For the best accuracy, the incperiod should be as small as possible. The 442 * incvalue is scaled by a factor as large as possible (while still fitting 443 * in bits 23:0) so that relatively small clock corrections can be made. 444 * 445 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of 446 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) 447 * bits to count nanoseconds leaving the rest for fractional nonseconds. 448 */ 449 #define INCVALUE_96MHz 125 450 #define INCVALUE_SHIFT_96MHz 17 451 #define INCPERIOD_SHIFT_96MHz 2 452 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz) 453 454 #define INCVALUE_25MHz 40 455 #define INCVALUE_SHIFT_25MHz 18 456 #define INCPERIOD_25MHz 1 457 458 /* Another drawback of scaling the incvalue by a large factor is the 459 * 64-bit SYSTIM register overflows more quickly. This is dealt with 460 * by simply reading the clock before it overflows. 461 * 462 * Clock ns bits Overflows after 463 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ 464 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs 465 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours 466 */ 467 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) 468 469 /* hardware capability, feature, and workaround flags */ 470 #define FLAG_HAS_AMT (1 << 0) 471 #define FLAG_HAS_FLASH (1 << 1) 472 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2) 473 #define FLAG_HAS_WOL (1 << 3) 474 /* reserved bit4 */ 475 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) 476 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) 477 #define FLAG_HAS_JUMBO_FRAMES (1 << 7) 478 #define FLAG_READ_ONLY_NVM (1 << 8) 479 #define FLAG_IS_ICH (1 << 9) 480 #define FLAG_HAS_MSIX (1 << 10) 481 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) 482 #define FLAG_IS_QUAD_PORT_A (1 << 12) 483 #define FLAG_IS_QUAD_PORT (1 << 13) 484 #define FLAG_HAS_HW_TIMESTAMP (1 << 14) 485 #define FLAG_APME_IN_WUC (1 << 15) 486 #define FLAG_APME_IN_CTRL3 (1 << 16) 487 #define FLAG_APME_CHECK_PORT_B (1 << 17) 488 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) 489 #define FLAG_NO_WAKE_UCAST (1 << 19) 490 #define FLAG_MNG_PT_ENABLED (1 << 20) 491 #define FLAG_RESET_OVERWRITES_LAA (1 << 21) 492 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) 493 #define FLAG_TARC_SET_BIT_ZERO (1 << 23) 494 #define FLAG_RX_NEEDS_RESTART (1 << 24) 495 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) 496 #define FLAG_SMART_POWER_DOWN (1 << 26) 497 #define FLAG_MSI_ENABLED (1 << 27) 498 /* reserved (1 << 28) */ 499 #define FLAG_TSO_FORCE (1 << 29) 500 #define FLAG_RESTART_NOW (1 << 30) 501 #define FLAG_MSI_TEST_FAILED (1 << 31) 502 503 #define FLAG2_CRC_STRIPPING (1 << 0) 504 #define FLAG2_HAS_PHY_WAKEUP (1 << 1) 505 #define FLAG2_IS_DISCARDING (1 << 2) 506 #define FLAG2_DISABLE_ASPM_L1 (1 << 3) 507 #define FLAG2_HAS_PHY_STATS (1 << 4) 508 #define FLAG2_HAS_EEE (1 << 5) 509 #define FLAG2_DMA_BURST (1 << 6) 510 #define FLAG2_DISABLE_ASPM_L0S (1 << 7) 511 #define FLAG2_DISABLE_AIM (1 << 8) 512 #define FLAG2_CHECK_PHY_HANG (1 << 9) 513 #define FLAG2_NO_DISABLE_RX (1 << 10) 514 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) 515 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12) 516 #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13) 517 518 #define E1000_RX_DESC_PS(R, i) \ 519 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 520 #define E1000_RX_DESC_EXT(R, i) \ 521 (&(((union e1000_rx_desc_extended *)((R).desc))[i])) 522 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 523 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 524 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 525 526 enum e1000_state_t { 527 __E1000_TESTING, 528 __E1000_RESETTING, 529 __E1000_ACCESS_SHARED_RESOURCE, 530 __E1000_DOWN 531 }; 532 533 enum latency_range { 534 lowest_latency = 0, 535 low_latency = 1, 536 bulk_latency = 2, 537 latency_invalid = 255 538 }; 539 540 extern char e1000e_driver_name[]; 541 extern const char e1000e_driver_version[]; 542 543 extern void e1000e_check_options(struct e1000_adapter *adapter); 544 extern void e1000e_set_ethtool_ops(struct net_device *netdev); 545 546 extern int e1000e_up(struct e1000_adapter *adapter); 547 extern void e1000e_down(struct e1000_adapter *adapter); 548 extern void e1000e_reinit_locked(struct e1000_adapter *adapter); 549 extern void e1000e_reset(struct e1000_adapter *adapter); 550 extern void e1000e_power_up_phy(struct e1000_adapter *adapter); 551 extern int e1000e_setup_rx_resources(struct e1000_ring *ring); 552 extern int e1000e_setup_tx_resources(struct e1000_ring *ring); 553 extern void e1000e_free_rx_resources(struct e1000_ring *ring); 554 extern void e1000e_free_tx_resources(struct e1000_ring *ring); 555 extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 556 struct rtnl_link_stats64 557 *stats); 558 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 559 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 560 extern void e1000e_get_hw_control(struct e1000_adapter *adapter); 561 extern void e1000e_release_hw_control(struct e1000_adapter *adapter); 562 extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); 563 564 extern unsigned int copybreak; 565 566 extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw); 567 568 extern const struct e1000_info e1000_82571_info; 569 extern const struct e1000_info e1000_82572_info; 570 extern const struct e1000_info e1000_82573_info; 571 extern const struct e1000_info e1000_82574_info; 572 extern const struct e1000_info e1000_82583_info; 573 extern const struct e1000_info e1000_ich8_info; 574 extern const struct e1000_info e1000_ich9_info; 575 extern const struct e1000_info e1000_ich10_info; 576 extern const struct e1000_info e1000_pch_info; 577 extern const struct e1000_info e1000_pch2_info; 578 extern const struct e1000_info e1000_pch_lpt_info; 579 extern const struct e1000_info e1000_es2_info; 580 581 extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 582 u32 pba_num_size); 583 584 extern s32 e1000e_commit_phy(struct e1000_hw *hw); 585 586 extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 587 588 extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw); 589 extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); 590 591 extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); 592 extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 593 bool state); 594 extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 595 extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 596 extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 597 extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 598 extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 599 extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 600 extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 601 602 extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw); 603 extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); 604 extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); 605 extern s32 e1000e_setup_led_generic(struct e1000_hw *hw); 606 extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); 607 extern s32 e1000e_led_on_generic(struct e1000_hw *hw); 608 extern s32 e1000e_led_off_generic(struct e1000_hw *hw); 609 extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); 610 extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 611 extern void e1000_set_lan_id_single_port(struct e1000_hw *hw); 612 extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex); 613 extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex); 614 extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw); 615 extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); 616 extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw); 617 extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); 618 extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); 619 extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); 620 extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); 621 extern s32 e1000e_setup_link_generic(struct e1000_hw *hw); 622 extern void e1000_clear_vfta_generic(struct e1000_hw *hw); 623 extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); 624 extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 625 u8 *mc_addr_list, 626 u32 mc_addr_count); 627 extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 628 extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); 629 extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); 630 extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); 631 extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); 632 extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw); 633 extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); 634 extern s32 e1000e_force_mac_fc(struct e1000_hw *hw); 635 extern s32 e1000e_blink_led_generic(struct e1000_hw *hw); 636 extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); 637 extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); 638 extern void e1000e_reset_adaptive(struct e1000_hw *hw); 639 extern void e1000e_update_adaptive(struct e1000_hw *hw); 640 641 extern s32 e1000e_setup_copper_link(struct e1000_hw *hw); 642 extern s32 e1000e_get_phy_id(struct e1000_hw *hw); 643 extern void e1000e_put_hw_semaphore(struct e1000_hw *hw); 644 extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); 645 extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); 646 extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); 647 extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); 648 extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 649 extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 650 extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, 651 u16 *data); 652 extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); 653 extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); 654 extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 655 extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, 656 u16 data); 657 extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw); 658 extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); 659 extern s32 e1000e_get_cfg_done(struct e1000_hw *hw); 660 extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); 661 extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); 662 extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 663 extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 664 extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); 665 extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); 666 extern s32 e1000e_determine_phy_address(struct e1000_hw *hw); 667 extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 668 extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 669 extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, 670 u16 *phy_reg); 671 extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, 672 u16 *phy_reg); 673 extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 674 extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 675 extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 676 extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); 677 extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, 678 u16 data); 679 extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); 680 extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, 681 u16 *data); 682 extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 683 u32 usec_interval, bool *success); 684 extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); 685 extern void e1000_power_up_phy_copper(struct e1000_hw *hw); 686 extern void e1000_power_down_phy_copper(struct e1000_hw *hw); 687 extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 688 extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 689 extern s32 e1000e_check_downshift(struct e1000_hw *hw); 690 extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 691 extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, 692 u16 *data); 693 extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, 694 u16 *data); 695 extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 696 extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, 697 u16 data); 698 extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, 699 u16 data); 700 extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 701 extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 702 extern s32 e1000_check_polarity_82577(struct e1000_hw *hw); 703 extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 704 extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 705 extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 706 707 extern s32 e1000_check_polarity_m88(struct e1000_hw *hw); 708 extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 709 extern s32 e1000_check_polarity_ife(struct e1000_hw *hw); 710 extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 711 extern s32 e1000_check_polarity_igp(struct e1000_hw *hw); 712 extern bool e1000_check_phy_82574(struct e1000_hw *hw); 713 extern s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 714 extern void e1000e_ptp_init(struct e1000_adapter *adapter); 715 extern void e1000e_ptp_remove(struct e1000_adapter *adapter); 716 717 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 718 { 719 return hw->phy.ops.reset(hw); 720 } 721 722 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 723 { 724 return hw->phy.ops.read_reg(hw, offset, data); 725 } 726 727 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) 728 { 729 return hw->phy.ops.read_reg_locked(hw, offset, data); 730 } 731 732 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 733 { 734 return hw->phy.ops.write_reg(hw, offset, data); 735 } 736 737 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) 738 { 739 return hw->phy.ops.write_reg_locked(hw, offset, data); 740 } 741 742 static inline s32 e1000_get_cable_length(struct e1000_hw *hw) 743 { 744 return hw->phy.ops.get_cable_length(hw); 745 } 746 747 extern s32 e1000e_acquire_nvm(struct e1000_hw *hw); 748 extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 749 extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw); 750 extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); 751 extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 752 extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); 753 extern void e1000e_release_nvm(struct e1000_hw *hw); 754 extern void e1000e_reload_nvm_generic(struct e1000_hw *hw); 755 extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); 756 757 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 758 { 759 if (hw->mac.ops.read_mac_addr) 760 return hw->mac.ops.read_mac_addr(hw); 761 762 return e1000_read_mac_addr_generic(hw); 763 } 764 765 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 766 { 767 return hw->nvm.ops.validate(hw); 768 } 769 770 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 771 { 772 return hw->nvm.ops.update(hw); 773 } 774 775 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 776 { 777 return hw->nvm.ops.read(hw, offset, words, data); 778 } 779 780 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 781 { 782 return hw->nvm.ops.write(hw, offset, words, data); 783 } 784 785 static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 786 { 787 return hw->phy.ops.get_info(hw); 788 } 789 790 extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); 791 extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); 792 extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); 793 794 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 795 { 796 return readl(hw->hw_addr + reg); 797 } 798 799 #define er32(reg) __er32(hw, E1000_##reg) 800 801 /** 802 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 803 * @hw: pointer to the HW structure 804 * 805 * When updating the MAC CSR registers, the Manageability Engine (ME) could 806 * be accessing the registers at the same time. Normally, this is handled in 807 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 808 * accesses later than it should which could result in the register to have 809 * an incorrect value. Workaround this by checking the FWSM register which 810 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 811 * and try again a number of times. 812 **/ 813 static inline s32 __ew32_prepare(struct e1000_hw *hw) 814 { 815 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 816 817 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 818 udelay(50); 819 820 return i; 821 } 822 823 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 824 { 825 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 826 __ew32_prepare(hw); 827 828 writel(val, hw->hw_addr + reg); 829 } 830 831 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 832 833 #define e1e_flush() er32(STATUS) 834 835 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 836 (__ew32((a), (reg + ((offset) << 2)), (value))) 837 838 #define E1000_READ_REG_ARRAY(a, reg, offset) \ 839 (readl((a)->hw_addr + reg + ((offset) << 2))) 840 841 #endif /* _E1000_H_ */ 842