1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 /* Linux PRO/1000 Ethernet Driver main header file */ 23 24 #ifndef _E1000_H_ 25 #define _E1000_H_ 26 27 #include <linux/bitops.h> 28 #include <linux/types.h> 29 #include <linux/timer.h> 30 #include <linux/workqueue.h> 31 #include <linux/io.h> 32 #include <linux/netdevice.h> 33 #include <linux/pci.h> 34 #include <linux/pci-aspm.h> 35 #include <linux/crc32.h> 36 #include <linux/if_vlan.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/ptp_clock_kernel.h> 40 #include <linux/ptp_classify.h> 41 #include <linux/mii.h> 42 #include <linux/mdio.h> 43 #include <linux/pm_qos.h> 44 #include "hw.h" 45 46 struct e1000_info; 47 48 #define e_dbg(format, arg...) \ 49 netdev_dbg(hw->adapter->netdev, format, ## arg) 50 #define e_err(format, arg...) \ 51 netdev_err(adapter->netdev, format, ## arg) 52 #define e_info(format, arg...) \ 53 netdev_info(adapter->netdev, format, ## arg) 54 #define e_warn(format, arg...) \ 55 netdev_warn(adapter->netdev, format, ## arg) 56 #define e_notice(format, arg...) \ 57 netdev_notice(adapter->netdev, format, ## arg) 58 59 /* Interrupt modes, as used by the IntMode parameter */ 60 #define E1000E_INT_MODE_LEGACY 0 61 #define E1000E_INT_MODE_MSI 1 62 #define E1000E_INT_MODE_MSIX 2 63 64 /* Tx/Rx descriptor defines */ 65 #define E1000_DEFAULT_TXD 256 66 #define E1000_MAX_TXD 4096 67 #define E1000_MIN_TXD 64 68 69 #define E1000_DEFAULT_RXD 256 70 #define E1000_MAX_RXD 4096 71 #define E1000_MIN_RXD 64 72 73 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 74 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 75 76 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 77 78 /* How many Tx Descriptors do we need to call netif_wake_queue ? */ 79 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 80 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 81 82 #define AUTO_ALL_MODES 0 83 #define E1000_EEPROM_APME 0x0400 84 85 #define E1000_MNG_VLAN_NONE (-1) 86 87 #define DEFAULT_JUMBO 9234 88 89 /* Time to wait before putting the device into D3 if there's no link (in ms). */ 90 #define LINK_TIMEOUT 100 91 92 /* Count for polling __E1000_RESET condition every 10-20msec. 93 * Experimentation has shown the reset can take approximately 210msec. 94 */ 95 #define E1000_CHECK_RESET_COUNT 25 96 97 #define DEFAULT_RDTR 0 98 #define DEFAULT_RADV 8 99 #define BURST_RDTR 0x20 100 #define BURST_RADV 0x20 101 #define PCICFG_DESC_RING_STATUS 0xe4 102 #define FLUSH_DESC_REQUIRED 0x100 103 104 /* in the case of WTHRESH, it appears at least the 82571/2 hardware 105 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 106 * WTHRESH=4, so a setting of 5 gives the most efficient bus 107 * utilization but to avoid possible Tx stalls, set it to 1 108 */ 109 #define E1000_TXDCTL_DMA_BURST_ENABLE \ 110 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 111 E1000_TXDCTL_COUNT_DESC | \ 112 (1u << 16) | /* wthresh must be +1 more than desired */\ 113 (1u << 8) | /* hthresh */ \ 114 0x1f) /* pthresh */ 115 116 #define E1000_RXDCTL_DMA_BURST_ENABLE \ 117 (0x01000000 | /* set descriptor granularity */ \ 118 (4u << 16) | /* set writeback threshold */ \ 119 (4u << 8) | /* set prefetch threshold */ \ 120 0x20) /* set hthresh */ 121 122 #define E1000_TIDV_FPD BIT(31) 123 #define E1000_RDTR_FPD BIT(31) 124 125 enum e1000_boards { 126 board_82571, 127 board_82572, 128 board_82573, 129 board_82574, 130 board_82583, 131 board_80003es2lan, 132 board_ich8lan, 133 board_ich9lan, 134 board_ich10lan, 135 board_pchlan, 136 board_pch2lan, 137 board_pch_lpt, 138 board_pch_spt, 139 board_pch_cnp 140 }; 141 142 struct e1000_ps_page { 143 struct page *page; 144 u64 dma; /* must be u64 - written to hw */ 145 }; 146 147 /* wrappers around a pointer to a socket buffer, 148 * so a DMA handle can be stored along with the buffer 149 */ 150 struct e1000_buffer { 151 dma_addr_t dma; 152 struct sk_buff *skb; 153 union { 154 /* Tx */ 155 struct { 156 unsigned long time_stamp; 157 u16 length; 158 u16 next_to_watch; 159 unsigned int segs; 160 unsigned int bytecount; 161 u16 mapped_as_page; 162 }; 163 /* Rx */ 164 struct { 165 /* arrays of page information for packet split */ 166 struct e1000_ps_page *ps_pages; 167 struct page *page; 168 }; 169 }; 170 }; 171 172 struct e1000_ring { 173 struct e1000_adapter *adapter; /* back pointer to adapter */ 174 void *desc; /* pointer to ring memory */ 175 dma_addr_t dma; /* phys address of ring */ 176 unsigned int size; /* length of ring in bytes */ 177 unsigned int count; /* number of desc. in ring */ 178 179 u16 next_to_use; 180 u16 next_to_clean; 181 182 void __iomem *head; 183 void __iomem *tail; 184 185 /* array of buffer information structs */ 186 struct e1000_buffer *buffer_info; 187 188 char name[IFNAMSIZ + 5]; 189 u32 ims_val; 190 u32 itr_val; 191 void __iomem *itr_register; 192 int set_itr; 193 194 struct sk_buff *rx_skb_top; 195 }; 196 197 /* PHY register snapshot values */ 198 struct e1000_phy_regs { 199 u16 bmcr; /* basic mode control register */ 200 u16 bmsr; /* basic mode status register */ 201 u16 advertise; /* auto-negotiation advertisement */ 202 u16 lpa; /* link partner ability register */ 203 u16 expansion; /* auto-negotiation expansion reg */ 204 u16 ctrl1000; /* 1000BASE-T control register */ 205 u16 stat1000; /* 1000BASE-T status register */ 206 u16 estatus; /* extended status register */ 207 }; 208 209 /* board specific private data structure */ 210 struct e1000_adapter { 211 struct timer_list watchdog_timer; 212 struct timer_list phy_info_timer; 213 struct timer_list blink_timer; 214 215 struct work_struct reset_task; 216 struct work_struct watchdog_task; 217 218 const struct e1000_info *ei; 219 220 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 221 u32 bd_number; 222 u32 rx_buffer_len; 223 u16 mng_vlan_id; 224 u16 link_speed; 225 u16 link_duplex; 226 u16 eeprom_vers; 227 228 /* track device up/down/testing state */ 229 unsigned long state; 230 231 /* Interrupt Throttle Rate */ 232 u32 itr; 233 u32 itr_setting; 234 u16 tx_itr; 235 u16 rx_itr; 236 237 /* Tx - one ring per active queue */ 238 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; 239 u32 tx_fifo_limit; 240 241 struct napi_struct napi; 242 243 unsigned int uncorr_errors; /* uncorrectable ECC errors */ 244 unsigned int corr_errors; /* correctable ECC errors */ 245 unsigned int restart_queue; 246 u32 txd_cmd; 247 248 bool detect_tx_hung; 249 bool tx_hang_recheck; 250 u8 tx_timeout_factor; 251 252 u32 tx_int_delay; 253 u32 tx_abs_int_delay; 254 255 unsigned int total_tx_bytes; 256 unsigned int total_tx_packets; 257 unsigned int total_rx_bytes; 258 unsigned int total_rx_packets; 259 260 /* Tx stats */ 261 u64 tpt_old; 262 u64 colc_old; 263 u32 gotc; 264 u64 gotc_old; 265 u32 tx_timeout_count; 266 u32 tx_fifo_head; 267 u32 tx_head_addr; 268 u32 tx_fifo_size; 269 u32 tx_dma_failed; 270 u32 tx_hwtstamp_timeouts; 271 u32 tx_hwtstamp_skipped; 272 273 /* Rx */ 274 bool (*clean_rx)(struct e1000_ring *ring, int *work_done, 275 int work_to_do) ____cacheline_aligned_in_smp; 276 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count, 277 gfp_t gfp); 278 struct e1000_ring *rx_ring; 279 280 u32 rx_int_delay; 281 u32 rx_abs_int_delay; 282 283 /* Rx stats */ 284 u64 hw_csum_err; 285 u64 hw_csum_good; 286 u64 rx_hdr_split; 287 u32 gorc; 288 u64 gorc_old; 289 u32 alloc_rx_buff_failed; 290 u32 rx_dma_failed; 291 u32 rx_hwtstamp_cleared; 292 293 unsigned int rx_ps_pages; 294 u16 rx_ps_bsize0; 295 u32 max_frame_size; 296 u32 min_frame_size; 297 298 /* OS defined structs */ 299 struct net_device *netdev; 300 struct pci_dev *pdev; 301 302 /* structs defined in e1000_hw.h */ 303 struct e1000_hw hw; 304 305 spinlock_t stats64_lock; /* protects statistics counters */ 306 struct e1000_hw_stats stats; 307 struct e1000_phy_info phy_info; 308 struct e1000_phy_stats phy_stats; 309 310 /* Snapshot of PHY registers */ 311 struct e1000_phy_regs phy_regs; 312 313 struct e1000_ring test_tx_ring; 314 struct e1000_ring test_rx_ring; 315 u32 test_icr; 316 317 u32 msg_enable; 318 unsigned int num_vectors; 319 struct msix_entry *msix_entries; 320 int int_mode; 321 u32 eiac_mask; 322 323 u32 eeprom_wol; 324 u32 wol; 325 u32 pba; 326 u32 max_hw_frame_size; 327 328 bool fc_autoneg; 329 330 unsigned int flags; 331 unsigned int flags2; 332 struct work_struct downshift_task; 333 struct work_struct update_phy_task; 334 struct work_struct print_hang_task; 335 336 int phy_hang_count; 337 338 u16 tx_ring_count; 339 u16 rx_ring_count; 340 341 struct hwtstamp_config hwtstamp_config; 342 struct delayed_work systim_overflow_work; 343 struct sk_buff *tx_hwtstamp_skb; 344 unsigned long tx_hwtstamp_start; 345 struct work_struct tx_hwtstamp_work; 346 spinlock_t systim_lock; /* protects SYSTIML/H regsters */ 347 struct cyclecounter cc; 348 struct timecounter tc; 349 struct ptp_clock *ptp_clock; 350 struct ptp_clock_info ptp_clock_info; 351 struct pm_qos_request pm_qos_req; 352 s32 ptp_delta; 353 354 u16 eee_advert; 355 }; 356 357 struct e1000_info { 358 enum e1000_mac_type mac; 359 unsigned int flags; 360 unsigned int flags2; 361 u32 pba; 362 u32 max_hw_frame_size; 363 s32 (*get_variants)(struct e1000_adapter *); 364 const struct e1000_mac_operations *mac_ops; 365 const struct e1000_phy_operations *phy_ops; 366 const struct e1000_nvm_operations *nvm_ops; 367 }; 368 369 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); 370 371 /* The system time is maintained by a 64-bit counter comprised of the 32-bit 372 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore 373 * its resolution) is based on the contents of the TIMINCA register - it 374 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). 375 * For the best accuracy, the incperiod should be as small as possible. The 376 * incvalue is scaled by a factor as large as possible (while still fitting 377 * in bits 23:0) so that relatively small clock corrections can be made. 378 * 379 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of 380 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) 381 * bits to count nanoseconds leaving the rest for fractional nonseconds. 382 */ 383 #define INCVALUE_96MHZ 125 384 #define INCVALUE_SHIFT_96MHZ 17 385 #define INCPERIOD_SHIFT_96MHZ 2 386 #define INCPERIOD_96MHZ (12 >> INCPERIOD_SHIFT_96MHZ) 387 388 #define INCVALUE_25MHZ 40 389 #define INCVALUE_SHIFT_25MHZ 18 390 #define INCPERIOD_25MHZ 1 391 392 #define INCVALUE_24MHZ 125 393 #define INCVALUE_SHIFT_24MHZ 14 394 #define INCPERIOD_24MHZ 3 395 396 #define INCVALUE_38400KHZ 26 397 #define INCVALUE_SHIFT_38400KHZ 19 398 #define INCPERIOD_38400KHZ 1 399 400 /* Another drawback of scaling the incvalue by a large factor is the 401 * 64-bit SYSTIM register overflows more quickly. This is dealt with 402 * by simply reading the clock before it overflows. 403 * 404 * Clock ns bits Overflows after 405 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ 406 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs 407 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours 408 */ 409 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) 410 #define E1000_MAX_82574_SYSTIM_REREADS 50 411 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL) 412 413 /* hardware capability, feature, and workaround flags */ 414 #define FLAG_HAS_AMT BIT(0) 415 #define FLAG_HAS_FLASH BIT(1) 416 #define FLAG_HAS_HW_VLAN_FILTER BIT(2) 417 #define FLAG_HAS_WOL BIT(3) 418 /* reserved BIT(4) */ 419 #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5) 420 #define FLAG_HAS_SWSM_ON_LOAD BIT(6) 421 #define FLAG_HAS_JUMBO_FRAMES BIT(7) 422 #define FLAG_READ_ONLY_NVM BIT(8) 423 #define FLAG_IS_ICH BIT(9) 424 #define FLAG_HAS_MSIX BIT(10) 425 #define FLAG_HAS_SMART_POWER_DOWN BIT(11) 426 #define FLAG_IS_QUAD_PORT_A BIT(12) 427 #define FLAG_IS_QUAD_PORT BIT(13) 428 #define FLAG_HAS_HW_TIMESTAMP BIT(14) 429 #define FLAG_APME_IN_WUC BIT(15) 430 #define FLAG_APME_IN_CTRL3 BIT(16) 431 #define FLAG_APME_CHECK_PORT_B BIT(17) 432 #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18) 433 #define FLAG_NO_WAKE_UCAST BIT(19) 434 #define FLAG_MNG_PT_ENABLED BIT(20) 435 #define FLAG_RESET_OVERWRITES_LAA BIT(21) 436 #define FLAG_TARC_SPEED_MODE_BIT BIT(22) 437 #define FLAG_TARC_SET_BIT_ZERO BIT(23) 438 #define FLAG_RX_NEEDS_RESTART BIT(24) 439 #define FLAG_LSC_GIG_SPEED_DROP BIT(25) 440 #define FLAG_SMART_POWER_DOWN BIT(26) 441 #define FLAG_MSI_ENABLED BIT(27) 442 /* reserved BIT(28) */ 443 #define FLAG_TSO_FORCE BIT(29) 444 #define FLAG_RESTART_NOW BIT(30) 445 #define FLAG_MSI_TEST_FAILED BIT(31) 446 447 #define FLAG2_CRC_STRIPPING BIT(0) 448 #define FLAG2_HAS_PHY_WAKEUP BIT(1) 449 #define FLAG2_IS_DISCARDING BIT(2) 450 #define FLAG2_DISABLE_ASPM_L1 BIT(3) 451 #define FLAG2_HAS_PHY_STATS BIT(4) 452 #define FLAG2_HAS_EEE BIT(5) 453 #define FLAG2_DMA_BURST BIT(6) 454 #define FLAG2_DISABLE_ASPM_L0S BIT(7) 455 #define FLAG2_DISABLE_AIM BIT(8) 456 #define FLAG2_CHECK_PHY_HANG BIT(9) 457 #define FLAG2_NO_DISABLE_RX BIT(10) 458 #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11) 459 #define FLAG2_DFLT_CRC_STRIPPING BIT(12) 460 #define FLAG2_CHECK_RX_HWTSTAMP BIT(13) 461 #define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14) 462 463 #define E1000_RX_DESC_PS(R, i) \ 464 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 465 #define E1000_RX_DESC_EXT(R, i) \ 466 (&(((union e1000_rx_desc_extended *)((R).desc))[i])) 467 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 468 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 469 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 470 471 enum e1000_state_t { 472 __E1000_TESTING, 473 __E1000_RESETTING, 474 __E1000_ACCESS_SHARED_RESOURCE, 475 __E1000_DOWN 476 }; 477 478 enum latency_range { 479 lowest_latency = 0, 480 low_latency = 1, 481 bulk_latency = 2, 482 latency_invalid = 255 483 }; 484 485 extern char e1000e_driver_name[]; 486 extern const char e1000e_driver_version[]; 487 488 void e1000e_check_options(struct e1000_adapter *adapter); 489 void e1000e_set_ethtool_ops(struct net_device *netdev); 490 491 int e1000e_open(struct net_device *netdev); 492 int e1000e_close(struct net_device *netdev); 493 void e1000e_up(struct e1000_adapter *adapter); 494 void e1000e_down(struct e1000_adapter *adapter, bool reset); 495 void e1000e_reinit_locked(struct e1000_adapter *adapter); 496 void e1000e_reset(struct e1000_adapter *adapter); 497 void e1000e_power_up_phy(struct e1000_adapter *adapter); 498 int e1000e_setup_rx_resources(struct e1000_ring *ring); 499 int e1000e_setup_tx_resources(struct e1000_ring *ring); 500 void e1000e_free_rx_resources(struct e1000_ring *ring); 501 void e1000e_free_tx_resources(struct e1000_ring *ring); 502 void e1000e_get_stats64(struct net_device *netdev, 503 struct rtnl_link_stats64 *stats); 504 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 505 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 506 void e1000e_get_hw_control(struct e1000_adapter *adapter); 507 void e1000e_release_hw_control(struct e1000_adapter *adapter); 508 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); 509 510 extern unsigned int copybreak; 511 512 extern const struct e1000_info e1000_82571_info; 513 extern const struct e1000_info e1000_82572_info; 514 extern const struct e1000_info e1000_82573_info; 515 extern const struct e1000_info e1000_82574_info; 516 extern const struct e1000_info e1000_82583_info; 517 extern const struct e1000_info e1000_ich8_info; 518 extern const struct e1000_info e1000_ich9_info; 519 extern const struct e1000_info e1000_ich10_info; 520 extern const struct e1000_info e1000_pch_info; 521 extern const struct e1000_info e1000_pch2_info; 522 extern const struct e1000_info e1000_pch_lpt_info; 523 extern const struct e1000_info e1000_pch_spt_info; 524 extern const struct e1000_info e1000_pch_cnp_info; 525 extern const struct e1000_info e1000_es2_info; 526 527 void e1000e_ptp_init(struct e1000_adapter *adapter); 528 void e1000e_ptp_remove(struct e1000_adapter *adapter); 529 530 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 531 { 532 return hw->phy.ops.reset(hw); 533 } 534 535 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 536 { 537 return hw->phy.ops.read_reg(hw, offset, data); 538 } 539 540 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) 541 { 542 return hw->phy.ops.read_reg_locked(hw, offset, data); 543 } 544 545 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 546 { 547 return hw->phy.ops.write_reg(hw, offset, data); 548 } 549 550 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) 551 { 552 return hw->phy.ops.write_reg_locked(hw, offset, data); 553 } 554 555 void e1000e_reload_nvm_generic(struct e1000_hw *hw); 556 557 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 558 { 559 if (hw->mac.ops.read_mac_addr) 560 return hw->mac.ops.read_mac_addr(hw); 561 562 return e1000_read_mac_addr_generic(hw); 563 } 564 565 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 566 { 567 return hw->nvm.ops.validate(hw); 568 } 569 570 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 571 { 572 return hw->nvm.ops.update(hw); 573 } 574 575 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, 576 u16 *data) 577 { 578 return hw->nvm.ops.read(hw, offset, words, data); 579 } 580 581 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, 582 u16 *data) 583 { 584 return hw->nvm.ops.write(hw, offset, words, data); 585 } 586 587 static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 588 { 589 return hw->phy.ops.get_info(hw); 590 } 591 592 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 593 { 594 return readl(hw->hw_addr + reg); 595 } 596 597 #define er32(reg) __er32(hw, E1000_##reg) 598 599 s32 __ew32_prepare(struct e1000_hw *hw); 600 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); 601 602 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 603 604 #define e1e_flush() er32(STATUS) 605 606 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 607 (__ew32((a), (reg + ((offset) << 2)), (value))) 608 609 #define E1000_READ_REG_ARRAY(a, reg, offset) \ 610 (readl((a)->hw_addr + reg + ((offset) << 2))) 611 612 #endif /* _E1000_H_ */ 613