1 /* Intel PRO/1000 Linux driver
2  * Copyright(c) 1999 - 2015 Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * The full GNU General Public License is included in this distribution in
14  * the file called "COPYING".
15  *
16  * Contact Information:
17  * Linux NICS <linux.nics@intel.com>
18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20  */
21 
22 /* Linux PRO/1000 Ethernet Driver main header file */
23 
24 #ifndef _E1000_H_
25 #define _E1000_H_
26 
27 #include <linux/bitops.h>
28 #include <linux/types.h>
29 #include <linux/timer.h>
30 #include <linux/workqueue.h>
31 #include <linux/io.h>
32 #include <linux/netdevice.h>
33 #include <linux/pci.h>
34 #include <linux/pci-aspm.h>
35 #include <linux/crc32.h>
36 #include <linux/if_vlan.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/ptp_classify.h>
41 #include <linux/mii.h>
42 #include <linux/mdio.h>
43 #include <linux/pm_qos.h>
44 #include "hw.h"
45 
46 struct e1000_info;
47 
48 #define e_dbg(format, arg...) \
49 	netdev_dbg(hw->adapter->netdev, format, ## arg)
50 #define e_err(format, arg...) \
51 	netdev_err(adapter->netdev, format, ## arg)
52 #define e_info(format, arg...) \
53 	netdev_info(adapter->netdev, format, ## arg)
54 #define e_warn(format, arg...) \
55 	netdev_warn(adapter->netdev, format, ## arg)
56 #define e_notice(format, arg...) \
57 	netdev_notice(adapter->netdev, format, ## arg)
58 
59 /* Interrupt modes, as used by the IntMode parameter */
60 #define E1000E_INT_MODE_LEGACY		0
61 #define E1000E_INT_MODE_MSI		1
62 #define E1000E_INT_MODE_MSIX		2
63 
64 /* Tx/Rx descriptor defines */
65 #define E1000_DEFAULT_TXD		256
66 #define E1000_MAX_TXD			4096
67 #define E1000_MIN_TXD			64
68 
69 #define E1000_DEFAULT_RXD		256
70 #define E1000_MAX_RXD			4096
71 #define E1000_MIN_RXD			64
72 
73 #define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
74 #define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */
75 
76 #define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */
77 
78 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
79 /* How many Rx Buffers do we bundle into one write to the hardware ? */
80 #define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */
81 
82 #define AUTO_ALL_MODES			0
83 #define E1000_EEPROM_APME		0x0400
84 
85 #define E1000_MNG_VLAN_NONE		(-1)
86 
87 #define DEFAULT_JUMBO			9234
88 
89 /* Time to wait before putting the device into D3 if there's no link (in ms). */
90 #define LINK_TIMEOUT		100
91 
92 /* Count for polling __E1000_RESET condition every 10-20msec.
93  * Experimentation has shown the reset can take approximately 210msec.
94  */
95 #define E1000_CHECK_RESET_COUNT		25
96 
97 #define PCICFG_DESC_RING_STATUS		0xe4
98 #define FLUSH_DESC_REQUIRED		0x100
99 
100 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
101  * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
102  * WTHRESH=4, so a setting of 5 gives the most efficient bus
103  * utilization but to avoid possible Tx stalls, set it to 1
104  */
105 #define E1000_TXDCTL_DMA_BURST_ENABLE                          \
106 	(E1000_TXDCTL_GRAN | /* set descriptor granularity */  \
107 	 E1000_TXDCTL_COUNT_DESC |                             \
108 	 (1u << 16) | /* wthresh must be +1 more than desired */\
109 	 (1u << 8)  | /* hthresh */                             \
110 	 0x1f)        /* pthresh */
111 
112 #define E1000_RXDCTL_DMA_BURST_ENABLE                          \
113 	(0x01000000 | /* set descriptor granularity */         \
114 	 (4u << 16) | /* set writeback threshold    */         \
115 	 (4u << 8)  | /* set prefetch threshold     */         \
116 	 0x20)        /* set hthresh                */
117 
118 #define E1000_TIDV_FPD BIT(31)
119 #define E1000_RDTR_FPD BIT(31)
120 
121 enum e1000_boards {
122 	board_82571,
123 	board_82572,
124 	board_82573,
125 	board_82574,
126 	board_82583,
127 	board_80003es2lan,
128 	board_ich8lan,
129 	board_ich9lan,
130 	board_ich10lan,
131 	board_pchlan,
132 	board_pch2lan,
133 	board_pch_lpt,
134 	board_pch_spt,
135 	board_pch_cnp
136 };
137 
138 struct e1000_ps_page {
139 	struct page *page;
140 	u64 dma; /* must be u64 - written to hw */
141 };
142 
143 /* wrappers around a pointer to a socket buffer,
144  * so a DMA handle can be stored along with the buffer
145  */
146 struct e1000_buffer {
147 	dma_addr_t dma;
148 	struct sk_buff *skb;
149 	union {
150 		/* Tx */
151 		struct {
152 			unsigned long time_stamp;
153 			u16 length;
154 			u16 next_to_watch;
155 			unsigned int segs;
156 			unsigned int bytecount;
157 			u16 mapped_as_page;
158 		};
159 		/* Rx */
160 		struct {
161 			/* arrays of page information for packet split */
162 			struct e1000_ps_page *ps_pages;
163 			struct page *page;
164 		};
165 	};
166 };
167 
168 struct e1000_ring {
169 	struct e1000_adapter *adapter;	/* back pointer to adapter */
170 	void *desc;			/* pointer to ring memory  */
171 	dma_addr_t dma;			/* phys address of ring    */
172 	unsigned int size;		/* length of ring in bytes */
173 	unsigned int count;		/* number of desc. in ring */
174 
175 	u16 next_to_use;
176 	u16 next_to_clean;
177 
178 	void __iomem *head;
179 	void __iomem *tail;
180 
181 	/* array of buffer information structs */
182 	struct e1000_buffer *buffer_info;
183 
184 	char name[IFNAMSIZ + 5];
185 	u32 ims_val;
186 	u32 itr_val;
187 	void __iomem *itr_register;
188 	int set_itr;
189 
190 	struct sk_buff *rx_skb_top;
191 };
192 
193 /* PHY register snapshot values */
194 struct e1000_phy_regs {
195 	u16 bmcr;		/* basic mode control register    */
196 	u16 bmsr;		/* basic mode status register     */
197 	u16 advertise;		/* auto-negotiation advertisement */
198 	u16 lpa;		/* link partner ability register  */
199 	u16 expansion;		/* auto-negotiation expansion reg */
200 	u16 ctrl1000;		/* 1000BASE-T control register    */
201 	u16 stat1000;		/* 1000BASE-T status register     */
202 	u16 estatus;		/* extended status register       */
203 };
204 
205 /* board specific private data structure */
206 struct e1000_adapter {
207 	struct timer_list watchdog_timer;
208 	struct timer_list phy_info_timer;
209 	struct timer_list blink_timer;
210 
211 	struct work_struct reset_task;
212 	struct work_struct watchdog_task;
213 
214 	const struct e1000_info *ei;
215 
216 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
217 	u32 bd_number;
218 	u32 rx_buffer_len;
219 	u16 mng_vlan_id;
220 	u16 link_speed;
221 	u16 link_duplex;
222 	u16 eeprom_vers;
223 
224 	/* track device up/down/testing state */
225 	unsigned long state;
226 
227 	/* Interrupt Throttle Rate */
228 	u32 itr;
229 	u32 itr_setting;
230 	u16 tx_itr;
231 	u16 rx_itr;
232 
233 	/* Tx - one ring per active queue */
234 	struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
235 	u32 tx_fifo_limit;
236 
237 	struct napi_struct napi;
238 
239 	unsigned int uncorr_errors;	/* uncorrectable ECC errors */
240 	unsigned int corr_errors;	/* correctable ECC errors */
241 	unsigned int restart_queue;
242 	u32 txd_cmd;
243 
244 	bool detect_tx_hung;
245 	bool tx_hang_recheck;
246 	u8 tx_timeout_factor;
247 
248 	u32 tx_int_delay;
249 	u32 tx_abs_int_delay;
250 
251 	unsigned int total_tx_bytes;
252 	unsigned int total_tx_packets;
253 	unsigned int total_rx_bytes;
254 	unsigned int total_rx_packets;
255 
256 	/* Tx stats */
257 	u64 tpt_old;
258 	u64 colc_old;
259 	u32 gotc;
260 	u64 gotc_old;
261 	u32 tx_timeout_count;
262 	u32 tx_fifo_head;
263 	u32 tx_head_addr;
264 	u32 tx_fifo_size;
265 	u32 tx_dma_failed;
266 	u32 tx_hwtstamp_timeouts;
267 	u32 tx_hwtstamp_skipped;
268 
269 	/* Rx */
270 	bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
271 			 int work_to_do) ____cacheline_aligned_in_smp;
272 	void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
273 			     gfp_t gfp);
274 	struct e1000_ring *rx_ring;
275 
276 	u32 rx_int_delay;
277 	u32 rx_abs_int_delay;
278 
279 	/* Rx stats */
280 	u64 hw_csum_err;
281 	u64 hw_csum_good;
282 	u64 rx_hdr_split;
283 	u32 gorc;
284 	u64 gorc_old;
285 	u32 alloc_rx_buff_failed;
286 	u32 rx_dma_failed;
287 	u32 rx_hwtstamp_cleared;
288 
289 	unsigned int rx_ps_pages;
290 	u16 rx_ps_bsize0;
291 	u32 max_frame_size;
292 	u32 min_frame_size;
293 
294 	/* OS defined structs */
295 	struct net_device *netdev;
296 	struct pci_dev *pdev;
297 
298 	/* structs defined in e1000_hw.h */
299 	struct e1000_hw hw;
300 
301 	spinlock_t stats64_lock;	/* protects statistics counters */
302 	struct e1000_hw_stats stats;
303 	struct e1000_phy_info phy_info;
304 	struct e1000_phy_stats phy_stats;
305 
306 	/* Snapshot of PHY registers */
307 	struct e1000_phy_regs phy_regs;
308 
309 	struct e1000_ring test_tx_ring;
310 	struct e1000_ring test_rx_ring;
311 	u32 test_icr;
312 
313 	u32 msg_enable;
314 	unsigned int num_vectors;
315 	struct msix_entry *msix_entries;
316 	int int_mode;
317 	u32 eiac_mask;
318 
319 	u32 eeprom_wol;
320 	u32 wol;
321 	u32 pba;
322 	u32 max_hw_frame_size;
323 
324 	bool fc_autoneg;
325 
326 	unsigned int flags;
327 	unsigned int flags2;
328 	struct work_struct downshift_task;
329 	struct work_struct update_phy_task;
330 	struct work_struct print_hang_task;
331 
332 	int phy_hang_count;
333 
334 	u16 tx_ring_count;
335 	u16 rx_ring_count;
336 
337 	struct hwtstamp_config hwtstamp_config;
338 	struct delayed_work systim_overflow_work;
339 	struct sk_buff *tx_hwtstamp_skb;
340 	unsigned long tx_hwtstamp_start;
341 	struct work_struct tx_hwtstamp_work;
342 	spinlock_t systim_lock;	/* protects SYSTIML/H regsters */
343 	struct cyclecounter cc;
344 	struct timecounter tc;
345 	struct ptp_clock *ptp_clock;
346 	struct ptp_clock_info ptp_clock_info;
347 	struct pm_qos_request pm_qos_req;
348 	s32 ptp_delta;
349 
350 	u16 eee_advert;
351 };
352 
353 struct e1000_info {
354 	enum e1000_mac_type	mac;
355 	unsigned int		flags;
356 	unsigned int		flags2;
357 	u32			pba;
358 	u32			max_hw_frame_size;
359 	s32			(*get_variants)(struct e1000_adapter *);
360 	const struct e1000_mac_operations *mac_ops;
361 	const struct e1000_phy_operations *phy_ops;
362 	const struct e1000_nvm_operations *nvm_ops;
363 };
364 
365 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
366 
367 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
368  * SYSTIMH and SYSTIML registers.  How the counter increments (and therefore
369  * its resolution) is based on the contents of the TIMINCA register - it
370  * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
371  * For the best accuracy, the incperiod should be as small as possible.  The
372  * incvalue is scaled by a factor as large as possible (while still fitting
373  * in bits 23:0) so that relatively small clock corrections can be made.
374  *
375  * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
376  * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
377  * bits to count nanoseconds leaving the rest for fractional nonseconds.
378  */
379 #define INCVALUE_96MHZ		125
380 #define INCVALUE_SHIFT_96MHZ	17
381 #define INCPERIOD_SHIFT_96MHZ	2
382 #define INCPERIOD_96MHZ		(12 >> INCPERIOD_SHIFT_96MHZ)
383 
384 #define INCVALUE_25MHZ		40
385 #define INCVALUE_SHIFT_25MHZ	18
386 #define INCPERIOD_25MHZ		1
387 
388 #define INCVALUE_24MHZ		125
389 #define INCVALUE_SHIFT_24MHZ	14
390 #define INCPERIOD_24MHZ		3
391 
392 #define INCVALUE_38400KHZ	26
393 #define INCVALUE_SHIFT_38400KHZ	19
394 #define INCPERIOD_38400KHZ	1
395 
396 /* Another drawback of scaling the incvalue by a large factor is the
397  * 64-bit SYSTIM register overflows more quickly.  This is dealt with
398  * by simply reading the clock before it overflows.
399  *
400  * Clock	ns bits	Overflows after
401  * ~~~~~~	~~~~~~~	~~~~~~~~~~~~~~~
402  * 96MHz	47-bit	2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
403  * 25MHz	46-bit	2^46 / 10^9 / 3600 = 19.55 hours
404  */
405 #define E1000_SYSTIM_OVERFLOW_PERIOD	(HZ * 60 * 60 * 4)
406 #define E1000_MAX_82574_SYSTIM_REREADS	50
407 #define E1000_82574_SYSTIM_EPSILON	(1ULL << 35ULL)
408 
409 /* hardware capability, feature, and workaround flags */
410 #define FLAG_HAS_AMT                      BIT(0)
411 #define FLAG_HAS_FLASH                    BIT(1)
412 #define FLAG_HAS_HW_VLAN_FILTER           BIT(2)
413 #define FLAG_HAS_WOL                      BIT(3)
414 /* reserved BIT(4) */
415 #define FLAG_HAS_CTRLEXT_ON_LOAD          BIT(5)
416 #define FLAG_HAS_SWSM_ON_LOAD             BIT(6)
417 #define FLAG_HAS_JUMBO_FRAMES             BIT(7)
418 #define FLAG_READ_ONLY_NVM                BIT(8)
419 #define FLAG_IS_ICH                       BIT(9)
420 #define FLAG_HAS_MSIX                     BIT(10)
421 #define FLAG_HAS_SMART_POWER_DOWN         BIT(11)
422 #define FLAG_IS_QUAD_PORT_A               BIT(12)
423 #define FLAG_IS_QUAD_PORT                 BIT(13)
424 #define FLAG_HAS_HW_TIMESTAMP             BIT(14)
425 #define FLAG_APME_IN_WUC                  BIT(15)
426 #define FLAG_APME_IN_CTRL3                BIT(16)
427 #define FLAG_APME_CHECK_PORT_B            BIT(17)
428 #define FLAG_DISABLE_FC_PAUSE_TIME        BIT(18)
429 #define FLAG_NO_WAKE_UCAST                BIT(19)
430 #define FLAG_MNG_PT_ENABLED               BIT(20)
431 #define FLAG_RESET_OVERWRITES_LAA         BIT(21)
432 #define FLAG_TARC_SPEED_MODE_BIT          BIT(22)
433 #define FLAG_TARC_SET_BIT_ZERO            BIT(23)
434 #define FLAG_RX_NEEDS_RESTART             BIT(24)
435 #define FLAG_LSC_GIG_SPEED_DROP           BIT(25)
436 #define FLAG_SMART_POWER_DOWN             BIT(26)
437 #define FLAG_MSI_ENABLED                  BIT(27)
438 /* reserved BIT(28) */
439 #define FLAG_TSO_FORCE                    BIT(29)
440 #define FLAG_RESTART_NOW                  BIT(30)
441 #define FLAG_MSI_TEST_FAILED              BIT(31)
442 
443 #define FLAG2_CRC_STRIPPING               BIT(0)
444 #define FLAG2_HAS_PHY_WAKEUP              BIT(1)
445 #define FLAG2_IS_DISCARDING               BIT(2)
446 #define FLAG2_DISABLE_ASPM_L1             BIT(3)
447 #define FLAG2_HAS_PHY_STATS               BIT(4)
448 #define FLAG2_HAS_EEE                     BIT(5)
449 #define FLAG2_DMA_BURST                   BIT(6)
450 #define FLAG2_DISABLE_ASPM_L0S            BIT(7)
451 #define FLAG2_DISABLE_AIM                 BIT(8)
452 #define FLAG2_CHECK_PHY_HANG              BIT(9)
453 #define FLAG2_NO_DISABLE_RX               BIT(10)
454 #define FLAG2_PCIM2PCI_ARBITER_WA         BIT(11)
455 #define FLAG2_DFLT_CRC_STRIPPING          BIT(12)
456 #define FLAG2_CHECK_RX_HWTSTAMP           BIT(13)
457 #define FLAG2_CHECK_SYSTIM_OVERFLOW       BIT(14)
458 
459 #define E1000_RX_DESC_PS(R, i)	    \
460 	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
461 #define E1000_RX_DESC_EXT(R, i)	    \
462 	(&(((union e1000_rx_desc_extended *)((R).desc))[i]))
463 #define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
464 #define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
465 #define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
466 
467 enum e1000_state_t {
468 	__E1000_TESTING,
469 	__E1000_RESETTING,
470 	__E1000_ACCESS_SHARED_RESOURCE,
471 	__E1000_DOWN
472 };
473 
474 enum latency_range {
475 	lowest_latency = 0,
476 	low_latency = 1,
477 	bulk_latency = 2,
478 	latency_invalid = 255
479 };
480 
481 extern char e1000e_driver_name[];
482 extern const char e1000e_driver_version[];
483 
484 void e1000e_check_options(struct e1000_adapter *adapter);
485 void e1000e_set_ethtool_ops(struct net_device *netdev);
486 
487 int e1000e_open(struct net_device *netdev);
488 int e1000e_close(struct net_device *netdev);
489 void e1000e_up(struct e1000_adapter *adapter);
490 void e1000e_down(struct e1000_adapter *adapter, bool reset);
491 void e1000e_reinit_locked(struct e1000_adapter *adapter);
492 void e1000e_reset(struct e1000_adapter *adapter);
493 void e1000e_power_up_phy(struct e1000_adapter *adapter);
494 int e1000e_setup_rx_resources(struct e1000_ring *ring);
495 int e1000e_setup_tx_resources(struct e1000_ring *ring);
496 void e1000e_free_rx_resources(struct e1000_ring *ring);
497 void e1000e_free_tx_resources(struct e1000_ring *ring);
498 void e1000e_get_stats64(struct net_device *netdev,
499 			struct rtnl_link_stats64 *stats);
500 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
501 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
502 void e1000e_get_hw_control(struct e1000_adapter *adapter);
503 void e1000e_release_hw_control(struct e1000_adapter *adapter);
504 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
505 
506 extern unsigned int copybreak;
507 
508 extern const struct e1000_info e1000_82571_info;
509 extern const struct e1000_info e1000_82572_info;
510 extern const struct e1000_info e1000_82573_info;
511 extern const struct e1000_info e1000_82574_info;
512 extern const struct e1000_info e1000_82583_info;
513 extern const struct e1000_info e1000_ich8_info;
514 extern const struct e1000_info e1000_ich9_info;
515 extern const struct e1000_info e1000_ich10_info;
516 extern const struct e1000_info e1000_pch_info;
517 extern const struct e1000_info e1000_pch2_info;
518 extern const struct e1000_info e1000_pch_lpt_info;
519 extern const struct e1000_info e1000_pch_spt_info;
520 extern const struct e1000_info e1000_pch_cnp_info;
521 extern const struct e1000_info e1000_es2_info;
522 
523 void e1000e_ptp_init(struct e1000_adapter *adapter);
524 void e1000e_ptp_remove(struct e1000_adapter *adapter);
525 
526 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
527 {
528 	return hw->phy.ops.reset(hw);
529 }
530 
531 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
532 {
533 	return hw->phy.ops.read_reg(hw, offset, data);
534 }
535 
536 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
537 {
538 	return hw->phy.ops.read_reg_locked(hw, offset, data);
539 }
540 
541 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
542 {
543 	return hw->phy.ops.write_reg(hw, offset, data);
544 }
545 
546 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
547 {
548 	return hw->phy.ops.write_reg_locked(hw, offset, data);
549 }
550 
551 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
552 
553 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
554 {
555 	if (hw->mac.ops.read_mac_addr)
556 		return hw->mac.ops.read_mac_addr(hw);
557 
558 	return e1000_read_mac_addr_generic(hw);
559 }
560 
561 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
562 {
563 	return hw->nvm.ops.validate(hw);
564 }
565 
566 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
567 {
568 	return hw->nvm.ops.update(hw);
569 }
570 
571 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
572 				 u16 *data)
573 {
574 	return hw->nvm.ops.read(hw, offset, words, data);
575 }
576 
577 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
578 				  u16 *data)
579 {
580 	return hw->nvm.ops.write(hw, offset, words, data);
581 }
582 
583 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
584 {
585 	return hw->phy.ops.get_info(hw);
586 }
587 
588 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
589 {
590 	return readl(hw->hw_addr + reg);
591 }
592 
593 #define er32(reg)	__er32(hw, E1000_##reg)
594 
595 s32 __ew32_prepare(struct e1000_hw *hw);
596 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
597 
598 #define ew32(reg, val)	__ew32(hw, E1000_##reg, (val))
599 
600 #define e1e_flush()	er32(STATUS)
601 
602 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
603 	(__ew32((a), (reg + ((offset) << 2)), (value)))
604 
605 #define E1000_READ_REG_ARRAY(a, reg, offset) \
606 	(readl((a)->hw_addr + reg + ((offset) << 2)))
607 
608 #endif /* _E1000_H_ */
609