1 /* Intel PRO/1000 Linux driver
2  * Copyright(c) 1999 - 2014 Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * The full GNU General Public License is included in this distribution in
14  * the file called "COPYING".
15  *
16  * Contact Information:
17  * Linux NICS <linux.nics@intel.com>
18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20  */
21 
22 /* Linux PRO/1000 Ethernet Driver main header file */
23 
24 #ifndef _E1000_H_
25 #define _E1000_H_
26 
27 #include <linux/bitops.h>
28 #include <linux/types.h>
29 #include <linux/timer.h>
30 #include <linux/workqueue.h>
31 #include <linux/io.h>
32 #include <linux/netdevice.h>
33 #include <linux/pci.h>
34 #include <linux/pci-aspm.h>
35 #include <linux/crc32.h>
36 #include <linux/if_vlan.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/ptp_classify.h>
41 #include <linux/mii.h>
42 #include <linux/mdio.h>
43 #include <linux/pm_qos.h>
44 #include "hw.h"
45 
46 struct e1000_info;
47 
48 #define e_dbg(format, arg...) \
49 	netdev_dbg(hw->adapter->netdev, format, ## arg)
50 #define e_err(format, arg...) \
51 	netdev_err(adapter->netdev, format, ## arg)
52 #define e_info(format, arg...) \
53 	netdev_info(adapter->netdev, format, ## arg)
54 #define e_warn(format, arg...) \
55 	netdev_warn(adapter->netdev, format, ## arg)
56 #define e_notice(format, arg...) \
57 	netdev_notice(adapter->netdev, format, ## arg)
58 
59 /* Interrupt modes, as used by the IntMode parameter */
60 #define E1000E_INT_MODE_LEGACY		0
61 #define E1000E_INT_MODE_MSI		1
62 #define E1000E_INT_MODE_MSIX		2
63 
64 /* Tx/Rx descriptor defines */
65 #define E1000_DEFAULT_TXD		256
66 #define E1000_MAX_TXD			4096
67 #define E1000_MIN_TXD			64
68 
69 #define E1000_DEFAULT_RXD		256
70 #define E1000_MAX_RXD			4096
71 #define E1000_MIN_RXD			64
72 
73 #define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
74 #define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */
75 
76 #define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */
77 
78 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
79 /* How many Rx Buffers do we bundle into one write to the hardware ? */
80 #define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */
81 
82 #define AUTO_ALL_MODES			0
83 #define E1000_EEPROM_APME		0x0400
84 
85 #define E1000_MNG_VLAN_NONE		(-1)
86 
87 #define DEFAULT_JUMBO			9234
88 
89 /* Time to wait before putting the device into D3 if there's no link (in ms). */
90 #define LINK_TIMEOUT		100
91 
92 /* Count for polling __E1000_RESET condition every 10-20msec.
93  * Experimentation has shown the reset can take approximately 210msec.
94  */
95 #define E1000_CHECK_RESET_COUNT		25
96 
97 #define DEFAULT_RDTR			0
98 #define DEFAULT_RADV			8
99 #define BURST_RDTR			0x20
100 #define BURST_RADV			0x20
101 
102 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
103  * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
104  * WTHRESH=4, so a setting of 5 gives the most efficient bus
105  * utilization but to avoid possible Tx stalls, set it to 1
106  */
107 #define E1000_TXDCTL_DMA_BURST_ENABLE                          \
108 	(E1000_TXDCTL_GRAN | /* set descriptor granularity */  \
109 	 E1000_TXDCTL_COUNT_DESC |                             \
110 	 (1 << 16) | /* wthresh must be +1 more than desired */\
111 	 (1 << 8)  | /* hthresh */                             \
112 	 0x1f)       /* pthresh */
113 
114 #define E1000_RXDCTL_DMA_BURST_ENABLE                          \
115 	(0x01000000 | /* set descriptor granularity */         \
116 	 (4 << 16)  | /* set writeback threshold    */         \
117 	 (4 << 8)   | /* set prefetch threshold     */         \
118 	 0x20)        /* set hthresh                */
119 
120 #define E1000_TIDV_FPD (1 << 31)
121 #define E1000_RDTR_FPD (1 << 31)
122 
123 enum e1000_boards {
124 	board_82571,
125 	board_82572,
126 	board_82573,
127 	board_82574,
128 	board_82583,
129 	board_80003es2lan,
130 	board_ich8lan,
131 	board_ich9lan,
132 	board_ich10lan,
133 	board_pchlan,
134 	board_pch2lan,
135 	board_pch_lpt,
136 	board_pch_spt
137 };
138 
139 struct e1000_ps_page {
140 	struct page *page;
141 	u64 dma; /* must be u64 - written to hw */
142 };
143 
144 /* wrappers around a pointer to a socket buffer,
145  * so a DMA handle can be stored along with the buffer
146  */
147 struct e1000_buffer {
148 	dma_addr_t dma;
149 	struct sk_buff *skb;
150 	union {
151 		/* Tx */
152 		struct {
153 			unsigned long time_stamp;
154 			u16 length;
155 			u16 next_to_watch;
156 			unsigned int segs;
157 			unsigned int bytecount;
158 			u16 mapped_as_page;
159 		};
160 		/* Rx */
161 		struct {
162 			/* arrays of page information for packet split */
163 			struct e1000_ps_page *ps_pages;
164 			struct page *page;
165 		};
166 	};
167 };
168 
169 struct e1000_ring {
170 	struct e1000_adapter *adapter;	/* back pointer to adapter */
171 	void *desc;			/* pointer to ring memory  */
172 	dma_addr_t dma;			/* phys address of ring    */
173 	unsigned int size;		/* length of ring in bytes */
174 	unsigned int count;		/* number of desc. in ring */
175 
176 	u16 next_to_use;
177 	u16 next_to_clean;
178 
179 	void __iomem *head;
180 	void __iomem *tail;
181 
182 	/* array of buffer information structs */
183 	struct e1000_buffer *buffer_info;
184 
185 	char name[IFNAMSIZ + 5];
186 	u32 ims_val;
187 	u32 itr_val;
188 	void __iomem *itr_register;
189 	int set_itr;
190 
191 	struct sk_buff *rx_skb_top;
192 };
193 
194 /* PHY register snapshot values */
195 struct e1000_phy_regs {
196 	u16 bmcr;		/* basic mode control register    */
197 	u16 bmsr;		/* basic mode status register     */
198 	u16 advertise;		/* auto-negotiation advertisement */
199 	u16 lpa;		/* link partner ability register  */
200 	u16 expansion;		/* auto-negotiation expansion reg */
201 	u16 ctrl1000;		/* 1000BASE-T control register    */
202 	u16 stat1000;		/* 1000BASE-T status register     */
203 	u16 estatus;		/* extended status register       */
204 };
205 
206 /* board specific private data structure */
207 struct e1000_adapter {
208 	struct timer_list watchdog_timer;
209 	struct timer_list phy_info_timer;
210 	struct timer_list blink_timer;
211 
212 	struct work_struct reset_task;
213 	struct work_struct watchdog_task;
214 
215 	const struct e1000_info *ei;
216 
217 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
218 	u32 bd_number;
219 	u32 rx_buffer_len;
220 	u16 mng_vlan_id;
221 	u16 link_speed;
222 	u16 link_duplex;
223 	u16 eeprom_vers;
224 
225 	/* track device up/down/testing state */
226 	unsigned long state;
227 
228 	/* Interrupt Throttle Rate */
229 	u32 itr;
230 	u32 itr_setting;
231 	u16 tx_itr;
232 	u16 rx_itr;
233 
234 	/* Tx - one ring per active queue */
235 	struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
236 	u32 tx_fifo_limit;
237 
238 	struct napi_struct napi;
239 
240 	unsigned int uncorr_errors;	/* uncorrectable ECC errors */
241 	unsigned int corr_errors;	/* correctable ECC errors */
242 	unsigned int restart_queue;
243 	u32 txd_cmd;
244 
245 	bool detect_tx_hung;
246 	bool tx_hang_recheck;
247 	u8 tx_timeout_factor;
248 
249 	u32 tx_int_delay;
250 	u32 tx_abs_int_delay;
251 
252 	unsigned int total_tx_bytes;
253 	unsigned int total_tx_packets;
254 	unsigned int total_rx_bytes;
255 	unsigned int total_rx_packets;
256 
257 	/* Tx stats */
258 	u64 tpt_old;
259 	u64 colc_old;
260 	u32 gotc;
261 	u64 gotc_old;
262 	u32 tx_timeout_count;
263 	u32 tx_fifo_head;
264 	u32 tx_head_addr;
265 	u32 tx_fifo_size;
266 	u32 tx_dma_failed;
267 	u32 tx_hwtstamp_timeouts;
268 
269 	/* Rx */
270 	bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
271 			 int work_to_do) ____cacheline_aligned_in_smp;
272 	void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
273 			     gfp_t gfp);
274 	struct e1000_ring *rx_ring;
275 
276 	u32 rx_int_delay;
277 	u32 rx_abs_int_delay;
278 
279 	/* Rx stats */
280 	u64 hw_csum_err;
281 	u64 hw_csum_good;
282 	u64 rx_hdr_split;
283 	u32 gorc;
284 	u64 gorc_old;
285 	u32 alloc_rx_buff_failed;
286 	u32 rx_dma_failed;
287 	u32 rx_hwtstamp_cleared;
288 
289 	unsigned int rx_ps_pages;
290 	u16 rx_ps_bsize0;
291 	u32 max_frame_size;
292 	u32 min_frame_size;
293 
294 	/* OS defined structs */
295 	struct net_device *netdev;
296 	struct pci_dev *pdev;
297 
298 	/* structs defined in e1000_hw.h */
299 	struct e1000_hw hw;
300 
301 	spinlock_t stats64_lock;	/* protects statistics counters */
302 	struct e1000_hw_stats stats;
303 	struct e1000_phy_info phy_info;
304 	struct e1000_phy_stats phy_stats;
305 
306 	/* Snapshot of PHY registers */
307 	struct e1000_phy_regs phy_regs;
308 
309 	struct e1000_ring test_tx_ring;
310 	struct e1000_ring test_rx_ring;
311 	u32 test_icr;
312 
313 	u32 msg_enable;
314 	unsigned int num_vectors;
315 	struct msix_entry *msix_entries;
316 	int int_mode;
317 	u32 eiac_mask;
318 
319 	u32 eeprom_wol;
320 	u32 wol;
321 	u32 pba;
322 	u32 max_hw_frame_size;
323 
324 	bool fc_autoneg;
325 
326 	unsigned int flags;
327 	unsigned int flags2;
328 	struct work_struct downshift_task;
329 	struct work_struct update_phy_task;
330 	struct work_struct print_hang_task;
331 
332 	int phy_hang_count;
333 
334 	u16 tx_ring_count;
335 	u16 rx_ring_count;
336 
337 	struct hwtstamp_config hwtstamp_config;
338 	struct delayed_work systim_overflow_work;
339 	struct sk_buff *tx_hwtstamp_skb;
340 	unsigned long tx_hwtstamp_start;
341 	struct work_struct tx_hwtstamp_work;
342 	spinlock_t systim_lock;	/* protects SYSTIML/H regsters */
343 	struct cyclecounter cc;
344 	struct timecounter tc;
345 	struct ptp_clock *ptp_clock;
346 	struct ptp_clock_info ptp_clock_info;
347 	struct pm_qos_request pm_qos_req;
348 
349 	u16 eee_advert;
350 };
351 
352 struct e1000_info {
353 	enum e1000_mac_type	mac;
354 	unsigned int		flags;
355 	unsigned int		flags2;
356 	u32			pba;
357 	u32			max_hw_frame_size;
358 	s32			(*get_variants)(struct e1000_adapter *);
359 	const struct e1000_mac_operations *mac_ops;
360 	const struct e1000_phy_operations *phy_ops;
361 	const struct e1000_nvm_operations *nvm_ops;
362 };
363 
364 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
365 
366 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
367  * SYSTIMH and SYSTIML registers.  How the counter increments (and therefore
368  * its resolution) is based on the contents of the TIMINCA register - it
369  * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
370  * For the best accuracy, the incperiod should be as small as possible.  The
371  * incvalue is scaled by a factor as large as possible (while still fitting
372  * in bits 23:0) so that relatively small clock corrections can be made.
373  *
374  * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
375  * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
376  * bits to count nanoseconds leaving the rest for fractional nonseconds.
377  */
378 #define INCVALUE_96MHz		125
379 #define INCVALUE_SHIFT_96MHz	17
380 #define INCPERIOD_SHIFT_96MHz	2
381 #define INCPERIOD_96MHz		(12 >> INCPERIOD_SHIFT_96MHz)
382 
383 #define INCVALUE_25MHz		40
384 #define INCVALUE_SHIFT_25MHz	18
385 #define INCPERIOD_25MHz		1
386 
387 /* Another drawback of scaling the incvalue by a large factor is the
388  * 64-bit SYSTIM register overflows more quickly.  This is dealt with
389  * by simply reading the clock before it overflows.
390  *
391  * Clock	ns bits	Overflows after
392  * ~~~~~~	~~~~~~~	~~~~~~~~~~~~~~~
393  * 96MHz	47-bit	2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
394  * 25MHz	46-bit	2^46 / 10^9 / 3600 = 19.55 hours
395  */
396 #define E1000_SYSTIM_OVERFLOW_PERIOD	(HZ * 60 * 60 * 4)
397 #define E1000_MAX_82574_SYSTIM_REREADS	50
398 #define E1000_82574_SYSTIM_EPSILON	(1ULL << 35ULL)
399 
400 /* hardware capability, feature, and workaround flags */
401 #define FLAG_HAS_AMT                      (1 << 0)
402 #define FLAG_HAS_FLASH                    (1 << 1)
403 #define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
404 #define FLAG_HAS_WOL                      (1 << 3)
405 /* reserved bit4 */
406 #define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
407 #define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
408 #define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
409 #define FLAG_READ_ONLY_NVM                (1 << 8)
410 #define FLAG_IS_ICH                       (1 << 9)
411 #define FLAG_HAS_MSIX                     (1 << 10)
412 #define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
413 #define FLAG_IS_QUAD_PORT_A               (1 << 12)
414 #define FLAG_IS_QUAD_PORT                 (1 << 13)
415 #define FLAG_HAS_HW_TIMESTAMP             (1 << 14)
416 #define FLAG_APME_IN_WUC                  (1 << 15)
417 #define FLAG_APME_IN_CTRL3                (1 << 16)
418 #define FLAG_APME_CHECK_PORT_B            (1 << 17)
419 #define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
420 #define FLAG_NO_WAKE_UCAST                (1 << 19)
421 #define FLAG_MNG_PT_ENABLED               (1 << 20)
422 #define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
423 #define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
424 #define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
425 #define FLAG_RX_NEEDS_RESTART             (1 << 24)
426 #define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
427 #define FLAG_SMART_POWER_DOWN             (1 << 26)
428 #define FLAG_MSI_ENABLED                  (1 << 27)
429 /* reserved (1 << 28) */
430 #define FLAG_TSO_FORCE                    (1 << 29)
431 #define FLAG_RESTART_NOW                  (1 << 30)
432 #define FLAG_MSI_TEST_FAILED              (1 << 31)
433 
434 #define FLAG2_CRC_STRIPPING               (1 << 0)
435 #define FLAG2_HAS_PHY_WAKEUP              (1 << 1)
436 #define FLAG2_IS_DISCARDING               (1 << 2)
437 #define FLAG2_DISABLE_ASPM_L1             (1 << 3)
438 #define FLAG2_HAS_PHY_STATS               (1 << 4)
439 #define FLAG2_HAS_EEE                     (1 << 5)
440 #define FLAG2_DMA_BURST                   (1 << 6)
441 #define FLAG2_DISABLE_ASPM_L0S            (1 << 7)
442 #define FLAG2_DISABLE_AIM                 (1 << 8)
443 #define FLAG2_CHECK_PHY_HANG              (1 << 9)
444 #define FLAG2_NO_DISABLE_RX               (1 << 10)
445 #define FLAG2_PCIM2PCI_ARBITER_WA         (1 << 11)
446 #define FLAG2_DFLT_CRC_STRIPPING          (1 << 12)
447 #define FLAG2_CHECK_RX_HWTSTAMP           (1 << 13)
448 
449 #define E1000_RX_DESC_PS(R, i)	    \
450 	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
451 #define E1000_RX_DESC_EXT(R, i)	    \
452 	(&(((union e1000_rx_desc_extended *)((R).desc))[i]))
453 #define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
454 #define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
455 #define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
456 
457 enum e1000_state_t {
458 	__E1000_TESTING,
459 	__E1000_RESETTING,
460 	__E1000_ACCESS_SHARED_RESOURCE,
461 	__E1000_DOWN
462 };
463 
464 enum latency_range {
465 	lowest_latency = 0,
466 	low_latency = 1,
467 	bulk_latency = 2,
468 	latency_invalid = 255
469 };
470 
471 extern char e1000e_driver_name[];
472 extern const char e1000e_driver_version[];
473 
474 void e1000e_check_options(struct e1000_adapter *adapter);
475 void e1000e_set_ethtool_ops(struct net_device *netdev);
476 
477 int e1000e_up(struct e1000_adapter *adapter);
478 void e1000e_down(struct e1000_adapter *adapter, bool reset);
479 void e1000e_reinit_locked(struct e1000_adapter *adapter);
480 void e1000e_reset(struct e1000_adapter *adapter);
481 void e1000e_power_up_phy(struct e1000_adapter *adapter);
482 int e1000e_setup_rx_resources(struct e1000_ring *ring);
483 int e1000e_setup_tx_resources(struct e1000_ring *ring);
484 void e1000e_free_rx_resources(struct e1000_ring *ring);
485 void e1000e_free_tx_resources(struct e1000_ring *ring);
486 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
487 					     struct rtnl_link_stats64 *stats);
488 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
489 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
490 void e1000e_get_hw_control(struct e1000_adapter *adapter);
491 void e1000e_release_hw_control(struct e1000_adapter *adapter);
492 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
493 
494 extern unsigned int copybreak;
495 
496 extern const struct e1000_info e1000_82571_info;
497 extern const struct e1000_info e1000_82572_info;
498 extern const struct e1000_info e1000_82573_info;
499 extern const struct e1000_info e1000_82574_info;
500 extern const struct e1000_info e1000_82583_info;
501 extern const struct e1000_info e1000_ich8_info;
502 extern const struct e1000_info e1000_ich9_info;
503 extern const struct e1000_info e1000_ich10_info;
504 extern const struct e1000_info e1000_pch_info;
505 extern const struct e1000_info e1000_pch2_info;
506 extern const struct e1000_info e1000_pch_lpt_info;
507 extern const struct e1000_info e1000_pch_spt_info;
508 extern const struct e1000_info e1000_es2_info;
509 
510 void e1000e_ptp_init(struct e1000_adapter *adapter);
511 void e1000e_ptp_remove(struct e1000_adapter *adapter);
512 
513 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
514 {
515 	return hw->phy.ops.reset(hw);
516 }
517 
518 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
519 {
520 	return hw->phy.ops.read_reg(hw, offset, data);
521 }
522 
523 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
524 {
525 	return hw->phy.ops.read_reg_locked(hw, offset, data);
526 }
527 
528 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
529 {
530 	return hw->phy.ops.write_reg(hw, offset, data);
531 }
532 
533 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
534 {
535 	return hw->phy.ops.write_reg_locked(hw, offset, data);
536 }
537 
538 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
539 
540 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
541 {
542 	if (hw->mac.ops.read_mac_addr)
543 		return hw->mac.ops.read_mac_addr(hw);
544 
545 	return e1000_read_mac_addr_generic(hw);
546 }
547 
548 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
549 {
550 	return hw->nvm.ops.validate(hw);
551 }
552 
553 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
554 {
555 	return hw->nvm.ops.update(hw);
556 }
557 
558 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
559 				 u16 *data)
560 {
561 	return hw->nvm.ops.read(hw, offset, words, data);
562 }
563 
564 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
565 				  u16 *data)
566 {
567 	return hw->nvm.ops.write(hw, offset, words, data);
568 }
569 
570 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
571 {
572 	return hw->phy.ops.get_info(hw);
573 }
574 
575 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
576 {
577 	return readl(hw->hw_addr + reg);
578 }
579 
580 #define er32(reg)	__er32(hw, E1000_##reg)
581 
582 s32 __ew32_prepare(struct e1000_hw *hw);
583 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
584 
585 #define ew32(reg, val)	__ew32(hw, E1000_##reg, (val))
586 
587 #define e1e_flush()	er32(STATUS)
588 
589 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
590 	(__ew32((a), (reg + ((offset) << 2)), (value)))
591 
592 #define E1000_READ_REG_ARRAY(a, reg, offset) \
593 	(readl((a)->hw_addr + reg + ((offset) << 2)))
594 
595 #endif /* _E1000_H_ */
596