1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Intel PRO/1000 Linux driver 3 * Copyright(c) 1999 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 * Contact Information: 18 * Linux NICS <linux.nics@intel.com> 19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 21 */ 22 23 /* Linux PRO/1000 Ethernet Driver main header file */ 24 25 #ifndef _E1000_H_ 26 #define _E1000_H_ 27 28 #include <linux/bitops.h> 29 #include <linux/types.h> 30 #include <linux/timer.h> 31 #include <linux/workqueue.h> 32 #include <linux/io.h> 33 #include <linux/netdevice.h> 34 #include <linux/pci.h> 35 #include <linux/pci-aspm.h> 36 #include <linux/crc32.h> 37 #include <linux/if_vlan.h> 38 #include <linux/timecounter.h> 39 #include <linux/net_tstamp.h> 40 #include <linux/ptp_clock_kernel.h> 41 #include <linux/ptp_classify.h> 42 #include <linux/mii.h> 43 #include <linux/mdio.h> 44 #include <linux/pm_qos.h> 45 #include "hw.h" 46 47 struct e1000_info; 48 49 #define e_dbg(format, arg...) \ 50 netdev_dbg(hw->adapter->netdev, format, ## arg) 51 #define e_err(format, arg...) \ 52 netdev_err(adapter->netdev, format, ## arg) 53 #define e_info(format, arg...) \ 54 netdev_info(adapter->netdev, format, ## arg) 55 #define e_warn(format, arg...) \ 56 netdev_warn(adapter->netdev, format, ## arg) 57 #define e_notice(format, arg...) \ 58 netdev_notice(adapter->netdev, format, ## arg) 59 60 /* Interrupt modes, as used by the IntMode parameter */ 61 #define E1000E_INT_MODE_LEGACY 0 62 #define E1000E_INT_MODE_MSI 1 63 #define E1000E_INT_MODE_MSIX 2 64 65 /* Tx/Rx descriptor defines */ 66 #define E1000_DEFAULT_TXD 256 67 #define E1000_MAX_TXD 4096 68 #define E1000_MIN_TXD 64 69 70 #define E1000_DEFAULT_RXD 256 71 #define E1000_MAX_RXD 4096 72 #define E1000_MIN_RXD 64 73 74 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 75 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 76 77 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 78 79 /* How many Tx Descriptors do we need to call netif_wake_queue ? */ 80 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 81 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 82 83 #define AUTO_ALL_MODES 0 84 #define E1000_EEPROM_APME 0x0400 85 86 #define E1000_MNG_VLAN_NONE (-1) 87 88 #define DEFAULT_JUMBO 9234 89 90 /* Time to wait before putting the device into D3 if there's no link (in ms). */ 91 #define LINK_TIMEOUT 100 92 93 /* Count for polling __E1000_RESET condition every 10-20msec. 94 * Experimentation has shown the reset can take approximately 210msec. 95 */ 96 #define E1000_CHECK_RESET_COUNT 25 97 98 #define PCICFG_DESC_RING_STATUS 0xe4 99 #define FLUSH_DESC_REQUIRED 0x100 100 101 /* in the case of WTHRESH, it appears at least the 82571/2 hardware 102 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 103 * WTHRESH=4, so a setting of 5 gives the most efficient bus 104 * utilization but to avoid possible Tx stalls, set it to 1 105 */ 106 #define E1000_TXDCTL_DMA_BURST_ENABLE \ 107 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 108 E1000_TXDCTL_COUNT_DESC | \ 109 (1u << 16) | /* wthresh must be +1 more than desired */\ 110 (1u << 8) | /* hthresh */ \ 111 0x1f) /* pthresh */ 112 113 #define E1000_RXDCTL_DMA_BURST_ENABLE \ 114 (0x01000000 | /* set descriptor granularity */ \ 115 (4u << 16) | /* set writeback threshold */ \ 116 (4u << 8) | /* set prefetch threshold */ \ 117 0x20) /* set hthresh */ 118 119 #define E1000_TIDV_FPD BIT(31) 120 #define E1000_RDTR_FPD BIT(31) 121 122 enum e1000_boards { 123 board_82571, 124 board_82572, 125 board_82573, 126 board_82574, 127 board_82583, 128 board_80003es2lan, 129 board_ich8lan, 130 board_ich9lan, 131 board_ich10lan, 132 board_pchlan, 133 board_pch2lan, 134 board_pch_lpt, 135 board_pch_spt, 136 board_pch_cnp 137 }; 138 139 struct e1000_ps_page { 140 struct page *page; 141 u64 dma; /* must be u64 - written to hw */ 142 }; 143 144 /* wrappers around a pointer to a socket buffer, 145 * so a DMA handle can be stored along with the buffer 146 */ 147 struct e1000_buffer { 148 dma_addr_t dma; 149 struct sk_buff *skb; 150 union { 151 /* Tx */ 152 struct { 153 unsigned long time_stamp; 154 u16 length; 155 u16 next_to_watch; 156 unsigned int segs; 157 unsigned int bytecount; 158 u16 mapped_as_page; 159 }; 160 /* Rx */ 161 struct { 162 /* arrays of page information for packet split */ 163 struct e1000_ps_page *ps_pages; 164 struct page *page; 165 }; 166 }; 167 }; 168 169 struct e1000_ring { 170 struct e1000_adapter *adapter; /* back pointer to adapter */ 171 void *desc; /* pointer to ring memory */ 172 dma_addr_t dma; /* phys address of ring */ 173 unsigned int size; /* length of ring in bytes */ 174 unsigned int count; /* number of desc. in ring */ 175 176 u16 next_to_use; 177 u16 next_to_clean; 178 179 void __iomem *head; 180 void __iomem *tail; 181 182 /* array of buffer information structs */ 183 struct e1000_buffer *buffer_info; 184 185 char name[IFNAMSIZ + 5]; 186 u32 ims_val; 187 u32 itr_val; 188 void __iomem *itr_register; 189 int set_itr; 190 191 struct sk_buff *rx_skb_top; 192 }; 193 194 /* PHY register snapshot values */ 195 struct e1000_phy_regs { 196 u16 bmcr; /* basic mode control register */ 197 u16 bmsr; /* basic mode status register */ 198 u16 advertise; /* auto-negotiation advertisement */ 199 u16 lpa; /* link partner ability register */ 200 u16 expansion; /* auto-negotiation expansion reg */ 201 u16 ctrl1000; /* 1000BASE-T control register */ 202 u16 stat1000; /* 1000BASE-T status register */ 203 u16 estatus; /* extended status register */ 204 }; 205 206 /* board specific private data structure */ 207 struct e1000_adapter { 208 struct timer_list watchdog_timer; 209 struct timer_list phy_info_timer; 210 struct timer_list blink_timer; 211 212 struct work_struct reset_task; 213 struct work_struct watchdog_task; 214 215 const struct e1000_info *ei; 216 217 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 218 u32 bd_number; 219 u32 rx_buffer_len; 220 u16 mng_vlan_id; 221 u16 link_speed; 222 u16 link_duplex; 223 u16 eeprom_vers; 224 225 /* track device up/down/testing state */ 226 unsigned long state; 227 228 /* Interrupt Throttle Rate */ 229 u32 itr; 230 u32 itr_setting; 231 u16 tx_itr; 232 u16 rx_itr; 233 234 /* Tx - one ring per active queue */ 235 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; 236 u32 tx_fifo_limit; 237 238 struct napi_struct napi; 239 240 unsigned int uncorr_errors; /* uncorrectable ECC errors */ 241 unsigned int corr_errors; /* correctable ECC errors */ 242 unsigned int restart_queue; 243 u32 txd_cmd; 244 245 bool detect_tx_hung; 246 bool tx_hang_recheck; 247 u8 tx_timeout_factor; 248 249 u32 tx_int_delay; 250 u32 tx_abs_int_delay; 251 252 unsigned int total_tx_bytes; 253 unsigned int total_tx_packets; 254 unsigned int total_rx_bytes; 255 unsigned int total_rx_packets; 256 257 /* Tx stats */ 258 u64 tpt_old; 259 u64 colc_old; 260 u32 gotc; 261 u64 gotc_old; 262 u32 tx_timeout_count; 263 u32 tx_fifo_head; 264 u32 tx_head_addr; 265 u32 tx_fifo_size; 266 u32 tx_dma_failed; 267 u32 tx_hwtstamp_timeouts; 268 u32 tx_hwtstamp_skipped; 269 270 /* Rx */ 271 bool (*clean_rx)(struct e1000_ring *ring, int *work_done, 272 int work_to_do) ____cacheline_aligned_in_smp; 273 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count, 274 gfp_t gfp); 275 struct e1000_ring *rx_ring; 276 277 u32 rx_int_delay; 278 u32 rx_abs_int_delay; 279 280 /* Rx stats */ 281 u64 hw_csum_err; 282 u64 hw_csum_good; 283 u64 rx_hdr_split; 284 u32 gorc; 285 u64 gorc_old; 286 u32 alloc_rx_buff_failed; 287 u32 rx_dma_failed; 288 u32 rx_hwtstamp_cleared; 289 290 unsigned int rx_ps_pages; 291 u16 rx_ps_bsize0; 292 u32 max_frame_size; 293 u32 min_frame_size; 294 295 /* OS defined structs */ 296 struct net_device *netdev; 297 struct pci_dev *pdev; 298 299 /* structs defined in e1000_hw.h */ 300 struct e1000_hw hw; 301 302 spinlock_t stats64_lock; /* protects statistics counters */ 303 struct e1000_hw_stats stats; 304 struct e1000_phy_info phy_info; 305 struct e1000_phy_stats phy_stats; 306 307 /* Snapshot of PHY registers */ 308 struct e1000_phy_regs phy_regs; 309 310 struct e1000_ring test_tx_ring; 311 struct e1000_ring test_rx_ring; 312 u32 test_icr; 313 314 u32 msg_enable; 315 unsigned int num_vectors; 316 struct msix_entry *msix_entries; 317 int int_mode; 318 u32 eiac_mask; 319 320 u32 eeprom_wol; 321 u32 wol; 322 u32 pba; 323 u32 max_hw_frame_size; 324 325 bool fc_autoneg; 326 327 unsigned int flags; 328 unsigned int flags2; 329 struct work_struct downshift_task; 330 struct work_struct update_phy_task; 331 struct work_struct print_hang_task; 332 333 int phy_hang_count; 334 335 u16 tx_ring_count; 336 u16 rx_ring_count; 337 338 struct hwtstamp_config hwtstamp_config; 339 struct delayed_work systim_overflow_work; 340 struct sk_buff *tx_hwtstamp_skb; 341 unsigned long tx_hwtstamp_start; 342 struct work_struct tx_hwtstamp_work; 343 spinlock_t systim_lock; /* protects SYSTIML/H regsters */ 344 struct cyclecounter cc; 345 struct timecounter tc; 346 struct ptp_clock *ptp_clock; 347 struct ptp_clock_info ptp_clock_info; 348 struct pm_qos_request pm_qos_req; 349 s32 ptp_delta; 350 351 u16 eee_advert; 352 }; 353 354 struct e1000_info { 355 enum e1000_mac_type mac; 356 unsigned int flags; 357 unsigned int flags2; 358 u32 pba; 359 u32 max_hw_frame_size; 360 s32 (*get_variants)(struct e1000_adapter *); 361 const struct e1000_mac_operations *mac_ops; 362 const struct e1000_phy_operations *phy_ops; 363 const struct e1000_nvm_operations *nvm_ops; 364 }; 365 366 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); 367 368 /* The system time is maintained by a 64-bit counter comprised of the 32-bit 369 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore 370 * its resolution) is based on the contents of the TIMINCA register - it 371 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). 372 * For the best accuracy, the incperiod should be as small as possible. The 373 * incvalue is scaled by a factor as large as possible (while still fitting 374 * in bits 23:0) so that relatively small clock corrections can be made. 375 * 376 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of 377 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) 378 * bits to count nanoseconds leaving the rest for fractional nonseconds. 379 */ 380 #define INCVALUE_96MHZ 125 381 #define INCVALUE_SHIFT_96MHZ 17 382 #define INCPERIOD_SHIFT_96MHZ 2 383 #define INCPERIOD_96MHZ (12 >> INCPERIOD_SHIFT_96MHZ) 384 385 #define INCVALUE_25MHZ 40 386 #define INCVALUE_SHIFT_25MHZ 18 387 #define INCPERIOD_25MHZ 1 388 389 #define INCVALUE_24MHZ 125 390 #define INCVALUE_SHIFT_24MHZ 14 391 #define INCPERIOD_24MHZ 3 392 393 #define INCVALUE_38400KHZ 26 394 #define INCVALUE_SHIFT_38400KHZ 19 395 #define INCPERIOD_38400KHZ 1 396 397 /* Another drawback of scaling the incvalue by a large factor is the 398 * 64-bit SYSTIM register overflows more quickly. This is dealt with 399 * by simply reading the clock before it overflows. 400 * 401 * Clock ns bits Overflows after 402 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ 403 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs 404 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours 405 */ 406 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) 407 #define E1000_MAX_82574_SYSTIM_REREADS 50 408 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL) 409 410 /* hardware capability, feature, and workaround flags */ 411 #define FLAG_HAS_AMT BIT(0) 412 #define FLAG_HAS_FLASH BIT(1) 413 #define FLAG_HAS_HW_VLAN_FILTER BIT(2) 414 #define FLAG_HAS_WOL BIT(3) 415 /* reserved BIT(4) */ 416 #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5) 417 #define FLAG_HAS_SWSM_ON_LOAD BIT(6) 418 #define FLAG_HAS_JUMBO_FRAMES BIT(7) 419 #define FLAG_READ_ONLY_NVM BIT(8) 420 #define FLAG_IS_ICH BIT(9) 421 #define FLAG_HAS_MSIX BIT(10) 422 #define FLAG_HAS_SMART_POWER_DOWN BIT(11) 423 #define FLAG_IS_QUAD_PORT_A BIT(12) 424 #define FLAG_IS_QUAD_PORT BIT(13) 425 #define FLAG_HAS_HW_TIMESTAMP BIT(14) 426 #define FLAG_APME_IN_WUC BIT(15) 427 #define FLAG_APME_IN_CTRL3 BIT(16) 428 #define FLAG_APME_CHECK_PORT_B BIT(17) 429 #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18) 430 #define FLAG_NO_WAKE_UCAST BIT(19) 431 #define FLAG_MNG_PT_ENABLED BIT(20) 432 #define FLAG_RESET_OVERWRITES_LAA BIT(21) 433 #define FLAG_TARC_SPEED_MODE_BIT BIT(22) 434 #define FLAG_TARC_SET_BIT_ZERO BIT(23) 435 #define FLAG_RX_NEEDS_RESTART BIT(24) 436 #define FLAG_LSC_GIG_SPEED_DROP BIT(25) 437 #define FLAG_SMART_POWER_DOWN BIT(26) 438 #define FLAG_MSI_ENABLED BIT(27) 439 /* reserved BIT(28) */ 440 #define FLAG_TSO_FORCE BIT(29) 441 #define FLAG_RESTART_NOW BIT(30) 442 #define FLAG_MSI_TEST_FAILED BIT(31) 443 444 #define FLAG2_CRC_STRIPPING BIT(0) 445 #define FLAG2_HAS_PHY_WAKEUP BIT(1) 446 #define FLAG2_IS_DISCARDING BIT(2) 447 #define FLAG2_DISABLE_ASPM_L1 BIT(3) 448 #define FLAG2_HAS_PHY_STATS BIT(4) 449 #define FLAG2_HAS_EEE BIT(5) 450 #define FLAG2_DMA_BURST BIT(6) 451 #define FLAG2_DISABLE_ASPM_L0S BIT(7) 452 #define FLAG2_DISABLE_AIM BIT(8) 453 #define FLAG2_CHECK_PHY_HANG BIT(9) 454 #define FLAG2_NO_DISABLE_RX BIT(10) 455 #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11) 456 #define FLAG2_DFLT_CRC_STRIPPING BIT(12) 457 #define FLAG2_CHECK_RX_HWTSTAMP BIT(13) 458 #define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14) 459 460 #define E1000_RX_DESC_PS(R, i) \ 461 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 462 #define E1000_RX_DESC_EXT(R, i) \ 463 (&(((union e1000_rx_desc_extended *)((R).desc))[i])) 464 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 465 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 466 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 467 468 enum e1000_state_t { 469 __E1000_TESTING, 470 __E1000_RESETTING, 471 __E1000_ACCESS_SHARED_RESOURCE, 472 __E1000_DOWN 473 }; 474 475 enum latency_range { 476 lowest_latency = 0, 477 low_latency = 1, 478 bulk_latency = 2, 479 latency_invalid = 255 480 }; 481 482 extern char e1000e_driver_name[]; 483 extern const char e1000e_driver_version[]; 484 485 void e1000e_check_options(struct e1000_adapter *adapter); 486 void e1000e_set_ethtool_ops(struct net_device *netdev); 487 488 int e1000e_open(struct net_device *netdev); 489 int e1000e_close(struct net_device *netdev); 490 void e1000e_up(struct e1000_adapter *adapter); 491 void e1000e_down(struct e1000_adapter *adapter, bool reset); 492 void e1000e_reinit_locked(struct e1000_adapter *adapter); 493 void e1000e_reset(struct e1000_adapter *adapter); 494 void e1000e_power_up_phy(struct e1000_adapter *adapter); 495 int e1000e_setup_rx_resources(struct e1000_ring *ring); 496 int e1000e_setup_tx_resources(struct e1000_ring *ring); 497 void e1000e_free_rx_resources(struct e1000_ring *ring); 498 void e1000e_free_tx_resources(struct e1000_ring *ring); 499 void e1000e_get_stats64(struct net_device *netdev, 500 struct rtnl_link_stats64 *stats); 501 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 502 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 503 void e1000e_get_hw_control(struct e1000_adapter *adapter); 504 void e1000e_release_hw_control(struct e1000_adapter *adapter); 505 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); 506 507 extern unsigned int copybreak; 508 509 extern const struct e1000_info e1000_82571_info; 510 extern const struct e1000_info e1000_82572_info; 511 extern const struct e1000_info e1000_82573_info; 512 extern const struct e1000_info e1000_82574_info; 513 extern const struct e1000_info e1000_82583_info; 514 extern const struct e1000_info e1000_ich8_info; 515 extern const struct e1000_info e1000_ich9_info; 516 extern const struct e1000_info e1000_ich10_info; 517 extern const struct e1000_info e1000_pch_info; 518 extern const struct e1000_info e1000_pch2_info; 519 extern const struct e1000_info e1000_pch_lpt_info; 520 extern const struct e1000_info e1000_pch_spt_info; 521 extern const struct e1000_info e1000_pch_cnp_info; 522 extern const struct e1000_info e1000_es2_info; 523 524 void e1000e_ptp_init(struct e1000_adapter *adapter); 525 void e1000e_ptp_remove(struct e1000_adapter *adapter); 526 527 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 528 { 529 return hw->phy.ops.reset(hw); 530 } 531 532 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 533 { 534 return hw->phy.ops.read_reg(hw, offset, data); 535 } 536 537 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) 538 { 539 return hw->phy.ops.read_reg_locked(hw, offset, data); 540 } 541 542 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 543 { 544 return hw->phy.ops.write_reg(hw, offset, data); 545 } 546 547 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) 548 { 549 return hw->phy.ops.write_reg_locked(hw, offset, data); 550 } 551 552 void e1000e_reload_nvm_generic(struct e1000_hw *hw); 553 554 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 555 { 556 if (hw->mac.ops.read_mac_addr) 557 return hw->mac.ops.read_mac_addr(hw); 558 559 return e1000_read_mac_addr_generic(hw); 560 } 561 562 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 563 { 564 return hw->nvm.ops.validate(hw); 565 } 566 567 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 568 { 569 return hw->nvm.ops.update(hw); 570 } 571 572 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, 573 u16 *data) 574 { 575 return hw->nvm.ops.read(hw, offset, words, data); 576 } 577 578 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, 579 u16 *data) 580 { 581 return hw->nvm.ops.write(hw, offset, words, data); 582 } 583 584 static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 585 { 586 return hw->phy.ops.get_info(hw); 587 } 588 589 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 590 { 591 return readl(hw->hw_addr + reg); 592 } 593 594 #define er32(reg) __er32(hw, E1000_##reg) 595 596 s32 __ew32_prepare(struct e1000_hw *hw); 597 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); 598 599 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 600 601 #define e1e_flush() er32(STATUS) 602 603 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 604 (__ew32((a), (reg + ((offset) << 2)), (value))) 605 606 #define E1000_READ_REG_ARRAY(a, reg, offset) \ 607 (readl((a)->hw_addr + reg + ((offset) << 2))) 608 609 #endif /* _E1000_H_ */ 610