1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 /* Linux PRO/1000 Ethernet Driver main header file */ 23 24 #ifndef _E1000_H_ 25 #define _E1000_H_ 26 27 #include <linux/bitops.h> 28 #include <linux/types.h> 29 #include <linux/timer.h> 30 #include <linux/workqueue.h> 31 #include <linux/io.h> 32 #include <linux/netdevice.h> 33 #include <linux/pci.h> 34 #include <linux/pci-aspm.h> 35 #include <linux/crc32.h> 36 #include <linux/if_vlan.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/ptp_clock_kernel.h> 40 #include <linux/ptp_classify.h> 41 #include <linux/mii.h> 42 #include <linux/mdio.h> 43 #include <linux/pm_qos.h> 44 #include "hw.h" 45 46 struct e1000_info; 47 48 #define e_dbg(format, arg...) \ 49 netdev_dbg(hw->adapter->netdev, format, ## arg) 50 #define e_err(format, arg...) \ 51 netdev_err(adapter->netdev, format, ## arg) 52 #define e_info(format, arg...) \ 53 netdev_info(adapter->netdev, format, ## arg) 54 #define e_warn(format, arg...) \ 55 netdev_warn(adapter->netdev, format, ## arg) 56 #define e_notice(format, arg...) \ 57 netdev_notice(adapter->netdev, format, ## arg) 58 59 /* Interrupt modes, as used by the IntMode parameter */ 60 #define E1000E_INT_MODE_LEGACY 0 61 #define E1000E_INT_MODE_MSI 1 62 #define E1000E_INT_MODE_MSIX 2 63 64 /* Tx/Rx descriptor defines */ 65 #define E1000_DEFAULT_TXD 256 66 #define E1000_MAX_TXD 4096 67 #define E1000_MIN_TXD 64 68 69 #define E1000_DEFAULT_RXD 256 70 #define E1000_MAX_RXD 4096 71 #define E1000_MIN_RXD 64 72 73 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 74 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 75 76 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 77 78 /* How many Tx Descriptors do we need to call netif_wake_queue ? */ 79 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 80 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 81 82 #define AUTO_ALL_MODES 0 83 #define E1000_EEPROM_APME 0x0400 84 85 #define E1000_MNG_VLAN_NONE (-1) 86 87 #define DEFAULT_JUMBO 9234 88 89 /* Time to wait before putting the device into D3 if there's no link (in ms). */ 90 #define LINK_TIMEOUT 100 91 92 /* Count for polling __E1000_RESET condition every 10-20msec. 93 * Experimentation has shown the reset can take approximately 210msec. 94 */ 95 #define E1000_CHECK_RESET_COUNT 25 96 97 #define DEFAULT_RDTR 0 98 #define DEFAULT_RADV 8 99 #define BURST_RDTR 0x20 100 #define BURST_RADV 0x20 101 #define PCICFG_DESC_RING_STATUS 0xe4 102 #define FLUSH_DESC_REQUIRED 0x100 103 104 /* in the case of WTHRESH, it appears at least the 82571/2 hardware 105 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 106 * WTHRESH=4, so a setting of 5 gives the most efficient bus 107 * utilization but to avoid possible Tx stalls, set it to 1 108 */ 109 #define E1000_TXDCTL_DMA_BURST_ENABLE \ 110 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 111 E1000_TXDCTL_COUNT_DESC | \ 112 (1u << 16) | /* wthresh must be +1 more than desired */\ 113 (1u << 8) | /* hthresh */ \ 114 0x1f) /* pthresh */ 115 116 #define E1000_RXDCTL_DMA_BURST_ENABLE \ 117 (0x01000000 | /* set descriptor granularity */ \ 118 (4u << 16) | /* set writeback threshold */ \ 119 (4u << 8) | /* set prefetch threshold */ \ 120 0x20) /* set hthresh */ 121 122 #define E1000_TIDV_FPD BIT(31) 123 #define E1000_RDTR_FPD BIT(31) 124 125 enum e1000_boards { 126 board_82571, 127 board_82572, 128 board_82573, 129 board_82574, 130 board_82583, 131 board_80003es2lan, 132 board_ich8lan, 133 board_ich9lan, 134 board_ich10lan, 135 board_pchlan, 136 board_pch2lan, 137 board_pch_lpt, 138 board_pch_spt 139 }; 140 141 struct e1000_ps_page { 142 struct page *page; 143 u64 dma; /* must be u64 - written to hw */ 144 }; 145 146 /* wrappers around a pointer to a socket buffer, 147 * so a DMA handle can be stored along with the buffer 148 */ 149 struct e1000_buffer { 150 dma_addr_t dma; 151 struct sk_buff *skb; 152 union { 153 /* Tx */ 154 struct { 155 unsigned long time_stamp; 156 u16 length; 157 u16 next_to_watch; 158 unsigned int segs; 159 unsigned int bytecount; 160 u16 mapped_as_page; 161 }; 162 /* Rx */ 163 struct { 164 /* arrays of page information for packet split */ 165 struct e1000_ps_page *ps_pages; 166 struct page *page; 167 }; 168 }; 169 }; 170 171 struct e1000_ring { 172 struct e1000_adapter *adapter; /* back pointer to adapter */ 173 void *desc; /* pointer to ring memory */ 174 dma_addr_t dma; /* phys address of ring */ 175 unsigned int size; /* length of ring in bytes */ 176 unsigned int count; /* number of desc. in ring */ 177 178 u16 next_to_use; 179 u16 next_to_clean; 180 181 void __iomem *head; 182 void __iomem *tail; 183 184 /* array of buffer information structs */ 185 struct e1000_buffer *buffer_info; 186 187 char name[IFNAMSIZ + 5]; 188 u32 ims_val; 189 u32 itr_val; 190 void __iomem *itr_register; 191 int set_itr; 192 193 struct sk_buff *rx_skb_top; 194 }; 195 196 /* PHY register snapshot values */ 197 struct e1000_phy_regs { 198 u16 bmcr; /* basic mode control register */ 199 u16 bmsr; /* basic mode status register */ 200 u16 advertise; /* auto-negotiation advertisement */ 201 u16 lpa; /* link partner ability register */ 202 u16 expansion; /* auto-negotiation expansion reg */ 203 u16 ctrl1000; /* 1000BASE-T control register */ 204 u16 stat1000; /* 1000BASE-T status register */ 205 u16 estatus; /* extended status register */ 206 }; 207 208 /* board specific private data structure */ 209 struct e1000_adapter { 210 struct timer_list watchdog_timer; 211 struct timer_list phy_info_timer; 212 struct timer_list blink_timer; 213 214 struct work_struct reset_task; 215 struct work_struct watchdog_task; 216 217 const struct e1000_info *ei; 218 219 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 220 u32 bd_number; 221 u32 rx_buffer_len; 222 u16 mng_vlan_id; 223 u16 link_speed; 224 u16 link_duplex; 225 u16 eeprom_vers; 226 227 /* track device up/down/testing state */ 228 unsigned long state; 229 230 /* Interrupt Throttle Rate */ 231 u32 itr; 232 u32 itr_setting; 233 u16 tx_itr; 234 u16 rx_itr; 235 236 /* Tx - one ring per active queue */ 237 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; 238 u32 tx_fifo_limit; 239 240 struct napi_struct napi; 241 242 unsigned int uncorr_errors; /* uncorrectable ECC errors */ 243 unsigned int corr_errors; /* correctable ECC errors */ 244 unsigned int restart_queue; 245 u32 txd_cmd; 246 247 bool detect_tx_hung; 248 bool tx_hang_recheck; 249 u8 tx_timeout_factor; 250 251 u32 tx_int_delay; 252 u32 tx_abs_int_delay; 253 254 unsigned int total_tx_bytes; 255 unsigned int total_tx_packets; 256 unsigned int total_rx_bytes; 257 unsigned int total_rx_packets; 258 259 /* Tx stats */ 260 u64 tpt_old; 261 u64 colc_old; 262 u32 gotc; 263 u64 gotc_old; 264 u32 tx_timeout_count; 265 u32 tx_fifo_head; 266 u32 tx_head_addr; 267 u32 tx_fifo_size; 268 u32 tx_dma_failed; 269 u32 tx_hwtstamp_timeouts; 270 271 /* Rx */ 272 bool (*clean_rx)(struct e1000_ring *ring, int *work_done, 273 int work_to_do) ____cacheline_aligned_in_smp; 274 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count, 275 gfp_t gfp); 276 struct e1000_ring *rx_ring; 277 278 u32 rx_int_delay; 279 u32 rx_abs_int_delay; 280 281 /* Rx stats */ 282 u64 hw_csum_err; 283 u64 hw_csum_good; 284 u64 rx_hdr_split; 285 u32 gorc; 286 u64 gorc_old; 287 u32 alloc_rx_buff_failed; 288 u32 rx_dma_failed; 289 u32 rx_hwtstamp_cleared; 290 291 unsigned int rx_ps_pages; 292 u16 rx_ps_bsize0; 293 u32 max_frame_size; 294 u32 min_frame_size; 295 296 /* OS defined structs */ 297 struct net_device *netdev; 298 struct pci_dev *pdev; 299 300 /* structs defined in e1000_hw.h */ 301 struct e1000_hw hw; 302 303 spinlock_t stats64_lock; /* protects statistics counters */ 304 struct e1000_hw_stats stats; 305 struct e1000_phy_info phy_info; 306 struct e1000_phy_stats phy_stats; 307 308 /* Snapshot of PHY registers */ 309 struct e1000_phy_regs phy_regs; 310 311 struct e1000_ring test_tx_ring; 312 struct e1000_ring test_rx_ring; 313 u32 test_icr; 314 315 u32 msg_enable; 316 unsigned int num_vectors; 317 struct msix_entry *msix_entries; 318 int int_mode; 319 u32 eiac_mask; 320 321 u32 eeprom_wol; 322 u32 wol; 323 u32 pba; 324 u32 max_hw_frame_size; 325 326 bool fc_autoneg; 327 328 unsigned int flags; 329 unsigned int flags2; 330 struct work_struct downshift_task; 331 struct work_struct update_phy_task; 332 struct work_struct print_hang_task; 333 334 int phy_hang_count; 335 336 u16 tx_ring_count; 337 u16 rx_ring_count; 338 339 struct hwtstamp_config hwtstamp_config; 340 struct delayed_work systim_overflow_work; 341 struct sk_buff *tx_hwtstamp_skb; 342 unsigned long tx_hwtstamp_start; 343 struct work_struct tx_hwtstamp_work; 344 spinlock_t systim_lock; /* protects SYSTIML/H regsters */ 345 struct cyclecounter cc; 346 struct timecounter tc; 347 struct ptp_clock *ptp_clock; 348 struct ptp_clock_info ptp_clock_info; 349 struct pm_qos_request pm_qos_req; 350 s32 ptp_delta; 351 352 u16 eee_advert; 353 }; 354 355 struct e1000_info { 356 enum e1000_mac_type mac; 357 unsigned int flags; 358 unsigned int flags2; 359 u32 pba; 360 u32 max_hw_frame_size; 361 s32 (*get_variants)(struct e1000_adapter *); 362 const struct e1000_mac_operations *mac_ops; 363 const struct e1000_phy_operations *phy_ops; 364 const struct e1000_nvm_operations *nvm_ops; 365 }; 366 367 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); 368 369 /* The system time is maintained by a 64-bit counter comprised of the 32-bit 370 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore 371 * its resolution) is based on the contents of the TIMINCA register - it 372 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). 373 * For the best accuracy, the incperiod should be as small as possible. The 374 * incvalue is scaled by a factor as large as possible (while still fitting 375 * in bits 23:0) so that relatively small clock corrections can be made. 376 * 377 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of 378 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) 379 * bits to count nanoseconds leaving the rest for fractional nonseconds. 380 */ 381 #define INCVALUE_96MHz 125 382 #define INCVALUE_SHIFT_96MHz 17 383 #define INCPERIOD_SHIFT_96MHz 2 384 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz) 385 386 #define INCVALUE_25MHz 40 387 #define INCVALUE_SHIFT_25MHz 18 388 #define INCPERIOD_25MHz 1 389 390 #define INCVALUE_24MHz 125 391 #define INCVALUE_SHIFT_24MHz 14 392 #define INCPERIOD_24MHz 3 393 394 /* Another drawback of scaling the incvalue by a large factor is the 395 * 64-bit SYSTIM register overflows more quickly. This is dealt with 396 * by simply reading the clock before it overflows. 397 * 398 * Clock ns bits Overflows after 399 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ 400 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs 401 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours 402 */ 403 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) 404 #define E1000_MAX_82574_SYSTIM_REREADS 50 405 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL) 406 407 /* hardware capability, feature, and workaround flags */ 408 #define FLAG_HAS_AMT BIT(0) 409 #define FLAG_HAS_FLASH BIT(1) 410 #define FLAG_HAS_HW_VLAN_FILTER BIT(2) 411 #define FLAG_HAS_WOL BIT(3) 412 /* reserved BIT(4) */ 413 #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5) 414 #define FLAG_HAS_SWSM_ON_LOAD BIT(6) 415 #define FLAG_HAS_JUMBO_FRAMES BIT(7) 416 #define FLAG_READ_ONLY_NVM BIT(8) 417 #define FLAG_IS_ICH BIT(9) 418 #define FLAG_HAS_MSIX BIT(10) 419 #define FLAG_HAS_SMART_POWER_DOWN BIT(11) 420 #define FLAG_IS_QUAD_PORT_A BIT(12) 421 #define FLAG_IS_QUAD_PORT BIT(13) 422 #define FLAG_HAS_HW_TIMESTAMP BIT(14) 423 #define FLAG_APME_IN_WUC BIT(15) 424 #define FLAG_APME_IN_CTRL3 BIT(16) 425 #define FLAG_APME_CHECK_PORT_B BIT(17) 426 #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18) 427 #define FLAG_NO_WAKE_UCAST BIT(19) 428 #define FLAG_MNG_PT_ENABLED BIT(20) 429 #define FLAG_RESET_OVERWRITES_LAA BIT(21) 430 #define FLAG_TARC_SPEED_MODE_BIT BIT(22) 431 #define FLAG_TARC_SET_BIT_ZERO BIT(23) 432 #define FLAG_RX_NEEDS_RESTART BIT(24) 433 #define FLAG_LSC_GIG_SPEED_DROP BIT(25) 434 #define FLAG_SMART_POWER_DOWN BIT(26) 435 #define FLAG_MSI_ENABLED BIT(27) 436 /* reserved BIT(28) */ 437 #define FLAG_TSO_FORCE BIT(29) 438 #define FLAG_RESTART_NOW BIT(30) 439 #define FLAG_MSI_TEST_FAILED BIT(31) 440 441 #define FLAG2_CRC_STRIPPING BIT(0) 442 #define FLAG2_HAS_PHY_WAKEUP BIT(1) 443 #define FLAG2_IS_DISCARDING BIT(2) 444 #define FLAG2_DISABLE_ASPM_L1 BIT(3) 445 #define FLAG2_HAS_PHY_STATS BIT(4) 446 #define FLAG2_HAS_EEE BIT(5) 447 #define FLAG2_DMA_BURST BIT(6) 448 #define FLAG2_DISABLE_ASPM_L0S BIT(7) 449 #define FLAG2_DISABLE_AIM BIT(8) 450 #define FLAG2_CHECK_PHY_HANG BIT(9) 451 #define FLAG2_NO_DISABLE_RX BIT(10) 452 #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11) 453 #define FLAG2_DFLT_CRC_STRIPPING BIT(12) 454 #define FLAG2_CHECK_RX_HWTSTAMP BIT(13) 455 456 #define E1000_RX_DESC_PS(R, i) \ 457 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 458 #define E1000_RX_DESC_EXT(R, i) \ 459 (&(((union e1000_rx_desc_extended *)((R).desc))[i])) 460 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 461 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 462 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 463 464 enum e1000_state_t { 465 __E1000_TESTING, 466 __E1000_RESETTING, 467 __E1000_ACCESS_SHARED_RESOURCE, 468 __E1000_DOWN 469 }; 470 471 enum latency_range { 472 lowest_latency = 0, 473 low_latency = 1, 474 bulk_latency = 2, 475 latency_invalid = 255 476 }; 477 478 extern char e1000e_driver_name[]; 479 extern const char e1000e_driver_version[]; 480 481 void e1000e_check_options(struct e1000_adapter *adapter); 482 void e1000e_set_ethtool_ops(struct net_device *netdev); 483 484 int e1000e_open(struct net_device *netdev); 485 int e1000e_close(struct net_device *netdev); 486 void e1000e_up(struct e1000_adapter *adapter); 487 void e1000e_down(struct e1000_adapter *adapter, bool reset); 488 void e1000e_reinit_locked(struct e1000_adapter *adapter); 489 void e1000e_reset(struct e1000_adapter *adapter); 490 void e1000e_power_up_phy(struct e1000_adapter *adapter); 491 int e1000e_setup_rx_resources(struct e1000_ring *ring); 492 int e1000e_setup_tx_resources(struct e1000_ring *ring); 493 void e1000e_free_rx_resources(struct e1000_ring *ring); 494 void e1000e_free_tx_resources(struct e1000_ring *ring); 495 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 496 struct rtnl_link_stats64 *stats); 497 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 498 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 499 void e1000e_get_hw_control(struct e1000_adapter *adapter); 500 void e1000e_release_hw_control(struct e1000_adapter *adapter); 501 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); 502 503 extern unsigned int copybreak; 504 505 extern const struct e1000_info e1000_82571_info; 506 extern const struct e1000_info e1000_82572_info; 507 extern const struct e1000_info e1000_82573_info; 508 extern const struct e1000_info e1000_82574_info; 509 extern const struct e1000_info e1000_82583_info; 510 extern const struct e1000_info e1000_ich8_info; 511 extern const struct e1000_info e1000_ich9_info; 512 extern const struct e1000_info e1000_ich10_info; 513 extern const struct e1000_info e1000_pch_info; 514 extern const struct e1000_info e1000_pch2_info; 515 extern const struct e1000_info e1000_pch_lpt_info; 516 extern const struct e1000_info e1000_pch_spt_info; 517 extern const struct e1000_info e1000_es2_info; 518 519 void e1000e_ptp_init(struct e1000_adapter *adapter); 520 void e1000e_ptp_remove(struct e1000_adapter *adapter); 521 522 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 523 { 524 return hw->phy.ops.reset(hw); 525 } 526 527 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 528 { 529 return hw->phy.ops.read_reg(hw, offset, data); 530 } 531 532 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) 533 { 534 return hw->phy.ops.read_reg_locked(hw, offset, data); 535 } 536 537 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 538 { 539 return hw->phy.ops.write_reg(hw, offset, data); 540 } 541 542 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) 543 { 544 return hw->phy.ops.write_reg_locked(hw, offset, data); 545 } 546 547 void e1000e_reload_nvm_generic(struct e1000_hw *hw); 548 549 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 550 { 551 if (hw->mac.ops.read_mac_addr) 552 return hw->mac.ops.read_mac_addr(hw); 553 554 return e1000_read_mac_addr_generic(hw); 555 } 556 557 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 558 { 559 return hw->nvm.ops.validate(hw); 560 } 561 562 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 563 { 564 return hw->nvm.ops.update(hw); 565 } 566 567 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, 568 u16 *data) 569 { 570 return hw->nvm.ops.read(hw, offset, words, data); 571 } 572 573 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, 574 u16 *data) 575 { 576 return hw->nvm.ops.write(hw, offset, words, data); 577 } 578 579 static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 580 { 581 return hw->phy.ops.get_info(hw); 582 } 583 584 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 585 { 586 return readl(hw->hw_addr + reg); 587 } 588 589 #define er32(reg) __er32(hw, E1000_##reg) 590 591 s32 __ew32_prepare(struct e1000_hw *hw); 592 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); 593 594 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 595 596 #define e1e_flush() er32(STATUS) 597 598 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 599 (__ew32((a), (reg + ((offset) << 2)), (value))) 600 601 #define E1000_READ_REG_ARRAY(a, reg, offset) \ 602 (readl((a)->hw_addr + reg + ((offset) << 2))) 603 604 #endif /* _E1000_H_ */ 605