1 /****************************************************************************/ 2 3 /* 4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 5 * processors. 6 * 7 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 8 * (C) Copyright 2000-2001, Lineo (www.lineo.com) 9 */ 10 11 /****************************************************************************/ 12 #ifndef FEC_H 13 #define FEC_H 14 /****************************************************************************/ 15 16 #include <linux/clocksource.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 20 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 21 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ 22 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 23 /* 24 * Just figures, Motorola would have to change the offsets for 25 * registers in the same peripheral device on different models 26 * of the ColdFire! 27 */ 28 #define FEC_IEVENT 0x004 /* Interrupt event reg */ 29 #define FEC_IMASK 0x008 /* Interrupt mask reg */ 30 #define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ 31 #define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ 32 #define FEC_ECNTRL 0x024 /* Ethernet control reg */ 33 #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 34 #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 35 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 36 #define FEC_R_CNTRL 0x084 /* Receive control reg */ 37 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 38 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 39 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 40 #define FEC_OPD 0x0ec /* Opcode + Pause duration */ 41 #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 42 #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 43 #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 44 #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 45 #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 46 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 47 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 48 #define FEC_R_DES_START 0x180 /* Receive descriptor ring */ 49 #define FEC_X_DES_START 0x184 /* Transmit descriptor ring */ 50 #define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ 51 #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */ 52 #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ 53 #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ 54 #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ 55 #define FEC_RACC 0x1C4 /* Receive Accelerator function */ 56 #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 57 #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 58 59 #define BM_MIIGSK_CFGR_MII 0x00 60 #define BM_MIIGSK_CFGR_RMII 0x01 61 #define BM_MIIGSK_CFGR_FRCONT_10M 0x40 62 63 #else 64 65 #define FEC_ECNTRL 0x000 /* Ethernet control reg */ 66 #define FEC_IEVENT 0x004 /* Interrupt even reg */ 67 #define FEC_IMASK 0x008 /* Interrupt mask reg */ 68 #define FEC_IVEC 0x00c /* Interrupt vec status reg */ 69 #define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ 70 #define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ 71 #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 72 #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 73 #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 74 #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 75 #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 76 #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 77 #define FEC_R_CNTRL 0x104 /* Receive control reg */ 78 #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 79 #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 80 #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 81 #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 82 #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 83 #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 84 #define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */ 85 #define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */ 86 #define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */ 87 #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 88 89 #endif /* CONFIG_M5272 */ 90 91 92 /* 93 * Define the buffer descriptor structure. 94 */ 95 #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 96 struct bufdesc { 97 unsigned short cbd_datlen; /* Data length */ 98 unsigned short cbd_sc; /* Control and status info */ 99 unsigned long cbd_bufaddr; /* Buffer address */ 100 }; 101 #else 102 struct bufdesc { 103 unsigned short cbd_sc; /* Control and status info */ 104 unsigned short cbd_datlen; /* Data length */ 105 unsigned long cbd_bufaddr; /* Buffer address */ 106 }; 107 #endif 108 109 struct bufdesc_ex { 110 struct bufdesc desc; 111 unsigned long cbd_esc; 112 unsigned long cbd_prot; 113 unsigned long cbd_bdu; 114 unsigned long ts; 115 unsigned short res0[4]; 116 }; 117 118 /* 119 * The following definitions courtesy of commproc.h, which where 120 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 121 */ 122 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 123 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 124 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 125 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 126 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 127 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 128 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 129 #define BD_SC_BR ((ushort)0x0020) /* Break received */ 130 #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 131 #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 132 #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 133 #define BD_SC_CD ((ushort)0x0001) /* ?? */ 134 135 /* Buffer descriptor control/status used by Ethernet receive. 136 */ 137 #define BD_ENET_RX_EMPTY ((ushort)0x8000) 138 #define BD_ENET_RX_WRAP ((ushort)0x2000) 139 #define BD_ENET_RX_INTR ((ushort)0x1000) 140 #define BD_ENET_RX_LAST ((ushort)0x0800) 141 #define BD_ENET_RX_FIRST ((ushort)0x0400) 142 #define BD_ENET_RX_MISS ((ushort)0x0100) 143 #define BD_ENET_RX_LG ((ushort)0x0020) 144 #define BD_ENET_RX_NO ((ushort)0x0010) 145 #define BD_ENET_RX_SH ((ushort)0x0008) 146 #define BD_ENET_RX_CR ((ushort)0x0004) 147 #define BD_ENET_RX_OV ((ushort)0x0002) 148 #define BD_ENET_RX_CL ((ushort)0x0001) 149 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 150 151 /* Buffer descriptor control/status used by Ethernet transmit. 152 */ 153 #define BD_ENET_TX_READY ((ushort)0x8000) 154 #define BD_ENET_TX_PAD ((ushort)0x4000) 155 #define BD_ENET_TX_WRAP ((ushort)0x2000) 156 #define BD_ENET_TX_INTR ((ushort)0x1000) 157 #define BD_ENET_TX_LAST ((ushort)0x0800) 158 #define BD_ENET_TX_TC ((ushort)0x0400) 159 #define BD_ENET_TX_DEF ((ushort)0x0200) 160 #define BD_ENET_TX_HB ((ushort)0x0100) 161 #define BD_ENET_TX_LC ((ushort)0x0080) 162 #define BD_ENET_TX_RL ((ushort)0x0040) 163 #define BD_ENET_TX_RCMASK ((ushort)0x003c) 164 #define BD_ENET_TX_UN ((ushort)0x0002) 165 #define BD_ENET_TX_CSL ((ushort)0x0001) 166 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 167 168 /*enhanced buffer descriptor control/status used by Ethernet transmit*/ 169 #define BD_ENET_TX_INT 0x40000000 170 #define BD_ENET_TX_TS 0x20000000 171 #define BD_ENET_TX_PINS 0x10000000 172 #define BD_ENET_TX_IINS 0x08000000 173 174 175 /* This device has up to three irqs on some platforms */ 176 #define FEC_IRQ_NUM 3 177 178 /* The number of Tx and Rx buffers. These are allocated from the page 179 * pool. The code may assume these are power of two, so it it best 180 * to keep them that size. 181 * We don't need to allocate pages for the transmitter. We just use 182 * the skbuffer directly. 183 */ 184 185 #define FEC_ENET_RX_PAGES 8 186 #define FEC_ENET_RX_FRSIZE 2048 187 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 188 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 189 #define FEC_ENET_TX_FRSIZE 2048 190 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 191 #define TX_RING_SIZE 16 /* Must be power of two */ 192 #define TX_RING_MOD_MASK 15 /* for this to work */ 193 194 #define BD_ENET_RX_INT 0x00800000 195 #define BD_ENET_RX_PTP ((ushort)0x0400) 196 #define BD_ENET_RX_ICE 0x00000020 197 #define BD_ENET_RX_PCR 0x00000010 198 #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 199 #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 200 201 struct fec_enet_delayed_work { 202 struct delayed_work delay_work; 203 bool timeout; 204 }; 205 206 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 207 * tx_bd_base always point to the base of the buffer descriptors. The 208 * cur_rx and cur_tx point to the currently available buffer. 209 * The dirty_tx tracks the current buffer that is being sent by the 210 * controller. The cur_tx and dirty_tx are equal under both completely 211 * empty and completely full conditions. The empty/ready indicator in 212 * the buffer descriptor determines the actual condition. 213 */ 214 struct fec_enet_private { 215 /* Hardware registers of the FEC device */ 216 void __iomem *hwp; 217 218 struct net_device *netdev; 219 220 struct clk *clk_ipg; 221 struct clk *clk_ahb; 222 struct clk *clk_enet_out; 223 struct clk *clk_ptp; 224 225 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 226 unsigned char *tx_bounce[TX_RING_SIZE]; 227 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 228 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 229 230 /* CPM dual port RAM relative addresses */ 231 dma_addr_t bd_dma; 232 /* Address of Rx and Tx buffers */ 233 struct bufdesc *rx_bd_base; 234 struct bufdesc *tx_bd_base; 235 /* The next free ring entry */ 236 struct bufdesc *cur_rx, *cur_tx; 237 /* The ring entries to be free()ed */ 238 struct bufdesc *dirty_tx; 239 240 struct platform_device *pdev; 241 242 int opened; 243 int dev_id; 244 245 /* Phylib and MDIO interface */ 246 struct mii_bus *mii_bus; 247 struct phy_device *phy_dev; 248 int mii_timeout; 249 uint phy_speed; 250 phy_interface_t phy_interface; 251 int link; 252 int full_duplex; 253 int speed; 254 struct completion mdio_done; 255 int irq[FEC_IRQ_NUM]; 256 int bufdesc_ex; 257 int pause_flag; 258 259 struct napi_struct napi; 260 int csum_flags; 261 262 struct ptp_clock *ptp_clock; 263 struct ptp_clock_info ptp_caps; 264 unsigned long last_overflow_check; 265 spinlock_t tmreg_lock; 266 struct cyclecounter cc; 267 struct timecounter tc; 268 int rx_hwtstamp_filter; 269 u32 base_incval; 270 u32 cycle_speed; 271 int hwts_rx_en; 272 int hwts_tx_en; 273 struct timer_list time_keep; 274 struct fec_enet_delayed_work delay_work; 275 }; 276 277 void fec_ptp_init(struct net_device *ndev, struct platform_device *pdev); 278 void fec_ptp_start_cyclecounter(struct net_device *ndev); 279 int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd); 280 281 /****************************************************************************/ 282 #endif /* FEC_H */ 283