1 /****************************************************************************/ 2 3 /* 4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 5 * processors. 6 * 7 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 8 * (C) Copyright 2000-2001, Lineo (www.lineo.com) 9 */ 10 11 /****************************************************************************/ 12 #ifndef FEC_H 13 #define FEC_H 14 /****************************************************************************/ 15 16 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 17 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ 18 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 19 /* 20 * Just figures, Motorola would have to change the offsets for 21 * registers in the same peripheral device on different models 22 * of the ColdFire! 23 */ 24 #define FEC_IEVENT 0x004 /* Interrupt event reg */ 25 #define FEC_IMASK 0x008 /* Interrupt mask reg */ 26 #define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ 27 #define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ 28 #define FEC_ECNTRL 0x024 /* Ethernet control reg */ 29 #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 30 #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 31 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 32 #define FEC_R_CNTRL 0x084 /* Receive control reg */ 33 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 34 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 35 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 36 #define FEC_OPD 0x0ec /* Opcode + Pause duration */ 37 #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 38 #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 39 #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 40 #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 41 #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 42 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 43 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 44 #define FEC_R_DES_START 0x180 /* Receive descriptor ring */ 45 #define FEC_X_DES_START 0x184 /* Transmit descriptor ring */ 46 #define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ 47 #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 48 #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 49 50 #define BM_MIIGSK_CFGR_MII 0x00 51 #define BM_MIIGSK_CFGR_RMII 0x01 52 #define BM_MIIGSK_CFGR_FRCONT_10M 0x40 53 54 #else 55 56 #define FEC_ECNTRL 0x000 /* Ethernet control reg */ 57 #define FEC_IEVENT 0x004 /* Interrupt even reg */ 58 #define FEC_IMASK 0x008 /* Interrupt mask reg */ 59 #define FEC_IVEC 0x00c /* Interrupt vec status reg */ 60 #define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ 61 #define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ 62 #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 63 #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 64 #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 65 #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 66 #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 67 #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 68 #define FEC_R_CNTRL 0x104 /* Receive control reg */ 69 #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 70 #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 71 #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 72 #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 73 #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 74 #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 75 #define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */ 76 #define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */ 77 #define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */ 78 #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 79 80 #endif /* CONFIG_M5272 */ 81 82 83 /* 84 * Define the buffer descriptor structure. 85 */ 86 #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) 87 struct bufdesc { 88 unsigned short cbd_datlen; /* Data length */ 89 unsigned short cbd_sc; /* Control and status info */ 90 unsigned long cbd_bufaddr; /* Buffer address */ 91 }; 92 #else 93 struct bufdesc { 94 unsigned short cbd_sc; /* Control and status info */ 95 unsigned short cbd_datlen; /* Data length */ 96 unsigned long cbd_bufaddr; /* Buffer address */ 97 }; 98 #endif 99 100 /* 101 * The following definitions courtesy of commproc.h, which where 102 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 103 */ 104 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 105 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 106 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 107 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 108 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 109 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 110 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 111 #define BD_SC_BR ((ushort)0x0020) /* Break received */ 112 #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 113 #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 114 #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 115 #define BD_SC_CD ((ushort)0x0001) /* ?? */ 116 117 /* Buffer descriptor control/status used by Ethernet receive. 118 */ 119 #define BD_ENET_RX_EMPTY ((ushort)0x8000) 120 #define BD_ENET_RX_WRAP ((ushort)0x2000) 121 #define BD_ENET_RX_INTR ((ushort)0x1000) 122 #define BD_ENET_RX_LAST ((ushort)0x0800) 123 #define BD_ENET_RX_FIRST ((ushort)0x0400) 124 #define BD_ENET_RX_MISS ((ushort)0x0100) 125 #define BD_ENET_RX_LG ((ushort)0x0020) 126 #define BD_ENET_RX_NO ((ushort)0x0010) 127 #define BD_ENET_RX_SH ((ushort)0x0008) 128 #define BD_ENET_RX_CR ((ushort)0x0004) 129 #define BD_ENET_RX_OV ((ushort)0x0002) 130 #define BD_ENET_RX_CL ((ushort)0x0001) 131 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 132 133 /* Buffer descriptor control/status used by Ethernet transmit. 134 */ 135 #define BD_ENET_TX_READY ((ushort)0x8000) 136 #define BD_ENET_TX_PAD ((ushort)0x4000) 137 #define BD_ENET_TX_WRAP ((ushort)0x2000) 138 #define BD_ENET_TX_INTR ((ushort)0x1000) 139 #define BD_ENET_TX_LAST ((ushort)0x0800) 140 #define BD_ENET_TX_TC ((ushort)0x0400) 141 #define BD_ENET_TX_DEF ((ushort)0x0200) 142 #define BD_ENET_TX_HB ((ushort)0x0100) 143 #define BD_ENET_TX_LC ((ushort)0x0080) 144 #define BD_ENET_TX_RL ((ushort)0x0040) 145 #define BD_ENET_TX_RCMASK ((ushort)0x003c) 146 #define BD_ENET_TX_UN ((ushort)0x0002) 147 #define BD_ENET_TX_CSL ((ushort)0x0001) 148 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 149 150 151 /****************************************************************************/ 152 #endif /* FEC_H */ 153