1 /* SPDX-License-Identifier: GPL-2.0 */
2 /****************************************************************************/
3 
4 /*
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
6  *		   processors.
7  *
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
10  */
11 
12 /****************************************************************************/
13 #ifndef FEC_H
14 #define	FEC_H
15 /****************************************************************************/
16 
17 #include <linux/clocksource.h>
18 #include <linux/net_tstamp.h>
19 #include <linux/pm_qos.h>
20 #include <linux/bpf.h>
21 #include <linux/ptp_clock_kernel.h>
22 #include <linux/timecounter.h>
23 #include <dt-bindings/firmware/imx/rsrc.h>
24 #include <linux/firmware/imx/sci.h>
25 
26 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
27     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
28     defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
29 /*
30  *	Just figures, Motorola would have to change the offsets for
31  *	registers in the same peripheral device on different models
32  *	of the ColdFire!
33  */
34 #define FEC_IEVENT		0x004 /* Interrupt event reg */
35 #define FEC_IMASK		0x008 /* Interrupt mask reg */
36 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
37 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
38 #define FEC_ECNTRL		0x024 /* Ethernet control reg */
39 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
40 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
41 #define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
42 #define FEC_R_CNTRL		0x084 /* Receive control reg */
43 #define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
44 #define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
45 #define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
46 #define FEC_OPD			0x0ec /* Opcode + Pause duration */
47 #define FEC_TXIC0		0x0f0 /* Tx Interrupt Coalescing for ring 0 */
48 #define FEC_TXIC1		0x0f4 /* Tx Interrupt Coalescing for ring 1 */
49 #define FEC_TXIC2		0x0f8 /* Tx Interrupt Coalescing for ring 2 */
50 #define FEC_RXIC0		0x100 /* Rx Interrupt Coalescing for ring 0 */
51 #define FEC_RXIC1		0x104 /* Rx Interrupt Coalescing for ring 1 */
52 #define FEC_RXIC2		0x108 /* Rx Interrupt Coalescing for ring 2 */
53 #define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
54 #define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
55 #define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
56 #define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
57 #define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
58 #define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
59 #define FEC_R_FSTART		0x150 /* FIFO receive start reg */
60 #define FEC_R_DES_START_1	0x160 /* Receive descriptor ring 1 */
61 #define FEC_X_DES_START_1	0x164 /* Transmit descriptor ring 1 */
62 #define FEC_R_BUFF_SIZE_1	0x168 /* Maximum receive buff ring1 size */
63 #define FEC_R_DES_START_2	0x16c /* Receive descriptor ring 2 */
64 #define FEC_X_DES_START_2	0x170 /* Transmit descriptor ring 2 */
65 #define FEC_R_BUFF_SIZE_2	0x174 /* Maximum receive buff ring2 size */
66 #define FEC_R_DES_START_0	0x180 /* Receive descriptor ring */
67 #define FEC_X_DES_START_0	0x184 /* Transmit descriptor ring */
68 #define FEC_R_BUFF_SIZE_0	0x188 /* Maximum receive buff size */
69 #define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
70 #define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
71 #define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
72 #define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
73 #define FEC_FTRL		0x1b0 /* Frame truncation receive length*/
74 #define FEC_RACC		0x1c4 /* Receive Accelerator function */
75 #define FEC_RCMR_1		0x1c8 /* Receive classification match ring 1 */
76 #define FEC_RCMR_2		0x1cc /* Receive classification match ring 2 */
77 #define FEC_DMA_CFG_1		0x1d8 /* DMA class configuration for ring 1 */
78 #define FEC_DMA_CFG_2		0x1dc /* DMA class Configuration for ring 2 */
79 #define FEC_R_DES_ACTIVE_1	0x1e0 /* Rx descriptor active for ring 1 */
80 #define FEC_X_DES_ACTIVE_1	0x1e4 /* Tx descriptor active for ring 1 */
81 #define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */
82 #define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */
83 #define FEC_QOS_SCHEME		0x1f0 /* Set multi queues Qos scheme */
84 #define FEC_LPI_SLEEP		0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */
85 #define FEC_LPI_WAKE		0x1f8 /* Set IEEE802.3az LPI Wake Tw time */
86 #define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
87 #define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */
88 
89 #define BM_MIIGSK_CFGR_MII		0x00
90 #define BM_MIIGSK_CFGR_RMII		0x01
91 #define BM_MIIGSK_CFGR_FRCONT_10M	0x40
92 
93 #define RMON_T_DROP		0x200 /* Count of frames not cntd correctly */
94 #define RMON_T_PACKETS		0x204 /* RMON TX packet count */
95 #define RMON_T_BC_PKT		0x208 /* RMON TX broadcast pkts */
96 #define RMON_T_MC_PKT		0x20c /* RMON TX multicast pkts */
97 #define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
98 #define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
99 #define RMON_T_OVERSIZE		0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
100 #define RMON_T_FRAG		0x21c /* RMON TX pkts < 64 bytes, bad CRC */
101 #define RMON_T_JAB		0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
102 #define RMON_T_COL		0x224 /* RMON TX collision count */
103 #define RMON_T_P64		0x228 /* RMON TX 64 byte pkts */
104 #define RMON_T_P65TO127		0x22c /* RMON TX 65 to 127 byte pkts */
105 #define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
106 #define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
107 #define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
108 #define RMON_T_P1024TO2047	0x23c /* RMON TX 1024 to 2047 byte pkts */
109 #define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
110 #define RMON_T_OCTETS		0x244 /* RMON TX octets */
111 #define IEEE_T_DROP		0x248 /* Count of frames not counted crtly */
112 #define IEEE_T_FRAME_OK		0x24c /* Frames tx'd OK */
113 #define IEEE_T_1COL		0x250 /* Frames tx'd with single collision */
114 #define IEEE_T_MCOL		0x254 /* Frames tx'd with multiple collision */
115 #define IEEE_T_DEF		0x258 /* Frames tx'd after deferral delay */
116 #define IEEE_T_LCOL		0x25c /* Frames tx'd with late collision */
117 #define IEEE_T_EXCOL		0x260 /* Frames tx'd with excesv collisions */
118 #define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
119 #define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
120 #define IEEE_T_SQE		0x26c /* Frames tx'd with SQE err */
121 #define IEEE_T_FDXFC		0x270 /* Flow control pause frames tx'd */
122 #define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
123 #define RMON_R_PACKETS		0x284 /* RMON RX packet count */
124 #define RMON_R_BC_PKT		0x288 /* RMON RX broadcast pkts */
125 #define RMON_R_MC_PKT		0x28c /* RMON RX multicast pkts */
126 #define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
127 #define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
128 #define RMON_R_OVERSIZE		0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
129 #define RMON_R_FRAG		0x29c /* RMON RX pkts < 64 bytes, bad CRC */
130 #define RMON_R_JAB		0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
131 #define RMON_R_RESVD_O		0x2a4 /* Reserved */
132 #define RMON_R_P64		0x2a8 /* RMON RX 64 byte pkts */
133 #define RMON_R_P65TO127		0x2ac /* RMON RX 65 to 127 byte pkts */
134 #define RMON_R_P128TO255	0x2b0 /* RMON RX 128 to 255 byte pkts */
135 #define RMON_R_P256TO511	0x2b4 /* RMON RX 256 to 511 byte pkts */
136 #define RMON_R_P512TO1023	0x2b8 /* RMON RX 512 to 1023 byte pkts */
137 #define RMON_R_P1024TO2047	0x2bc /* RMON RX 1024 to 2047 byte pkts */
138 #define RMON_R_P_GTE2048	0x2c0 /* RMON RX pkts > 2048 bytes */
139 #define RMON_R_OCTETS		0x2c4 /* RMON RX octets */
140 #define IEEE_R_DROP		0x2c8 /* Count frames not counted correctly */
141 #define IEEE_R_FRAME_OK		0x2cc /* Frames rx'd OK */
142 #define IEEE_R_CRC		0x2d0 /* Frames rx'd with CRC err */
143 #define IEEE_R_ALIGN		0x2d4 /* Frames rx'd with alignment err */
144 #define IEEE_R_MACERR		0x2d8 /* Receive FIFO overflow count */
145 #define IEEE_R_FDXFC		0x2dc /* Flow control pause frames rx'd */
146 #define IEEE_R_OCTETS_OK	0x2e0 /* Octet cnt for frames rx'd w/o err */
147 
148 #else
149 
150 #define FEC_ECNTRL		0x000 /* Ethernet control reg */
151 #define FEC_IEVENT		0x004 /* Interrupt even reg */
152 #define FEC_IMASK		0x008 /* Interrupt mask reg */
153 #define FEC_IVEC		0x00c /* Interrupt vec status reg */
154 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
155 #define FEC_R_DES_ACTIVE_1	FEC_R_DES_ACTIVE_0
156 #define FEC_R_DES_ACTIVE_2	FEC_R_DES_ACTIVE_0
157 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
158 #define FEC_X_DES_ACTIVE_1	FEC_X_DES_ACTIVE_0
159 #define FEC_X_DES_ACTIVE_2	FEC_X_DES_ACTIVE_0
160 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
161 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
162 #define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
163 #define FEC_R_FSTART		0x090 /* FIFO receive start reg */
164 #define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
165 #define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
166 #define FEC_R_CNTRL		0x104 /* Receive control reg */
167 #define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
168 #define FEC_X_CNTRL		0x144 /* Transmit Control reg */
169 #define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
170 #define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
171 #define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
172 #define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
173 #define FEC_R_DES_START_0	0x3d0 /* Receive descriptor ring */
174 #define FEC_R_DES_START_1	FEC_R_DES_START_0
175 #define FEC_R_DES_START_2	FEC_R_DES_START_0
176 #define FEC_X_DES_START_0	0x3d4 /* Transmit descriptor ring */
177 #define FEC_X_DES_START_1	FEC_X_DES_START_0
178 #define FEC_X_DES_START_2	FEC_X_DES_START_0
179 #define FEC_R_BUFF_SIZE_0	0x3d8 /* Maximum receive buff size */
180 #define FEC_R_BUFF_SIZE_1	FEC_R_BUFF_SIZE_0
181 #define FEC_R_BUFF_SIZE_2	FEC_R_BUFF_SIZE_0
182 #define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */
183 /* Not existed in real chip
184  * Just for pass build.
185  */
186 #define FEC_RCMR_1		0xfff
187 #define FEC_RCMR_2		0xfff
188 #define FEC_DMA_CFG_1		0xfff
189 #define FEC_DMA_CFG_2		0xfff
190 #define FEC_TXIC0		0xfff
191 #define FEC_TXIC1		0xfff
192 #define FEC_TXIC2		0xfff
193 #define FEC_RXIC0		0xfff
194 #define FEC_RXIC1		0xfff
195 #define FEC_RXIC2		0xfff
196 #define FEC_LPI_SLEEP		0xfff
197 #define FEC_LPI_WAKE		0xfff
198 #endif /* CONFIG_M5272 */
199 
200 
201 /*
202  *	Define the buffer descriptor structure.
203  *
204  *	Evidently, ARM SoCs have the FEC block generated in a
205  *	little endian mode so adjust endianness accordingly.
206  */
207 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
208 #define fec32_to_cpu le32_to_cpu
209 #define fec16_to_cpu le16_to_cpu
210 #define cpu_to_fec32 cpu_to_le32
211 #define cpu_to_fec16 cpu_to_le16
212 #define __fec32 __le32
213 #define __fec16 __le16
214 
215 struct bufdesc {
216 	__fec16 cbd_datlen;	/* Data length */
217 	__fec16 cbd_sc;		/* Control and status info */
218 	__fec32 cbd_bufaddr;	/* Buffer address */
219 };
220 #else
221 #define fec32_to_cpu be32_to_cpu
222 #define fec16_to_cpu be16_to_cpu
223 #define cpu_to_fec32 cpu_to_be32
224 #define cpu_to_fec16 cpu_to_be16
225 #define __fec32 __be32
226 #define __fec16 __be16
227 
228 struct bufdesc {
229 	__fec16	cbd_sc;		/* Control and status info */
230 	__fec16	cbd_datlen;	/* Data length */
231 	__fec32	cbd_bufaddr;	/* Buffer address */
232 };
233 #endif
234 
235 struct bufdesc_ex {
236 	struct bufdesc desc;
237 	__fec32 cbd_esc;
238 	__fec32 cbd_prot;
239 	__fec32 cbd_bdu;
240 	__fec32 ts;
241 	__fec16 res0[4];
242 };
243 
244 /*
245  *	The following definitions courtesy of commproc.h, which where
246  *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
247  */
248 #define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
249 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
250 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
251 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
252 #define BD_SC_CM	((ushort)0x0200)	/* Continuous mode */
253 #define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
254 #define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
255 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
256 #define BD_SC_FR	((ushort)0x0010)	/* Framing error */
257 #define BD_SC_PR	((ushort)0x0008)	/* Parity error */
258 #define BD_SC_OV	((ushort)0x0002)	/* Overrun */
259 #define BD_SC_CD	((ushort)0x0001)	/* ?? */
260 
261 /* Buffer descriptor control/status used by Ethernet receive.
262  */
263 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
264 #define BD_ENET_RX_WRAP		((ushort)0x2000)
265 #define BD_ENET_RX_INTR		((ushort)0x1000)
266 #define BD_ENET_RX_LAST		((ushort)0x0800)
267 #define BD_ENET_RX_FIRST	((ushort)0x0400)
268 #define BD_ENET_RX_MISS		((ushort)0x0100)
269 #define BD_ENET_RX_LG		((ushort)0x0020)
270 #define BD_ENET_RX_NO		((ushort)0x0010)
271 #define BD_ENET_RX_SH		((ushort)0x0008)
272 #define BD_ENET_RX_CR		((ushort)0x0004)
273 #define BD_ENET_RX_OV		((ushort)0x0002)
274 #define BD_ENET_RX_CL		((ushort)0x0001)
275 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
276 
277 /* Enhanced buffer descriptor control/status used by Ethernet receive */
278 #define BD_ENET_RX_VLAN		0x00000004
279 
280 /* Buffer descriptor control/status used by Ethernet transmit.
281  */
282 #define BD_ENET_TX_READY	((ushort)0x8000)
283 #define BD_ENET_TX_PAD		((ushort)0x4000)
284 #define BD_ENET_TX_WRAP		((ushort)0x2000)
285 #define BD_ENET_TX_INTR		((ushort)0x1000)
286 #define BD_ENET_TX_LAST		((ushort)0x0800)
287 #define BD_ENET_TX_TC		((ushort)0x0400)
288 #define BD_ENET_TX_DEF		((ushort)0x0200)
289 #define BD_ENET_TX_HB		((ushort)0x0100)
290 #define BD_ENET_TX_LC		((ushort)0x0080)
291 #define BD_ENET_TX_RL		((ushort)0x0040)
292 #define BD_ENET_TX_RCMASK	((ushort)0x003c)
293 #define BD_ENET_TX_UN		((ushort)0x0002)
294 #define BD_ENET_TX_CSL		((ushort)0x0001)
295 #define BD_ENET_TX_STATS	((ushort)0x0fff)	/* All status bits */
296 
297 /* enhanced buffer descriptor control/status used by Ethernet transmit */
298 #define BD_ENET_TX_INT		0x40000000
299 #define BD_ENET_TX_TS		0x20000000
300 #define BD_ENET_TX_PINS		0x10000000
301 #define BD_ENET_TX_IINS		0x08000000
302 
303 
304 /* This device has up to three irqs on some platforms */
305 #define FEC_IRQ_NUM		3
306 
307 /* Maximum number of queues supported
308  * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
309  * User can point the queue number that is less than or equal to 3.
310  */
311 #define FEC_ENET_MAX_TX_QS	3
312 #define FEC_ENET_MAX_RX_QS	3
313 
314 #define FEC_R_DES_START(X)	(((X) == 1) ? FEC_R_DES_START_1 : \
315 				(((X) == 2) ? \
316 					FEC_R_DES_START_2 : FEC_R_DES_START_0))
317 #define FEC_X_DES_START(X)	(((X) == 1) ? FEC_X_DES_START_1 : \
318 				(((X) == 2) ? \
319 					FEC_X_DES_START_2 : FEC_X_DES_START_0))
320 #define FEC_R_BUFF_SIZE(X)	(((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
321 				(((X) == 2) ? \
322 					FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
323 
324 #define FEC_DMA_CFG(X)		(((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
325 
326 #define DMA_CLASS_EN		(1 << 16)
327 #define FEC_RCMR(X)		(((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
328 #define IDLE_SLOPE_MASK		0xffff
329 #define IDLE_SLOPE_1		0x200 /* BW fraction: 0.5 */
330 #define IDLE_SLOPE_2		0x200 /* BW fraction: 0.5 */
331 #define IDLE_SLOPE(X)		(((X) == 1) ?				\
332 				(IDLE_SLOPE_1 & IDLE_SLOPE_MASK) :	\
333 				(IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
334 #define RCMR_MATCHEN		(0x1 << 16)
335 #define RCMR_CMP_CFG(v, n)	(((v) & 0x7) <<  (n << 2))
336 #define RCMR_CMP_1		(RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
337 				RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
338 #define RCMR_CMP_2		(RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
339 				RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
340 #define RCMR_CMP(X)		(((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
341 #define FEC_TX_BD_FTYPE(X)	(((X) & 0xf) << 20)
342 
343 /* The number of Tx and Rx buffers.  These are allocated from the page
344  * pool.  The code may assume these are power of two, so it it best
345  * to keep them that size.
346  * We don't need to allocate pages for the transmitter.  We just use
347  * the skbuffer directly.
348  */
349 
350 #define FEC_ENET_XDP_HEADROOM	(XDP_PACKET_HEADROOM)
351 #define FEC_ENET_RX_PAGES	256
352 #define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_ENET_XDP_HEADROOM \
353 		- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
354 #define FEC_ENET_RX_FRPPG	(PAGE_SIZE / FEC_ENET_RX_FRSIZE)
355 #define RX_RING_SIZE		(FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
356 #define FEC_ENET_TX_FRSIZE	2048
357 #define FEC_ENET_TX_FRPPG	(PAGE_SIZE / FEC_ENET_TX_FRSIZE)
358 #define TX_RING_SIZE		512	/* Must be power of two */
359 #define TX_RING_MOD_MASK	511	/*   for this to work */
360 
361 #define BD_ENET_RX_INT		0x00800000
362 #define BD_ENET_RX_PTP		((ushort)0x0400)
363 #define BD_ENET_RX_ICE		0x00000020
364 #define BD_ENET_RX_PCR		0x00000010
365 #define FLAG_RX_CSUM_ENABLED	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
366 #define FLAG_RX_CSUM_ERROR	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
367 
368 /* Interrupt events/masks. */
369 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
370 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
371 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
372 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
373 #define FEC_ENET_TXF_0	((uint)0x08000000)	/* Full frame transmitted */
374 #define FEC_ENET_TXF_1	((uint)0x00000008)	/* Full frame transmitted */
375 #define FEC_ENET_TXF_2	((uint)0x00000080)	/* Full frame transmitted */
376 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
377 #define FEC_ENET_RXF_0	((uint)0x02000000)	/* Full frame received */
378 #define FEC_ENET_RXF_1	((uint)0x00000002)	/* Full frame received */
379 #define FEC_ENET_RXF_2	((uint)0x00000020)	/* Full frame received */
380 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
381 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
382 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
383 #define FEC_ENET_WAKEUP	((uint)0x00020000)	/* Wakeup request */
384 #define FEC_ENET_TXF	(FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
385 #define FEC_ENET_RXF	(FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
386 #define FEC_ENET_RXF_GET(X)	(((X) == 0) ? FEC_ENET_RXF_0 :	\
387 				(((X) == 1) ? FEC_ENET_RXF_1 :	\
388 				FEC_ENET_RXF_2))
389 #define FEC_ENET_TS_AVAIL       ((uint)0x00010000)
390 #define FEC_ENET_TS_TIMER       ((uint)0x00008000)
391 
392 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)
393 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
394 
395 #define FEC_ENET_TXC_DLY	((uint)0x00010000)
396 #define FEC_ENET_RXC_DLY	((uint)0x00020000)
397 
398 /* ENET interrupt coalescing macro define */
399 #define FEC_ITR_CLK_SEL		(0x1 << 30)
400 #define FEC_ITR_EN		(0x1 << 31)
401 #define FEC_ITR_ICFT(X)		(((X) & 0xff) << 20)
402 #define FEC_ITR_ICTT(X)		((X) & 0xffff)
403 #define FEC_ITR_ICFT_DEFAULT	200  /* Set 200 frame count threshold */
404 #define FEC_ITR_ICTT_DEFAULT	1000 /* Set 1000us timer threshold */
405 
406 #define FEC_VLAN_TAG_LEN	0x04
407 #define FEC_ETHTYPE_LEN		0x02
408 
409 /* Controller is ENET-MAC */
410 #define FEC_QUIRK_ENET_MAC		(1 << 0)
411 /* Controller needs driver to swap frame */
412 #define FEC_QUIRK_SWAP_FRAME		(1 << 1)
413 /* Controller uses gasket */
414 #define FEC_QUIRK_USE_GASKET		(1 << 2)
415 /* Controller has GBIT support */
416 #define FEC_QUIRK_HAS_GBIT		(1 << 3)
417 /* Controller has extend desc buffer */
418 #define FEC_QUIRK_HAS_BUFDESC_EX	(1 << 4)
419 /* Controller has hardware checksum support */
420 #define FEC_QUIRK_HAS_CSUM		(1 << 5)
421 /* Controller has hardware vlan support */
422 #define FEC_QUIRK_HAS_VLAN		(1 << 6)
423 /* ENET IP errata ERR006358
424  *
425  * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
426  * detected as not set during a prior frame transmission, then the
427  * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
428  * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
429  * frames not being transmitted until there is a 0-to-1 transition on
430  * ENET_TDAR[TDAR].
431  */
432 #define FEC_QUIRK_ERR006358		(1 << 7)
433 /* ENET IP hw AVB
434  *
435  * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
436  * - Two class indicators on receive with configurable priority
437  * - Two class indicators and line speed timer on transmit allowing
438  *   implementation class credit based shapers externally
439  * - Additional DMA registers provisioned to allow managing up to 3
440  *   independent rings
441  */
442 #define FEC_QUIRK_HAS_AVB		(1 << 8)
443 /* There is a TDAR race condition for mutliQ when the software sets TDAR
444  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
445  * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
446  * The issue exist at i.MX6SX enet IP.
447  */
448 #define FEC_QUIRK_ERR007885		(1 << 9)
449 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
450  * After set ENET_ATCR[Capture], there need some time cycles before the counter
451  * value is capture in the register clock domain.
452  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
453  * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
454  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
455  * (40ns * 6).
456  */
457 #define FEC_QUIRK_BUG_CAPTURE		(1 << 10)
458 /* Controller has only one MDIO bus */
459 #define FEC_QUIRK_SINGLE_MDIO		(1 << 11)
460 /* Controller supports RACC register */
461 #define FEC_QUIRK_HAS_RACC		(1 << 12)
462 /* Controller supports interrupt coalesc */
463 #define FEC_QUIRK_HAS_COALESCE		(1 << 13)
464 /* Interrupt doesn't wake CPU from deep idle */
465 #define FEC_QUIRK_ERR006687		(1 << 14)
466 /* The MIB counters should be cleared and enabled during
467  * initialisation.
468  */
469 #define FEC_QUIRK_MIB_CLEAR		(1 << 15)
470 /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers,
471  * those FIFO receive registers are resolved in other platforms.
472  */
473 #define FEC_QUIRK_HAS_FRREG		(1 << 16)
474 
475 /* Some FEC hardware blocks need the MMFR cleared at setup time to avoid
476  * the generation of an MII event. This must be avoided in the older
477  * FEC blocks where it will stop MII events being generated.
478  */
479 #define FEC_QUIRK_CLEAR_SETUP_MII	(1 << 17)
480 
481 /* Some link partners do not tolerate the momentary reset of the REF_CLK
482  * frequency when the RNCTL register is cleared by hardware reset.
483  */
484 #define FEC_QUIRK_NO_HARD_RESET		(1 << 18)
485 
486 /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to
487  * represents this ENET IP.
488  */
489 #define FEC_QUIRK_HAS_MULTI_QUEUES	(1 << 19)
490 
491 /* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE
492  * standard. For the transmission, MAC supply two user registers to set
493  * Sleep (TS) and Wake (TW) time.
494  */
495 #define FEC_QUIRK_HAS_EEE		(1 << 20)
496 
497 /* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC
498  * as an alternative option to make sure it works well with various PHYs.
499  * For the implementation of delayed clock, ENET takes synchronized 250MHz
500  * clocks to generate 2ns delay.
501  */
502 #define FEC_QUIRK_DELAYED_CLKS_SUPPORT	(1 << 21)
503 
504 /* i.MX8MQ SoC integration mix wakeup interrupt signal into "int2" interrupt line. */
505 #define FEC_QUIRK_WAKEUP_FROM_INT2	(1 << 22)
506 
507 /* i.MX6Q adds pm_qos support */
508 #define FEC_QUIRK_HAS_PMQOS			BIT(23)
509 
510 struct bufdesc_prop {
511 	int qid;
512 	/* Address of Rx and Tx buffers */
513 	struct bufdesc	*base;
514 	struct bufdesc	*last;
515 	struct bufdesc	*cur;
516 	void __iomem	*reg_desc_active;
517 	dma_addr_t	dma;
518 	unsigned short ring_size;
519 	unsigned char dsize;
520 	unsigned char dsize_log2;
521 };
522 
523 struct fec_enet_priv_txrx_info {
524 	int	offset;
525 	struct	page *page;
526 	struct  sk_buff *skb;
527 };
528 
529 enum {
530 	RX_XDP_REDIRECT = 0,
531 	RX_XDP_PASS,
532 	RX_XDP_DROP,
533 	RX_XDP_TX,
534 	RX_XDP_TX_ERRORS,
535 	TX_XDP_XMIT,
536 	TX_XDP_XMIT_ERRORS,
537 
538 	/* The following must be the last one */
539 	XDP_STATS_TOTAL,
540 };
541 
542 struct fec_enet_priv_tx_q {
543 	struct bufdesc_prop bd;
544 	unsigned char *tx_bounce[TX_RING_SIZE];
545 	struct  sk_buff *tx_skbuff[TX_RING_SIZE];
546 
547 	unsigned short tx_stop_threshold;
548 	unsigned short tx_wake_threshold;
549 
550 	struct bufdesc	*dirty_tx;
551 	char *tso_hdrs;
552 	dma_addr_t tso_hdrs_dma;
553 };
554 
555 struct fec_enet_priv_rx_q {
556 	struct bufdesc_prop bd;
557 	struct  fec_enet_priv_txrx_info rx_skb_info[RX_RING_SIZE];
558 
559 	/* page_pool */
560 	struct page_pool *page_pool;
561 	struct xdp_rxq_info xdp_rxq;
562 	u32 stats[XDP_STATS_TOTAL];
563 
564 	/* rx queue number, in the range 0-7 */
565 	u8 id;
566 };
567 
568 struct fec_stop_mode_gpr {
569 	struct regmap *gpr;
570 	u8 reg;
571 	u8 bit;
572 };
573 
574 /* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
575  * tx_bd_base always point to the base of the buffer descriptors.  The
576  * cur_rx and cur_tx point to the currently available buffer.
577  * The dirty_tx tracks the current buffer that is being sent by the
578  * controller.  The cur_tx and dirty_tx are equal under both completely
579  * empty and completely full conditions.  The empty/ready indicator in
580  * the buffer descriptor determines the actual condition.
581  */
582 struct fec_enet_private {
583 	/* Hardware registers of the FEC device */
584 	void __iomem *hwp;
585 
586 	struct net_device *netdev;
587 
588 	struct clk *clk_ipg;
589 	struct clk *clk_ahb;
590 	struct clk *clk_ref;
591 	struct clk *clk_enet_out;
592 	struct clk *clk_ptp;
593 	struct clk *clk_2x_txclk;
594 
595 	bool ptp_clk_on;
596 	struct mutex ptp_clk_mutex;
597 	unsigned int num_tx_queues;
598 	unsigned int num_rx_queues;
599 
600 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
601 	struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
602 	struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
603 
604 	unsigned int total_tx_ring_size;
605 	unsigned int total_rx_ring_size;
606 
607 	struct	platform_device *pdev;
608 
609 	int	dev_id;
610 
611 	/* Phylib and MDIO interface */
612 	struct	mii_bus *mii_bus;
613 	uint	phy_speed;
614 	phy_interface_t	phy_interface;
615 	struct device_node *phy_node;
616 	bool	rgmii_txc_dly;
617 	bool	rgmii_rxc_dly;
618 	bool	rpm_active;
619 	int	link;
620 	int	full_duplex;
621 	int	speed;
622 	int	irq[FEC_IRQ_NUM];
623 	bool	bufdesc_ex;
624 	int	pause_flag;
625 	int	wol_flag;
626 	int	wake_irq;
627 	u32	quirks;
628 
629 	struct	napi_struct napi;
630 	int	csum_flags;
631 
632 	struct work_struct tx_timeout_work;
633 
634 	struct ptp_clock *ptp_clock;
635 	struct ptp_clock_info ptp_caps;
636 	unsigned long last_overflow_check;
637 	spinlock_t tmreg_lock;
638 	struct cyclecounter cc;
639 	struct timecounter tc;
640 	int rx_hwtstamp_filter;
641 	u32 base_incval;
642 	u32 cycle_speed;
643 	int hwts_rx_en;
644 	int hwts_tx_en;
645 	struct delayed_work time_keep;
646 	struct regulator *reg_phy;
647 	struct fec_stop_mode_gpr stop_gpr;
648 	struct pm_qos_request pm_qos_req;
649 
650 	unsigned int tx_align;
651 	unsigned int rx_align;
652 
653 	/* hw interrupt coalesce */
654 	unsigned int rx_pkts_itr;
655 	unsigned int rx_time_itr;
656 	unsigned int tx_pkts_itr;
657 	unsigned int tx_time_itr;
658 	unsigned int itr_clk_rate;
659 
660 	/* tx lpi eee mode */
661 	struct ethtool_eee eee;
662 	unsigned int clk_ref_rate;
663 
664 	u32 rx_copybreak;
665 
666 	/* ptp clock period in ns*/
667 	unsigned int ptp_inc;
668 
669 	/* pps  */
670 	int pps_channel;
671 	unsigned int reload_period;
672 	int pps_enable;
673 	unsigned int next_counter;
674 	struct hrtimer perout_timer;
675 	u64 perout_stime;
676 
677 	struct imx_sc_ipc *ipc_handle;
678 
679 	/* XDP BPF Program */
680 	struct bpf_prog *xdp_prog;
681 
682 	u64 ethtool_stats[];
683 };
684 
685 void fec_ptp_init(struct platform_device *pdev, int irq_idx);
686 void fec_ptp_stop(struct platform_device *pdev);
687 void fec_ptp_start_cyclecounter(struct net_device *ndev);
688 void fec_ptp_disable_hwts(struct net_device *ndev);
689 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
690 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
691 
692 /****************************************************************************/
693 #endif /* FEC_H */
694