1 /****************************************************************************/
2 
3 /*
4  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
5  *		   processors.
6  *
7  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
8  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
9  */
10 
11 /****************************************************************************/
12 #ifndef FEC_H
13 #define	FEC_H
14 /****************************************************************************/
15 
16 #include <linux/clocksource.h>
17 #include <linux/net_tstamp.h>
18 #include <linux/ptp_clock_kernel.h>
19 
20 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
21     defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
22     defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
23 /*
24  *	Just figures, Motorola would have to change the offsets for
25  *	registers in the same peripheral device on different models
26  *	of the ColdFire!
27  */
28 #define FEC_IEVENT		0x004 /* Interrupt event reg */
29 #define FEC_IMASK		0x008 /* Interrupt mask reg */
30 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
31 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
32 #define FEC_ECNTRL		0x024 /* Ethernet control reg */
33 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
34 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
35 #define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
36 #define FEC_R_CNTRL		0x084 /* Receive control reg */
37 #define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
38 #define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
39 #define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
40 #define FEC_OPD			0x0ec /* Opcode + Pause duration */
41 #define FEC_TXIC0		0xF0  /* Tx Interrupt Coalescing for ring 0 */
42 #define FEC_TXIC1		0xF4  /* Tx Interrupt Coalescing for ring 1 */
43 #define FEC_TXIC2		0xF8  /* Tx Interrupt Coalescing for ring 2 */
44 #define FEC_RXIC0		0x100 /* Rx Interrupt Coalescing for ring 0 */
45 #define FEC_RXIC1		0x104 /* Rx Interrupt Coalescing for ring 1 */
46 #define FEC_RXIC2		0x108 /* Rx Interrupt Coalescing for ring 2 */
47 #define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
48 #define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
49 #define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
50 #define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
51 #define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
52 #define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
53 #define FEC_R_FSTART		0x150 /* FIFO receive start reg */
54 #define FEC_R_DES_START_1	0x160 /* Receive descriptor ring 1 */
55 #define FEC_X_DES_START_1	0x164 /* Transmit descriptor ring 1 */
56 #define FEC_R_DES_START_2	0x16c /* Receive descriptor ring 2 */
57 #define FEC_X_DES_START_2	0x170 /* Transmit descriptor ring 2 */
58 #define FEC_R_DES_START_0	0x180 /* Receive descriptor ring */
59 #define FEC_X_DES_START_0	0x184 /* Transmit descriptor ring */
60 #define FEC_R_BUFF_SIZE		0x188 /* Maximum receive buff size */
61 #define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
62 #define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
63 #define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
64 #define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
65 #define FEC_RACC		0x1C4 /* Receive Accelerator function */
66 #define FEC_RCMR_1		0x1c8 /* Receive classification match ring 1 */
67 #define FEC_RCMR_2		0x1cc /* Receive classification match ring 2 */
68 #define FEC_DMA_CFG_1		0x1d8 /* DMA class configuration for ring 1 */
69 #define FEC_DMA_CFG_2		0x1dc /* DMA class Configuration for ring 2 */
70 #define FEC_R_DES_ACTIVE_1	0x1e0 /* Rx descriptor active for ring 1 */
71 #define FEC_X_DES_ACTIVE_1	0x1e4 /* Tx descriptor active for ring 1 */
72 #define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */
73 #define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */
74 #define FEC_QOS_SCHEME		0x1f0 /* Set multi queues Qos scheme */
75 #define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
76 #define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */
77 
78 #define BM_MIIGSK_CFGR_MII		0x00
79 #define BM_MIIGSK_CFGR_RMII		0x01
80 #define BM_MIIGSK_CFGR_FRCONT_10M	0x40
81 
82 #define RMON_T_DROP		0x200 /* Count of frames not cntd correctly */
83 #define RMON_T_PACKETS		0x204 /* RMON TX packet count */
84 #define RMON_T_BC_PKT		0x208 /* RMON TX broadcast pkts */
85 #define RMON_T_MC_PKT		0x20C /* RMON TX multicast pkts */
86 #define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
87 #define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
88 #define RMON_T_OVERSIZE		0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
89 #define RMON_T_FRAG		0x21C /* RMON TX pkts < 64 bytes, bad CRC */
90 #define RMON_T_JAB		0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
91 #define RMON_T_COL		0x224 /* RMON TX collision count */
92 #define RMON_T_P64		0x228 /* RMON TX 64 byte pkts */
93 #define RMON_T_P65TO127		0x22C /* RMON TX 65 to 127 byte pkts */
94 #define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
95 #define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
96 #define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
97 #define RMON_T_P1024TO2047	0x23C /* RMON TX 1024 to 2047 byte pkts */
98 #define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
99 #define RMON_T_OCTETS		0x244 /* RMON TX octets */
100 #define IEEE_T_DROP		0x248 /* Count of frames not counted crtly */
101 #define IEEE_T_FRAME_OK		0x24C /* Frames tx'd OK */
102 #define IEEE_T_1COL		0x250 /* Frames tx'd with single collision */
103 #define IEEE_T_MCOL		0x254 /* Frames tx'd with multiple collision */
104 #define IEEE_T_DEF		0x258 /* Frames tx'd after deferral delay */
105 #define IEEE_T_LCOL		0x25C /* Frames tx'd with late collision */
106 #define IEEE_T_EXCOL		0x260 /* Frames tx'd with excesv collisions */
107 #define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
108 #define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
109 #define IEEE_T_SQE		0x26C /* Frames tx'd with SQE err */
110 #define IEEE_T_FDXFC		0x270 /* Flow control pause frames tx'd */
111 #define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
112 #define RMON_R_PACKETS		0x284 /* RMON RX packet count */
113 #define RMON_R_BC_PKT		0x288 /* RMON RX broadcast pkts */
114 #define RMON_R_MC_PKT		0x28C /* RMON RX multicast pkts */
115 #define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
116 #define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
117 #define RMON_R_OVERSIZE		0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
118 #define RMON_R_FRAG		0x29C /* RMON RX pkts < 64 bytes, bad CRC */
119 #define RMON_R_JAB		0x2A0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
120 #define RMON_R_RESVD_O		0x2A4 /* Reserved */
121 #define RMON_R_P64		0x2A8 /* RMON RX 64 byte pkts */
122 #define RMON_R_P65TO127		0x2AC /* RMON RX 65 to 127 byte pkts */
123 #define RMON_R_P128TO255	0x2B0 /* RMON RX 128 to 255 byte pkts */
124 #define RMON_R_P256TO511	0x2B4 /* RMON RX 256 to 511 byte pkts */
125 #define RMON_R_P512TO1023	0x2B8 /* RMON RX 512 to 1023 byte pkts */
126 #define RMON_R_P1024TO2047	0x2BC /* RMON RX 1024 to 2047 byte pkts */
127 #define RMON_R_P_GTE2048	0x2C0 /* RMON RX pkts > 2048 bytes */
128 #define RMON_R_OCTETS		0x2C4 /* RMON RX octets */
129 #define IEEE_R_DROP		0x2C8 /* Count frames not counted correctly */
130 #define IEEE_R_FRAME_OK		0x2CC /* Frames rx'd OK */
131 #define IEEE_R_CRC		0x2D0 /* Frames rx'd with CRC err */
132 #define IEEE_R_ALIGN		0x2D4 /* Frames rx'd with alignment err */
133 #define IEEE_R_MACERR		0x2D8 /* Receive FIFO overflow count */
134 #define IEEE_R_FDXFC		0x2DC /* Flow control pause frames rx'd */
135 #define IEEE_R_OCTETS_OK	0x2E0 /* Octet cnt for frames rx'd w/o err */
136 
137 #else
138 
139 #define FEC_ECNTRL		0x000 /* Ethernet control reg */
140 #define FEC_IEVENT		0x004 /* Interrupt even reg */
141 #define FEC_IMASK		0x008 /* Interrupt mask reg */
142 #define FEC_IVEC		0x00c /* Interrupt vec status reg */
143 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
144 #define FEC_R_DES_ACTIVE_1	FEC_R_DES_ACTIVE_0
145 #define FEC_R_DES_ACTIVE_2	FEC_R_DES_ACTIVE_0
146 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
147 #define FEC_X_DES_ACTIVE_1	FEC_X_DES_ACTIVE_0
148 #define FEC_X_DES_ACTIVE_2	FEC_X_DES_ACTIVE_0
149 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
150 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
151 #define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
152 #define FEC_R_FSTART		0x090 /* FIFO receive start reg */
153 #define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
154 #define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
155 #define FEC_R_CNTRL		0x104 /* Receive control reg */
156 #define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
157 #define FEC_X_CNTRL		0x144 /* Transmit Control reg */
158 #define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
159 #define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
160 #define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
161 #define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
162 #define FEC_R_DES_START_0	0x3d0 /* Receive descriptor ring */
163 #define FEC_R_DES_START_1	FEC_R_DES_START_0
164 #define FEC_R_DES_START_2	FEC_R_DES_START_0
165 #define FEC_X_DES_START_0	0x3d4 /* Transmit descriptor ring */
166 #define FEC_X_DES_START_1	FEC_X_DES_START_0
167 #define FEC_X_DES_START_2	FEC_X_DES_START_0
168 #define FEC_R_BUFF_SIZE		0x3d8 /* Maximum receive buff size */
169 #define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */
170 /* Not existed in real chip
171  * Just for pass build.
172  */
173 #define FEC_RCMR_1		0xFFF
174 #define FEC_RCMR_2		0xFFF
175 #define FEC_DMA_CFG_1		0xFFF
176 #define FEC_DMA_CFG_2		0xFFF
177 #define FEC_TXIC0		0xFFF
178 #define FEC_TXIC1		0xFFF
179 #define FEC_TXIC2		0xFFF
180 #define FEC_RXIC0		0xFFF
181 #define FEC_RXIC1		0xFFF
182 #define FEC_RXIC2		0xFFF
183 #endif /* CONFIG_M5272 */
184 
185 
186 /*
187  *	Define the buffer descriptor structure.
188  */
189 #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
190 struct bufdesc {
191 	unsigned short cbd_datlen;	/* Data length */
192 	unsigned short cbd_sc;	/* Control and status info */
193 	unsigned long cbd_bufaddr;	/* Buffer address */
194 };
195 #else
196 struct bufdesc {
197 	unsigned short	cbd_sc;			/* Control and status info */
198 	unsigned short	cbd_datlen;		/* Data length */
199 	unsigned long	cbd_bufaddr;		/* Buffer address */
200 };
201 #endif
202 
203 struct bufdesc_ex {
204 	struct bufdesc desc;
205 	unsigned long cbd_esc;
206 	unsigned long cbd_prot;
207 	unsigned long cbd_bdu;
208 	unsigned long ts;
209 	unsigned short res0[4];
210 };
211 
212 /*
213  *	The following definitions courtesy of commproc.h, which where
214  *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
215  */
216 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
217 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
218 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
219 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
220 #define BD_SC_CM        ((ushort)0x0200)        /* Continuous mode */
221 #define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
222 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
223 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
224 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
225 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
226 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
227 #define BD_SC_CD        ((ushort)0x0001)        /* ?? */
228 
229 /* Buffer descriptor control/status used by Ethernet receive.
230 */
231 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
232 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
233 #define BD_ENET_RX_INTR         ((ushort)0x1000)
234 #define BD_ENET_RX_LAST         ((ushort)0x0800)
235 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
236 #define BD_ENET_RX_MISS         ((ushort)0x0100)
237 #define BD_ENET_RX_LG           ((ushort)0x0020)
238 #define BD_ENET_RX_NO           ((ushort)0x0010)
239 #define BD_ENET_RX_SH           ((ushort)0x0008)
240 #define BD_ENET_RX_CR           ((ushort)0x0004)
241 #define BD_ENET_RX_OV           ((ushort)0x0002)
242 #define BD_ENET_RX_CL           ((ushort)0x0001)
243 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
244 
245 /* Enhanced buffer descriptor control/status used by Ethernet receive */
246 #define BD_ENET_RX_VLAN         0x00000004
247 
248 /* Buffer descriptor control/status used by Ethernet transmit.
249 */
250 #define BD_ENET_TX_READY        ((ushort)0x8000)
251 #define BD_ENET_TX_PAD          ((ushort)0x4000)
252 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
253 #define BD_ENET_TX_INTR         ((ushort)0x1000)
254 #define BD_ENET_TX_LAST         ((ushort)0x0800)
255 #define BD_ENET_TX_TC           ((ushort)0x0400)
256 #define BD_ENET_TX_DEF          ((ushort)0x0200)
257 #define BD_ENET_TX_HB           ((ushort)0x0100)
258 #define BD_ENET_TX_LC           ((ushort)0x0080)
259 #define BD_ENET_TX_RL           ((ushort)0x0040)
260 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
261 #define BD_ENET_TX_UN           ((ushort)0x0002)
262 #define BD_ENET_TX_CSL          ((ushort)0x0001)
263 #define BD_ENET_TX_STATS        ((ushort)0x0fff)        /* All status bits */
264 
265 /*enhanced buffer descriptor control/status used by Ethernet transmit*/
266 #define BD_ENET_TX_INT          0x40000000
267 #define BD_ENET_TX_TS           0x20000000
268 #define BD_ENET_TX_PINS         0x10000000
269 #define BD_ENET_TX_IINS         0x08000000
270 
271 
272 /* This device has up to three irqs on some platforms */
273 #define FEC_IRQ_NUM		3
274 
275 /* Maximum number of queues supported
276  * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
277  * User can point the queue number that is less than or equal to 3.
278  */
279 #define FEC_ENET_MAX_TX_QS	3
280 #define FEC_ENET_MAX_RX_QS	3
281 
282 #define FEC_R_DES_START(X)	((X == 1) ? FEC_R_DES_START_1 : \
283 				((X == 2) ? \
284 					FEC_R_DES_START_2 : FEC_R_DES_START_0))
285 #define FEC_X_DES_START(X)	((X == 1) ? FEC_X_DES_START_1 : \
286 				((X == 2) ? \
287 					FEC_X_DES_START_2 : FEC_X_DES_START_0))
288 #define FEC_R_DES_ACTIVE(X)	((X == 1) ? FEC_R_DES_ACTIVE_1 : \
289 				((X == 2) ? \
290 				   FEC_R_DES_ACTIVE_2 : FEC_R_DES_ACTIVE_0))
291 #define FEC_X_DES_ACTIVE(X)	((X == 1) ? FEC_X_DES_ACTIVE_1 : \
292 				((X == 2) ? \
293 				   FEC_X_DES_ACTIVE_2 : FEC_X_DES_ACTIVE_0))
294 
295 #define FEC_DMA_CFG(X)		((X == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
296 
297 #define DMA_CLASS_EN		(1 << 16)
298 #define FEC_RCMR(X)		((X == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
299 #define IDLE_SLOPE_MASK		0xFFFF
300 #define IDLE_SLOPE_1		0x200 /* BW fraction: 0.5 */
301 #define IDLE_SLOPE_2		0x200 /* BW fraction: 0.5 */
302 #define IDLE_SLOPE(X)		((X == 1) ? (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \
303 				(IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
304 #define RCMR_MATCHEN            (0x1 << 16)
305 #define RCMR_CMP_CFG(v, n)	((v & 0x7) <<  (n << 2))
306 #define RCMR_CMP_1		(RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
307 				RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
308 #define RCMR_CMP_2		(RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
309 				RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
310 #define RCMR_CMP(X)		((X == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
311 #define FEC_TX_BD_FTYPE(X)	((X & 0xF) << 20)
312 
313 /* The number of Tx and Rx buffers.  These are allocated from the page
314  * pool.  The code may assume these are power of two, so it it best
315  * to keep them that size.
316  * We don't need to allocate pages for the transmitter.  We just use
317  * the skbuffer directly.
318  */
319 
320 #define FEC_ENET_RX_PAGES	256
321 #define FEC_ENET_RX_FRSIZE	2048
322 #define FEC_ENET_RX_FRPPG	(PAGE_SIZE / FEC_ENET_RX_FRSIZE)
323 #define RX_RING_SIZE		(FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
324 #define FEC_ENET_TX_FRSIZE	2048
325 #define FEC_ENET_TX_FRPPG	(PAGE_SIZE / FEC_ENET_TX_FRSIZE)
326 #define TX_RING_SIZE		512	/* Must be power of two */
327 #define TX_RING_MOD_MASK	511	/*   for this to work */
328 
329 #define BD_ENET_RX_INT          0x00800000
330 #define BD_ENET_RX_PTP          ((ushort)0x0400)
331 #define BD_ENET_RX_ICE		0x00000020
332 #define BD_ENET_RX_PCR		0x00000010
333 #define FLAG_RX_CSUM_ENABLED	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
334 #define FLAG_RX_CSUM_ERROR	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
335 
336 /* Interrupt events/masks. */
337 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
338 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
339 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
340 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
341 #define FEC_ENET_TXF_0	((uint)0x08000000)	/* Full frame transmitted */
342 #define FEC_ENET_TXF_1	((uint)0x00000008)	/* Full frame transmitted */
343 #define FEC_ENET_TXF_2	((uint)0x00000080)	/* Full frame transmitted */
344 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
345 #define FEC_ENET_RXF_0	((uint)0x02000000)	/* Full frame received */
346 #define FEC_ENET_RXF_1	((uint)0x00000002)	/* Full frame received */
347 #define FEC_ENET_RXF_2	((uint)0x00000020)	/* Full frame received */
348 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
349 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
350 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
351 #define FEC_ENET_TXF	(FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
352 #define FEC_ENET_RXF	(FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
353 #define FEC_ENET_TS_AVAIL       ((uint)0x00010000)
354 #define FEC_ENET_TS_TIMER       ((uint)0x00008000)
355 
356 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | FEC_ENET_TS_TIMER)
357 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
358 
359 /* ENET interrupt coalescing macro define */
360 #define FEC_ITR_CLK_SEL		(0x1 << 30)
361 #define FEC_ITR_EN		(0x1 << 31)
362 #define FEC_ITR_ICFT(X)		((X & 0xFF) << 20)
363 #define FEC_ITR_ICTT(X)		((X) & 0xFFFF)
364 #define FEC_ITR_ICFT_DEFAULT	200  /* Set 200 frame count threshold */
365 #define FEC_ITR_ICTT_DEFAULT	1000 /* Set 1000us timer threshold */
366 
367 #define FEC_VLAN_TAG_LEN       0x04
368 #define FEC_ETHTYPE_LEN                0x02
369 
370 /* Controller is ENET-MAC */
371 #define FEC_QUIRK_ENET_MAC		(1 << 0)
372 /* Controller needs driver to swap frame */
373 #define FEC_QUIRK_SWAP_FRAME		(1 << 1)
374 /* Controller uses gasket */
375 #define FEC_QUIRK_USE_GASKET		(1 << 2)
376 /* Controller has GBIT support */
377 #define FEC_QUIRK_HAS_GBIT		(1 << 3)
378 /* Controller has extend desc buffer */
379 #define FEC_QUIRK_HAS_BUFDESC_EX	(1 << 4)
380 /* Controller has hardware checksum support */
381 #define FEC_QUIRK_HAS_CSUM		(1 << 5)
382 /* Controller has hardware vlan support */
383 #define FEC_QUIRK_HAS_VLAN		(1 << 6)
384 /* ENET IP errata ERR006358
385  *
386  * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
387  * detected as not set during a prior frame transmission, then the
388  * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
389  * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
390  * frames not being transmitted until there is a 0-to-1 transition on
391  * ENET_TDAR[TDAR].
392  */
393 #define FEC_QUIRK_ERR006358            (1 << 7)
394 /* ENET IP hw AVB
395  *
396  * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
397  * - Two class indicators on receive with configurable priority
398  * - Two class indicators and line speed timer on transmit allowing
399  *   implementation class credit based shapers externally
400  * - Additional DMA registers provisioned to allow managing up to 3
401  *   independent rings
402  */
403 #define FEC_QUIRK_HAS_AVB		(1 << 8)
404 /* There is a TDAR race condition for mutliQ when the software sets TDAR
405  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
406  * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
407  * The issue exist at i.MX6SX enet IP.
408  */
409 #define FEC_QUIRK_ERR007885		(1 << 9)
410 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
411  * After set ENET_ATCR[Capture], there need some time cycles before the counter
412  * value is capture in the register clock domain.
413  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
414  * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
415  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
416  * (40ns * 6).
417  */
418 #define FEC_QUIRK_BUG_CAPTURE		(1 << 10)
419 
420 struct fec_enet_priv_tx_q {
421 	int index;
422 	unsigned char *tx_bounce[TX_RING_SIZE];
423 	struct  sk_buff *tx_skbuff[TX_RING_SIZE];
424 
425 	dma_addr_t	bd_dma;
426 	struct bufdesc	*tx_bd_base;
427 	uint tx_ring_size;
428 
429 	unsigned short tx_stop_threshold;
430 	unsigned short tx_wake_threshold;
431 
432 	struct bufdesc	*cur_tx;
433 	struct bufdesc	*dirty_tx;
434 	char *tso_hdrs;
435 	dma_addr_t tso_hdrs_dma;
436 };
437 
438 struct fec_enet_priv_rx_q {
439 	int index;
440 	struct  sk_buff *rx_skbuff[RX_RING_SIZE];
441 
442 	dma_addr_t	bd_dma;
443 	struct bufdesc	*rx_bd_base;
444 	uint rx_ring_size;
445 
446 	struct bufdesc	*cur_rx;
447 };
448 
449 /* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
450  * tx_bd_base always point to the base of the buffer descriptors.  The
451  * cur_rx and cur_tx point to the currently available buffer.
452  * The dirty_tx tracks the current buffer that is being sent by the
453  * controller.  The cur_tx and dirty_tx are equal under both completely
454  * empty and completely full conditions.  The empty/ready indicator in
455  * the buffer descriptor determines the actual condition.
456  */
457 struct fec_enet_private {
458 	/* Hardware registers of the FEC device */
459 	void __iomem *hwp;
460 
461 	struct net_device *netdev;
462 
463 	struct clk *clk_ipg;
464 	struct clk *clk_ahb;
465 	struct clk *clk_ref;
466 	struct clk *clk_enet_out;
467 	struct clk *clk_ptp;
468 
469 	bool ptp_clk_on;
470 	struct mutex ptp_clk_mutex;
471 	unsigned int num_tx_queues;
472 	unsigned int num_rx_queues;
473 
474 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
475 	struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
476 	struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
477 
478 	unsigned int total_tx_ring_size;
479 	unsigned int total_rx_ring_size;
480 
481 	unsigned long work_tx;
482 	unsigned long work_rx;
483 	unsigned long work_ts;
484 	unsigned long work_mdio;
485 
486 	unsigned short bufdesc_size;
487 
488 	struct	platform_device *pdev;
489 
490 	int	dev_id;
491 
492 	/* Phylib and MDIO interface */
493 	struct	mii_bus *mii_bus;
494 	struct	phy_device *phy_dev;
495 	int	mii_timeout;
496 	uint	phy_speed;
497 	phy_interface_t	phy_interface;
498 	struct device_node *phy_node;
499 	int	link;
500 	int	full_duplex;
501 	int	speed;
502 	struct	completion mdio_done;
503 	int	irq[FEC_IRQ_NUM];
504 	int	bufdesc_ex;
505 	int	pause_flag;
506 
507 	struct	napi_struct napi;
508 	int	csum_flags;
509 
510 	struct work_struct tx_timeout_work;
511 
512 	struct ptp_clock *ptp_clock;
513 	struct ptp_clock_info ptp_caps;
514 	unsigned long last_overflow_check;
515 	spinlock_t tmreg_lock;
516 	struct cyclecounter cc;
517 	struct timecounter tc;
518 	int rx_hwtstamp_filter;
519 	u32 base_incval;
520 	u32 cycle_speed;
521 	int hwts_rx_en;
522 	int hwts_tx_en;
523 	struct delayed_work time_keep;
524 	struct regulator *reg_phy;
525 
526 	unsigned int tx_align;
527 	unsigned int rx_align;
528 
529 	/* hw interrupt coalesce */
530 	unsigned int rx_pkts_itr;
531 	unsigned int rx_time_itr;
532 	unsigned int tx_pkts_itr;
533 	unsigned int tx_time_itr;
534 	unsigned int itr_clk_rate;
535 
536 	u32 rx_copybreak;
537 
538 	/* ptp clock period in ns*/
539 	unsigned int ptp_inc;
540 
541 	/* pps  */
542 	int pps_channel;
543 	unsigned int reload_period;
544 	int pps_enable;
545 	unsigned int next_counter;
546 };
547 
548 void fec_ptp_init(struct platform_device *pdev);
549 void fec_ptp_start_cyclecounter(struct net_device *ndev);
550 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
551 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
552 uint fec_ptp_check_pps_event(struct fec_enet_private *fep);
553 
554 /****************************************************************************/
555 #endif /* FEC_H */
556