1 /* SPDX-License-Identifier: GPL-2.0 */
2 /****************************************************************************/
3 
4 /*
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
6  *		   processors.
7  *
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
10  */
11 
12 /****************************************************************************/
13 #ifndef FEC_H
14 #define	FEC_H
15 /****************************************************************************/
16 
17 #include <linux/clocksource.h>
18 #include <linux/net_tstamp.h>
19 #include <linux/ptp_clock_kernel.h>
20 #include <linux/timecounter.h>
21 
22 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
23     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
24     defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
25 /*
26  *	Just figures, Motorola would have to change the offsets for
27  *	registers in the same peripheral device on different models
28  *	of the ColdFire!
29  */
30 #define FEC_IEVENT		0x004 /* Interrupt event reg */
31 #define FEC_IMASK		0x008 /* Interrupt mask reg */
32 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
33 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
34 #define FEC_ECNTRL		0x024 /* Ethernet control reg */
35 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
36 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
37 #define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
38 #define FEC_R_CNTRL		0x084 /* Receive control reg */
39 #define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
40 #define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
41 #define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
42 #define FEC_OPD			0x0ec /* Opcode + Pause duration */
43 #define FEC_TXIC0		0x0f0 /* Tx Interrupt Coalescing for ring 0 */
44 #define FEC_TXIC1		0x0f4 /* Tx Interrupt Coalescing for ring 1 */
45 #define FEC_TXIC2		0x0f8 /* Tx Interrupt Coalescing for ring 2 */
46 #define FEC_RXIC0		0x100 /* Rx Interrupt Coalescing for ring 0 */
47 #define FEC_RXIC1		0x104 /* Rx Interrupt Coalescing for ring 1 */
48 #define FEC_RXIC2		0x108 /* Rx Interrupt Coalescing for ring 2 */
49 #define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
50 #define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
51 #define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
52 #define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
53 #define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
54 #define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
55 #define FEC_R_FSTART		0x150 /* FIFO receive start reg */
56 #define FEC_R_DES_START_1	0x160 /* Receive descriptor ring 1 */
57 #define FEC_X_DES_START_1	0x164 /* Transmit descriptor ring 1 */
58 #define FEC_R_BUFF_SIZE_1	0x168 /* Maximum receive buff ring1 size */
59 #define FEC_R_DES_START_2	0x16c /* Receive descriptor ring 2 */
60 #define FEC_X_DES_START_2	0x170 /* Transmit descriptor ring 2 */
61 #define FEC_R_BUFF_SIZE_2	0x174 /* Maximum receive buff ring2 size */
62 #define FEC_R_DES_START_0	0x180 /* Receive descriptor ring */
63 #define FEC_X_DES_START_0	0x184 /* Transmit descriptor ring */
64 #define FEC_R_BUFF_SIZE_0	0x188 /* Maximum receive buff size */
65 #define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
66 #define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
67 #define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
68 #define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
69 #define FEC_FTRL		0x1b0 /* Frame truncation receive length*/
70 #define FEC_RACC		0x1c4 /* Receive Accelerator function */
71 #define FEC_RCMR_1		0x1c8 /* Receive classification match ring 1 */
72 #define FEC_RCMR_2		0x1cc /* Receive classification match ring 2 */
73 #define FEC_DMA_CFG_1		0x1d8 /* DMA class configuration for ring 1 */
74 #define FEC_DMA_CFG_2		0x1dc /* DMA class Configuration for ring 2 */
75 #define FEC_R_DES_ACTIVE_1	0x1e0 /* Rx descriptor active for ring 1 */
76 #define FEC_X_DES_ACTIVE_1	0x1e4 /* Tx descriptor active for ring 1 */
77 #define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */
78 #define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */
79 #define FEC_QOS_SCHEME		0x1f0 /* Set multi queues Qos scheme */
80 #define FEC_LPI_SLEEP		0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */
81 #define FEC_LPI_WAKE		0x1f8 /* Set IEEE802.3az LPI Wake Tw time */
82 #define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
83 #define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */
84 
85 #define BM_MIIGSK_CFGR_MII		0x00
86 #define BM_MIIGSK_CFGR_RMII		0x01
87 #define BM_MIIGSK_CFGR_FRCONT_10M	0x40
88 
89 #define RMON_T_DROP		0x200 /* Count of frames not cntd correctly */
90 #define RMON_T_PACKETS		0x204 /* RMON TX packet count */
91 #define RMON_T_BC_PKT		0x208 /* RMON TX broadcast pkts */
92 #define RMON_T_MC_PKT		0x20c /* RMON TX multicast pkts */
93 #define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
94 #define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
95 #define RMON_T_OVERSIZE		0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
96 #define RMON_T_FRAG		0x21c /* RMON TX pkts < 64 bytes, bad CRC */
97 #define RMON_T_JAB		0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
98 #define RMON_T_COL		0x224 /* RMON TX collision count */
99 #define RMON_T_P64		0x228 /* RMON TX 64 byte pkts */
100 #define RMON_T_P65TO127		0x22c /* RMON TX 65 to 127 byte pkts */
101 #define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
102 #define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
103 #define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
104 #define RMON_T_P1024TO2047	0x23c /* RMON TX 1024 to 2047 byte pkts */
105 #define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
106 #define RMON_T_OCTETS		0x244 /* RMON TX octets */
107 #define IEEE_T_DROP		0x248 /* Count of frames not counted crtly */
108 #define IEEE_T_FRAME_OK		0x24c /* Frames tx'd OK */
109 #define IEEE_T_1COL		0x250 /* Frames tx'd with single collision */
110 #define IEEE_T_MCOL		0x254 /* Frames tx'd with multiple collision */
111 #define IEEE_T_DEF		0x258 /* Frames tx'd after deferral delay */
112 #define IEEE_T_LCOL		0x25c /* Frames tx'd with late collision */
113 #define IEEE_T_EXCOL		0x260 /* Frames tx'd with excesv collisions */
114 #define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
115 #define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
116 #define IEEE_T_SQE		0x26c /* Frames tx'd with SQE err */
117 #define IEEE_T_FDXFC		0x270 /* Flow control pause frames tx'd */
118 #define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
119 #define RMON_R_PACKETS		0x284 /* RMON RX packet count */
120 #define RMON_R_BC_PKT		0x288 /* RMON RX broadcast pkts */
121 #define RMON_R_MC_PKT		0x28c /* RMON RX multicast pkts */
122 #define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
123 #define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
124 #define RMON_R_OVERSIZE		0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
125 #define RMON_R_FRAG		0x29c /* RMON RX pkts < 64 bytes, bad CRC */
126 #define RMON_R_JAB		0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
127 #define RMON_R_RESVD_O		0x2a4 /* Reserved */
128 #define RMON_R_P64		0x2a8 /* RMON RX 64 byte pkts */
129 #define RMON_R_P65TO127		0x2ac /* RMON RX 65 to 127 byte pkts */
130 #define RMON_R_P128TO255	0x2b0 /* RMON RX 128 to 255 byte pkts */
131 #define RMON_R_P256TO511	0x2b4 /* RMON RX 256 to 511 byte pkts */
132 #define RMON_R_P512TO1023	0x2b8 /* RMON RX 512 to 1023 byte pkts */
133 #define RMON_R_P1024TO2047	0x2bc /* RMON RX 1024 to 2047 byte pkts */
134 #define RMON_R_P_GTE2048	0x2c0 /* RMON RX pkts > 2048 bytes */
135 #define RMON_R_OCTETS		0x2c4 /* RMON RX octets */
136 #define IEEE_R_DROP		0x2c8 /* Count frames not counted correctly */
137 #define IEEE_R_FRAME_OK		0x2cc /* Frames rx'd OK */
138 #define IEEE_R_CRC		0x2d0 /* Frames rx'd with CRC err */
139 #define IEEE_R_ALIGN		0x2d4 /* Frames rx'd with alignment err */
140 #define IEEE_R_MACERR		0x2d8 /* Receive FIFO overflow count */
141 #define IEEE_R_FDXFC		0x2dc /* Flow control pause frames rx'd */
142 #define IEEE_R_OCTETS_OK	0x2e0 /* Octet cnt for frames rx'd w/o err */
143 
144 #else
145 
146 #define FEC_ECNTRL		0x000 /* Ethernet control reg */
147 #define FEC_IEVENT		0x004 /* Interrupt even reg */
148 #define FEC_IMASK		0x008 /* Interrupt mask reg */
149 #define FEC_IVEC		0x00c /* Interrupt vec status reg */
150 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
151 #define FEC_R_DES_ACTIVE_1	FEC_R_DES_ACTIVE_0
152 #define FEC_R_DES_ACTIVE_2	FEC_R_DES_ACTIVE_0
153 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
154 #define FEC_X_DES_ACTIVE_1	FEC_X_DES_ACTIVE_0
155 #define FEC_X_DES_ACTIVE_2	FEC_X_DES_ACTIVE_0
156 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
157 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
158 #define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
159 #define FEC_R_FSTART		0x090 /* FIFO receive start reg */
160 #define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
161 #define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
162 #define FEC_R_CNTRL		0x104 /* Receive control reg */
163 #define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
164 #define FEC_X_CNTRL		0x144 /* Transmit Control reg */
165 #define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
166 #define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
167 #define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
168 #define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
169 #define FEC_R_DES_START_0	0x3d0 /* Receive descriptor ring */
170 #define FEC_R_DES_START_1	FEC_R_DES_START_0
171 #define FEC_R_DES_START_2	FEC_R_DES_START_0
172 #define FEC_X_DES_START_0	0x3d4 /* Transmit descriptor ring */
173 #define FEC_X_DES_START_1	FEC_X_DES_START_0
174 #define FEC_X_DES_START_2	FEC_X_DES_START_0
175 #define FEC_R_BUFF_SIZE_0	0x3d8 /* Maximum receive buff size */
176 #define FEC_R_BUFF_SIZE_1	FEC_R_BUFF_SIZE_0
177 #define FEC_R_BUFF_SIZE_2	FEC_R_BUFF_SIZE_0
178 #define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */
179 /* Not existed in real chip
180  * Just for pass build.
181  */
182 #define FEC_RCMR_1		0xfff
183 #define FEC_RCMR_2		0xfff
184 #define FEC_DMA_CFG_1		0xfff
185 #define FEC_DMA_CFG_2		0xfff
186 #define FEC_TXIC0		0xfff
187 #define FEC_TXIC1		0xfff
188 #define FEC_TXIC2		0xfff
189 #define FEC_RXIC0		0xfff
190 #define FEC_RXIC1		0xfff
191 #define FEC_RXIC2		0xfff
192 #define FEC_LPI_SLEEP		0xfff
193 #define FEC_LPI_WAKE		0xfff
194 #endif /* CONFIG_M5272 */
195 
196 
197 /*
198  *	Define the buffer descriptor structure.
199  *
200  *	Evidently, ARM SoCs have the FEC block generated in a
201  *	little endian mode so adjust endianness accordingly.
202  */
203 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
204 #define fec32_to_cpu le32_to_cpu
205 #define fec16_to_cpu le16_to_cpu
206 #define cpu_to_fec32 cpu_to_le32
207 #define cpu_to_fec16 cpu_to_le16
208 #define __fec32 __le32
209 #define __fec16 __le16
210 
211 struct bufdesc {
212 	__fec16 cbd_datlen;	/* Data length */
213 	__fec16 cbd_sc;		/* Control and status info */
214 	__fec32 cbd_bufaddr;	/* Buffer address */
215 };
216 #else
217 #define fec32_to_cpu be32_to_cpu
218 #define fec16_to_cpu be16_to_cpu
219 #define cpu_to_fec32 cpu_to_be32
220 #define cpu_to_fec16 cpu_to_be16
221 #define __fec32 __be32
222 #define __fec16 __be16
223 
224 struct bufdesc {
225 	__fec16	cbd_sc;		/* Control and status info */
226 	__fec16	cbd_datlen;	/* Data length */
227 	__fec32	cbd_bufaddr;	/* Buffer address */
228 };
229 #endif
230 
231 struct bufdesc_ex {
232 	struct bufdesc desc;
233 	__fec32 cbd_esc;
234 	__fec32 cbd_prot;
235 	__fec32 cbd_bdu;
236 	__fec32 ts;
237 	__fec16 res0[4];
238 };
239 
240 /*
241  *	The following definitions courtesy of commproc.h, which where
242  *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
243  */
244 #define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
245 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
246 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
247 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
248 #define BD_SC_CM	((ushort)0x0200)	/* Continuous mode */
249 #define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
250 #define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
251 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
252 #define BD_SC_FR	((ushort)0x0010)	/* Framing error */
253 #define BD_SC_PR	((ushort)0x0008)	/* Parity error */
254 #define BD_SC_OV	((ushort)0x0002)	/* Overrun */
255 #define BD_SC_CD	((ushort)0x0001)	/* ?? */
256 
257 /* Buffer descriptor control/status used by Ethernet receive.
258  */
259 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
260 #define BD_ENET_RX_WRAP		((ushort)0x2000)
261 #define BD_ENET_RX_INTR		((ushort)0x1000)
262 #define BD_ENET_RX_LAST		((ushort)0x0800)
263 #define BD_ENET_RX_FIRST	((ushort)0x0400)
264 #define BD_ENET_RX_MISS		((ushort)0x0100)
265 #define BD_ENET_RX_LG		((ushort)0x0020)
266 #define BD_ENET_RX_NO		((ushort)0x0010)
267 #define BD_ENET_RX_SH		((ushort)0x0008)
268 #define BD_ENET_RX_CR		((ushort)0x0004)
269 #define BD_ENET_RX_OV		((ushort)0x0002)
270 #define BD_ENET_RX_CL		((ushort)0x0001)
271 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
272 
273 /* Enhanced buffer descriptor control/status used by Ethernet receive */
274 #define BD_ENET_RX_VLAN		0x00000004
275 
276 /* Buffer descriptor control/status used by Ethernet transmit.
277  */
278 #define BD_ENET_TX_READY	((ushort)0x8000)
279 #define BD_ENET_TX_PAD		((ushort)0x4000)
280 #define BD_ENET_TX_WRAP		((ushort)0x2000)
281 #define BD_ENET_TX_INTR		((ushort)0x1000)
282 #define BD_ENET_TX_LAST		((ushort)0x0800)
283 #define BD_ENET_TX_TC		((ushort)0x0400)
284 #define BD_ENET_TX_DEF		((ushort)0x0200)
285 #define BD_ENET_TX_HB		((ushort)0x0100)
286 #define BD_ENET_TX_LC		((ushort)0x0080)
287 #define BD_ENET_TX_RL		((ushort)0x0040)
288 #define BD_ENET_TX_RCMASK	((ushort)0x003c)
289 #define BD_ENET_TX_UN		((ushort)0x0002)
290 #define BD_ENET_TX_CSL		((ushort)0x0001)
291 #define BD_ENET_TX_STATS	((ushort)0x0fff)	/* All status bits */
292 
293 /* enhanced buffer descriptor control/status used by Ethernet transmit */
294 #define BD_ENET_TX_INT		0x40000000
295 #define BD_ENET_TX_TS		0x20000000
296 #define BD_ENET_TX_PINS		0x10000000
297 #define BD_ENET_TX_IINS		0x08000000
298 
299 
300 /* This device has up to three irqs on some platforms */
301 #define FEC_IRQ_NUM		3
302 
303 /* Maximum number of queues supported
304  * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
305  * User can point the queue number that is less than or equal to 3.
306  */
307 #define FEC_ENET_MAX_TX_QS	3
308 #define FEC_ENET_MAX_RX_QS	3
309 
310 #define FEC_R_DES_START(X)	(((X) == 1) ? FEC_R_DES_START_1 : \
311 				(((X) == 2) ? \
312 					FEC_R_DES_START_2 : FEC_R_DES_START_0))
313 #define FEC_X_DES_START(X)	(((X) == 1) ? FEC_X_DES_START_1 : \
314 				(((X) == 2) ? \
315 					FEC_X_DES_START_2 : FEC_X_DES_START_0))
316 #define FEC_R_BUFF_SIZE(X)	(((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
317 				(((X) == 2) ? \
318 					FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
319 
320 #define FEC_DMA_CFG(X)		(((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
321 
322 #define DMA_CLASS_EN		(1 << 16)
323 #define FEC_RCMR(X)		(((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
324 #define IDLE_SLOPE_MASK		0xffff
325 #define IDLE_SLOPE_1		0x200 /* BW fraction: 0.5 */
326 #define IDLE_SLOPE_2		0x200 /* BW fraction: 0.5 */
327 #define IDLE_SLOPE(X)		(((X) == 1) ?				\
328 				(IDLE_SLOPE_1 & IDLE_SLOPE_MASK) :	\
329 				(IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
330 #define RCMR_MATCHEN		(0x1 << 16)
331 #define RCMR_CMP_CFG(v, n)	(((v) & 0x7) <<  (n << 2))
332 #define RCMR_CMP_1		(RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
333 				RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
334 #define RCMR_CMP_2		(RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
335 				RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
336 #define RCMR_CMP(X)		(((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
337 #define FEC_TX_BD_FTYPE(X)	(((X) & 0xf) << 20)
338 
339 /* The number of Tx and Rx buffers.  These are allocated from the page
340  * pool.  The code may assume these are power of two, so it it best
341  * to keep them that size.
342  * We don't need to allocate pages for the transmitter.  We just use
343  * the skbuffer directly.
344  */
345 
346 #define FEC_ENET_RX_PAGES	256
347 #define FEC_ENET_RX_FRSIZE	2048
348 #define FEC_ENET_RX_FRPPG	(PAGE_SIZE / FEC_ENET_RX_FRSIZE)
349 #define RX_RING_SIZE		(FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
350 #define FEC_ENET_TX_FRSIZE	2048
351 #define FEC_ENET_TX_FRPPG	(PAGE_SIZE / FEC_ENET_TX_FRSIZE)
352 #define TX_RING_SIZE		512	/* Must be power of two */
353 #define TX_RING_MOD_MASK	511	/*   for this to work */
354 
355 #define BD_ENET_RX_INT		0x00800000
356 #define BD_ENET_RX_PTP		((ushort)0x0400)
357 #define BD_ENET_RX_ICE		0x00000020
358 #define BD_ENET_RX_PCR		0x00000010
359 #define FLAG_RX_CSUM_ENABLED	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
360 #define FLAG_RX_CSUM_ERROR	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
361 
362 /* Interrupt events/masks. */
363 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
364 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
365 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
366 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
367 #define FEC_ENET_TXF_0	((uint)0x08000000)	/* Full frame transmitted */
368 #define FEC_ENET_TXF_1	((uint)0x00000008)	/* Full frame transmitted */
369 #define FEC_ENET_TXF_2	((uint)0x00000080)	/* Full frame transmitted */
370 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
371 #define FEC_ENET_RXF_0	((uint)0x02000000)	/* Full frame received */
372 #define FEC_ENET_RXF_1	((uint)0x00000002)	/* Full frame received */
373 #define FEC_ENET_RXF_2	((uint)0x00000020)	/* Full frame received */
374 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
375 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
376 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
377 #define FEC_ENET_WAKEUP	((uint)0x00020000)	/* Wakeup request */
378 #define FEC_ENET_TXF	(FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
379 #define FEC_ENET_RXF	(FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
380 #define FEC_ENET_RXF_GET(X)	(((X) == 0) ? FEC_ENET_RXF_0 :	\
381 				(((X) == 1) ? FEC_ENET_RXF_1 :	\
382 				FEC_ENET_RXF_2))
383 #define FEC_ENET_TS_AVAIL       ((uint)0x00010000)
384 #define FEC_ENET_TS_TIMER       ((uint)0x00008000)
385 
386 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)
387 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
388 
389 #define FEC_ENET_TXC_DLY	((uint)0x00010000)
390 #define FEC_ENET_RXC_DLY	((uint)0x00020000)
391 
392 /* ENET interrupt coalescing macro define */
393 #define FEC_ITR_CLK_SEL		(0x1 << 30)
394 #define FEC_ITR_EN		(0x1 << 31)
395 #define FEC_ITR_ICFT(X)		(((X) & 0xff) << 20)
396 #define FEC_ITR_ICTT(X)		((X) & 0xffff)
397 #define FEC_ITR_ICFT_DEFAULT	200  /* Set 200 frame count threshold */
398 #define FEC_ITR_ICTT_DEFAULT	1000 /* Set 1000us timer threshold */
399 
400 #define FEC_VLAN_TAG_LEN	0x04
401 #define FEC_ETHTYPE_LEN		0x02
402 
403 /* Controller is ENET-MAC */
404 #define FEC_QUIRK_ENET_MAC		(1 << 0)
405 /* Controller needs driver to swap frame */
406 #define FEC_QUIRK_SWAP_FRAME		(1 << 1)
407 /* Controller uses gasket */
408 #define FEC_QUIRK_USE_GASKET		(1 << 2)
409 /* Controller has GBIT support */
410 #define FEC_QUIRK_HAS_GBIT		(1 << 3)
411 /* Controller has extend desc buffer */
412 #define FEC_QUIRK_HAS_BUFDESC_EX	(1 << 4)
413 /* Controller has hardware checksum support */
414 #define FEC_QUIRK_HAS_CSUM		(1 << 5)
415 /* Controller has hardware vlan support */
416 #define FEC_QUIRK_HAS_VLAN		(1 << 6)
417 /* ENET IP errata ERR006358
418  *
419  * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
420  * detected as not set during a prior frame transmission, then the
421  * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
422  * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
423  * frames not being transmitted until there is a 0-to-1 transition on
424  * ENET_TDAR[TDAR].
425  */
426 #define FEC_QUIRK_ERR006358		(1 << 7)
427 /* ENET IP hw AVB
428  *
429  * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
430  * - Two class indicators on receive with configurable priority
431  * - Two class indicators and line speed timer on transmit allowing
432  *   implementation class credit based shapers externally
433  * - Additional DMA registers provisioned to allow managing up to 3
434  *   independent rings
435  */
436 #define FEC_QUIRK_HAS_AVB		(1 << 8)
437 /* There is a TDAR race condition for mutliQ when the software sets TDAR
438  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
439  * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
440  * The issue exist at i.MX6SX enet IP.
441  */
442 #define FEC_QUIRK_ERR007885		(1 << 9)
443 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
444  * After set ENET_ATCR[Capture], there need some time cycles before the counter
445  * value is capture in the register clock domain.
446  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
447  * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
448  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
449  * (40ns * 6).
450  */
451 #define FEC_QUIRK_BUG_CAPTURE		(1 << 10)
452 /* Controller has only one MDIO bus */
453 #define FEC_QUIRK_SINGLE_MDIO		(1 << 11)
454 /* Controller supports RACC register */
455 #define FEC_QUIRK_HAS_RACC		(1 << 12)
456 /* Controller supports interrupt coalesc */
457 #define FEC_QUIRK_HAS_COALESCE		(1 << 13)
458 /* Interrupt doesn't wake CPU from deep idle */
459 #define FEC_QUIRK_ERR006687		(1 << 14)
460 /* The MIB counters should be cleared and enabled during
461  * initialisation.
462  */
463 #define FEC_QUIRK_MIB_CLEAR		(1 << 15)
464 /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers,
465  * those FIFO receive registers are resolved in other platforms.
466  */
467 #define FEC_QUIRK_HAS_FRREG		(1 << 16)
468 
469 /* Some FEC hardware blocks need the MMFR cleared at setup time to avoid
470  * the generation of an MII event. This must be avoided in the older
471  * FEC blocks where it will stop MII events being generated.
472  */
473 #define FEC_QUIRK_CLEAR_SETUP_MII	(1 << 17)
474 
475 /* Some link partners do not tolerate the momentary reset of the REF_CLK
476  * frequency when the RNCTL register is cleared by hardware reset.
477  */
478 #define FEC_QUIRK_NO_HARD_RESET		(1 << 18)
479 
480 /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to
481  * represents this ENET IP.
482  */
483 #define FEC_QUIRK_HAS_MULTI_QUEUES	(1 << 19)
484 
485 /* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE
486  * standard. For the transmission, MAC supply two user registers to set
487  * Sleep (TS) and Wake (TW) time.
488  */
489 #define FEC_QUIRK_HAS_EEE		(1 << 20)
490 
491 /* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC
492  * as an alternative option to make sure it works well with various PHYs.
493  * For the implementation of delayed clock, ENET takes synchronized 250MHz
494  * clocks to generate 2ns delay.
495  */
496 #define FEC_QUIRK_DELAYED_CLKS_SUPPORT	(1 << 21)
497 
498 /* i.MX8MQ SoC integration mix wakeup interrupt signal into "int2" interrupt line. */
499 #define FEC_QUIRK_WAKEUP_FROM_INT2	(1 << 22)
500 
501 struct bufdesc_prop {
502 	int qid;
503 	/* Address of Rx and Tx buffers */
504 	struct bufdesc	*base;
505 	struct bufdesc	*last;
506 	struct bufdesc	*cur;
507 	void __iomem	*reg_desc_active;
508 	dma_addr_t	dma;
509 	unsigned short ring_size;
510 	unsigned char dsize;
511 	unsigned char dsize_log2;
512 };
513 
514 struct fec_enet_priv_tx_q {
515 	struct bufdesc_prop bd;
516 	unsigned char *tx_bounce[TX_RING_SIZE];
517 	struct  sk_buff *tx_skbuff[TX_RING_SIZE];
518 
519 	unsigned short tx_stop_threshold;
520 	unsigned short tx_wake_threshold;
521 
522 	struct bufdesc	*dirty_tx;
523 	char *tso_hdrs;
524 	dma_addr_t tso_hdrs_dma;
525 };
526 
527 struct fec_enet_priv_rx_q {
528 	struct bufdesc_prop bd;
529 	struct  sk_buff *rx_skbuff[RX_RING_SIZE];
530 };
531 
532 struct fec_stop_mode_gpr {
533 	struct regmap *gpr;
534 	u8 reg;
535 	u8 bit;
536 };
537 
538 /* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
539  * tx_bd_base always point to the base of the buffer descriptors.  The
540  * cur_rx and cur_tx point to the currently available buffer.
541  * The dirty_tx tracks the current buffer that is being sent by the
542  * controller.  The cur_tx and dirty_tx are equal under both completely
543  * empty and completely full conditions.  The empty/ready indicator in
544  * the buffer descriptor determines the actual condition.
545  */
546 struct fec_enet_private {
547 	/* Hardware registers of the FEC device */
548 	void __iomem *hwp;
549 
550 	struct net_device *netdev;
551 
552 	struct clk *clk_ipg;
553 	struct clk *clk_ahb;
554 	struct clk *clk_ref;
555 	struct clk *clk_enet_out;
556 	struct clk *clk_ptp;
557 	struct clk *clk_2x_txclk;
558 
559 	bool ptp_clk_on;
560 	struct mutex ptp_clk_mutex;
561 	unsigned int num_tx_queues;
562 	unsigned int num_rx_queues;
563 
564 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
565 	struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
566 	struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
567 
568 	unsigned int total_tx_ring_size;
569 	unsigned int total_rx_ring_size;
570 
571 	struct	platform_device *pdev;
572 
573 	int	dev_id;
574 
575 	/* Phylib and MDIO interface */
576 	struct	mii_bus *mii_bus;
577 	uint	phy_speed;
578 	phy_interface_t	phy_interface;
579 	struct device_node *phy_node;
580 	bool	rgmii_txc_dly;
581 	bool	rgmii_rxc_dly;
582 	int	link;
583 	int	full_duplex;
584 	int	speed;
585 	int	irq[FEC_IRQ_NUM];
586 	bool	bufdesc_ex;
587 	int	pause_flag;
588 	int	wol_flag;
589 	int	wake_irq;
590 	u32	quirks;
591 
592 	struct	napi_struct napi;
593 	int	csum_flags;
594 
595 	struct work_struct tx_timeout_work;
596 
597 	struct ptp_clock *ptp_clock;
598 	struct ptp_clock_info ptp_caps;
599 	unsigned long last_overflow_check;
600 	spinlock_t tmreg_lock;
601 	struct cyclecounter cc;
602 	struct timecounter tc;
603 	int rx_hwtstamp_filter;
604 	u32 base_incval;
605 	u32 cycle_speed;
606 	int hwts_rx_en;
607 	int hwts_tx_en;
608 	struct delayed_work time_keep;
609 	struct regulator *reg_phy;
610 	struct fec_stop_mode_gpr stop_gpr;
611 
612 	unsigned int tx_align;
613 	unsigned int rx_align;
614 
615 	/* hw interrupt coalesce */
616 	unsigned int rx_pkts_itr;
617 	unsigned int rx_time_itr;
618 	unsigned int tx_pkts_itr;
619 	unsigned int tx_time_itr;
620 	unsigned int itr_clk_rate;
621 
622 	/* tx lpi eee mode */
623 	struct ethtool_eee eee;
624 	unsigned int clk_ref_rate;
625 
626 	u32 rx_copybreak;
627 
628 	/* ptp clock period in ns*/
629 	unsigned int ptp_inc;
630 
631 	/* pps  */
632 	int pps_channel;
633 	unsigned int reload_period;
634 	int pps_enable;
635 	unsigned int next_counter;
636 
637 	struct {
638 		struct timespec64 ts_phc;
639 		u64 ns_sys;
640 		u32 at_corr;
641 		u8 at_inc_corr;
642 	} ptp_saved_state;
643 
644 	u64 ethtool_stats[];
645 };
646 
647 void fec_ptp_init(struct platform_device *pdev, int irq_idx);
648 void fec_ptp_stop(struct platform_device *pdev);
649 void fec_ptp_start_cyclecounter(struct net_device *ndev);
650 void fec_ptp_disable_hwts(struct net_device *ndev);
651 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
652 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
653 
654 void fec_ptp_save_state(struct fec_enet_private *fep);
655 int fec_ptp_restore_state(struct fec_enet_private *fep);
656 
657 /****************************************************************************/
658 #endif /* FEC_H */
659