1 /* SPDX-License-Identifier: GPL-2.0 */
2 /****************************************************************************/
3 
4 /*
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
6  *		   processors.
7  *
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
10  */
11 
12 /****************************************************************************/
13 #ifndef FEC_H
14 #define	FEC_H
15 /****************************************************************************/
16 
17 #include <linux/clocksource.h>
18 #include <linux/net_tstamp.h>
19 #include <linux/ptp_clock_kernel.h>
20 #include <linux/timecounter.h>
21 
22 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
23     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
24 /*
25  *	Just figures, Motorola would have to change the offsets for
26  *	registers in the same peripheral device on different models
27  *	of the ColdFire!
28  */
29 #define FEC_IEVENT		0x004 /* Interrupt event reg */
30 #define FEC_IMASK		0x008 /* Interrupt mask reg */
31 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
32 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
33 #define FEC_ECNTRL		0x024 /* Ethernet control reg */
34 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
35 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
36 #define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
37 #define FEC_R_CNTRL		0x084 /* Receive control reg */
38 #define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
39 #define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
40 #define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
41 #define FEC_OPD			0x0ec /* Opcode + Pause duration */
42 #define FEC_TXIC0		0x0f0 /* Tx Interrupt Coalescing for ring 0 */
43 #define FEC_TXIC1		0x0f4 /* Tx Interrupt Coalescing for ring 1 */
44 #define FEC_TXIC2		0x0f8 /* Tx Interrupt Coalescing for ring 2 */
45 #define FEC_RXIC0		0x100 /* Rx Interrupt Coalescing for ring 0 */
46 #define FEC_RXIC1		0x104 /* Rx Interrupt Coalescing for ring 1 */
47 #define FEC_RXIC2		0x108 /* Rx Interrupt Coalescing for ring 2 */
48 #define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
49 #define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
50 #define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
51 #define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
52 #define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
53 #define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
54 #define FEC_R_FSTART		0x150 /* FIFO receive start reg */
55 #define FEC_R_DES_START_1	0x160 /* Receive descriptor ring 1 */
56 #define FEC_X_DES_START_1	0x164 /* Transmit descriptor ring 1 */
57 #define FEC_R_BUFF_SIZE_1	0x168 /* Maximum receive buff ring1 size */
58 #define FEC_R_DES_START_2	0x16c /* Receive descriptor ring 2 */
59 #define FEC_X_DES_START_2	0x170 /* Transmit descriptor ring 2 */
60 #define FEC_R_BUFF_SIZE_2	0x174 /* Maximum receive buff ring2 size */
61 #define FEC_R_DES_START_0	0x180 /* Receive descriptor ring */
62 #define FEC_X_DES_START_0	0x184 /* Transmit descriptor ring */
63 #define FEC_R_BUFF_SIZE_0	0x188 /* Maximum receive buff size */
64 #define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
65 #define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
66 #define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
67 #define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
68 #define FEC_FTRL		0x1b0 /* Frame truncation receive length*/
69 #define FEC_RACC		0x1c4 /* Receive Accelerator function */
70 #define FEC_RCMR_1		0x1c8 /* Receive classification match ring 1 */
71 #define FEC_RCMR_2		0x1cc /* Receive classification match ring 2 */
72 #define FEC_DMA_CFG_1		0x1d8 /* DMA class configuration for ring 1 */
73 #define FEC_DMA_CFG_2		0x1dc /* DMA class Configuration for ring 2 */
74 #define FEC_R_DES_ACTIVE_1	0x1e0 /* Rx descriptor active for ring 1 */
75 #define FEC_X_DES_ACTIVE_1	0x1e4 /* Tx descriptor active for ring 1 */
76 #define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */
77 #define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */
78 #define FEC_QOS_SCHEME		0x1f0 /* Set multi queues Qos scheme */
79 #define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
80 #define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */
81 
82 #define BM_MIIGSK_CFGR_MII		0x00
83 #define BM_MIIGSK_CFGR_RMII		0x01
84 #define BM_MIIGSK_CFGR_FRCONT_10M	0x40
85 
86 #define RMON_T_DROP		0x200 /* Count of frames not cntd correctly */
87 #define RMON_T_PACKETS		0x204 /* RMON TX packet count */
88 #define RMON_T_BC_PKT		0x208 /* RMON TX broadcast pkts */
89 #define RMON_T_MC_PKT		0x20c /* RMON TX multicast pkts */
90 #define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
91 #define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
92 #define RMON_T_OVERSIZE		0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
93 #define RMON_T_FRAG		0x21c /* RMON TX pkts < 64 bytes, bad CRC */
94 #define RMON_T_JAB		0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
95 #define RMON_T_COL		0x224 /* RMON TX collision count */
96 #define RMON_T_P64		0x228 /* RMON TX 64 byte pkts */
97 #define RMON_T_P65TO127		0x22c /* RMON TX 65 to 127 byte pkts */
98 #define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
99 #define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
100 #define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
101 #define RMON_T_P1024TO2047	0x23c /* RMON TX 1024 to 2047 byte pkts */
102 #define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
103 #define RMON_T_OCTETS		0x244 /* RMON TX octets */
104 #define IEEE_T_DROP		0x248 /* Count of frames not counted crtly */
105 #define IEEE_T_FRAME_OK		0x24c /* Frames tx'd OK */
106 #define IEEE_T_1COL		0x250 /* Frames tx'd with single collision */
107 #define IEEE_T_MCOL		0x254 /* Frames tx'd with multiple collision */
108 #define IEEE_T_DEF		0x258 /* Frames tx'd after deferral delay */
109 #define IEEE_T_LCOL		0x25c /* Frames tx'd with late collision */
110 #define IEEE_T_EXCOL		0x260 /* Frames tx'd with excesv collisions */
111 #define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
112 #define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
113 #define IEEE_T_SQE		0x26c /* Frames tx'd with SQE err */
114 #define IEEE_T_FDXFC		0x270 /* Flow control pause frames tx'd */
115 #define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
116 #define RMON_R_PACKETS		0x284 /* RMON RX packet count */
117 #define RMON_R_BC_PKT		0x288 /* RMON RX broadcast pkts */
118 #define RMON_R_MC_PKT		0x28c /* RMON RX multicast pkts */
119 #define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
120 #define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
121 #define RMON_R_OVERSIZE		0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
122 #define RMON_R_FRAG		0x29c /* RMON RX pkts < 64 bytes, bad CRC */
123 #define RMON_R_JAB		0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
124 #define RMON_R_RESVD_O		0x2a4 /* Reserved */
125 #define RMON_R_P64		0x2a8 /* RMON RX 64 byte pkts */
126 #define RMON_R_P65TO127		0x2ac /* RMON RX 65 to 127 byte pkts */
127 #define RMON_R_P128TO255	0x2b0 /* RMON RX 128 to 255 byte pkts */
128 #define RMON_R_P256TO511	0x2b4 /* RMON RX 256 to 511 byte pkts */
129 #define RMON_R_P512TO1023	0x2b8 /* RMON RX 512 to 1023 byte pkts */
130 #define RMON_R_P1024TO2047	0x2bc /* RMON RX 1024 to 2047 byte pkts */
131 #define RMON_R_P_GTE2048	0x2c0 /* RMON RX pkts > 2048 bytes */
132 #define RMON_R_OCTETS		0x2c4 /* RMON RX octets */
133 #define IEEE_R_DROP		0x2c8 /* Count frames not counted correctly */
134 #define IEEE_R_FRAME_OK		0x2cc /* Frames rx'd OK */
135 #define IEEE_R_CRC		0x2d0 /* Frames rx'd with CRC err */
136 #define IEEE_R_ALIGN		0x2d4 /* Frames rx'd with alignment err */
137 #define IEEE_R_MACERR		0x2d8 /* Receive FIFO overflow count */
138 #define IEEE_R_FDXFC		0x2dc /* Flow control pause frames rx'd */
139 #define IEEE_R_OCTETS_OK	0x2e0 /* Octet cnt for frames rx'd w/o err */
140 
141 #else
142 
143 #define FEC_ECNTRL		0x000 /* Ethernet control reg */
144 #define FEC_IEVENT		0x004 /* Interrupt even reg */
145 #define FEC_IMASK		0x008 /* Interrupt mask reg */
146 #define FEC_IVEC		0x00c /* Interrupt vec status reg */
147 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
148 #define FEC_R_DES_ACTIVE_1	FEC_R_DES_ACTIVE_0
149 #define FEC_R_DES_ACTIVE_2	FEC_R_DES_ACTIVE_0
150 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
151 #define FEC_X_DES_ACTIVE_1	FEC_X_DES_ACTIVE_0
152 #define FEC_X_DES_ACTIVE_2	FEC_X_DES_ACTIVE_0
153 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
154 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
155 #define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
156 #define FEC_R_FSTART		0x090 /* FIFO receive start reg */
157 #define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
158 #define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
159 #define FEC_R_CNTRL		0x104 /* Receive control reg */
160 #define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
161 #define FEC_X_CNTRL		0x144 /* Transmit Control reg */
162 #define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
163 #define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
164 #define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
165 #define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
166 #define FEC_R_DES_START_0	0x3d0 /* Receive descriptor ring */
167 #define FEC_R_DES_START_1	FEC_R_DES_START_0
168 #define FEC_R_DES_START_2	FEC_R_DES_START_0
169 #define FEC_X_DES_START_0	0x3d4 /* Transmit descriptor ring */
170 #define FEC_X_DES_START_1	FEC_X_DES_START_0
171 #define FEC_X_DES_START_2	FEC_X_DES_START_0
172 #define FEC_R_BUFF_SIZE_0	0x3d8 /* Maximum receive buff size */
173 #define FEC_R_BUFF_SIZE_1	FEC_R_BUFF_SIZE_0
174 #define FEC_R_BUFF_SIZE_2	FEC_R_BUFF_SIZE_0
175 #define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */
176 /* Not existed in real chip
177  * Just for pass build.
178  */
179 #define FEC_RCMR_1		0xfff
180 #define FEC_RCMR_2		0xfff
181 #define FEC_DMA_CFG_1		0xfff
182 #define FEC_DMA_CFG_2		0xfff
183 #define FEC_TXIC0		0xfff
184 #define FEC_TXIC1		0xfff
185 #define FEC_TXIC2		0xfff
186 #define FEC_RXIC0		0xfff
187 #define FEC_RXIC1		0xfff
188 #define FEC_RXIC2		0xfff
189 #endif /* CONFIG_M5272 */
190 
191 
192 /*
193  *	Define the buffer descriptor structure.
194  *
195  *	Evidently, ARM SoCs have the FEC block generated in a
196  *	little endian mode so adjust endianness accordingly.
197  */
198 #if defined(CONFIG_ARM)
199 #define fec32_to_cpu le32_to_cpu
200 #define fec16_to_cpu le16_to_cpu
201 #define cpu_to_fec32 cpu_to_le32
202 #define cpu_to_fec16 cpu_to_le16
203 #define __fec32 __le32
204 #define __fec16 __le16
205 
206 struct bufdesc {
207 	__fec16 cbd_datlen;	/* Data length */
208 	__fec16 cbd_sc;		/* Control and status info */
209 	__fec32 cbd_bufaddr;	/* Buffer address */
210 };
211 #else
212 #define fec32_to_cpu be32_to_cpu
213 #define fec16_to_cpu be16_to_cpu
214 #define cpu_to_fec32 cpu_to_be32
215 #define cpu_to_fec16 cpu_to_be16
216 #define __fec32 __be32
217 #define __fec16 __be16
218 
219 struct bufdesc {
220 	__fec16	cbd_sc;		/* Control and status info */
221 	__fec16	cbd_datlen;	/* Data length */
222 	__fec32	cbd_bufaddr;	/* Buffer address */
223 };
224 #endif
225 
226 struct bufdesc_ex {
227 	struct bufdesc desc;
228 	__fec32 cbd_esc;
229 	__fec32 cbd_prot;
230 	__fec32 cbd_bdu;
231 	__fec32 ts;
232 	__fec16 res0[4];
233 };
234 
235 /*
236  *	The following definitions courtesy of commproc.h, which where
237  *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
238  */
239 #define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
240 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
241 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
242 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
243 #define BD_SC_CM	((ushort)0x0200)	/* Continuous mode */
244 #define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
245 #define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
246 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
247 #define BD_SC_FR	((ushort)0x0010)	/* Framing error */
248 #define BD_SC_PR	((ushort)0x0008)	/* Parity error */
249 #define BD_SC_OV	((ushort)0x0002)	/* Overrun */
250 #define BD_SC_CD	((ushort)0x0001)	/* ?? */
251 
252 /* Buffer descriptor control/status used by Ethernet receive.
253  */
254 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
255 #define BD_ENET_RX_WRAP		((ushort)0x2000)
256 #define BD_ENET_RX_INTR		((ushort)0x1000)
257 #define BD_ENET_RX_LAST		((ushort)0x0800)
258 #define BD_ENET_RX_FIRST	((ushort)0x0400)
259 #define BD_ENET_RX_MISS		((ushort)0x0100)
260 #define BD_ENET_RX_LG		((ushort)0x0020)
261 #define BD_ENET_RX_NO		((ushort)0x0010)
262 #define BD_ENET_RX_SH		((ushort)0x0008)
263 #define BD_ENET_RX_CR		((ushort)0x0004)
264 #define BD_ENET_RX_OV		((ushort)0x0002)
265 #define BD_ENET_RX_CL		((ushort)0x0001)
266 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
267 
268 /* Enhanced buffer descriptor control/status used by Ethernet receive */
269 #define BD_ENET_RX_VLAN		0x00000004
270 
271 /* Buffer descriptor control/status used by Ethernet transmit.
272  */
273 #define BD_ENET_TX_READY	((ushort)0x8000)
274 #define BD_ENET_TX_PAD		((ushort)0x4000)
275 #define BD_ENET_TX_WRAP		((ushort)0x2000)
276 #define BD_ENET_TX_INTR		((ushort)0x1000)
277 #define BD_ENET_TX_LAST		((ushort)0x0800)
278 #define BD_ENET_TX_TC		((ushort)0x0400)
279 #define BD_ENET_TX_DEF		((ushort)0x0200)
280 #define BD_ENET_TX_HB		((ushort)0x0100)
281 #define BD_ENET_TX_LC		((ushort)0x0080)
282 #define BD_ENET_TX_RL		((ushort)0x0040)
283 #define BD_ENET_TX_RCMASK	((ushort)0x003c)
284 #define BD_ENET_TX_UN		((ushort)0x0002)
285 #define BD_ENET_TX_CSL		((ushort)0x0001)
286 #define BD_ENET_TX_STATS	((ushort)0x0fff)	/* All status bits */
287 
288 /* enhanced buffer descriptor control/status used by Ethernet transmit */
289 #define BD_ENET_TX_INT		0x40000000
290 #define BD_ENET_TX_TS		0x20000000
291 #define BD_ENET_TX_PINS		0x10000000
292 #define BD_ENET_TX_IINS		0x08000000
293 
294 
295 /* This device has up to three irqs on some platforms */
296 #define FEC_IRQ_NUM		3
297 
298 /* Maximum number of queues supported
299  * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
300  * User can point the queue number that is less than or equal to 3.
301  */
302 #define FEC_ENET_MAX_TX_QS	3
303 #define FEC_ENET_MAX_RX_QS	3
304 
305 #define FEC_R_DES_START(X)	(((X) == 1) ? FEC_R_DES_START_1 : \
306 				(((X) == 2) ? \
307 					FEC_R_DES_START_2 : FEC_R_DES_START_0))
308 #define FEC_X_DES_START(X)	(((X) == 1) ? FEC_X_DES_START_1 : \
309 				(((X) == 2) ? \
310 					FEC_X_DES_START_2 : FEC_X_DES_START_0))
311 #define FEC_R_BUFF_SIZE(X)	(((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
312 				(((X) == 2) ? \
313 					FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
314 
315 #define FEC_DMA_CFG(X)		(((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
316 
317 #define DMA_CLASS_EN		(1 << 16)
318 #define FEC_RCMR(X)		(((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
319 #define IDLE_SLOPE_MASK		0xffff
320 #define IDLE_SLOPE_1		0x200 /* BW fraction: 0.5 */
321 #define IDLE_SLOPE_2		0x200 /* BW fraction: 0.5 */
322 #define IDLE_SLOPE(X)		(((X) == 1) ?				\
323 				(IDLE_SLOPE_1 & IDLE_SLOPE_MASK) :	\
324 				(IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
325 #define RCMR_MATCHEN		(0x1 << 16)
326 #define RCMR_CMP_CFG(v, n)	(((v) & 0x7) <<  (n << 2))
327 #define RCMR_CMP_1		(RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
328 				RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
329 #define RCMR_CMP_2		(RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
330 				RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
331 #define RCMR_CMP(X)		(((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
332 #define FEC_TX_BD_FTYPE(X)	(((X) & 0xf) << 20)
333 
334 /* The number of Tx and Rx buffers.  These are allocated from the page
335  * pool.  The code may assume these are power of two, so it it best
336  * to keep them that size.
337  * We don't need to allocate pages for the transmitter.  We just use
338  * the skbuffer directly.
339  */
340 
341 #define FEC_ENET_RX_PAGES	256
342 #define FEC_ENET_RX_FRSIZE	2048
343 #define FEC_ENET_RX_FRPPG	(PAGE_SIZE / FEC_ENET_RX_FRSIZE)
344 #define RX_RING_SIZE		(FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
345 #define FEC_ENET_TX_FRSIZE	2048
346 #define FEC_ENET_TX_FRPPG	(PAGE_SIZE / FEC_ENET_TX_FRSIZE)
347 #define TX_RING_SIZE		512	/* Must be power of two */
348 #define TX_RING_MOD_MASK	511	/*   for this to work */
349 
350 #define BD_ENET_RX_INT		0x00800000
351 #define BD_ENET_RX_PTP		((ushort)0x0400)
352 #define BD_ENET_RX_ICE		0x00000020
353 #define BD_ENET_RX_PCR		0x00000010
354 #define FLAG_RX_CSUM_ENABLED	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
355 #define FLAG_RX_CSUM_ERROR	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
356 
357 /* Interrupt events/masks. */
358 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
359 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
360 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
361 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
362 #define FEC_ENET_TXF_0	((uint)0x08000000)	/* Full frame transmitted */
363 #define FEC_ENET_TXF_1	((uint)0x00000008)	/* Full frame transmitted */
364 #define FEC_ENET_TXF_2	((uint)0x00000080)	/* Full frame transmitted */
365 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
366 #define FEC_ENET_RXF_0	((uint)0x02000000)	/* Full frame received */
367 #define FEC_ENET_RXF_1	((uint)0x00000002)	/* Full frame received */
368 #define FEC_ENET_RXF_2	((uint)0x00000020)	/* Full frame received */
369 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
370 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
371 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
372 #define FEC_ENET_WAKEUP	((uint)0x00020000)	/* Wakeup request */
373 #define FEC_ENET_TXF	(FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
374 #define FEC_ENET_RXF	(FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
375 #define FEC_ENET_TS_AVAIL       ((uint)0x00010000)
376 #define FEC_ENET_TS_TIMER       ((uint)0x00008000)
377 
378 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
379 #define FEC_NAPI_IMASK	FEC_ENET_MII
380 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
381 
382 /* ENET interrupt coalescing macro define */
383 #define FEC_ITR_CLK_SEL		(0x1 << 30)
384 #define FEC_ITR_EN		(0x1 << 31)
385 #define FEC_ITR_ICFT(X)		(((X) & 0xff) << 20)
386 #define FEC_ITR_ICTT(X)		((X) & 0xffff)
387 #define FEC_ITR_ICFT_DEFAULT	200  /* Set 200 frame count threshold */
388 #define FEC_ITR_ICTT_DEFAULT	1000 /* Set 1000us timer threshold */
389 
390 #define FEC_VLAN_TAG_LEN	0x04
391 #define FEC_ETHTYPE_LEN		0x02
392 
393 /* Controller is ENET-MAC */
394 #define FEC_QUIRK_ENET_MAC		(1 << 0)
395 /* Controller needs driver to swap frame */
396 #define FEC_QUIRK_SWAP_FRAME		(1 << 1)
397 /* Controller uses gasket */
398 #define FEC_QUIRK_USE_GASKET		(1 << 2)
399 /* Controller has GBIT support */
400 #define FEC_QUIRK_HAS_GBIT		(1 << 3)
401 /* Controller has extend desc buffer */
402 #define FEC_QUIRK_HAS_BUFDESC_EX	(1 << 4)
403 /* Controller has hardware checksum support */
404 #define FEC_QUIRK_HAS_CSUM		(1 << 5)
405 /* Controller has hardware vlan support */
406 #define FEC_QUIRK_HAS_VLAN		(1 << 6)
407 /* ENET IP errata ERR006358
408  *
409  * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
410  * detected as not set during a prior frame transmission, then the
411  * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
412  * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
413  * frames not being transmitted until there is a 0-to-1 transition on
414  * ENET_TDAR[TDAR].
415  */
416 #define FEC_QUIRK_ERR006358		(1 << 7)
417 /* ENET IP hw AVB
418  *
419  * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
420  * - Two class indicators on receive with configurable priority
421  * - Two class indicators and line speed timer on transmit allowing
422  *   implementation class credit based shapers externally
423  * - Additional DMA registers provisioned to allow managing up to 3
424  *   independent rings
425  */
426 #define FEC_QUIRK_HAS_AVB		(1 << 8)
427 /* There is a TDAR race condition for mutliQ when the software sets TDAR
428  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
429  * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
430  * The issue exist at i.MX6SX enet IP.
431  */
432 #define FEC_QUIRK_ERR007885		(1 << 9)
433 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
434  * After set ENET_ATCR[Capture], there need some time cycles before the counter
435  * value is capture in the register clock domain.
436  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
437  * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
438  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
439  * (40ns * 6).
440  */
441 #define FEC_QUIRK_BUG_CAPTURE		(1 << 10)
442 /* Controller has only one MDIO bus */
443 #define FEC_QUIRK_SINGLE_MDIO		(1 << 11)
444 /* Controller supports RACC register */
445 #define FEC_QUIRK_HAS_RACC		(1 << 12)
446 /* Controller supports interrupt coalesc */
447 #define FEC_QUIRK_HAS_COALESCE		(1 << 13)
448 /* Interrupt doesn't wake CPU from deep idle */
449 #define FEC_QUIRK_ERR006687		(1 << 14)
450 /* The MIB counters should be cleared and enabled during
451  * initialisation.
452  */
453 #define FEC_QUIRK_MIB_CLEAR		(1 << 15)
454 
455 struct bufdesc_prop {
456 	int qid;
457 	/* Address of Rx and Tx buffers */
458 	struct bufdesc	*base;
459 	struct bufdesc	*last;
460 	struct bufdesc	*cur;
461 	void __iomem	*reg_desc_active;
462 	dma_addr_t	dma;
463 	unsigned short ring_size;
464 	unsigned char dsize;
465 	unsigned char dsize_log2;
466 };
467 
468 struct fec_enet_priv_tx_q {
469 	struct bufdesc_prop bd;
470 	unsigned char *tx_bounce[TX_RING_SIZE];
471 	struct  sk_buff *tx_skbuff[TX_RING_SIZE];
472 
473 	unsigned short tx_stop_threshold;
474 	unsigned short tx_wake_threshold;
475 
476 	struct bufdesc	*dirty_tx;
477 	char *tso_hdrs;
478 	dma_addr_t tso_hdrs_dma;
479 };
480 
481 struct fec_enet_priv_rx_q {
482 	struct bufdesc_prop bd;
483 	struct  sk_buff *rx_skbuff[RX_RING_SIZE];
484 };
485 
486 /* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
487  * tx_bd_base always point to the base of the buffer descriptors.  The
488  * cur_rx and cur_tx point to the currently available buffer.
489  * The dirty_tx tracks the current buffer that is being sent by the
490  * controller.  The cur_tx and dirty_tx are equal under both completely
491  * empty and completely full conditions.  The empty/ready indicator in
492  * the buffer descriptor determines the actual condition.
493  */
494 struct fec_enet_private {
495 	/* Hardware registers of the FEC device */
496 	void __iomem *hwp;
497 
498 	struct net_device *netdev;
499 
500 	struct clk *clk_ipg;
501 	struct clk *clk_ahb;
502 	struct clk *clk_ref;
503 	struct clk *clk_enet_out;
504 	struct clk *clk_ptp;
505 
506 	bool ptp_clk_on;
507 	struct mutex ptp_clk_mutex;
508 	unsigned int num_tx_queues;
509 	unsigned int num_rx_queues;
510 
511 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
512 	struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
513 	struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
514 
515 	unsigned int total_tx_ring_size;
516 	unsigned int total_rx_ring_size;
517 
518 	unsigned long work_tx;
519 	unsigned long work_rx;
520 	unsigned long work_ts;
521 	unsigned long work_mdio;
522 
523 	struct	platform_device *pdev;
524 
525 	int	dev_id;
526 
527 	/* Phylib and MDIO interface */
528 	struct	mii_bus *mii_bus;
529 	int	mii_timeout;
530 	uint	phy_speed;
531 	phy_interface_t	phy_interface;
532 	struct device_node *phy_node;
533 	int	link;
534 	int	full_duplex;
535 	int	speed;
536 	struct	completion mdio_done;
537 	int	irq[FEC_IRQ_NUM];
538 	bool	bufdesc_ex;
539 	int	pause_flag;
540 	int	wol_flag;
541 	u32	quirks;
542 
543 	struct	napi_struct napi;
544 	int	csum_flags;
545 
546 	struct work_struct tx_timeout_work;
547 
548 	struct ptp_clock *ptp_clock;
549 	struct ptp_clock_info ptp_caps;
550 	unsigned long last_overflow_check;
551 	spinlock_t tmreg_lock;
552 	struct cyclecounter cc;
553 	struct timecounter tc;
554 	int rx_hwtstamp_filter;
555 	u32 base_incval;
556 	u32 cycle_speed;
557 	int hwts_rx_en;
558 	int hwts_tx_en;
559 	struct delayed_work time_keep;
560 	struct regulator *reg_phy;
561 
562 	unsigned int tx_align;
563 	unsigned int rx_align;
564 
565 	/* hw interrupt coalesce */
566 	unsigned int rx_pkts_itr;
567 	unsigned int rx_time_itr;
568 	unsigned int tx_pkts_itr;
569 	unsigned int tx_time_itr;
570 	unsigned int itr_clk_rate;
571 
572 	u32 rx_copybreak;
573 
574 	/* ptp clock period in ns*/
575 	unsigned int ptp_inc;
576 
577 	/* pps  */
578 	int pps_channel;
579 	unsigned int reload_period;
580 	int pps_enable;
581 	unsigned int next_counter;
582 
583 	u64 ethtool_stats[0];
584 };
585 
586 void fec_ptp_init(struct platform_device *pdev, int irq_idx);
587 void fec_ptp_stop(struct platform_device *pdev);
588 void fec_ptp_start_cyclecounter(struct net_device *ndev);
589 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
590 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
591 
592 /****************************************************************************/
593 #endif /* FEC_H */
594