1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Faraday FTGMAC100 Gigabit Ethernet
4  *
5  * (C) Copyright 2009-2011 Faraday Technology
6  * Po-Yu Chuang <ratbert@faraday-tech.com>
7  */
8 
9 #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
10 
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
19 #include <linux/of.h>
20 #include <linux/of_mdio.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/crc32.h>
25 #include <linux/if_vlan.h>
26 #include <linux/of_net.h>
27 #include <net/ip.h>
28 #include <net/ncsi.h>
29 
30 #include "ftgmac100.h"
31 
32 #define DRV_NAME	"ftgmac100"
33 
34 /* Arbitrary values, I am not sure the HW has limits */
35 #define MAX_RX_QUEUE_ENTRIES	1024
36 #define MAX_TX_QUEUE_ENTRIES	1024
37 #define MIN_RX_QUEUE_ENTRIES	32
38 #define MIN_TX_QUEUE_ENTRIES	32
39 
40 /* Defaults */
41 #define DEF_RX_QUEUE_ENTRIES	128
42 #define DEF_TX_QUEUE_ENTRIES	128
43 
44 #define MAX_PKT_SIZE		1536
45 #define RX_BUF_SIZE		MAX_PKT_SIZE	/* must be smaller than 0x3fff */
46 
47 /* Min number of tx ring entries before stopping queue */
48 #define TX_THRESHOLD		(MAX_SKB_FRAGS + 1)
49 
50 #define FTGMAC_100MHZ		100000000
51 #define FTGMAC_25MHZ		25000000
52 
53 struct ftgmac100 {
54 	/* Registers */
55 	struct resource *res;
56 	void __iomem *base;
57 
58 	/* Rx ring */
59 	unsigned int rx_q_entries;
60 	struct ftgmac100_rxdes *rxdes;
61 	dma_addr_t rxdes_dma;
62 	struct sk_buff **rx_skbs;
63 	unsigned int rx_pointer;
64 	u32 rxdes0_edorr_mask;
65 
66 	/* Tx ring */
67 	unsigned int tx_q_entries;
68 	struct ftgmac100_txdes *txdes;
69 	dma_addr_t txdes_dma;
70 	struct sk_buff **tx_skbs;
71 	unsigned int tx_clean_pointer;
72 	unsigned int tx_pointer;
73 	u32 txdes0_edotr_mask;
74 
75 	/* Used to signal the reset task of ring change request */
76 	unsigned int new_rx_q_entries;
77 	unsigned int new_tx_q_entries;
78 
79 	/* Scratch page to use when rx skb alloc fails */
80 	void *rx_scratch;
81 	dma_addr_t rx_scratch_dma;
82 
83 	/* Component structures */
84 	struct net_device *netdev;
85 	struct device *dev;
86 	struct ncsi_dev *ndev;
87 	struct napi_struct napi;
88 	struct work_struct reset_task;
89 	struct mii_bus *mii_bus;
90 	struct clk *clk;
91 
92 	/* AST2500/AST2600 RMII ref clock gate */
93 	struct clk *rclk;
94 
95 	/* Link management */
96 	int cur_speed;
97 	int cur_duplex;
98 	bool use_ncsi;
99 
100 	/* Multicast filter settings */
101 	u32 maht0;
102 	u32 maht1;
103 
104 	/* Flow control settings */
105 	bool tx_pause;
106 	bool rx_pause;
107 	bool aneg_pause;
108 
109 	/* Misc */
110 	bool need_mac_restart;
111 	bool is_aspeed;
112 };
113 
114 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
115 {
116 	struct net_device *netdev = priv->netdev;
117 	int i;
118 
119 	/* NOTE: reset clears all registers */
120 	iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
121 	iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
122 		  priv->base + FTGMAC100_OFFSET_MACCR);
123 	for (i = 0; i < 200; i++) {
124 		unsigned int maccr;
125 
126 		maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
127 		if (!(maccr & FTGMAC100_MACCR_SW_RST))
128 			return 0;
129 
130 		udelay(1);
131 	}
132 
133 	netdev_err(netdev, "Hardware reset failed\n");
134 	return -EIO;
135 }
136 
137 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
138 {
139 	u32 maccr = 0;
140 
141 	switch (priv->cur_speed) {
142 	case SPEED_10:
143 	case 0: /* no link */
144 		break;
145 
146 	case SPEED_100:
147 		maccr |= FTGMAC100_MACCR_FAST_MODE;
148 		break;
149 
150 	case SPEED_1000:
151 		maccr |= FTGMAC100_MACCR_GIGA_MODE;
152 		break;
153 	default:
154 		netdev_err(priv->netdev, "Unknown speed %d !\n",
155 			   priv->cur_speed);
156 		break;
157 	}
158 
159 	/* (Re)initialize the queue pointers */
160 	priv->rx_pointer = 0;
161 	priv->tx_clean_pointer = 0;
162 	priv->tx_pointer = 0;
163 
164 	/* The doc says reset twice with 10us interval */
165 	if (ftgmac100_reset_mac(priv, maccr))
166 		return -EIO;
167 	usleep_range(10, 1000);
168 	return ftgmac100_reset_mac(priv, maccr);
169 }
170 
171 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
172 {
173 	unsigned int maddr = mac[0] << 8 | mac[1];
174 	unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
175 
176 	iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
177 	iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
178 }
179 
180 static void ftgmac100_initial_mac(struct ftgmac100 *priv)
181 {
182 	u8 mac[ETH_ALEN];
183 	unsigned int m;
184 	unsigned int l;
185 
186 	if (!device_get_ethdev_address(priv->dev, priv->netdev)) {
187 		dev_info(priv->dev, "Read MAC address %pM from device tree\n",
188 			 priv->netdev->dev_addr);
189 		return;
190 	}
191 
192 	m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
193 	l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
194 
195 	mac[0] = (m >> 8) & 0xff;
196 	mac[1] = m & 0xff;
197 	mac[2] = (l >> 24) & 0xff;
198 	mac[3] = (l >> 16) & 0xff;
199 	mac[4] = (l >> 8) & 0xff;
200 	mac[5] = l & 0xff;
201 
202 	if (is_valid_ether_addr(mac)) {
203 		eth_hw_addr_set(priv->netdev, mac);
204 		dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
205 	} else {
206 		eth_hw_addr_random(priv->netdev);
207 		dev_info(priv->dev, "Generated random MAC address %pM\n",
208 			 priv->netdev->dev_addr);
209 	}
210 }
211 
212 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
213 {
214 	int ret;
215 
216 	ret = eth_prepare_mac_addr_change(dev, p);
217 	if (ret < 0)
218 		return ret;
219 
220 	eth_commit_mac_addr_change(dev, p);
221 	ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
222 
223 	return 0;
224 }
225 
226 static void ftgmac100_config_pause(struct ftgmac100 *priv)
227 {
228 	u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
229 
230 	/* Throttle tx queue when receiving pause frames */
231 	if (priv->rx_pause)
232 		fcr |= FTGMAC100_FCR_FC_EN;
233 
234 	/* Enables sending pause frames when the RX queue is past a
235 	 * certain threshold.
236 	 */
237 	if (priv->tx_pause)
238 		fcr |= FTGMAC100_FCR_FCTHR_EN;
239 
240 	iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
241 }
242 
243 static void ftgmac100_init_hw(struct ftgmac100 *priv)
244 {
245 	u32 reg, rfifo_sz, tfifo_sz;
246 
247 	/* Clear stale interrupts */
248 	reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
249 	iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
250 
251 	/* Setup RX ring buffer base */
252 	iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
253 
254 	/* Setup TX ring buffer base */
255 	iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
256 
257 	/* Configure RX buffer size */
258 	iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
259 		  priv->base + FTGMAC100_OFFSET_RBSR);
260 
261 	/* Set RX descriptor autopoll */
262 	iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
263 		  priv->base + FTGMAC100_OFFSET_APTC);
264 
265 	/* Write MAC address */
266 	ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
267 
268 	/* Write multicast filter */
269 	iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
270 	iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
271 
272 	/* Configure descriptor sizes and increase burst sizes according
273 	 * to values in Aspeed SDK. The FIFO arbitration is enabled and
274 	 * the thresholds set based on the recommended values in the
275 	 * AST2400 specification.
276 	 */
277 	iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) |   /* 2*8 bytes RX descs */
278 		  FTGMAC100_DBLAC_TXDES_SIZE(2) |   /* 2*8 bytes TX descs */
279 		  FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
280 		  FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
281 		  FTGMAC100_DBLAC_RX_THR_EN |       /* Enable fifo threshold arb */
282 		  FTGMAC100_DBLAC_RXFIFO_HTHR(6) |  /* 6/8 of FIFO high threshold */
283 		  FTGMAC100_DBLAC_RXFIFO_LTHR(2),   /* 2/8 of FIFO low threshold */
284 		  priv->base + FTGMAC100_OFFSET_DBLAC);
285 
286 	/* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
287 	 * mitigation doesn't seem to provide any benefit with NAPI so leave
288 	 * it at that.
289 	 */
290 	iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
291 		  FTGMAC100_ITC_TXINT_THR(1),
292 		  priv->base + FTGMAC100_OFFSET_ITC);
293 
294 	/* Configure FIFO sizes in the TPAFCR register */
295 	reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
296 	rfifo_sz = reg & 0x00000007;
297 	tfifo_sz = (reg >> 3) & 0x00000007;
298 	reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
299 	reg &= ~0x3f000000;
300 	reg |= (tfifo_sz << 27);
301 	reg |= (rfifo_sz << 24);
302 	iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
303 }
304 
305 static void ftgmac100_start_hw(struct ftgmac100 *priv)
306 {
307 	u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
308 
309 	/* Keep the original GMAC and FAST bits */
310 	maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
311 
312 	/* Add all the main enable bits */
313 	maccr |= FTGMAC100_MACCR_TXDMA_EN	|
314 		 FTGMAC100_MACCR_RXDMA_EN	|
315 		 FTGMAC100_MACCR_TXMAC_EN	|
316 		 FTGMAC100_MACCR_RXMAC_EN	|
317 		 FTGMAC100_MACCR_CRC_APD	|
318 		 FTGMAC100_MACCR_PHY_LINK_LEVEL	|
319 		 FTGMAC100_MACCR_RX_RUNT	|
320 		 FTGMAC100_MACCR_RX_BROADPKT;
321 
322 	/* Add other bits as needed */
323 	if (priv->cur_duplex == DUPLEX_FULL)
324 		maccr |= FTGMAC100_MACCR_FULLDUP;
325 	if (priv->netdev->flags & IFF_PROMISC)
326 		maccr |= FTGMAC100_MACCR_RX_ALL;
327 	if (priv->netdev->flags & IFF_ALLMULTI)
328 		maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
329 	else if (netdev_mc_count(priv->netdev))
330 		maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
331 
332 	/* Vlan filtering enabled */
333 	if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
334 		maccr |= FTGMAC100_MACCR_RM_VLAN;
335 
336 	/* Hit the HW */
337 	iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
338 }
339 
340 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
341 {
342 	iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
343 }
344 
345 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
346 {
347 	struct netdev_hw_addr *ha;
348 
349 	priv->maht1 = 0;
350 	priv->maht0 = 0;
351 	netdev_for_each_mc_addr(ha, priv->netdev) {
352 		u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
353 
354 		crc_val = (~(crc_val >> 2)) & 0x3f;
355 		if (crc_val >= 32)
356 			priv->maht1 |= 1ul << (crc_val - 32);
357 		else
358 			priv->maht0 |= 1ul << (crc_val);
359 	}
360 }
361 
362 static void ftgmac100_set_rx_mode(struct net_device *netdev)
363 {
364 	struct ftgmac100 *priv = netdev_priv(netdev);
365 
366 	/* Setup the hash filter */
367 	ftgmac100_calc_mc_hash(priv);
368 
369 	/* Interface down ? that's all there is to do */
370 	if (!netif_running(netdev))
371 		return;
372 
373 	/* Update the HW */
374 	iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
375 	iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
376 
377 	/* Reconfigure MACCR */
378 	ftgmac100_start_hw(priv);
379 }
380 
381 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
382 				  struct ftgmac100_rxdes *rxdes, gfp_t gfp)
383 {
384 	struct net_device *netdev = priv->netdev;
385 	struct sk_buff *skb;
386 	dma_addr_t map;
387 	int err = 0;
388 
389 	skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
390 	if (unlikely(!skb)) {
391 		if (net_ratelimit())
392 			netdev_warn(netdev, "failed to allocate rx skb\n");
393 		err = -ENOMEM;
394 		map = priv->rx_scratch_dma;
395 	} else {
396 		map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
397 				     DMA_FROM_DEVICE);
398 		if (unlikely(dma_mapping_error(priv->dev, map))) {
399 			if (net_ratelimit())
400 				netdev_err(netdev, "failed to map rx page\n");
401 			dev_kfree_skb_any(skb);
402 			map = priv->rx_scratch_dma;
403 			skb = NULL;
404 			err = -ENOMEM;
405 		}
406 	}
407 
408 	/* Store skb */
409 	priv->rx_skbs[entry] = skb;
410 
411 	/* Store DMA address into RX desc */
412 	rxdes->rxdes3 = cpu_to_le32(map);
413 
414 	/* Ensure the above is ordered vs clearing the OWN bit */
415 	dma_wmb();
416 
417 	/* Clean status (which resets own bit) */
418 	if (entry == (priv->rx_q_entries - 1))
419 		rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
420 	else
421 		rxdes->rxdes0 = 0;
422 
423 	return err;
424 }
425 
426 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
427 					      unsigned int pointer)
428 {
429 	return (pointer + 1) & (priv->rx_q_entries - 1);
430 }
431 
432 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
433 {
434 	struct net_device *netdev = priv->netdev;
435 
436 	if (status & FTGMAC100_RXDES0_RX_ERR)
437 		netdev->stats.rx_errors++;
438 
439 	if (status & FTGMAC100_RXDES0_CRC_ERR)
440 		netdev->stats.rx_crc_errors++;
441 
442 	if (status & (FTGMAC100_RXDES0_FTL |
443 		      FTGMAC100_RXDES0_RUNT |
444 		      FTGMAC100_RXDES0_RX_ODD_NB))
445 		netdev->stats.rx_length_errors++;
446 }
447 
448 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
449 {
450 	struct net_device *netdev = priv->netdev;
451 	struct ftgmac100_rxdes *rxdes;
452 	struct sk_buff *skb;
453 	unsigned int pointer, size;
454 	u32 status, csum_vlan;
455 	dma_addr_t map;
456 
457 	/* Grab next RX descriptor */
458 	pointer = priv->rx_pointer;
459 	rxdes = &priv->rxdes[pointer];
460 
461 	/* Grab descriptor status */
462 	status = le32_to_cpu(rxdes->rxdes0);
463 
464 	/* Do we have a packet ? */
465 	if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
466 		return false;
467 
468 	/* Order subsequent reads with the test for the ready bit */
469 	dma_rmb();
470 
471 	/* We don't cope with fragmented RX packets */
472 	if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
473 		     !(status & FTGMAC100_RXDES0_LRS)))
474 		goto drop;
475 
476 	/* Grab received size and csum vlan field in the descriptor */
477 	size = status & FTGMAC100_RXDES0_VDBC;
478 	csum_vlan = le32_to_cpu(rxdes->rxdes1);
479 
480 	/* Any error (other than csum offload) flagged ? */
481 	if (unlikely(status & RXDES0_ANY_ERROR)) {
482 		/* Correct for incorrect flagging of runt packets
483 		 * with vlan tags... Just accept a runt packet that
484 		 * has been flagged as vlan and whose size is at
485 		 * least 60 bytes.
486 		 */
487 		if ((status & FTGMAC100_RXDES0_RUNT) &&
488 		    (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
489 		    (size >= 60))
490 			status &= ~FTGMAC100_RXDES0_RUNT;
491 
492 		/* Any error still in there ? */
493 		if (status & RXDES0_ANY_ERROR) {
494 			ftgmac100_rx_packet_error(priv, status);
495 			goto drop;
496 		}
497 	}
498 
499 	/* If the packet had no skb (failed to allocate earlier)
500 	 * then try to allocate one and skip
501 	 */
502 	skb = priv->rx_skbs[pointer];
503 	if (!unlikely(skb)) {
504 		ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
505 		goto drop;
506 	}
507 
508 	if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
509 		netdev->stats.multicast++;
510 
511 	/* If the HW found checksum errors, bounce it to software.
512 	 *
513 	 * If we didn't, we need to see if the packet was recognized
514 	 * by HW as one of the supported checksummed protocols before
515 	 * we accept the HW test results.
516 	 */
517 	if (netdev->features & NETIF_F_RXCSUM) {
518 		u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
519 			FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
520 			FTGMAC100_RXDES1_IP_CHKSUM_ERR;
521 		if ((csum_vlan & err_bits) ||
522 		    !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
523 			skb->ip_summed = CHECKSUM_NONE;
524 		else
525 			skb->ip_summed = CHECKSUM_UNNECESSARY;
526 	}
527 
528 	/* Transfer received size to skb */
529 	skb_put(skb, size);
530 
531 	/* Extract vlan tag */
532 	if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
533 	    (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
534 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
535 				       csum_vlan & 0xffff);
536 
537 	/* Tear down DMA mapping, do necessary cache management */
538 	map = le32_to_cpu(rxdes->rxdes3);
539 
540 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
541 	/* When we don't have an iommu, we can save cycles by not
542 	 * invalidating the cache for the part of the packet that
543 	 * wasn't received.
544 	 */
545 	dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
546 #else
547 	dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
548 #endif
549 
550 
551 	/* Resplenish rx ring */
552 	ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
553 	priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
554 
555 	skb->protocol = eth_type_trans(skb, netdev);
556 
557 	netdev->stats.rx_packets++;
558 	netdev->stats.rx_bytes += size;
559 
560 	/* push packet to protocol stack */
561 	if (skb->ip_summed == CHECKSUM_NONE)
562 		netif_receive_skb(skb);
563 	else
564 		napi_gro_receive(&priv->napi, skb);
565 
566 	(*processed)++;
567 	return true;
568 
569  drop:
570 	/* Clean rxdes0 (which resets own bit) */
571 	rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
572 	priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
573 	netdev->stats.rx_dropped++;
574 	return true;
575 }
576 
577 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
578 				     unsigned int index)
579 {
580 	if (index == (priv->tx_q_entries - 1))
581 		return priv->txdes0_edotr_mask;
582 	else
583 		return 0;
584 }
585 
586 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
587 					      unsigned int pointer)
588 {
589 	return (pointer + 1) & (priv->tx_q_entries - 1);
590 }
591 
592 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
593 {
594 	/* Returns the number of available slots in the TX queue
595 	 *
596 	 * This always leaves one free slot so we don't have to
597 	 * worry about empty vs. full, and this simplifies the
598 	 * test for ftgmac100_tx_buf_cleanable() below
599 	 */
600 	return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
601 		(priv->tx_q_entries - 1);
602 }
603 
604 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
605 {
606 	return priv->tx_pointer != priv->tx_clean_pointer;
607 }
608 
609 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
610 				     unsigned int pointer,
611 				     struct sk_buff *skb,
612 				     struct ftgmac100_txdes *txdes,
613 				     u32 ctl_stat)
614 {
615 	dma_addr_t map = le32_to_cpu(txdes->txdes3);
616 	size_t len;
617 
618 	if (ctl_stat & FTGMAC100_TXDES0_FTS) {
619 		len = skb_headlen(skb);
620 		dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
621 	} else {
622 		len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
623 		dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
624 	}
625 
626 	/* Free SKB on last segment */
627 	if (ctl_stat & FTGMAC100_TXDES0_LTS)
628 		dev_kfree_skb(skb);
629 	priv->tx_skbs[pointer] = NULL;
630 }
631 
632 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
633 {
634 	struct net_device *netdev = priv->netdev;
635 	struct ftgmac100_txdes *txdes;
636 	struct sk_buff *skb;
637 	unsigned int pointer;
638 	u32 ctl_stat;
639 
640 	pointer = priv->tx_clean_pointer;
641 	txdes = &priv->txdes[pointer];
642 
643 	ctl_stat = le32_to_cpu(txdes->txdes0);
644 	if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
645 		return false;
646 
647 	skb = priv->tx_skbs[pointer];
648 	netdev->stats.tx_packets++;
649 	netdev->stats.tx_bytes += skb->len;
650 	ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
651 	txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
652 
653 	priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
654 
655 	return true;
656 }
657 
658 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
659 {
660 	struct net_device *netdev = priv->netdev;
661 
662 	/* Process all completed packets */
663 	while (ftgmac100_tx_buf_cleanable(priv) &&
664 	       ftgmac100_tx_complete_packet(priv))
665 		;
666 
667 	/* Restart queue if needed */
668 	smp_mb();
669 	if (unlikely(netif_queue_stopped(netdev) &&
670 		     ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
671 		struct netdev_queue *txq;
672 
673 		txq = netdev_get_tx_queue(netdev, 0);
674 		__netif_tx_lock(txq, smp_processor_id());
675 		if (netif_queue_stopped(netdev) &&
676 		    ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
677 			netif_wake_queue(netdev);
678 		__netif_tx_unlock(txq);
679 	}
680 }
681 
682 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
683 {
684 	if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
685 		u8 ip_proto = ip_hdr(skb)->protocol;
686 
687 		*csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
688 		switch(ip_proto) {
689 		case IPPROTO_TCP:
690 			*csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
691 			return true;
692 		case IPPROTO_UDP:
693 			*csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
694 			return true;
695 		case IPPROTO_IP:
696 			return true;
697 		}
698 	}
699 	return skb_checksum_help(skb) == 0;
700 }
701 
702 static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb,
703 					     struct net_device *netdev)
704 {
705 	struct ftgmac100 *priv = netdev_priv(netdev);
706 	struct ftgmac100_txdes *txdes, *first;
707 	unsigned int pointer, nfrags, len, i, j;
708 	u32 f_ctl_stat, ctl_stat, csum_vlan;
709 	dma_addr_t map;
710 
711 	/* The HW doesn't pad small frames */
712 	if (eth_skb_pad(skb)) {
713 		netdev->stats.tx_dropped++;
714 		return NETDEV_TX_OK;
715 	}
716 
717 	/* Reject oversize packets */
718 	if (unlikely(skb->len > MAX_PKT_SIZE)) {
719 		if (net_ratelimit())
720 			netdev_dbg(netdev, "tx packet too big\n");
721 		goto drop;
722 	}
723 
724 	/* Do we have a limit on #fragments ? I yet have to get a reply
725 	 * from Aspeed. If there's one I haven't hit it.
726 	 */
727 	nfrags = skb_shinfo(skb)->nr_frags;
728 
729 	/* Setup HW checksumming */
730 	csum_vlan = 0;
731 	if (skb->ip_summed == CHECKSUM_PARTIAL &&
732 	    !ftgmac100_prep_tx_csum(skb, &csum_vlan))
733 		goto drop;
734 
735 	/* Add VLAN tag */
736 	if (skb_vlan_tag_present(skb)) {
737 		csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
738 		csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
739 	}
740 
741 	/* Get header len */
742 	len = skb_headlen(skb);
743 
744 	/* Map the packet head */
745 	map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
746 	if (dma_mapping_error(priv->dev, map)) {
747 		if (net_ratelimit())
748 			netdev_err(netdev, "map tx packet head failed\n");
749 		goto drop;
750 	}
751 
752 	/* Grab the next free tx descriptor */
753 	pointer = priv->tx_pointer;
754 	txdes = first = &priv->txdes[pointer];
755 
756 	/* Setup it up with the packet head. Don't write the head to the
757 	 * ring just yet
758 	 */
759 	priv->tx_skbs[pointer] = skb;
760 	f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
761 	f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
762 	f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
763 	f_ctl_stat |= FTGMAC100_TXDES0_FTS;
764 	if (nfrags == 0)
765 		f_ctl_stat |= FTGMAC100_TXDES0_LTS;
766 	txdes->txdes3 = cpu_to_le32(map);
767 	txdes->txdes1 = cpu_to_le32(csum_vlan);
768 
769 	/* Next descriptor */
770 	pointer = ftgmac100_next_tx_pointer(priv, pointer);
771 
772 	/* Add the fragments */
773 	for (i = 0; i < nfrags; i++) {
774 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
775 
776 		len = skb_frag_size(frag);
777 
778 		/* Map it */
779 		map = skb_frag_dma_map(priv->dev, frag, 0, len,
780 				       DMA_TO_DEVICE);
781 		if (dma_mapping_error(priv->dev, map))
782 			goto dma_err;
783 
784 		/* Setup descriptor */
785 		priv->tx_skbs[pointer] = skb;
786 		txdes = &priv->txdes[pointer];
787 		ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
788 		ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
789 		ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
790 		if (i == (nfrags - 1))
791 			ctl_stat |= FTGMAC100_TXDES0_LTS;
792 		txdes->txdes0 = cpu_to_le32(ctl_stat);
793 		txdes->txdes1 = 0;
794 		txdes->txdes3 = cpu_to_le32(map);
795 
796 		/* Next one */
797 		pointer = ftgmac100_next_tx_pointer(priv, pointer);
798 	}
799 
800 	/* Order the previous packet and descriptor udpates
801 	 * before setting the OWN bit on the first descriptor.
802 	 */
803 	dma_wmb();
804 	first->txdes0 = cpu_to_le32(f_ctl_stat);
805 
806 	/* Update next TX pointer */
807 	priv->tx_pointer = pointer;
808 
809 	/* If there isn't enough room for all the fragments of a new packet
810 	 * in the TX ring, stop the queue. The sequence below is race free
811 	 * vs. a concurrent restart in ftgmac100_poll()
812 	 */
813 	if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
814 		netif_stop_queue(netdev);
815 		/* Order the queue stop with the test below */
816 		smp_mb();
817 		if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
818 			netif_wake_queue(netdev);
819 	}
820 
821 	/* Poke transmitter to read the updated TX descriptors */
822 	iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
823 
824 	return NETDEV_TX_OK;
825 
826  dma_err:
827 	if (net_ratelimit())
828 		netdev_err(netdev, "map tx fragment failed\n");
829 
830 	/* Free head */
831 	pointer = priv->tx_pointer;
832 	ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
833 	first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
834 
835 	/* Then all fragments */
836 	for (j = 0; j < i; j++) {
837 		pointer = ftgmac100_next_tx_pointer(priv, pointer);
838 		txdes = &priv->txdes[pointer];
839 		ctl_stat = le32_to_cpu(txdes->txdes0);
840 		ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
841 		txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
842 	}
843 
844 	/* This cannot be reached if we successfully mapped the
845 	 * last fragment, so we know ftgmac100_free_tx_packet()
846 	 * hasn't freed the skb yet.
847 	 */
848  drop:
849 	/* Drop the packet */
850 	dev_kfree_skb_any(skb);
851 	netdev->stats.tx_dropped++;
852 
853 	return NETDEV_TX_OK;
854 }
855 
856 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
857 {
858 	int i;
859 
860 	/* Free all RX buffers */
861 	for (i = 0; i < priv->rx_q_entries; i++) {
862 		struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
863 		struct sk_buff *skb = priv->rx_skbs[i];
864 		dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
865 
866 		if (!skb)
867 			continue;
868 
869 		priv->rx_skbs[i] = NULL;
870 		dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
871 		dev_kfree_skb_any(skb);
872 	}
873 
874 	/* Free all TX buffers */
875 	for (i = 0; i < priv->tx_q_entries; i++) {
876 		struct ftgmac100_txdes *txdes = &priv->txdes[i];
877 		struct sk_buff *skb = priv->tx_skbs[i];
878 
879 		if (!skb)
880 			continue;
881 		ftgmac100_free_tx_packet(priv, i, skb, txdes,
882 					 le32_to_cpu(txdes->txdes0));
883 	}
884 }
885 
886 static void ftgmac100_free_rings(struct ftgmac100 *priv)
887 {
888 	/* Free skb arrays */
889 	kfree(priv->rx_skbs);
890 	kfree(priv->tx_skbs);
891 
892 	/* Free descriptors */
893 	if (priv->rxdes)
894 		dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
895 				  sizeof(struct ftgmac100_rxdes),
896 				  priv->rxdes, priv->rxdes_dma);
897 	priv->rxdes = NULL;
898 
899 	if (priv->txdes)
900 		dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
901 				  sizeof(struct ftgmac100_txdes),
902 				  priv->txdes, priv->txdes_dma);
903 	priv->txdes = NULL;
904 
905 	/* Free scratch packet buffer */
906 	if (priv->rx_scratch)
907 		dma_free_coherent(priv->dev, RX_BUF_SIZE,
908 				  priv->rx_scratch, priv->rx_scratch_dma);
909 }
910 
911 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
912 {
913 	/* Allocate skb arrays */
914 	priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
915 				GFP_KERNEL);
916 	if (!priv->rx_skbs)
917 		return -ENOMEM;
918 	priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
919 				GFP_KERNEL);
920 	if (!priv->tx_skbs)
921 		return -ENOMEM;
922 
923 	/* Allocate descriptors */
924 	priv->rxdes = dma_alloc_coherent(priv->dev,
925 					 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes),
926 					 &priv->rxdes_dma, GFP_KERNEL);
927 	if (!priv->rxdes)
928 		return -ENOMEM;
929 	priv->txdes = dma_alloc_coherent(priv->dev,
930 					 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes),
931 					 &priv->txdes_dma, GFP_KERNEL);
932 	if (!priv->txdes)
933 		return -ENOMEM;
934 
935 	/* Allocate scratch packet buffer */
936 	priv->rx_scratch = dma_alloc_coherent(priv->dev,
937 					      RX_BUF_SIZE,
938 					      &priv->rx_scratch_dma,
939 					      GFP_KERNEL);
940 	if (!priv->rx_scratch)
941 		return -ENOMEM;
942 
943 	return 0;
944 }
945 
946 static void ftgmac100_init_rings(struct ftgmac100 *priv)
947 {
948 	struct ftgmac100_rxdes *rxdes = NULL;
949 	struct ftgmac100_txdes *txdes = NULL;
950 	int i;
951 
952 	/* Update entries counts */
953 	priv->rx_q_entries = priv->new_rx_q_entries;
954 	priv->tx_q_entries = priv->new_tx_q_entries;
955 
956 	if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
957 		return;
958 
959 	/* Initialize RX ring */
960 	for (i = 0; i < priv->rx_q_entries; i++) {
961 		rxdes = &priv->rxdes[i];
962 		rxdes->rxdes0 = 0;
963 		rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
964 	}
965 	/* Mark the end of the ring */
966 	rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
967 
968 	if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
969 		return;
970 
971 	/* Initialize TX ring */
972 	for (i = 0; i < priv->tx_q_entries; i++) {
973 		txdes = &priv->txdes[i];
974 		txdes->txdes0 = 0;
975 	}
976 	txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
977 }
978 
979 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
980 {
981 	int i;
982 
983 	for (i = 0; i < priv->rx_q_entries; i++) {
984 		struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
985 
986 		if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
987 			return -ENOMEM;
988 	}
989 	return 0;
990 }
991 
992 static void ftgmac100_adjust_link(struct net_device *netdev)
993 {
994 	struct ftgmac100 *priv = netdev_priv(netdev);
995 	struct phy_device *phydev = netdev->phydev;
996 	bool tx_pause, rx_pause;
997 	int new_speed;
998 
999 	/* We store "no link" as speed 0 */
1000 	if (!phydev->link)
1001 		new_speed = 0;
1002 	else
1003 		new_speed = phydev->speed;
1004 
1005 	/* Grab pause settings from PHY if configured to do so */
1006 	if (priv->aneg_pause) {
1007 		rx_pause = tx_pause = phydev->pause;
1008 		if (phydev->asym_pause)
1009 			tx_pause = !rx_pause;
1010 	} else {
1011 		rx_pause = priv->rx_pause;
1012 		tx_pause = priv->tx_pause;
1013 	}
1014 
1015 	/* Link hasn't changed, do nothing */
1016 	if (phydev->speed == priv->cur_speed &&
1017 	    phydev->duplex == priv->cur_duplex &&
1018 	    rx_pause == priv->rx_pause &&
1019 	    tx_pause == priv->tx_pause)
1020 		return;
1021 
1022 	/* Print status if we have a link or we had one and just lost it,
1023 	 * don't print otherwise.
1024 	 */
1025 	if (new_speed || priv->cur_speed)
1026 		phy_print_status(phydev);
1027 
1028 	priv->cur_speed = new_speed;
1029 	priv->cur_duplex = phydev->duplex;
1030 	priv->rx_pause = rx_pause;
1031 	priv->tx_pause = tx_pause;
1032 
1033 	/* Link is down, do nothing else */
1034 	if (!new_speed)
1035 		return;
1036 
1037 	/* Disable all interrupts */
1038 	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1039 
1040 	/* Reset the adapter asynchronously */
1041 	schedule_work(&priv->reset_task);
1042 }
1043 
1044 static int ftgmac100_mii_probe(struct net_device *netdev)
1045 {
1046 	struct ftgmac100 *priv = netdev_priv(netdev);
1047 	struct platform_device *pdev = to_platform_device(priv->dev);
1048 	struct device_node *np = pdev->dev.of_node;
1049 	struct phy_device *phydev;
1050 	phy_interface_t phy_intf;
1051 	int err;
1052 
1053 	/* Default to RGMII. It's a gigabit part after all */
1054 	err = of_get_phy_mode(np, &phy_intf);
1055 	if (err)
1056 		phy_intf = PHY_INTERFACE_MODE_RGMII;
1057 
1058 	/* Aspeed only supports these. I don't know about other IP
1059 	 * block vendors so I'm going to just let them through for
1060 	 * now. Note that this is only a warning if for some obscure
1061 	 * reason the DT really means to lie about it or it's a newer
1062 	 * part we don't know about.
1063 	 *
1064 	 * On the Aspeed SoC there are additionally straps and SCU
1065 	 * control bits that could tell us what the interface is
1066 	 * (or allow us to configure it while the IP block is held
1067 	 * in reset). For now I chose to keep this driver away from
1068 	 * those SoC specific bits and assume the device-tree is
1069 	 * right and the SCU has been configured properly by pinmux
1070 	 * or the firmware.
1071 	 */
1072 	if (priv->is_aspeed && !(phy_interface_mode_is_rgmii(phy_intf))) {
1073 		netdev_warn(netdev,
1074 			    "Unsupported PHY mode %s !\n",
1075 			    phy_modes(phy_intf));
1076 	}
1077 
1078 	phydev = phy_find_first(priv->mii_bus);
1079 	if (!phydev) {
1080 		netdev_info(netdev, "%s: no PHY found\n", netdev->name);
1081 		return -ENODEV;
1082 	}
1083 
1084 	phydev = phy_connect(netdev, phydev_name(phydev),
1085 			     &ftgmac100_adjust_link, phy_intf);
1086 
1087 	if (IS_ERR(phydev)) {
1088 		netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1089 		return PTR_ERR(phydev);
1090 	}
1091 
1092 	/* Indicate that we support PAUSE frames (see comment in
1093 	 * Documentation/networking/phy.rst)
1094 	 */
1095 	phy_support_asym_pause(phydev);
1096 
1097 	/* Display what we found */
1098 	phy_attached_info(phydev);
1099 
1100 	return 0;
1101 }
1102 
1103 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1104 {
1105 	struct net_device *netdev = bus->priv;
1106 	struct ftgmac100 *priv = netdev_priv(netdev);
1107 	unsigned int phycr;
1108 	int i;
1109 
1110 	phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1111 
1112 	/* preserve MDC cycle threshold */
1113 	phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1114 
1115 	phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1116 		 FTGMAC100_PHYCR_REGAD(regnum) |
1117 		 FTGMAC100_PHYCR_MIIRD;
1118 
1119 	iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1120 
1121 	for (i = 0; i < 10; i++) {
1122 		phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1123 
1124 		if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1125 			int data;
1126 
1127 			data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1128 			return FTGMAC100_PHYDATA_MIIRDATA(data);
1129 		}
1130 
1131 		udelay(100);
1132 	}
1133 
1134 	netdev_err(netdev, "mdio read timed out\n");
1135 	return -EIO;
1136 }
1137 
1138 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1139 				   int regnum, u16 value)
1140 {
1141 	struct net_device *netdev = bus->priv;
1142 	struct ftgmac100 *priv = netdev_priv(netdev);
1143 	unsigned int phycr;
1144 	int data;
1145 	int i;
1146 
1147 	phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1148 
1149 	/* preserve MDC cycle threshold */
1150 	phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1151 
1152 	phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1153 		 FTGMAC100_PHYCR_REGAD(regnum) |
1154 		 FTGMAC100_PHYCR_MIIWR;
1155 
1156 	data = FTGMAC100_PHYDATA_MIIWDATA(value);
1157 
1158 	iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1159 	iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1160 
1161 	for (i = 0; i < 10; i++) {
1162 		phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1163 
1164 		if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1165 			return 0;
1166 
1167 		udelay(100);
1168 	}
1169 
1170 	netdev_err(netdev, "mdio write timed out\n");
1171 	return -EIO;
1172 }
1173 
1174 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1175 				  struct ethtool_drvinfo *info)
1176 {
1177 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1178 	strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1179 }
1180 
1181 static void ftgmac100_get_ringparam(struct net_device *netdev,
1182 				    struct ethtool_ringparam *ering)
1183 {
1184 	struct ftgmac100 *priv = netdev_priv(netdev);
1185 
1186 	memset(ering, 0, sizeof(*ering));
1187 	ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1188 	ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1189 	ering->rx_pending = priv->rx_q_entries;
1190 	ering->tx_pending = priv->tx_q_entries;
1191 }
1192 
1193 static int ftgmac100_set_ringparam(struct net_device *netdev,
1194 				   struct ethtool_ringparam *ering)
1195 {
1196 	struct ftgmac100 *priv = netdev_priv(netdev);
1197 
1198 	if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1199 	    ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1200 	    ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1201 	    ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1202 	    !is_power_of_2(ering->rx_pending) ||
1203 	    !is_power_of_2(ering->tx_pending))
1204 		return -EINVAL;
1205 
1206 	priv->new_rx_q_entries = ering->rx_pending;
1207 	priv->new_tx_q_entries = ering->tx_pending;
1208 	if (netif_running(netdev))
1209 		schedule_work(&priv->reset_task);
1210 
1211 	return 0;
1212 }
1213 
1214 static void ftgmac100_get_pauseparam(struct net_device *netdev,
1215 				     struct ethtool_pauseparam *pause)
1216 {
1217 	struct ftgmac100 *priv = netdev_priv(netdev);
1218 
1219 	pause->autoneg = priv->aneg_pause;
1220 	pause->tx_pause = priv->tx_pause;
1221 	pause->rx_pause = priv->rx_pause;
1222 }
1223 
1224 static int ftgmac100_set_pauseparam(struct net_device *netdev,
1225 				    struct ethtool_pauseparam *pause)
1226 {
1227 	struct ftgmac100 *priv = netdev_priv(netdev);
1228 	struct phy_device *phydev = netdev->phydev;
1229 
1230 	priv->aneg_pause = pause->autoneg;
1231 	priv->tx_pause = pause->tx_pause;
1232 	priv->rx_pause = pause->rx_pause;
1233 
1234 	if (phydev)
1235 		phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause);
1236 
1237 	if (netif_running(netdev)) {
1238 		if (!(phydev && priv->aneg_pause))
1239 			ftgmac100_config_pause(priv);
1240 	}
1241 
1242 	return 0;
1243 }
1244 
1245 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1246 	.get_drvinfo		= ftgmac100_get_drvinfo,
1247 	.get_link		= ethtool_op_get_link,
1248 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
1249 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
1250 	.nway_reset		= phy_ethtool_nway_reset,
1251 	.get_ringparam		= ftgmac100_get_ringparam,
1252 	.set_ringparam		= ftgmac100_set_ringparam,
1253 	.get_pauseparam		= ftgmac100_get_pauseparam,
1254 	.set_pauseparam		= ftgmac100_set_pauseparam,
1255 };
1256 
1257 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1258 {
1259 	struct net_device *netdev = dev_id;
1260 	struct ftgmac100 *priv = netdev_priv(netdev);
1261 	unsigned int status, new_mask = FTGMAC100_INT_BAD;
1262 
1263 	/* Fetch and clear interrupt bits, process abnormal ones */
1264 	status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1265 	iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1266 	if (unlikely(status & FTGMAC100_INT_BAD)) {
1267 
1268 		/* RX buffer unavailable */
1269 		if (status & FTGMAC100_INT_NO_RXBUF)
1270 			netdev->stats.rx_over_errors++;
1271 
1272 		/* received packet lost due to RX FIFO full */
1273 		if (status & FTGMAC100_INT_RPKT_LOST)
1274 			netdev->stats.rx_fifo_errors++;
1275 
1276 		/* sent packet lost due to excessive TX collision */
1277 		if (status & FTGMAC100_INT_XPKT_LOST)
1278 			netdev->stats.tx_fifo_errors++;
1279 
1280 		/* AHB error -> Reset the chip */
1281 		if (status & FTGMAC100_INT_AHB_ERR) {
1282 			if (net_ratelimit())
1283 				netdev_warn(netdev,
1284 					   "AHB bus error ! Resetting chip.\n");
1285 			iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1286 			schedule_work(&priv->reset_task);
1287 			return IRQ_HANDLED;
1288 		}
1289 
1290 		/* We may need to restart the MAC after such errors, delay
1291 		 * this until after we have freed some Rx buffers though
1292 		 */
1293 		priv->need_mac_restart = true;
1294 
1295 		/* Disable those errors until we restart */
1296 		new_mask &= ~status;
1297 	}
1298 
1299 	/* Only enable "bad" interrupts while NAPI is on */
1300 	iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1301 
1302 	/* Schedule NAPI bh */
1303 	napi_schedule_irqoff(&priv->napi);
1304 
1305 	return IRQ_HANDLED;
1306 }
1307 
1308 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1309 {
1310 	struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1311 
1312 	/* Do we have a packet ? */
1313 	return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1314 }
1315 
1316 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1317 {
1318 	struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1319 	int work_done = 0;
1320 	bool more;
1321 
1322 	/* Handle TX completions */
1323 	if (ftgmac100_tx_buf_cleanable(priv))
1324 		ftgmac100_tx_complete(priv);
1325 
1326 	/* Handle RX packets */
1327 	do {
1328 		more = ftgmac100_rx_packet(priv, &work_done);
1329 	} while (more && work_done < budget);
1330 
1331 
1332 	/* The interrupt is telling us to kick the MAC back to life
1333 	 * after an RX overflow
1334 	 */
1335 	if (unlikely(priv->need_mac_restart)) {
1336 		ftgmac100_start_hw(priv);
1337 		priv->need_mac_restart = false;
1338 
1339 		/* Re-enable "bad" interrupts */
1340 		iowrite32(FTGMAC100_INT_BAD,
1341 			  priv->base + FTGMAC100_OFFSET_IER);
1342 	}
1343 
1344 	/* As long as we are waiting for transmit packets to be
1345 	 * completed we keep NAPI going
1346 	 */
1347 	if (ftgmac100_tx_buf_cleanable(priv))
1348 		work_done = budget;
1349 
1350 	if (work_done < budget) {
1351 		/* We are about to re-enable all interrupts. However
1352 		 * the HW has been latching RX/TX packet interrupts while
1353 		 * they were masked. So we clear them first, then we need
1354 		 * to re-check if there's something to process
1355 		 */
1356 		iowrite32(FTGMAC100_INT_RXTX,
1357 			  priv->base + FTGMAC100_OFFSET_ISR);
1358 
1359 		/* Push the above (and provides a barrier vs. subsequent
1360 		 * reads of the descriptor).
1361 		 */
1362 		ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1363 
1364 		/* Check RX and TX descriptors for more work to do */
1365 		if (ftgmac100_check_rx(priv) ||
1366 		    ftgmac100_tx_buf_cleanable(priv))
1367 			return budget;
1368 
1369 		/* deschedule NAPI */
1370 		napi_complete(napi);
1371 
1372 		/* enable all interrupts */
1373 		iowrite32(FTGMAC100_INT_ALL,
1374 			  priv->base + FTGMAC100_OFFSET_IER);
1375 	}
1376 
1377 	return work_done;
1378 }
1379 
1380 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1381 {
1382 	int err = 0;
1383 
1384 	/* Re-init descriptors (adjust queue sizes) */
1385 	ftgmac100_init_rings(priv);
1386 
1387 	/* Realloc rx descriptors */
1388 	err = ftgmac100_alloc_rx_buffers(priv);
1389 	if (err && !ignore_alloc_err)
1390 		return err;
1391 
1392 	/* Reinit and restart HW */
1393 	ftgmac100_init_hw(priv);
1394 	ftgmac100_config_pause(priv);
1395 	ftgmac100_start_hw(priv);
1396 
1397 	/* Re-enable the device */
1398 	napi_enable(&priv->napi);
1399 	netif_start_queue(priv->netdev);
1400 
1401 	/* Enable all interrupts */
1402 	iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1403 
1404 	return err;
1405 }
1406 
1407 static void ftgmac100_reset_task(struct work_struct *work)
1408 {
1409 	struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1410 					      reset_task);
1411 	struct net_device *netdev = priv->netdev;
1412 	int err;
1413 
1414 	netdev_dbg(netdev, "Resetting NIC...\n");
1415 
1416 	/* Lock the world */
1417 	rtnl_lock();
1418 	if (netdev->phydev)
1419 		mutex_lock(&netdev->phydev->lock);
1420 	if (priv->mii_bus)
1421 		mutex_lock(&priv->mii_bus->mdio_lock);
1422 
1423 
1424 	/* Check if the interface is still up */
1425 	if (!netif_running(netdev))
1426 		goto bail;
1427 
1428 	/* Stop the network stack */
1429 	netif_trans_update(netdev);
1430 	napi_disable(&priv->napi);
1431 	netif_tx_disable(netdev);
1432 
1433 	/* Stop and reset the MAC */
1434 	ftgmac100_stop_hw(priv);
1435 	err = ftgmac100_reset_and_config_mac(priv);
1436 	if (err) {
1437 		/* Not much we can do ... it might come back... */
1438 		netdev_err(netdev, "attempting to continue...\n");
1439 	}
1440 
1441 	/* Free all rx and tx buffers */
1442 	ftgmac100_free_buffers(priv);
1443 
1444 	/* Setup everything again and restart chip */
1445 	ftgmac100_init_all(priv, true);
1446 
1447 	netdev_dbg(netdev, "Reset done !\n");
1448  bail:
1449 	if (priv->mii_bus)
1450 		mutex_unlock(&priv->mii_bus->mdio_lock);
1451 	if (netdev->phydev)
1452 		mutex_unlock(&netdev->phydev->lock);
1453 	rtnl_unlock();
1454 }
1455 
1456 static int ftgmac100_open(struct net_device *netdev)
1457 {
1458 	struct ftgmac100 *priv = netdev_priv(netdev);
1459 	int err;
1460 
1461 	/* Allocate ring buffers  */
1462 	err = ftgmac100_alloc_rings(priv);
1463 	if (err) {
1464 		netdev_err(netdev, "Failed to allocate descriptors\n");
1465 		return err;
1466 	}
1467 
1468 	/* When using NC-SI we force the speed to 100Mbit/s full duplex,
1469 	 *
1470 	 * Otherwise we leave it set to 0 (no link), the link
1471 	 * message from the PHY layer will handle setting it up to
1472 	 * something else if needed.
1473 	 */
1474 	if (priv->use_ncsi) {
1475 		priv->cur_duplex = DUPLEX_FULL;
1476 		priv->cur_speed = SPEED_100;
1477 	} else {
1478 		priv->cur_duplex = 0;
1479 		priv->cur_speed = 0;
1480 	}
1481 
1482 	/* Reset the hardware */
1483 	err = ftgmac100_reset_and_config_mac(priv);
1484 	if (err)
1485 		goto err_hw;
1486 
1487 	/* Initialize NAPI */
1488 	netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1489 
1490 	/* Grab our interrupt */
1491 	err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1492 	if (err) {
1493 		netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1494 		goto err_irq;
1495 	}
1496 
1497 	/* Start things up */
1498 	err = ftgmac100_init_all(priv, false);
1499 	if (err) {
1500 		netdev_err(netdev, "Failed to allocate packet buffers\n");
1501 		goto err_alloc;
1502 	}
1503 
1504 	if (netdev->phydev) {
1505 		/* If we have a PHY, start polling */
1506 		phy_start(netdev->phydev);
1507 	} else if (priv->use_ncsi) {
1508 		/* If using NC-SI, set our carrier on and start the stack */
1509 		netif_carrier_on(netdev);
1510 
1511 		/* Start the NCSI device */
1512 		err = ncsi_start_dev(priv->ndev);
1513 		if (err)
1514 			goto err_ncsi;
1515 	}
1516 
1517 	return 0;
1518 
1519  err_ncsi:
1520 	napi_disable(&priv->napi);
1521 	netif_stop_queue(netdev);
1522  err_alloc:
1523 	ftgmac100_free_buffers(priv);
1524 	free_irq(netdev->irq, netdev);
1525  err_irq:
1526 	netif_napi_del(&priv->napi);
1527  err_hw:
1528 	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1529 	ftgmac100_free_rings(priv);
1530 	return err;
1531 }
1532 
1533 static int ftgmac100_stop(struct net_device *netdev)
1534 {
1535 	struct ftgmac100 *priv = netdev_priv(netdev);
1536 
1537 	/* Note about the reset task: We are called with the rtnl lock
1538 	 * held, so we are synchronized against the core of the reset
1539 	 * task. We must not try to synchronously cancel it otherwise
1540 	 * we can deadlock. But since it will test for netif_running()
1541 	 * which has already been cleared by the net core, we don't
1542 	 * anything special to do.
1543 	 */
1544 
1545 	/* disable all interrupts */
1546 	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1547 
1548 	netif_stop_queue(netdev);
1549 	napi_disable(&priv->napi);
1550 	netif_napi_del(&priv->napi);
1551 	if (netdev->phydev)
1552 		phy_stop(netdev->phydev);
1553 	else if (priv->use_ncsi)
1554 		ncsi_stop_dev(priv->ndev);
1555 
1556 	ftgmac100_stop_hw(priv);
1557 	free_irq(netdev->irq, netdev);
1558 	ftgmac100_free_buffers(priv);
1559 	ftgmac100_free_rings(priv);
1560 
1561 	return 0;
1562 }
1563 
1564 static void ftgmac100_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1565 {
1566 	struct ftgmac100 *priv = netdev_priv(netdev);
1567 
1568 	/* Disable all interrupts */
1569 	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1570 
1571 	/* Do the reset outside of interrupt context */
1572 	schedule_work(&priv->reset_task);
1573 }
1574 
1575 static int ftgmac100_set_features(struct net_device *netdev,
1576 				  netdev_features_t features)
1577 {
1578 	struct ftgmac100 *priv = netdev_priv(netdev);
1579 	netdev_features_t changed = netdev->features ^ features;
1580 
1581 	if (!netif_running(netdev))
1582 		return 0;
1583 
1584 	/* Update the vlan filtering bit */
1585 	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
1586 		u32 maccr;
1587 
1588 		maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
1589 		if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1590 			maccr |= FTGMAC100_MACCR_RM_VLAN;
1591 		else
1592 			maccr &= ~FTGMAC100_MACCR_RM_VLAN;
1593 		iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
1594 	}
1595 
1596 	return 0;
1597 }
1598 
1599 #ifdef CONFIG_NET_POLL_CONTROLLER
1600 static void ftgmac100_poll_controller(struct net_device *netdev)
1601 {
1602 	unsigned long flags;
1603 
1604 	local_irq_save(flags);
1605 	ftgmac100_interrupt(netdev->irq, netdev);
1606 	local_irq_restore(flags);
1607 }
1608 #endif
1609 
1610 static const struct net_device_ops ftgmac100_netdev_ops = {
1611 	.ndo_open		= ftgmac100_open,
1612 	.ndo_stop		= ftgmac100_stop,
1613 	.ndo_start_xmit		= ftgmac100_hard_start_xmit,
1614 	.ndo_set_mac_address	= ftgmac100_set_mac_addr,
1615 	.ndo_validate_addr	= eth_validate_addr,
1616 	.ndo_eth_ioctl		= phy_do_ioctl,
1617 	.ndo_tx_timeout		= ftgmac100_tx_timeout,
1618 	.ndo_set_rx_mode	= ftgmac100_set_rx_mode,
1619 	.ndo_set_features	= ftgmac100_set_features,
1620 #ifdef CONFIG_NET_POLL_CONTROLLER
1621 	.ndo_poll_controller	= ftgmac100_poll_controller,
1622 #endif
1623 	.ndo_vlan_rx_add_vid	= ncsi_vlan_rx_add_vid,
1624 	.ndo_vlan_rx_kill_vid	= ncsi_vlan_rx_kill_vid,
1625 };
1626 
1627 static int ftgmac100_setup_mdio(struct net_device *netdev)
1628 {
1629 	struct ftgmac100 *priv = netdev_priv(netdev);
1630 	struct platform_device *pdev = to_platform_device(priv->dev);
1631 	struct device_node *np = pdev->dev.of_node;
1632 	struct device_node *mdio_np;
1633 	int i, err = 0;
1634 	u32 reg;
1635 
1636 	/* initialize mdio bus */
1637 	priv->mii_bus = mdiobus_alloc();
1638 	if (!priv->mii_bus)
1639 		return -EIO;
1640 
1641 	if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1642 	    of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1643 		/* The AST2600 has a separate MDIO controller */
1644 
1645 		/* For the AST2400 and AST2500 this driver only supports the
1646 		 * old MDIO interface
1647 		 */
1648 		reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1649 		reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1650 		iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1651 	}
1652 
1653 	priv->mii_bus->name = "ftgmac100_mdio";
1654 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1655 		 pdev->name, pdev->id);
1656 	priv->mii_bus->parent = priv->dev;
1657 	priv->mii_bus->priv = priv->netdev;
1658 	priv->mii_bus->read = ftgmac100_mdiobus_read;
1659 	priv->mii_bus->write = ftgmac100_mdiobus_write;
1660 
1661 	for (i = 0; i < PHY_MAX_ADDR; i++)
1662 		priv->mii_bus->irq[i] = PHY_POLL;
1663 
1664 	mdio_np = of_get_child_by_name(np, "mdio");
1665 
1666 	err = of_mdiobus_register(priv->mii_bus, mdio_np);
1667 	if (err) {
1668 		dev_err(priv->dev, "Cannot register MDIO bus!\n");
1669 		goto err_register_mdiobus;
1670 	}
1671 
1672 	of_node_put(mdio_np);
1673 
1674 	return 0;
1675 
1676 err_register_mdiobus:
1677 	mdiobus_free(priv->mii_bus);
1678 	return err;
1679 }
1680 
1681 static void ftgmac100_phy_disconnect(struct net_device *netdev)
1682 {
1683 	if (!netdev->phydev)
1684 		return;
1685 
1686 	phy_disconnect(netdev->phydev);
1687 }
1688 
1689 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1690 {
1691 	struct ftgmac100 *priv = netdev_priv(netdev);
1692 
1693 	if (!priv->mii_bus)
1694 		return;
1695 
1696 	mdiobus_unregister(priv->mii_bus);
1697 	mdiobus_free(priv->mii_bus);
1698 }
1699 
1700 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1701 {
1702 	if (unlikely(nd->state != ncsi_dev_state_functional))
1703 		return;
1704 
1705 	netdev_dbg(nd->dev, "NCSI interface %s\n",
1706 		   nd->link_up ? "up" : "down");
1707 }
1708 
1709 static int ftgmac100_setup_clk(struct ftgmac100 *priv)
1710 {
1711 	struct clk *clk;
1712 	int rc;
1713 
1714 	clk = devm_clk_get(priv->dev, NULL /* MACCLK */);
1715 	if (IS_ERR(clk))
1716 		return PTR_ERR(clk);
1717 	priv->clk = clk;
1718 	rc = clk_prepare_enable(priv->clk);
1719 	if (rc)
1720 		return rc;
1721 
1722 	/* Aspeed specifies a 100MHz clock is required for up to
1723 	 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz
1724 	 * is sufficient
1725 	 */
1726 	rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ :
1727 			  FTGMAC_100MHZ);
1728 	if (rc)
1729 		goto cleanup_clk;
1730 
1731 	/* RCLK is for RMII, typically used for NCSI. Optional because it's not
1732 	 * necessary if it's the AST2400 MAC, or the MAC is configured for
1733 	 * RGMII, or the controller is not an ASPEED-based controller.
1734 	 */
1735 	priv->rclk = devm_clk_get_optional(priv->dev, "RCLK");
1736 	rc = clk_prepare_enable(priv->rclk);
1737 	if (!rc)
1738 		return 0;
1739 
1740 cleanup_clk:
1741 	clk_disable_unprepare(priv->clk);
1742 
1743 	return rc;
1744 }
1745 
1746 static int ftgmac100_probe(struct platform_device *pdev)
1747 {
1748 	struct resource *res;
1749 	int irq;
1750 	struct net_device *netdev;
1751 	struct ftgmac100 *priv;
1752 	struct device_node *np;
1753 	int err = 0;
1754 
1755 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1756 	if (!res)
1757 		return -ENXIO;
1758 
1759 	irq = platform_get_irq(pdev, 0);
1760 	if (irq < 0)
1761 		return irq;
1762 
1763 	/* setup net_device */
1764 	netdev = alloc_etherdev(sizeof(*priv));
1765 	if (!netdev) {
1766 		err = -ENOMEM;
1767 		goto err_alloc_etherdev;
1768 	}
1769 
1770 	SET_NETDEV_DEV(netdev, &pdev->dev);
1771 
1772 	netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1773 	netdev->netdev_ops = &ftgmac100_netdev_ops;
1774 	netdev->watchdog_timeo = 5 * HZ;
1775 
1776 	platform_set_drvdata(pdev, netdev);
1777 
1778 	/* setup private data */
1779 	priv = netdev_priv(netdev);
1780 	priv->netdev = netdev;
1781 	priv->dev = &pdev->dev;
1782 	INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1783 
1784 	/* map io memory */
1785 	priv->res = request_mem_region(res->start, resource_size(res),
1786 				       dev_name(&pdev->dev));
1787 	if (!priv->res) {
1788 		dev_err(&pdev->dev, "Could not reserve memory region\n");
1789 		err = -ENOMEM;
1790 		goto err_req_mem;
1791 	}
1792 
1793 	priv->base = ioremap(res->start, resource_size(res));
1794 	if (!priv->base) {
1795 		dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1796 		err = -EIO;
1797 		goto err_ioremap;
1798 	}
1799 
1800 	netdev->irq = irq;
1801 
1802 	/* Enable pause */
1803 	priv->tx_pause = true;
1804 	priv->rx_pause = true;
1805 	priv->aneg_pause = true;
1806 
1807 	/* MAC address from chip or random one */
1808 	ftgmac100_initial_mac(priv);
1809 
1810 	np = pdev->dev.of_node;
1811 	if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1812 		   of_device_is_compatible(np, "aspeed,ast2500-mac") ||
1813 		   of_device_is_compatible(np, "aspeed,ast2600-mac"))) {
1814 		priv->rxdes0_edorr_mask = BIT(30);
1815 		priv->txdes0_edotr_mask = BIT(30);
1816 		priv->is_aspeed = true;
1817 		/* Disable ast2600 problematic HW arbitration */
1818 		if (of_device_is_compatible(np, "aspeed,ast2600-mac")) {
1819 			iowrite32(FTGMAC100_TM_DEFAULT,
1820 				  priv->base + FTGMAC100_OFFSET_TM);
1821 		}
1822 	} else {
1823 		priv->rxdes0_edorr_mask = BIT(15);
1824 		priv->txdes0_edotr_mask = BIT(15);
1825 	}
1826 
1827 	if (np && of_get_property(np, "use-ncsi", NULL)) {
1828 		if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1829 			dev_err(&pdev->dev, "NCSI stack not enabled\n");
1830 			err = -EINVAL;
1831 			goto err_phy_connect;
1832 		}
1833 
1834 		dev_info(&pdev->dev, "Using NCSI interface\n");
1835 		priv->use_ncsi = true;
1836 		priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1837 		if (!priv->ndev) {
1838 			err = -EINVAL;
1839 			goto err_phy_connect;
1840 		}
1841 	} else if (np && of_get_property(np, "phy-handle", NULL)) {
1842 		struct phy_device *phy;
1843 
1844 		/* Support "mdio"/"phy" child nodes for ast2400/2500 with
1845 		 * an embedded MDIO controller. Automatically scan the DTS for
1846 		 * available PHYs and register them.
1847 		 */
1848 		if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1849 		    of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1850 			err = ftgmac100_setup_mdio(netdev);
1851 			if (err)
1852 				goto err_setup_mdio;
1853 		}
1854 
1855 		phy = of_phy_get_and_connect(priv->netdev, np,
1856 					     &ftgmac100_adjust_link);
1857 		if (!phy) {
1858 			dev_err(&pdev->dev, "Failed to connect to phy\n");
1859 			err = -EINVAL;
1860 			goto err_phy_connect;
1861 		}
1862 
1863 		/* Indicate that we support PAUSE frames (see comment in
1864 		 * Documentation/networking/phy.rst)
1865 		 */
1866 		phy_support_asym_pause(phy);
1867 
1868 		/* Display what we found */
1869 		phy_attached_info(phy);
1870 	} else if (np && !of_get_child_by_name(np, "mdio")) {
1871 		/* Support legacy ASPEED devicetree descriptions that decribe a
1872 		 * MAC with an embedded MDIO controller but have no "mdio"
1873 		 * child node. Automatically scan the MDIO bus for available
1874 		 * PHYs.
1875 		 */
1876 		priv->use_ncsi = false;
1877 		err = ftgmac100_setup_mdio(netdev);
1878 		if (err)
1879 			goto err_setup_mdio;
1880 
1881 		err = ftgmac100_mii_probe(netdev);
1882 		if (err) {
1883 			dev_err(priv->dev, "MII probe failed!\n");
1884 			goto err_ncsi_dev;
1885 		}
1886 
1887 	}
1888 
1889 	if (priv->is_aspeed) {
1890 		err = ftgmac100_setup_clk(priv);
1891 		if (err)
1892 			goto err_phy_connect;
1893 	}
1894 
1895 	/* Default ring sizes */
1896 	priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1897 	priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1898 
1899 	/* Base feature set */
1900 	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1901 		NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX |
1902 		NETIF_F_HW_VLAN_CTAG_TX;
1903 
1904 	if (priv->use_ncsi)
1905 		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1906 
1907 	/* AST2400  doesn't have working HW checksum generation */
1908 	if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1909 		netdev->hw_features &= ~NETIF_F_HW_CSUM;
1910 	if (np && of_get_property(np, "no-hw-checksum", NULL))
1911 		netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
1912 	netdev->features |= netdev->hw_features;
1913 
1914 	/* register network device */
1915 	err = register_netdev(netdev);
1916 	if (err) {
1917 		dev_err(&pdev->dev, "Failed to register netdev\n");
1918 		goto err_register_netdev;
1919 	}
1920 
1921 	netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1922 
1923 	return 0;
1924 
1925 err_register_netdev:
1926 	clk_disable_unprepare(priv->rclk);
1927 	clk_disable_unprepare(priv->clk);
1928 err_phy_connect:
1929 	ftgmac100_phy_disconnect(netdev);
1930 err_ncsi_dev:
1931 	if (priv->ndev)
1932 		ncsi_unregister_dev(priv->ndev);
1933 	ftgmac100_destroy_mdio(netdev);
1934 err_setup_mdio:
1935 	iounmap(priv->base);
1936 err_ioremap:
1937 	release_resource(priv->res);
1938 err_req_mem:
1939 	free_netdev(netdev);
1940 err_alloc_etherdev:
1941 	return err;
1942 }
1943 
1944 static int ftgmac100_remove(struct platform_device *pdev)
1945 {
1946 	struct net_device *netdev;
1947 	struct ftgmac100 *priv;
1948 
1949 	netdev = platform_get_drvdata(pdev);
1950 	priv = netdev_priv(netdev);
1951 
1952 	if (priv->ndev)
1953 		ncsi_unregister_dev(priv->ndev);
1954 	unregister_netdev(netdev);
1955 
1956 	clk_disable_unprepare(priv->rclk);
1957 	clk_disable_unprepare(priv->clk);
1958 
1959 	/* There's a small chance the reset task will have been re-queued,
1960 	 * during stop, make sure it's gone before we free the structure.
1961 	 */
1962 	cancel_work_sync(&priv->reset_task);
1963 
1964 	ftgmac100_phy_disconnect(netdev);
1965 	ftgmac100_destroy_mdio(netdev);
1966 
1967 	iounmap(priv->base);
1968 	release_resource(priv->res);
1969 
1970 	netif_napi_del(&priv->napi);
1971 	free_netdev(netdev);
1972 	return 0;
1973 }
1974 
1975 static const struct of_device_id ftgmac100_of_match[] = {
1976 	{ .compatible = "faraday,ftgmac100" },
1977 	{ }
1978 };
1979 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1980 
1981 static struct platform_driver ftgmac100_driver = {
1982 	.probe	= ftgmac100_probe,
1983 	.remove	= ftgmac100_remove,
1984 	.driver	= {
1985 		.name		= DRV_NAME,
1986 		.of_match_table	= ftgmac100_of_match,
1987 	},
1988 };
1989 module_platform_driver(ftgmac100_driver);
1990 
1991 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1992 MODULE_DESCRIPTION("FTGMAC100 driver");
1993 MODULE_LICENSE("GPL");
1994