1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Faraday FTGMAC100 Gigabit Ethernet 4 * 5 * (C) Copyright 2009-2011 Faraday Technology 6 * Po-Yu Chuang <ratbert@faraday-tech.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/netdevice.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/property.h> 24 #include <linux/crc32.h> 25 #include <linux/if_vlan.h> 26 #include <linux/of_net.h> 27 #include <net/ip.h> 28 #include <net/ncsi.h> 29 30 #include "ftgmac100.h" 31 32 #define DRV_NAME "ftgmac100" 33 34 /* Arbitrary values, I am not sure the HW has limits */ 35 #define MAX_RX_QUEUE_ENTRIES 1024 36 #define MAX_TX_QUEUE_ENTRIES 1024 37 #define MIN_RX_QUEUE_ENTRIES 32 38 #define MIN_TX_QUEUE_ENTRIES 32 39 40 /* Defaults */ 41 #define DEF_RX_QUEUE_ENTRIES 128 42 #define DEF_TX_QUEUE_ENTRIES 128 43 44 #define MAX_PKT_SIZE 1536 45 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */ 46 47 /* Min number of tx ring entries before stopping queue */ 48 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1) 49 50 #define FTGMAC_100MHZ 100000000 51 #define FTGMAC_25MHZ 25000000 52 53 struct ftgmac100 { 54 /* Registers */ 55 struct resource *res; 56 void __iomem *base; 57 58 /* Rx ring */ 59 unsigned int rx_q_entries; 60 struct ftgmac100_rxdes *rxdes; 61 dma_addr_t rxdes_dma; 62 struct sk_buff **rx_skbs; 63 unsigned int rx_pointer; 64 u32 rxdes0_edorr_mask; 65 66 /* Tx ring */ 67 unsigned int tx_q_entries; 68 struct ftgmac100_txdes *txdes; 69 dma_addr_t txdes_dma; 70 struct sk_buff **tx_skbs; 71 unsigned int tx_clean_pointer; 72 unsigned int tx_pointer; 73 u32 txdes0_edotr_mask; 74 75 /* Used to signal the reset task of ring change request */ 76 unsigned int new_rx_q_entries; 77 unsigned int new_tx_q_entries; 78 79 /* Scratch page to use when rx skb alloc fails */ 80 void *rx_scratch; 81 dma_addr_t rx_scratch_dma; 82 83 /* Component structures */ 84 struct net_device *netdev; 85 struct device *dev; 86 struct ncsi_dev *ndev; 87 struct napi_struct napi; 88 struct work_struct reset_task; 89 struct mii_bus *mii_bus; 90 struct clk *clk; 91 92 /* AST2500/AST2600 RMII ref clock gate */ 93 struct clk *rclk; 94 95 /* Link management */ 96 int cur_speed; 97 int cur_duplex; 98 bool use_ncsi; 99 100 /* Multicast filter settings */ 101 u32 maht0; 102 u32 maht1; 103 104 /* Flow control settings */ 105 bool tx_pause; 106 bool rx_pause; 107 bool aneg_pause; 108 109 /* Misc */ 110 bool need_mac_restart; 111 bool is_aspeed; 112 }; 113 114 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr) 115 { 116 struct net_device *netdev = priv->netdev; 117 int i; 118 119 /* NOTE: reset clears all registers */ 120 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 121 iowrite32(maccr | FTGMAC100_MACCR_SW_RST, 122 priv->base + FTGMAC100_OFFSET_MACCR); 123 for (i = 0; i < 200; i++) { 124 unsigned int maccr; 125 126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 127 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 128 return 0; 129 130 udelay(1); 131 } 132 133 netdev_err(netdev, "Hardware reset failed\n"); 134 return -EIO; 135 } 136 137 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) 138 { 139 u32 maccr = 0; 140 141 switch (priv->cur_speed) { 142 case SPEED_10: 143 case 0: /* no link */ 144 break; 145 146 case SPEED_100: 147 maccr |= FTGMAC100_MACCR_FAST_MODE; 148 break; 149 150 case SPEED_1000: 151 maccr |= FTGMAC100_MACCR_GIGA_MODE; 152 break; 153 default: 154 netdev_err(priv->netdev, "Unknown speed %d !\n", 155 priv->cur_speed); 156 break; 157 } 158 159 /* (Re)initialize the queue pointers */ 160 priv->rx_pointer = 0; 161 priv->tx_clean_pointer = 0; 162 priv->tx_pointer = 0; 163 164 /* The doc says reset twice with 10us interval */ 165 if (ftgmac100_reset_mac(priv, maccr)) 166 return -EIO; 167 usleep_range(10, 1000); 168 return ftgmac100_reset_mac(priv, maccr); 169 } 170 171 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac) 172 { 173 unsigned int maddr = mac[0] << 8 | mac[1]; 174 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 175 176 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 177 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 178 } 179 180 static int ftgmac100_initial_mac(struct ftgmac100 *priv) 181 { 182 u8 mac[ETH_ALEN]; 183 unsigned int m; 184 unsigned int l; 185 int err; 186 187 err = of_get_ethdev_address(priv->dev->of_node, priv->netdev); 188 if (err == -EPROBE_DEFER) 189 return err; 190 if (!err) { 191 dev_info(priv->dev, "Read MAC address %pM from device tree\n", 192 priv->netdev->dev_addr); 193 return 0; 194 } 195 196 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); 197 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); 198 199 mac[0] = (m >> 8) & 0xff; 200 mac[1] = m & 0xff; 201 mac[2] = (l >> 24) & 0xff; 202 mac[3] = (l >> 16) & 0xff; 203 mac[4] = (l >> 8) & 0xff; 204 mac[5] = l & 0xff; 205 206 if (is_valid_ether_addr(mac)) { 207 eth_hw_addr_set(priv->netdev, mac); 208 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac); 209 } else { 210 eth_hw_addr_random(priv->netdev); 211 dev_info(priv->dev, "Generated random MAC address %pM\n", 212 priv->netdev->dev_addr); 213 } 214 215 return 0; 216 } 217 218 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p) 219 { 220 int ret; 221 222 ret = eth_prepare_mac_addr_change(dev, p); 223 if (ret < 0) 224 return ret; 225 226 eth_commit_mac_addr_change(dev, p); 227 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr); 228 229 return 0; 230 } 231 232 static void ftgmac100_config_pause(struct ftgmac100 *priv) 233 { 234 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16); 235 236 /* Throttle tx queue when receiving pause frames */ 237 if (priv->rx_pause) 238 fcr |= FTGMAC100_FCR_FC_EN; 239 240 /* Enables sending pause frames when the RX queue is past a 241 * certain threshold. 242 */ 243 if (priv->tx_pause) 244 fcr |= FTGMAC100_FCR_FCTHR_EN; 245 246 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR); 247 } 248 249 static void ftgmac100_init_hw(struct ftgmac100 *priv) 250 { 251 u32 reg, rfifo_sz, tfifo_sz; 252 253 /* Clear stale interrupts */ 254 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 255 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); 256 257 /* Setup RX ring buffer base */ 258 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR); 259 260 /* Setup TX ring buffer base */ 261 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 262 263 /* Configure RX buffer size */ 264 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE), 265 priv->base + FTGMAC100_OFFSET_RBSR); 266 267 /* Set RX descriptor autopoll */ 268 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), 269 priv->base + FTGMAC100_OFFSET_APTC); 270 271 /* Write MAC address */ 272 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr); 273 274 /* Write multicast filter */ 275 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 276 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 277 278 /* Configure descriptor sizes and increase burst sizes according 279 * to values in Aspeed SDK. The FIFO arbitration is enabled and 280 * the thresholds set based on the recommended values in the 281 * AST2400 specification. 282 */ 283 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */ 284 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */ 285 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */ 286 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */ 287 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */ 288 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */ 289 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */ 290 priv->base + FTGMAC100_OFFSET_DBLAC); 291 292 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt 293 * mitigation doesn't seem to provide any benefit with NAPI so leave 294 * it at that. 295 */ 296 iowrite32(FTGMAC100_ITC_RXINT_THR(1) | 297 FTGMAC100_ITC_TXINT_THR(1), 298 priv->base + FTGMAC100_OFFSET_ITC); 299 300 /* Configure FIFO sizes in the TPAFCR register */ 301 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); 302 rfifo_sz = reg & 0x00000007; 303 tfifo_sz = (reg >> 3) & 0x00000007; 304 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); 305 reg &= ~0x3f000000; 306 reg |= (tfifo_sz << 27); 307 reg |= (rfifo_sz << 24); 308 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); 309 } 310 311 static void ftgmac100_start_hw(struct ftgmac100 *priv) 312 { 313 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 314 315 /* Keep the original GMAC and FAST bits */ 316 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE); 317 318 /* Add all the main enable bits */ 319 maccr |= FTGMAC100_MACCR_TXDMA_EN | 320 FTGMAC100_MACCR_RXDMA_EN | 321 FTGMAC100_MACCR_TXMAC_EN | 322 FTGMAC100_MACCR_RXMAC_EN | 323 FTGMAC100_MACCR_CRC_APD | 324 FTGMAC100_MACCR_PHY_LINK_LEVEL | 325 FTGMAC100_MACCR_RX_RUNT | 326 FTGMAC100_MACCR_RX_BROADPKT; 327 328 /* Add other bits as needed */ 329 if (priv->cur_duplex == DUPLEX_FULL) 330 maccr |= FTGMAC100_MACCR_FULLDUP; 331 if (priv->netdev->flags & IFF_PROMISC) 332 maccr |= FTGMAC100_MACCR_RX_ALL; 333 if (priv->netdev->flags & IFF_ALLMULTI) 334 maccr |= FTGMAC100_MACCR_RX_MULTIPKT; 335 else if (netdev_mc_count(priv->netdev)) 336 maccr |= FTGMAC100_MACCR_HT_MULTI_EN; 337 338 /* Vlan filtering enabled */ 339 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 340 maccr |= FTGMAC100_MACCR_RM_VLAN; 341 342 /* Hit the HW */ 343 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 344 } 345 346 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 347 { 348 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 349 } 350 351 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv) 352 { 353 struct netdev_hw_addr *ha; 354 355 priv->maht1 = 0; 356 priv->maht0 = 0; 357 netdev_for_each_mc_addr(ha, priv->netdev) { 358 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr); 359 360 crc_val = (~(crc_val >> 2)) & 0x3f; 361 if (crc_val >= 32) 362 priv->maht1 |= 1ul << (crc_val - 32); 363 else 364 priv->maht0 |= 1ul << (crc_val); 365 } 366 } 367 368 static void ftgmac100_set_rx_mode(struct net_device *netdev) 369 { 370 struct ftgmac100 *priv = netdev_priv(netdev); 371 372 /* Setup the hash filter */ 373 ftgmac100_calc_mc_hash(priv); 374 375 /* Interface down ? that's all there is to do */ 376 if (!netif_running(netdev)) 377 return; 378 379 /* Update the HW */ 380 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 381 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 382 383 /* Reconfigure MACCR */ 384 ftgmac100_start_hw(priv); 385 } 386 387 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry, 388 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 389 { 390 struct net_device *netdev = priv->netdev; 391 struct sk_buff *skb; 392 dma_addr_t map; 393 int err = 0; 394 395 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE); 396 if (unlikely(!skb)) { 397 if (net_ratelimit()) 398 netdev_warn(netdev, "failed to allocate rx skb\n"); 399 err = -ENOMEM; 400 map = priv->rx_scratch_dma; 401 } else { 402 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE, 403 DMA_FROM_DEVICE); 404 if (unlikely(dma_mapping_error(priv->dev, map))) { 405 if (net_ratelimit()) 406 netdev_err(netdev, "failed to map rx page\n"); 407 dev_kfree_skb_any(skb); 408 map = priv->rx_scratch_dma; 409 skb = NULL; 410 err = -ENOMEM; 411 } 412 } 413 414 /* Store skb */ 415 priv->rx_skbs[entry] = skb; 416 417 /* Store DMA address into RX desc */ 418 rxdes->rxdes3 = cpu_to_le32(map); 419 420 /* Ensure the above is ordered vs clearing the OWN bit */ 421 dma_wmb(); 422 423 /* Clean status (which resets own bit) */ 424 if (entry == (priv->rx_q_entries - 1)) 425 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask); 426 else 427 rxdes->rxdes0 = 0; 428 429 return err; 430 } 431 432 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv, 433 unsigned int pointer) 434 { 435 return (pointer + 1) & (priv->rx_q_entries - 1); 436 } 437 438 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status) 439 { 440 struct net_device *netdev = priv->netdev; 441 442 if (status & FTGMAC100_RXDES0_RX_ERR) 443 netdev->stats.rx_errors++; 444 445 if (status & FTGMAC100_RXDES0_CRC_ERR) 446 netdev->stats.rx_crc_errors++; 447 448 if (status & (FTGMAC100_RXDES0_FTL | 449 FTGMAC100_RXDES0_RUNT | 450 FTGMAC100_RXDES0_RX_ODD_NB)) 451 netdev->stats.rx_length_errors++; 452 } 453 454 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 455 { 456 struct net_device *netdev = priv->netdev; 457 struct ftgmac100_rxdes *rxdes; 458 struct sk_buff *skb; 459 unsigned int pointer, size; 460 u32 status, csum_vlan; 461 dma_addr_t map; 462 463 /* Grab next RX descriptor */ 464 pointer = priv->rx_pointer; 465 rxdes = &priv->rxdes[pointer]; 466 467 /* Grab descriptor status */ 468 status = le32_to_cpu(rxdes->rxdes0); 469 470 /* Do we have a packet ? */ 471 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY)) 472 return false; 473 474 /* Order subsequent reads with the test for the ready bit */ 475 dma_rmb(); 476 477 /* We don't cope with fragmented RX packets */ 478 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) || 479 !(status & FTGMAC100_RXDES0_LRS))) 480 goto drop; 481 482 /* Grab received size and csum vlan field in the descriptor */ 483 size = status & FTGMAC100_RXDES0_VDBC; 484 csum_vlan = le32_to_cpu(rxdes->rxdes1); 485 486 /* Any error (other than csum offload) flagged ? */ 487 if (unlikely(status & RXDES0_ANY_ERROR)) { 488 /* Correct for incorrect flagging of runt packets 489 * with vlan tags... Just accept a runt packet that 490 * has been flagged as vlan and whose size is at 491 * least 60 bytes. 492 */ 493 if ((status & FTGMAC100_RXDES0_RUNT) && 494 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) && 495 (size >= 60)) 496 status &= ~FTGMAC100_RXDES0_RUNT; 497 498 /* Any error still in there ? */ 499 if (status & RXDES0_ANY_ERROR) { 500 ftgmac100_rx_packet_error(priv, status); 501 goto drop; 502 } 503 } 504 505 /* If the packet had no skb (failed to allocate earlier) 506 * then try to allocate one and skip 507 */ 508 skb = priv->rx_skbs[pointer]; 509 if (!unlikely(skb)) { 510 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 511 goto drop; 512 } 513 514 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST)) 515 netdev->stats.multicast++; 516 517 /* If the HW found checksum errors, bounce it to software. 518 * 519 * If we didn't, we need to see if the packet was recognized 520 * by HW as one of the supported checksummed protocols before 521 * we accept the HW test results. 522 */ 523 if (netdev->features & NETIF_F_RXCSUM) { 524 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR | 525 FTGMAC100_RXDES1_UDP_CHKSUM_ERR | 526 FTGMAC100_RXDES1_IP_CHKSUM_ERR; 527 if ((csum_vlan & err_bits) || 528 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK)) 529 skb->ip_summed = CHECKSUM_NONE; 530 else 531 skb->ip_summed = CHECKSUM_UNNECESSARY; 532 } 533 534 /* Transfer received size to skb */ 535 skb_put(skb, size); 536 537 /* Extract vlan tag */ 538 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 539 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL)) 540 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 541 csum_vlan & 0xffff); 542 543 /* Tear down DMA mapping, do necessary cache management */ 544 map = le32_to_cpu(rxdes->rxdes3); 545 546 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU) 547 /* When we don't have an iommu, we can save cycles by not 548 * invalidating the cache for the part of the packet that 549 * wasn't received. 550 */ 551 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE); 552 #else 553 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 554 #endif 555 556 557 /* Resplenish rx ring */ 558 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 559 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 560 561 skb->protocol = eth_type_trans(skb, netdev); 562 563 netdev->stats.rx_packets++; 564 netdev->stats.rx_bytes += size; 565 566 /* push packet to protocol stack */ 567 if (skb->ip_summed == CHECKSUM_NONE) 568 netif_receive_skb(skb); 569 else 570 napi_gro_receive(&priv->napi, skb); 571 572 (*processed)++; 573 return true; 574 575 drop: 576 /* Clean rxdes0 (which resets own bit) */ 577 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask); 578 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 579 netdev->stats.rx_dropped++; 580 return true; 581 } 582 583 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv, 584 unsigned int index) 585 { 586 if (index == (priv->tx_q_entries - 1)) 587 return priv->txdes0_edotr_mask; 588 else 589 return 0; 590 } 591 592 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv, 593 unsigned int pointer) 594 { 595 return (pointer + 1) & (priv->tx_q_entries - 1); 596 } 597 598 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv) 599 { 600 /* Returns the number of available slots in the TX queue 601 * 602 * This always leaves one free slot so we don't have to 603 * worry about empty vs. full, and this simplifies the 604 * test for ftgmac100_tx_buf_cleanable() below 605 */ 606 return (priv->tx_clean_pointer - priv->tx_pointer - 1) & 607 (priv->tx_q_entries - 1); 608 } 609 610 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv) 611 { 612 return priv->tx_pointer != priv->tx_clean_pointer; 613 } 614 615 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv, 616 unsigned int pointer, 617 struct sk_buff *skb, 618 struct ftgmac100_txdes *txdes, 619 u32 ctl_stat) 620 { 621 dma_addr_t map = le32_to_cpu(txdes->txdes3); 622 size_t len; 623 624 if (ctl_stat & FTGMAC100_TXDES0_FTS) { 625 len = skb_headlen(skb); 626 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE); 627 } else { 628 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat); 629 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE); 630 } 631 632 /* Free SKB on last segment */ 633 if (ctl_stat & FTGMAC100_TXDES0_LTS) 634 dev_kfree_skb(skb); 635 priv->tx_skbs[pointer] = NULL; 636 } 637 638 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 639 { 640 struct net_device *netdev = priv->netdev; 641 struct ftgmac100_txdes *txdes; 642 struct sk_buff *skb; 643 unsigned int pointer; 644 u32 ctl_stat; 645 646 pointer = priv->tx_clean_pointer; 647 txdes = &priv->txdes[pointer]; 648 649 ctl_stat = le32_to_cpu(txdes->txdes0); 650 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN) 651 return false; 652 653 skb = priv->tx_skbs[pointer]; 654 netdev->stats.tx_packets++; 655 netdev->stats.tx_bytes += skb->len; 656 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 657 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 658 659 /* Ensure the descriptor config is visible before setting the tx 660 * pointer. 661 */ 662 smp_wmb(); 663 664 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer); 665 666 return true; 667 } 668 669 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 670 { 671 struct net_device *netdev = priv->netdev; 672 673 /* Process all completed packets */ 674 while (ftgmac100_tx_buf_cleanable(priv) && 675 ftgmac100_tx_complete_packet(priv)) 676 ; 677 678 /* Restart queue if needed */ 679 smp_mb(); 680 if (unlikely(netif_queue_stopped(netdev) && 681 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) { 682 struct netdev_queue *txq; 683 684 txq = netdev_get_tx_queue(netdev, 0); 685 __netif_tx_lock(txq, smp_processor_id()); 686 if (netif_queue_stopped(netdev) && 687 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 688 netif_wake_queue(netdev); 689 __netif_tx_unlock(txq); 690 } 691 } 692 693 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan) 694 { 695 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 696 u8 ip_proto = ip_hdr(skb)->protocol; 697 698 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM; 699 switch(ip_proto) { 700 case IPPROTO_TCP: 701 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM; 702 return true; 703 case IPPROTO_UDP: 704 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM; 705 return true; 706 case IPPROTO_IP: 707 return true; 708 } 709 } 710 return skb_checksum_help(skb) == 0; 711 } 712 713 static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb, 714 struct net_device *netdev) 715 { 716 struct ftgmac100 *priv = netdev_priv(netdev); 717 struct ftgmac100_txdes *txdes, *first; 718 unsigned int pointer, nfrags, len, i, j; 719 u32 f_ctl_stat, ctl_stat, csum_vlan; 720 dma_addr_t map; 721 722 /* The HW doesn't pad small frames */ 723 if (eth_skb_pad(skb)) { 724 netdev->stats.tx_dropped++; 725 return NETDEV_TX_OK; 726 } 727 728 /* Reject oversize packets */ 729 if (unlikely(skb->len > MAX_PKT_SIZE)) { 730 if (net_ratelimit()) 731 netdev_dbg(netdev, "tx packet too big\n"); 732 goto drop; 733 } 734 735 /* Do we have a limit on #fragments ? I yet have to get a reply 736 * from Aspeed. If there's one I haven't hit it. 737 */ 738 nfrags = skb_shinfo(skb)->nr_frags; 739 740 /* Setup HW checksumming */ 741 csum_vlan = 0; 742 if (skb->ip_summed == CHECKSUM_PARTIAL && 743 !ftgmac100_prep_tx_csum(skb, &csum_vlan)) 744 goto drop; 745 746 /* Add VLAN tag */ 747 if (skb_vlan_tag_present(skb)) { 748 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG; 749 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff; 750 } 751 752 /* Get header len */ 753 len = skb_headlen(skb); 754 755 /* Map the packet head */ 756 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 757 if (dma_mapping_error(priv->dev, map)) { 758 if (net_ratelimit()) 759 netdev_err(netdev, "map tx packet head failed\n"); 760 goto drop; 761 } 762 763 /* Grab the next free tx descriptor */ 764 pointer = priv->tx_pointer; 765 txdes = first = &priv->txdes[pointer]; 766 767 /* Setup it up with the packet head. Don't write the head to the 768 * ring just yet 769 */ 770 priv->tx_skbs[pointer] = skb; 771 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 772 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 773 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 774 f_ctl_stat |= FTGMAC100_TXDES0_FTS; 775 if (nfrags == 0) 776 f_ctl_stat |= FTGMAC100_TXDES0_LTS; 777 txdes->txdes3 = cpu_to_le32(map); 778 txdes->txdes1 = cpu_to_le32(csum_vlan); 779 780 /* Next descriptor */ 781 pointer = ftgmac100_next_tx_pointer(priv, pointer); 782 783 /* Add the fragments */ 784 for (i = 0; i < nfrags; i++) { 785 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 786 787 len = skb_frag_size(frag); 788 789 /* Map it */ 790 map = skb_frag_dma_map(priv->dev, frag, 0, len, 791 DMA_TO_DEVICE); 792 if (dma_mapping_error(priv->dev, map)) 793 goto dma_err; 794 795 /* Setup descriptor */ 796 priv->tx_skbs[pointer] = skb; 797 txdes = &priv->txdes[pointer]; 798 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 799 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 800 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 801 if (i == (nfrags - 1)) 802 ctl_stat |= FTGMAC100_TXDES0_LTS; 803 txdes->txdes0 = cpu_to_le32(ctl_stat); 804 txdes->txdes1 = 0; 805 txdes->txdes3 = cpu_to_le32(map); 806 807 /* Next one */ 808 pointer = ftgmac100_next_tx_pointer(priv, pointer); 809 } 810 811 /* Order the previous packet and descriptor udpates 812 * before setting the OWN bit on the first descriptor. 813 */ 814 dma_wmb(); 815 first->txdes0 = cpu_to_le32(f_ctl_stat); 816 817 /* Ensure the descriptor config is visible before setting the tx 818 * pointer. 819 */ 820 smp_wmb(); 821 822 /* Update next TX pointer */ 823 priv->tx_pointer = pointer; 824 825 /* If there isn't enough room for all the fragments of a new packet 826 * in the TX ring, stop the queue. The sequence below is race free 827 * vs. a concurrent restart in ftgmac100_poll() 828 */ 829 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) { 830 netif_stop_queue(netdev); 831 /* Order the queue stop with the test below */ 832 smp_mb(); 833 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 834 netif_wake_queue(netdev); 835 } 836 837 /* Poke transmitter to read the updated TX descriptors */ 838 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 839 840 return NETDEV_TX_OK; 841 842 dma_err: 843 if (net_ratelimit()) 844 netdev_err(netdev, "map tx fragment failed\n"); 845 846 /* Free head */ 847 pointer = priv->tx_pointer; 848 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat); 849 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask); 850 851 /* Then all fragments */ 852 for (j = 0; j < i; j++) { 853 pointer = ftgmac100_next_tx_pointer(priv, pointer); 854 txdes = &priv->txdes[pointer]; 855 ctl_stat = le32_to_cpu(txdes->txdes0); 856 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 857 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 858 } 859 860 /* This cannot be reached if we successfully mapped the 861 * last fragment, so we know ftgmac100_free_tx_packet() 862 * hasn't freed the skb yet. 863 */ 864 drop: 865 /* Drop the packet */ 866 dev_kfree_skb_any(skb); 867 netdev->stats.tx_dropped++; 868 869 return NETDEV_TX_OK; 870 } 871 872 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 873 { 874 int i; 875 876 /* Free all RX buffers */ 877 for (i = 0; i < priv->rx_q_entries; i++) { 878 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 879 struct sk_buff *skb = priv->rx_skbs[i]; 880 dma_addr_t map = le32_to_cpu(rxdes->rxdes3); 881 882 if (!skb) 883 continue; 884 885 priv->rx_skbs[i] = NULL; 886 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 887 dev_kfree_skb_any(skb); 888 } 889 890 /* Free all TX buffers */ 891 for (i = 0; i < priv->tx_q_entries; i++) { 892 struct ftgmac100_txdes *txdes = &priv->txdes[i]; 893 struct sk_buff *skb = priv->tx_skbs[i]; 894 895 if (!skb) 896 continue; 897 ftgmac100_free_tx_packet(priv, i, skb, txdes, 898 le32_to_cpu(txdes->txdes0)); 899 } 900 } 901 902 static void ftgmac100_free_rings(struct ftgmac100 *priv) 903 { 904 /* Free skb arrays */ 905 kfree(priv->rx_skbs); 906 kfree(priv->tx_skbs); 907 908 /* Free descriptors */ 909 if (priv->rxdes) 910 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES * 911 sizeof(struct ftgmac100_rxdes), 912 priv->rxdes, priv->rxdes_dma); 913 priv->rxdes = NULL; 914 915 if (priv->txdes) 916 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES * 917 sizeof(struct ftgmac100_txdes), 918 priv->txdes, priv->txdes_dma); 919 priv->txdes = NULL; 920 921 /* Free scratch packet buffer */ 922 if (priv->rx_scratch) 923 dma_free_coherent(priv->dev, RX_BUF_SIZE, 924 priv->rx_scratch, priv->rx_scratch_dma); 925 } 926 927 static int ftgmac100_alloc_rings(struct ftgmac100 *priv) 928 { 929 /* Allocate skb arrays */ 930 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *), 931 GFP_KERNEL); 932 if (!priv->rx_skbs) 933 return -ENOMEM; 934 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *), 935 GFP_KERNEL); 936 if (!priv->tx_skbs) 937 return -ENOMEM; 938 939 /* Allocate descriptors */ 940 priv->rxdes = dma_alloc_coherent(priv->dev, 941 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes), 942 &priv->rxdes_dma, GFP_KERNEL); 943 if (!priv->rxdes) 944 return -ENOMEM; 945 priv->txdes = dma_alloc_coherent(priv->dev, 946 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes), 947 &priv->txdes_dma, GFP_KERNEL); 948 if (!priv->txdes) 949 return -ENOMEM; 950 951 /* Allocate scratch packet buffer */ 952 priv->rx_scratch = dma_alloc_coherent(priv->dev, 953 RX_BUF_SIZE, 954 &priv->rx_scratch_dma, 955 GFP_KERNEL); 956 if (!priv->rx_scratch) 957 return -ENOMEM; 958 959 return 0; 960 } 961 962 static void ftgmac100_init_rings(struct ftgmac100 *priv) 963 { 964 struct ftgmac100_rxdes *rxdes = NULL; 965 struct ftgmac100_txdes *txdes = NULL; 966 int i; 967 968 /* Update entries counts */ 969 priv->rx_q_entries = priv->new_rx_q_entries; 970 priv->tx_q_entries = priv->new_tx_q_entries; 971 972 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES)) 973 return; 974 975 /* Initialize RX ring */ 976 for (i = 0; i < priv->rx_q_entries; i++) { 977 rxdes = &priv->rxdes[i]; 978 rxdes->rxdes0 = 0; 979 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma); 980 } 981 /* Mark the end of the ring */ 982 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); 983 984 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES)) 985 return; 986 987 /* Initialize TX ring */ 988 for (i = 0; i < priv->tx_q_entries; i++) { 989 txdes = &priv->txdes[i]; 990 txdes->txdes0 = 0; 991 } 992 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask); 993 } 994 995 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv) 996 { 997 int i; 998 999 for (i = 0; i < priv->rx_q_entries; i++) { 1000 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 1001 1002 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL)) 1003 return -ENOMEM; 1004 } 1005 return 0; 1006 } 1007 1008 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 1009 { 1010 struct net_device *netdev = bus->priv; 1011 struct ftgmac100 *priv = netdev_priv(netdev); 1012 unsigned int phycr; 1013 int i; 1014 1015 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1016 1017 /* preserve MDC cycle threshold */ 1018 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1019 1020 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1021 FTGMAC100_PHYCR_REGAD(regnum) | 1022 FTGMAC100_PHYCR_MIIRD; 1023 1024 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1025 1026 for (i = 0; i < 10; i++) { 1027 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1028 1029 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 1030 int data; 1031 1032 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 1033 return FTGMAC100_PHYDATA_MIIRDATA(data); 1034 } 1035 1036 udelay(100); 1037 } 1038 1039 netdev_err(netdev, "mdio read timed out\n"); 1040 return -EIO; 1041 } 1042 1043 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 1044 int regnum, u16 value) 1045 { 1046 struct net_device *netdev = bus->priv; 1047 struct ftgmac100 *priv = netdev_priv(netdev); 1048 unsigned int phycr; 1049 int data; 1050 int i; 1051 1052 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1053 1054 /* preserve MDC cycle threshold */ 1055 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1056 1057 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1058 FTGMAC100_PHYCR_REGAD(regnum) | 1059 FTGMAC100_PHYCR_MIIWR; 1060 1061 data = FTGMAC100_PHYDATA_MIIWDATA(value); 1062 1063 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 1064 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1065 1066 for (i = 0; i < 10; i++) { 1067 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1068 1069 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 1070 return 0; 1071 1072 udelay(100); 1073 } 1074 1075 netdev_err(netdev, "mdio write timed out\n"); 1076 return -EIO; 1077 } 1078 1079 static void ftgmac100_get_drvinfo(struct net_device *netdev, 1080 struct ethtool_drvinfo *info) 1081 { 1082 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 1083 strscpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); 1084 } 1085 1086 static void 1087 ftgmac100_get_ringparam(struct net_device *netdev, 1088 struct ethtool_ringparam *ering, 1089 struct kernel_ethtool_ringparam *kernel_ering, 1090 struct netlink_ext_ack *extack) 1091 { 1092 struct ftgmac100 *priv = netdev_priv(netdev); 1093 1094 memset(ering, 0, sizeof(*ering)); 1095 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES; 1096 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES; 1097 ering->rx_pending = priv->rx_q_entries; 1098 ering->tx_pending = priv->tx_q_entries; 1099 } 1100 1101 static int 1102 ftgmac100_set_ringparam(struct net_device *netdev, 1103 struct ethtool_ringparam *ering, 1104 struct kernel_ethtool_ringparam *kernel_ering, 1105 struct netlink_ext_ack *extack) 1106 { 1107 struct ftgmac100 *priv = netdev_priv(netdev); 1108 1109 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES || 1110 ering->tx_pending > MAX_TX_QUEUE_ENTRIES || 1111 ering->rx_pending < MIN_RX_QUEUE_ENTRIES || 1112 ering->tx_pending < MIN_TX_QUEUE_ENTRIES || 1113 !is_power_of_2(ering->rx_pending) || 1114 !is_power_of_2(ering->tx_pending)) 1115 return -EINVAL; 1116 1117 priv->new_rx_q_entries = ering->rx_pending; 1118 priv->new_tx_q_entries = ering->tx_pending; 1119 if (netif_running(netdev)) 1120 schedule_work(&priv->reset_task); 1121 1122 return 0; 1123 } 1124 1125 static void ftgmac100_get_pauseparam(struct net_device *netdev, 1126 struct ethtool_pauseparam *pause) 1127 { 1128 struct ftgmac100 *priv = netdev_priv(netdev); 1129 1130 pause->autoneg = priv->aneg_pause; 1131 pause->tx_pause = priv->tx_pause; 1132 pause->rx_pause = priv->rx_pause; 1133 } 1134 1135 static int ftgmac100_set_pauseparam(struct net_device *netdev, 1136 struct ethtool_pauseparam *pause) 1137 { 1138 struct ftgmac100 *priv = netdev_priv(netdev); 1139 struct phy_device *phydev = netdev->phydev; 1140 1141 priv->aneg_pause = pause->autoneg; 1142 priv->tx_pause = pause->tx_pause; 1143 priv->rx_pause = pause->rx_pause; 1144 1145 if (phydev) 1146 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); 1147 1148 if (netif_running(netdev)) { 1149 if (!(phydev && priv->aneg_pause)) 1150 ftgmac100_config_pause(priv); 1151 } 1152 1153 return 0; 1154 } 1155 1156 static const struct ethtool_ops ftgmac100_ethtool_ops = { 1157 .get_drvinfo = ftgmac100_get_drvinfo, 1158 .get_link = ethtool_op_get_link, 1159 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1160 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1161 .nway_reset = phy_ethtool_nway_reset, 1162 .get_ringparam = ftgmac100_get_ringparam, 1163 .set_ringparam = ftgmac100_set_ringparam, 1164 .get_pauseparam = ftgmac100_get_pauseparam, 1165 .set_pauseparam = ftgmac100_set_pauseparam, 1166 }; 1167 1168 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 1169 { 1170 struct net_device *netdev = dev_id; 1171 struct ftgmac100 *priv = netdev_priv(netdev); 1172 unsigned int status, new_mask = FTGMAC100_INT_BAD; 1173 1174 /* Fetch and clear interrupt bits, process abnormal ones */ 1175 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1176 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1177 if (unlikely(status & FTGMAC100_INT_BAD)) { 1178 1179 /* RX buffer unavailable */ 1180 if (status & FTGMAC100_INT_NO_RXBUF) 1181 netdev->stats.rx_over_errors++; 1182 1183 /* received packet lost due to RX FIFO full */ 1184 if (status & FTGMAC100_INT_RPKT_LOST) 1185 netdev->stats.rx_fifo_errors++; 1186 1187 /* sent packet lost due to excessive TX collision */ 1188 if (status & FTGMAC100_INT_XPKT_LOST) 1189 netdev->stats.tx_fifo_errors++; 1190 1191 /* AHB error -> Reset the chip */ 1192 if (status & FTGMAC100_INT_AHB_ERR) { 1193 if (net_ratelimit()) 1194 netdev_warn(netdev, 1195 "AHB bus error ! Resetting chip.\n"); 1196 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1197 schedule_work(&priv->reset_task); 1198 return IRQ_HANDLED; 1199 } 1200 1201 /* We may need to restart the MAC after such errors, delay 1202 * this until after we have freed some Rx buffers though 1203 */ 1204 priv->need_mac_restart = true; 1205 1206 /* Disable those errors until we restart */ 1207 new_mask &= ~status; 1208 } 1209 1210 /* Only enable "bad" interrupts while NAPI is on */ 1211 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER); 1212 1213 /* Schedule NAPI bh */ 1214 napi_schedule_irqoff(&priv->napi); 1215 1216 return IRQ_HANDLED; 1217 } 1218 1219 static bool ftgmac100_check_rx(struct ftgmac100 *priv) 1220 { 1221 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer]; 1222 1223 /* Do we have a packet ? */ 1224 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY)); 1225 } 1226 1227 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1228 { 1229 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1230 int work_done = 0; 1231 bool more; 1232 1233 /* Handle TX completions */ 1234 if (ftgmac100_tx_buf_cleanable(priv)) 1235 ftgmac100_tx_complete(priv); 1236 1237 /* Handle RX packets */ 1238 do { 1239 more = ftgmac100_rx_packet(priv, &work_done); 1240 } while (more && work_done < budget); 1241 1242 1243 /* The interrupt is telling us to kick the MAC back to life 1244 * after an RX overflow 1245 */ 1246 if (unlikely(priv->need_mac_restart)) { 1247 ftgmac100_start_hw(priv); 1248 priv->need_mac_restart = false; 1249 1250 /* Re-enable "bad" interrupts */ 1251 iowrite32(FTGMAC100_INT_BAD, 1252 priv->base + FTGMAC100_OFFSET_IER); 1253 } 1254 1255 /* As long as we are waiting for transmit packets to be 1256 * completed we keep NAPI going 1257 */ 1258 if (ftgmac100_tx_buf_cleanable(priv)) 1259 work_done = budget; 1260 1261 if (work_done < budget) { 1262 /* We are about to re-enable all interrupts. However 1263 * the HW has been latching RX/TX packet interrupts while 1264 * they were masked. So we clear them first, then we need 1265 * to re-check if there's something to process 1266 */ 1267 iowrite32(FTGMAC100_INT_RXTX, 1268 priv->base + FTGMAC100_OFFSET_ISR); 1269 1270 /* Push the above (and provides a barrier vs. subsequent 1271 * reads of the descriptor). 1272 */ 1273 ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1274 1275 /* Check RX and TX descriptors for more work to do */ 1276 if (ftgmac100_check_rx(priv) || 1277 ftgmac100_tx_buf_cleanable(priv)) 1278 return budget; 1279 1280 /* deschedule NAPI */ 1281 napi_complete(napi); 1282 1283 /* enable all interrupts */ 1284 iowrite32(FTGMAC100_INT_ALL, 1285 priv->base + FTGMAC100_OFFSET_IER); 1286 } 1287 1288 return work_done; 1289 } 1290 1291 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err) 1292 { 1293 int err = 0; 1294 1295 /* Re-init descriptors (adjust queue sizes) */ 1296 ftgmac100_init_rings(priv); 1297 1298 /* Realloc rx descriptors */ 1299 err = ftgmac100_alloc_rx_buffers(priv); 1300 if (err && !ignore_alloc_err) 1301 return err; 1302 1303 /* Reinit and restart HW */ 1304 ftgmac100_init_hw(priv); 1305 ftgmac100_config_pause(priv); 1306 ftgmac100_start_hw(priv); 1307 1308 /* Re-enable the device */ 1309 napi_enable(&priv->napi); 1310 netif_start_queue(priv->netdev); 1311 1312 /* Enable all interrupts */ 1313 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER); 1314 1315 return err; 1316 } 1317 1318 static void ftgmac100_reset(struct ftgmac100 *priv) 1319 { 1320 struct net_device *netdev = priv->netdev; 1321 int err; 1322 1323 netdev_dbg(netdev, "Resetting NIC...\n"); 1324 1325 /* Lock the world */ 1326 rtnl_lock(); 1327 if (netdev->phydev) 1328 mutex_lock(&netdev->phydev->lock); 1329 if (priv->mii_bus) 1330 mutex_lock(&priv->mii_bus->mdio_lock); 1331 1332 1333 /* Check if the interface is still up */ 1334 if (!netif_running(netdev)) 1335 goto bail; 1336 1337 /* Stop the network stack */ 1338 netif_trans_update(netdev); 1339 napi_disable(&priv->napi); 1340 netif_tx_disable(netdev); 1341 1342 /* Stop and reset the MAC */ 1343 ftgmac100_stop_hw(priv); 1344 err = ftgmac100_reset_and_config_mac(priv); 1345 if (err) { 1346 /* Not much we can do ... it might come back... */ 1347 netdev_err(netdev, "attempting to continue...\n"); 1348 } 1349 1350 /* Free all rx and tx buffers */ 1351 ftgmac100_free_buffers(priv); 1352 1353 /* Setup everything again and restart chip */ 1354 ftgmac100_init_all(priv, true); 1355 1356 netdev_dbg(netdev, "Reset done !\n"); 1357 bail: 1358 if (priv->mii_bus) 1359 mutex_unlock(&priv->mii_bus->mdio_lock); 1360 if (netdev->phydev) 1361 mutex_unlock(&netdev->phydev->lock); 1362 rtnl_unlock(); 1363 } 1364 1365 static void ftgmac100_reset_task(struct work_struct *work) 1366 { 1367 struct ftgmac100 *priv = container_of(work, struct ftgmac100, 1368 reset_task); 1369 1370 ftgmac100_reset(priv); 1371 } 1372 1373 static void ftgmac100_adjust_link(struct net_device *netdev) 1374 { 1375 struct ftgmac100 *priv = netdev_priv(netdev); 1376 struct phy_device *phydev = netdev->phydev; 1377 bool tx_pause, rx_pause; 1378 int new_speed; 1379 1380 /* We store "no link" as speed 0 */ 1381 if (!phydev->link) 1382 new_speed = 0; 1383 else 1384 new_speed = phydev->speed; 1385 1386 /* Grab pause settings from PHY if configured to do so */ 1387 if (priv->aneg_pause) { 1388 rx_pause = tx_pause = phydev->pause; 1389 if (phydev->asym_pause) 1390 tx_pause = !rx_pause; 1391 } else { 1392 rx_pause = priv->rx_pause; 1393 tx_pause = priv->tx_pause; 1394 } 1395 1396 /* Link hasn't changed, do nothing */ 1397 if (phydev->speed == priv->cur_speed && 1398 phydev->duplex == priv->cur_duplex && 1399 rx_pause == priv->rx_pause && 1400 tx_pause == priv->tx_pause) 1401 return; 1402 1403 /* Print status if we have a link or we had one and just lost it, 1404 * don't print otherwise. 1405 */ 1406 if (new_speed || priv->cur_speed) 1407 phy_print_status(phydev); 1408 1409 priv->cur_speed = new_speed; 1410 priv->cur_duplex = phydev->duplex; 1411 priv->rx_pause = rx_pause; 1412 priv->tx_pause = tx_pause; 1413 1414 /* Link is down, do nothing else */ 1415 if (!new_speed) 1416 return; 1417 1418 /* Disable all interrupts */ 1419 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1420 1421 /* Release phy lock to allow ftgmac100_reset to aquire it, keeping lock 1422 * order consistent to prevent dead lock. 1423 */ 1424 if (netdev->phydev) 1425 mutex_unlock(&netdev->phydev->lock); 1426 1427 ftgmac100_reset(priv); 1428 1429 if (netdev->phydev) 1430 mutex_lock(&netdev->phydev->lock); 1431 1432 } 1433 1434 static int ftgmac100_mii_probe(struct net_device *netdev) 1435 { 1436 struct ftgmac100 *priv = netdev_priv(netdev); 1437 struct platform_device *pdev = to_platform_device(priv->dev); 1438 struct device_node *np = pdev->dev.of_node; 1439 struct phy_device *phydev; 1440 phy_interface_t phy_intf; 1441 int err; 1442 1443 /* Default to RGMII. It's a gigabit part after all */ 1444 err = of_get_phy_mode(np, &phy_intf); 1445 if (err) 1446 phy_intf = PHY_INTERFACE_MODE_RGMII; 1447 1448 /* Aspeed only supports these. I don't know about other IP 1449 * block vendors so I'm going to just let them through for 1450 * now. Note that this is only a warning if for some obscure 1451 * reason the DT really means to lie about it or it's a newer 1452 * part we don't know about. 1453 * 1454 * On the Aspeed SoC there are additionally straps and SCU 1455 * control bits that could tell us what the interface is 1456 * (or allow us to configure it while the IP block is held 1457 * in reset). For now I chose to keep this driver away from 1458 * those SoC specific bits and assume the device-tree is 1459 * right and the SCU has been configured properly by pinmux 1460 * or the firmware. 1461 */ 1462 if (priv->is_aspeed && !(phy_interface_mode_is_rgmii(phy_intf))) { 1463 netdev_warn(netdev, 1464 "Unsupported PHY mode %s !\n", 1465 phy_modes(phy_intf)); 1466 } 1467 1468 phydev = phy_find_first(priv->mii_bus); 1469 if (!phydev) { 1470 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 1471 return -ENODEV; 1472 } 1473 1474 phydev = phy_connect(netdev, phydev_name(phydev), 1475 &ftgmac100_adjust_link, phy_intf); 1476 1477 if (IS_ERR(phydev)) { 1478 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 1479 return PTR_ERR(phydev); 1480 } 1481 1482 /* Indicate that we support PAUSE frames (see comment in 1483 * Documentation/networking/phy.rst) 1484 */ 1485 phy_support_asym_pause(phydev); 1486 1487 /* Display what we found */ 1488 phy_attached_info(phydev); 1489 1490 return 0; 1491 } 1492 1493 static int ftgmac100_open(struct net_device *netdev) 1494 { 1495 struct ftgmac100 *priv = netdev_priv(netdev); 1496 int err; 1497 1498 /* Allocate ring buffers */ 1499 err = ftgmac100_alloc_rings(priv); 1500 if (err) { 1501 netdev_err(netdev, "Failed to allocate descriptors\n"); 1502 return err; 1503 } 1504 1505 /* When using NC-SI we force the speed to 100Mbit/s full duplex, 1506 * 1507 * Otherwise we leave it set to 0 (no link), the link 1508 * message from the PHY layer will handle setting it up to 1509 * something else if needed. 1510 */ 1511 if (priv->use_ncsi) { 1512 priv->cur_duplex = DUPLEX_FULL; 1513 priv->cur_speed = SPEED_100; 1514 } else { 1515 priv->cur_duplex = 0; 1516 priv->cur_speed = 0; 1517 } 1518 1519 /* Reset the hardware */ 1520 err = ftgmac100_reset_and_config_mac(priv); 1521 if (err) 1522 goto err_hw; 1523 1524 /* Initialize NAPI */ 1525 netif_napi_add(netdev, &priv->napi, ftgmac100_poll); 1526 1527 /* Grab our interrupt */ 1528 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1529 if (err) { 1530 netdev_err(netdev, "failed to request irq %d\n", netdev->irq); 1531 goto err_irq; 1532 } 1533 1534 /* Start things up */ 1535 err = ftgmac100_init_all(priv, false); 1536 if (err) { 1537 netdev_err(netdev, "Failed to allocate packet buffers\n"); 1538 goto err_alloc; 1539 } 1540 1541 if (netdev->phydev) { 1542 /* If we have a PHY, start polling */ 1543 phy_start(netdev->phydev); 1544 } else if (priv->use_ncsi) { 1545 /* If using NC-SI, set our carrier on and start the stack */ 1546 netif_carrier_on(netdev); 1547 1548 /* Start the NCSI device */ 1549 err = ncsi_start_dev(priv->ndev); 1550 if (err) 1551 goto err_ncsi; 1552 } 1553 1554 return 0; 1555 1556 err_ncsi: 1557 napi_disable(&priv->napi); 1558 netif_stop_queue(netdev); 1559 err_alloc: 1560 ftgmac100_free_buffers(priv); 1561 free_irq(netdev->irq, netdev); 1562 err_irq: 1563 netif_napi_del(&priv->napi); 1564 err_hw: 1565 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1566 ftgmac100_free_rings(priv); 1567 return err; 1568 } 1569 1570 static int ftgmac100_stop(struct net_device *netdev) 1571 { 1572 struct ftgmac100 *priv = netdev_priv(netdev); 1573 1574 /* Note about the reset task: We are called with the rtnl lock 1575 * held, so we are synchronized against the core of the reset 1576 * task. We must not try to synchronously cancel it otherwise 1577 * we can deadlock. But since it will test for netif_running() 1578 * which has already been cleared by the net core, we don't 1579 * anything special to do. 1580 */ 1581 1582 /* disable all interrupts */ 1583 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1584 1585 netif_stop_queue(netdev); 1586 napi_disable(&priv->napi); 1587 netif_napi_del(&priv->napi); 1588 if (netdev->phydev) 1589 phy_stop(netdev->phydev); 1590 else if (priv->use_ncsi) 1591 ncsi_stop_dev(priv->ndev); 1592 1593 ftgmac100_stop_hw(priv); 1594 free_irq(netdev->irq, netdev); 1595 ftgmac100_free_buffers(priv); 1596 ftgmac100_free_rings(priv); 1597 1598 return 0; 1599 } 1600 1601 static void ftgmac100_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1602 { 1603 struct ftgmac100 *priv = netdev_priv(netdev); 1604 1605 /* Disable all interrupts */ 1606 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1607 1608 /* Do the reset outside of interrupt context */ 1609 schedule_work(&priv->reset_task); 1610 } 1611 1612 static int ftgmac100_set_features(struct net_device *netdev, 1613 netdev_features_t features) 1614 { 1615 struct ftgmac100 *priv = netdev_priv(netdev); 1616 netdev_features_t changed = netdev->features ^ features; 1617 1618 if (!netif_running(netdev)) 1619 return 0; 1620 1621 /* Update the vlan filtering bit */ 1622 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 1623 u32 maccr; 1624 1625 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 1626 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 1627 maccr |= FTGMAC100_MACCR_RM_VLAN; 1628 else 1629 maccr &= ~FTGMAC100_MACCR_RM_VLAN; 1630 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 1631 } 1632 1633 return 0; 1634 } 1635 1636 #ifdef CONFIG_NET_POLL_CONTROLLER 1637 static void ftgmac100_poll_controller(struct net_device *netdev) 1638 { 1639 unsigned long flags; 1640 1641 local_irq_save(flags); 1642 ftgmac100_interrupt(netdev->irq, netdev); 1643 local_irq_restore(flags); 1644 } 1645 #endif 1646 1647 static const struct net_device_ops ftgmac100_netdev_ops = { 1648 .ndo_open = ftgmac100_open, 1649 .ndo_stop = ftgmac100_stop, 1650 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1651 .ndo_set_mac_address = ftgmac100_set_mac_addr, 1652 .ndo_validate_addr = eth_validate_addr, 1653 .ndo_eth_ioctl = phy_do_ioctl, 1654 .ndo_tx_timeout = ftgmac100_tx_timeout, 1655 .ndo_set_rx_mode = ftgmac100_set_rx_mode, 1656 .ndo_set_features = ftgmac100_set_features, 1657 #ifdef CONFIG_NET_POLL_CONTROLLER 1658 .ndo_poll_controller = ftgmac100_poll_controller, 1659 #endif 1660 .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid, 1661 .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid, 1662 }; 1663 1664 static int ftgmac100_setup_mdio(struct net_device *netdev) 1665 { 1666 struct ftgmac100 *priv = netdev_priv(netdev); 1667 struct platform_device *pdev = to_platform_device(priv->dev); 1668 struct device_node *np = pdev->dev.of_node; 1669 struct device_node *mdio_np; 1670 int i, err = 0; 1671 u32 reg; 1672 1673 /* initialize mdio bus */ 1674 priv->mii_bus = mdiobus_alloc(); 1675 if (!priv->mii_bus) 1676 return -EIO; 1677 1678 if (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1679 of_device_is_compatible(np, "aspeed,ast2500-mac")) { 1680 /* The AST2600 has a separate MDIO controller */ 1681 1682 /* For the AST2400 and AST2500 this driver only supports the 1683 * old MDIO interface 1684 */ 1685 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); 1686 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; 1687 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); 1688 } 1689 1690 priv->mii_bus->name = "ftgmac100_mdio"; 1691 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1692 pdev->name, pdev->id); 1693 priv->mii_bus->parent = priv->dev; 1694 priv->mii_bus->priv = priv->netdev; 1695 priv->mii_bus->read = ftgmac100_mdiobus_read; 1696 priv->mii_bus->write = ftgmac100_mdiobus_write; 1697 1698 for (i = 0; i < PHY_MAX_ADDR; i++) 1699 priv->mii_bus->irq[i] = PHY_POLL; 1700 1701 mdio_np = of_get_child_by_name(np, "mdio"); 1702 1703 err = of_mdiobus_register(priv->mii_bus, mdio_np); 1704 if (err) { 1705 dev_err(priv->dev, "Cannot register MDIO bus!\n"); 1706 goto err_register_mdiobus; 1707 } 1708 1709 of_node_put(mdio_np); 1710 1711 return 0; 1712 1713 err_register_mdiobus: 1714 mdiobus_free(priv->mii_bus); 1715 return err; 1716 } 1717 1718 static void ftgmac100_phy_disconnect(struct net_device *netdev) 1719 { 1720 struct ftgmac100 *priv = netdev_priv(netdev); 1721 1722 if (!netdev->phydev) 1723 return; 1724 1725 phy_disconnect(netdev->phydev); 1726 if (of_phy_is_fixed_link(priv->dev->of_node)) 1727 of_phy_deregister_fixed_link(priv->dev->of_node); 1728 } 1729 1730 static void ftgmac100_destroy_mdio(struct net_device *netdev) 1731 { 1732 struct ftgmac100 *priv = netdev_priv(netdev); 1733 1734 if (!priv->mii_bus) 1735 return; 1736 1737 mdiobus_unregister(priv->mii_bus); 1738 mdiobus_free(priv->mii_bus); 1739 } 1740 1741 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) 1742 { 1743 if (unlikely(nd->state != ncsi_dev_state_functional)) 1744 return; 1745 1746 netdev_dbg(nd->dev, "NCSI interface %s\n", 1747 nd->link_up ? "up" : "down"); 1748 } 1749 1750 static int ftgmac100_setup_clk(struct ftgmac100 *priv) 1751 { 1752 struct clk *clk; 1753 int rc; 1754 1755 clk = devm_clk_get(priv->dev, NULL /* MACCLK */); 1756 if (IS_ERR(clk)) 1757 return PTR_ERR(clk); 1758 priv->clk = clk; 1759 rc = clk_prepare_enable(priv->clk); 1760 if (rc) 1761 return rc; 1762 1763 /* Aspeed specifies a 100MHz clock is required for up to 1764 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz 1765 * is sufficient 1766 */ 1767 rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ : 1768 FTGMAC_100MHZ); 1769 if (rc) 1770 goto cleanup_clk; 1771 1772 /* RCLK is for RMII, typically used for NCSI. Optional because it's not 1773 * necessary if it's the AST2400 MAC, or the MAC is configured for 1774 * RGMII, or the controller is not an ASPEED-based controller. 1775 */ 1776 priv->rclk = devm_clk_get_optional(priv->dev, "RCLK"); 1777 rc = clk_prepare_enable(priv->rclk); 1778 if (!rc) 1779 return 0; 1780 1781 cleanup_clk: 1782 clk_disable_unprepare(priv->clk); 1783 1784 return rc; 1785 } 1786 1787 static bool ftgmac100_has_child_node(struct device_node *np, const char *name) 1788 { 1789 struct device_node *child_np = of_get_child_by_name(np, name); 1790 bool ret = false; 1791 1792 if (child_np) { 1793 ret = true; 1794 of_node_put(child_np); 1795 } 1796 1797 return ret; 1798 } 1799 1800 static int ftgmac100_probe(struct platform_device *pdev) 1801 { 1802 struct resource *res; 1803 int irq; 1804 struct net_device *netdev; 1805 struct ftgmac100 *priv; 1806 struct device_node *np; 1807 int err = 0; 1808 1809 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1810 if (!res) 1811 return -ENXIO; 1812 1813 irq = platform_get_irq(pdev, 0); 1814 if (irq < 0) 1815 return irq; 1816 1817 /* setup net_device */ 1818 netdev = alloc_etherdev(sizeof(*priv)); 1819 if (!netdev) { 1820 err = -ENOMEM; 1821 goto err_alloc_etherdev; 1822 } 1823 1824 SET_NETDEV_DEV(netdev, &pdev->dev); 1825 1826 netdev->ethtool_ops = &ftgmac100_ethtool_ops; 1827 netdev->netdev_ops = &ftgmac100_netdev_ops; 1828 netdev->watchdog_timeo = 5 * HZ; 1829 1830 platform_set_drvdata(pdev, netdev); 1831 1832 /* setup private data */ 1833 priv = netdev_priv(netdev); 1834 priv->netdev = netdev; 1835 priv->dev = &pdev->dev; 1836 INIT_WORK(&priv->reset_task, ftgmac100_reset_task); 1837 1838 /* map io memory */ 1839 priv->res = request_mem_region(res->start, resource_size(res), 1840 dev_name(&pdev->dev)); 1841 if (!priv->res) { 1842 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1843 err = -ENOMEM; 1844 goto err_req_mem; 1845 } 1846 1847 priv->base = ioremap(res->start, resource_size(res)); 1848 if (!priv->base) { 1849 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1850 err = -EIO; 1851 goto err_ioremap; 1852 } 1853 1854 netdev->irq = irq; 1855 1856 /* Enable pause */ 1857 priv->tx_pause = true; 1858 priv->rx_pause = true; 1859 priv->aneg_pause = true; 1860 1861 /* MAC address from chip or random one */ 1862 err = ftgmac100_initial_mac(priv); 1863 if (err) 1864 goto err_phy_connect; 1865 1866 np = pdev->dev.of_node; 1867 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1868 of_device_is_compatible(np, "aspeed,ast2500-mac") || 1869 of_device_is_compatible(np, "aspeed,ast2600-mac"))) { 1870 priv->rxdes0_edorr_mask = BIT(30); 1871 priv->txdes0_edotr_mask = BIT(30); 1872 priv->is_aspeed = true; 1873 } else { 1874 priv->rxdes0_edorr_mask = BIT(15); 1875 priv->txdes0_edotr_mask = BIT(15); 1876 } 1877 1878 if (np && of_get_property(np, "use-ncsi", NULL)) { 1879 if (!IS_ENABLED(CONFIG_NET_NCSI)) { 1880 dev_err(&pdev->dev, "NCSI stack not enabled\n"); 1881 err = -EINVAL; 1882 goto err_phy_connect; 1883 } 1884 1885 dev_info(&pdev->dev, "Using NCSI interface\n"); 1886 priv->use_ncsi = true; 1887 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); 1888 if (!priv->ndev) { 1889 err = -EINVAL; 1890 goto err_phy_connect; 1891 } 1892 } else if (np && of_phy_is_fixed_link(np)) { 1893 struct phy_device *phy; 1894 1895 err = of_phy_register_fixed_link(np); 1896 if (err) { 1897 dev_err(&pdev->dev, "Failed to register fixed PHY\n"); 1898 goto err_phy_connect; 1899 } 1900 1901 phy = of_phy_get_and_connect(priv->netdev, np, 1902 &ftgmac100_adjust_link); 1903 if (!phy) { 1904 dev_err(&pdev->dev, "Failed to connect to fixed PHY\n"); 1905 of_phy_deregister_fixed_link(np); 1906 err = -EINVAL; 1907 goto err_phy_connect; 1908 } 1909 1910 /* Display what we found */ 1911 phy_attached_info(phy); 1912 } else if (np && of_get_property(np, "phy-handle", NULL)) { 1913 struct phy_device *phy; 1914 1915 /* Support "mdio"/"phy" child nodes for ast2400/2500 with 1916 * an embedded MDIO controller. Automatically scan the DTS for 1917 * available PHYs and register them. 1918 */ 1919 if (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1920 of_device_is_compatible(np, "aspeed,ast2500-mac")) { 1921 err = ftgmac100_setup_mdio(netdev); 1922 if (err) 1923 goto err_setup_mdio; 1924 } 1925 1926 phy = of_phy_get_and_connect(priv->netdev, np, 1927 &ftgmac100_adjust_link); 1928 if (!phy) { 1929 dev_err(&pdev->dev, "Failed to connect to phy\n"); 1930 err = -EINVAL; 1931 goto err_phy_connect; 1932 } 1933 1934 /* Indicate that we support PAUSE frames (see comment in 1935 * Documentation/networking/phy.rst) 1936 */ 1937 phy_support_asym_pause(phy); 1938 1939 /* Display what we found */ 1940 phy_attached_info(phy); 1941 } else if (np && !ftgmac100_has_child_node(np, "mdio")) { 1942 /* Support legacy ASPEED devicetree descriptions that decribe a 1943 * MAC with an embedded MDIO controller but have no "mdio" 1944 * child node. Automatically scan the MDIO bus for available 1945 * PHYs. 1946 */ 1947 priv->use_ncsi = false; 1948 err = ftgmac100_setup_mdio(netdev); 1949 if (err) 1950 goto err_setup_mdio; 1951 1952 err = ftgmac100_mii_probe(netdev); 1953 if (err) { 1954 dev_err(priv->dev, "MII probe failed!\n"); 1955 goto err_ncsi_dev; 1956 } 1957 1958 } 1959 1960 if (priv->is_aspeed) { 1961 err = ftgmac100_setup_clk(priv); 1962 if (err) 1963 goto err_phy_connect; 1964 1965 /* Disable ast2600 problematic HW arbitration */ 1966 if (of_device_is_compatible(np, "aspeed,ast2600-mac")) 1967 iowrite32(FTGMAC100_TM_DEFAULT, 1968 priv->base + FTGMAC100_OFFSET_TM); 1969 } 1970 1971 /* Default ring sizes */ 1972 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES; 1973 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES; 1974 1975 /* Base feature set */ 1976 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM | 1977 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX | 1978 NETIF_F_HW_VLAN_CTAG_TX; 1979 1980 if (priv->use_ncsi) 1981 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1982 1983 /* AST2400 doesn't have working HW checksum generation */ 1984 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac"))) 1985 netdev->hw_features &= ~NETIF_F_HW_CSUM; 1986 1987 /* AST2600 tx checksum with NCSI is broken */ 1988 if (priv->use_ncsi && of_device_is_compatible(np, "aspeed,ast2600-mac")) 1989 netdev->hw_features &= ~NETIF_F_HW_CSUM; 1990 1991 if (np && of_get_property(np, "no-hw-checksum", NULL)) 1992 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM); 1993 netdev->features |= netdev->hw_features; 1994 1995 /* register network device */ 1996 err = register_netdev(netdev); 1997 if (err) { 1998 dev_err(&pdev->dev, "Failed to register netdev\n"); 1999 goto err_register_netdev; 2000 } 2001 2002 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base); 2003 2004 return 0; 2005 2006 err_register_netdev: 2007 clk_disable_unprepare(priv->rclk); 2008 clk_disable_unprepare(priv->clk); 2009 err_phy_connect: 2010 ftgmac100_phy_disconnect(netdev); 2011 err_ncsi_dev: 2012 if (priv->ndev) 2013 ncsi_unregister_dev(priv->ndev); 2014 ftgmac100_destroy_mdio(netdev); 2015 err_setup_mdio: 2016 iounmap(priv->base); 2017 err_ioremap: 2018 release_resource(priv->res); 2019 err_req_mem: 2020 free_netdev(netdev); 2021 err_alloc_etherdev: 2022 return err; 2023 } 2024 2025 static int ftgmac100_remove(struct platform_device *pdev) 2026 { 2027 struct net_device *netdev; 2028 struct ftgmac100 *priv; 2029 2030 netdev = platform_get_drvdata(pdev); 2031 priv = netdev_priv(netdev); 2032 2033 if (priv->ndev) 2034 ncsi_unregister_dev(priv->ndev); 2035 unregister_netdev(netdev); 2036 2037 clk_disable_unprepare(priv->rclk); 2038 clk_disable_unprepare(priv->clk); 2039 2040 /* There's a small chance the reset task will have been re-queued, 2041 * during stop, make sure it's gone before we free the structure. 2042 */ 2043 cancel_work_sync(&priv->reset_task); 2044 2045 ftgmac100_phy_disconnect(netdev); 2046 ftgmac100_destroy_mdio(netdev); 2047 2048 iounmap(priv->base); 2049 release_resource(priv->res); 2050 2051 netif_napi_del(&priv->napi); 2052 free_netdev(netdev); 2053 return 0; 2054 } 2055 2056 static const struct of_device_id ftgmac100_of_match[] = { 2057 { .compatible = "faraday,ftgmac100" }, 2058 { } 2059 }; 2060 MODULE_DEVICE_TABLE(of, ftgmac100_of_match); 2061 2062 static struct platform_driver ftgmac100_driver = { 2063 .probe = ftgmac100_probe, 2064 .remove = ftgmac100_remove, 2065 .driver = { 2066 .name = DRV_NAME, 2067 .of_match_table = ftgmac100_of_match, 2068 }, 2069 }; 2070 module_platform_driver(ftgmac100_driver); 2071 2072 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 2073 MODULE_DESCRIPTION("FTGMAC100 driver"); 2074 MODULE_LICENSE("GPL"); 2075