1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Faraday FTGMAC100 Gigabit Ethernet 4 * 5 * (C) Copyright 2009-2011 Faraday Technology 6 * Po-Yu Chuang <ratbert@faraday-tech.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/netdevice.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/property.h> 24 #include <linux/crc32.h> 25 #include <linux/if_vlan.h> 26 #include <linux/of_net.h> 27 #include <net/ip.h> 28 #include <net/ncsi.h> 29 30 #include "ftgmac100.h" 31 32 #define DRV_NAME "ftgmac100" 33 #define DRV_VERSION "0.7" 34 35 /* Arbitrary values, I am not sure the HW has limits */ 36 #define MAX_RX_QUEUE_ENTRIES 1024 37 #define MAX_TX_QUEUE_ENTRIES 1024 38 #define MIN_RX_QUEUE_ENTRIES 32 39 #define MIN_TX_QUEUE_ENTRIES 32 40 41 /* Defaults */ 42 #define DEF_RX_QUEUE_ENTRIES 128 43 #define DEF_TX_QUEUE_ENTRIES 128 44 45 #define MAX_PKT_SIZE 1536 46 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */ 47 48 /* Min number of tx ring entries before stopping queue */ 49 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1) 50 51 #define FTGMAC_100MHZ 100000000 52 #define FTGMAC_25MHZ 25000000 53 54 struct ftgmac100 { 55 /* Registers */ 56 struct resource *res; 57 void __iomem *base; 58 59 /* Rx ring */ 60 unsigned int rx_q_entries; 61 struct ftgmac100_rxdes *rxdes; 62 dma_addr_t rxdes_dma; 63 struct sk_buff **rx_skbs; 64 unsigned int rx_pointer; 65 u32 rxdes0_edorr_mask; 66 67 /* Tx ring */ 68 unsigned int tx_q_entries; 69 struct ftgmac100_txdes *txdes; 70 dma_addr_t txdes_dma; 71 struct sk_buff **tx_skbs; 72 unsigned int tx_clean_pointer; 73 unsigned int tx_pointer; 74 u32 txdes0_edotr_mask; 75 76 /* Used to signal the reset task of ring change request */ 77 unsigned int new_rx_q_entries; 78 unsigned int new_tx_q_entries; 79 80 /* Scratch page to use when rx skb alloc fails */ 81 void *rx_scratch; 82 dma_addr_t rx_scratch_dma; 83 84 /* Component structures */ 85 struct net_device *netdev; 86 struct device *dev; 87 struct ncsi_dev *ndev; 88 struct napi_struct napi; 89 struct work_struct reset_task; 90 struct mii_bus *mii_bus; 91 struct clk *clk; 92 93 /* AST2500/AST2600 RMII ref clock gate */ 94 struct clk *rclk; 95 96 /* Link management */ 97 int cur_speed; 98 int cur_duplex; 99 bool use_ncsi; 100 101 /* Multicast filter settings */ 102 u32 maht0; 103 u32 maht1; 104 105 /* Flow control settings */ 106 bool tx_pause; 107 bool rx_pause; 108 bool aneg_pause; 109 110 /* Misc */ 111 bool need_mac_restart; 112 bool is_aspeed; 113 }; 114 115 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr) 116 { 117 struct net_device *netdev = priv->netdev; 118 int i; 119 120 /* NOTE: reset clears all registers */ 121 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 122 iowrite32(maccr | FTGMAC100_MACCR_SW_RST, 123 priv->base + FTGMAC100_OFFSET_MACCR); 124 for (i = 0; i < 200; i++) { 125 unsigned int maccr; 126 127 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 128 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 129 return 0; 130 131 udelay(1); 132 } 133 134 netdev_err(netdev, "Hardware reset failed\n"); 135 return -EIO; 136 } 137 138 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) 139 { 140 u32 maccr = 0; 141 142 switch (priv->cur_speed) { 143 case SPEED_10: 144 case 0: /* no link */ 145 break; 146 147 case SPEED_100: 148 maccr |= FTGMAC100_MACCR_FAST_MODE; 149 break; 150 151 case SPEED_1000: 152 maccr |= FTGMAC100_MACCR_GIGA_MODE; 153 break; 154 default: 155 netdev_err(priv->netdev, "Unknown speed %d !\n", 156 priv->cur_speed); 157 break; 158 } 159 160 /* (Re)initialize the queue pointers */ 161 priv->rx_pointer = 0; 162 priv->tx_clean_pointer = 0; 163 priv->tx_pointer = 0; 164 165 /* The doc says reset twice with 10us interval */ 166 if (ftgmac100_reset_mac(priv, maccr)) 167 return -EIO; 168 usleep_range(10, 1000); 169 return ftgmac100_reset_mac(priv, maccr); 170 } 171 172 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac) 173 { 174 unsigned int maddr = mac[0] << 8 | mac[1]; 175 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 176 177 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 178 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 179 } 180 181 static void ftgmac100_initial_mac(struct ftgmac100 *priv) 182 { 183 u8 mac[ETH_ALEN]; 184 unsigned int m; 185 unsigned int l; 186 void *addr; 187 188 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN); 189 if (addr) { 190 ether_addr_copy(priv->netdev->dev_addr, mac); 191 dev_info(priv->dev, "Read MAC address %pM from device tree\n", 192 mac); 193 return; 194 } 195 196 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); 197 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); 198 199 mac[0] = (m >> 8) & 0xff; 200 mac[1] = m & 0xff; 201 mac[2] = (l >> 24) & 0xff; 202 mac[3] = (l >> 16) & 0xff; 203 mac[4] = (l >> 8) & 0xff; 204 mac[5] = l & 0xff; 205 206 if (is_valid_ether_addr(mac)) { 207 ether_addr_copy(priv->netdev->dev_addr, mac); 208 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac); 209 } else { 210 eth_hw_addr_random(priv->netdev); 211 dev_info(priv->dev, "Generated random MAC address %pM\n", 212 priv->netdev->dev_addr); 213 } 214 } 215 216 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p) 217 { 218 int ret; 219 220 ret = eth_prepare_mac_addr_change(dev, p); 221 if (ret < 0) 222 return ret; 223 224 eth_commit_mac_addr_change(dev, p); 225 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr); 226 227 return 0; 228 } 229 230 static void ftgmac100_config_pause(struct ftgmac100 *priv) 231 { 232 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16); 233 234 /* Throttle tx queue when receiving pause frames */ 235 if (priv->rx_pause) 236 fcr |= FTGMAC100_FCR_FC_EN; 237 238 /* Enables sending pause frames when the RX queue is past a 239 * certain threshold. 240 */ 241 if (priv->tx_pause) 242 fcr |= FTGMAC100_FCR_FCTHR_EN; 243 244 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR); 245 } 246 247 static void ftgmac100_init_hw(struct ftgmac100 *priv) 248 { 249 u32 reg, rfifo_sz, tfifo_sz; 250 251 /* Clear stale interrupts */ 252 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 253 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); 254 255 /* Setup RX ring buffer base */ 256 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR); 257 258 /* Setup TX ring buffer base */ 259 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 260 261 /* Configure RX buffer size */ 262 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE), 263 priv->base + FTGMAC100_OFFSET_RBSR); 264 265 /* Set RX descriptor autopoll */ 266 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), 267 priv->base + FTGMAC100_OFFSET_APTC); 268 269 /* Write MAC address */ 270 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr); 271 272 /* Write multicast filter */ 273 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 274 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 275 276 /* Configure descriptor sizes and increase burst sizes according 277 * to values in Aspeed SDK. The FIFO arbitration is enabled and 278 * the thresholds set based on the recommended values in the 279 * AST2400 specification. 280 */ 281 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */ 282 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */ 283 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */ 284 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */ 285 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */ 286 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */ 287 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */ 288 priv->base + FTGMAC100_OFFSET_DBLAC); 289 290 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt 291 * mitigation doesn't seem to provide any benefit with NAPI so leave 292 * it at that. 293 */ 294 iowrite32(FTGMAC100_ITC_RXINT_THR(1) | 295 FTGMAC100_ITC_TXINT_THR(1), 296 priv->base + FTGMAC100_OFFSET_ITC); 297 298 /* Configure FIFO sizes in the TPAFCR register */ 299 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); 300 rfifo_sz = reg & 0x00000007; 301 tfifo_sz = (reg >> 3) & 0x00000007; 302 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); 303 reg &= ~0x3f000000; 304 reg |= (tfifo_sz << 27); 305 reg |= (rfifo_sz << 24); 306 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); 307 } 308 309 static void ftgmac100_start_hw(struct ftgmac100 *priv) 310 { 311 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 312 313 /* Keep the original GMAC and FAST bits */ 314 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE); 315 316 /* Add all the main enable bits */ 317 maccr |= FTGMAC100_MACCR_TXDMA_EN | 318 FTGMAC100_MACCR_RXDMA_EN | 319 FTGMAC100_MACCR_TXMAC_EN | 320 FTGMAC100_MACCR_RXMAC_EN | 321 FTGMAC100_MACCR_CRC_APD | 322 FTGMAC100_MACCR_PHY_LINK_LEVEL | 323 FTGMAC100_MACCR_RX_RUNT | 324 FTGMAC100_MACCR_RX_BROADPKT; 325 326 /* Add other bits as needed */ 327 if (priv->cur_duplex == DUPLEX_FULL) 328 maccr |= FTGMAC100_MACCR_FULLDUP; 329 if (priv->netdev->flags & IFF_PROMISC) 330 maccr |= FTGMAC100_MACCR_RX_ALL; 331 if (priv->netdev->flags & IFF_ALLMULTI) 332 maccr |= FTGMAC100_MACCR_RX_MULTIPKT; 333 else if (netdev_mc_count(priv->netdev)) 334 maccr |= FTGMAC100_MACCR_HT_MULTI_EN; 335 336 /* Vlan filtering enabled */ 337 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 338 maccr |= FTGMAC100_MACCR_RM_VLAN; 339 340 /* Hit the HW */ 341 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 342 } 343 344 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 345 { 346 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 347 } 348 349 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv) 350 { 351 struct netdev_hw_addr *ha; 352 353 priv->maht1 = 0; 354 priv->maht0 = 0; 355 netdev_for_each_mc_addr(ha, priv->netdev) { 356 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr); 357 358 crc_val = (~(crc_val >> 2)) & 0x3f; 359 if (crc_val >= 32) 360 priv->maht1 |= 1ul << (crc_val - 32); 361 else 362 priv->maht0 |= 1ul << (crc_val); 363 } 364 } 365 366 static void ftgmac100_set_rx_mode(struct net_device *netdev) 367 { 368 struct ftgmac100 *priv = netdev_priv(netdev); 369 370 /* Setup the hash filter */ 371 ftgmac100_calc_mc_hash(priv); 372 373 /* Interface down ? that's all there is to do */ 374 if (!netif_running(netdev)) 375 return; 376 377 /* Update the HW */ 378 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 379 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 380 381 /* Reconfigure MACCR */ 382 ftgmac100_start_hw(priv); 383 } 384 385 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry, 386 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 387 { 388 struct net_device *netdev = priv->netdev; 389 struct sk_buff *skb; 390 dma_addr_t map; 391 int err = 0; 392 393 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE); 394 if (unlikely(!skb)) { 395 if (net_ratelimit()) 396 netdev_warn(netdev, "failed to allocate rx skb\n"); 397 err = -ENOMEM; 398 map = priv->rx_scratch_dma; 399 } else { 400 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE, 401 DMA_FROM_DEVICE); 402 if (unlikely(dma_mapping_error(priv->dev, map))) { 403 if (net_ratelimit()) 404 netdev_err(netdev, "failed to map rx page\n"); 405 dev_kfree_skb_any(skb); 406 map = priv->rx_scratch_dma; 407 skb = NULL; 408 err = -ENOMEM; 409 } 410 } 411 412 /* Store skb */ 413 priv->rx_skbs[entry] = skb; 414 415 /* Store DMA address into RX desc */ 416 rxdes->rxdes3 = cpu_to_le32(map); 417 418 /* Ensure the above is ordered vs clearing the OWN bit */ 419 dma_wmb(); 420 421 /* Clean status (which resets own bit) */ 422 if (entry == (priv->rx_q_entries - 1)) 423 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask); 424 else 425 rxdes->rxdes0 = 0; 426 427 return err; 428 } 429 430 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv, 431 unsigned int pointer) 432 { 433 return (pointer + 1) & (priv->rx_q_entries - 1); 434 } 435 436 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status) 437 { 438 struct net_device *netdev = priv->netdev; 439 440 if (status & FTGMAC100_RXDES0_RX_ERR) 441 netdev->stats.rx_errors++; 442 443 if (status & FTGMAC100_RXDES0_CRC_ERR) 444 netdev->stats.rx_crc_errors++; 445 446 if (status & (FTGMAC100_RXDES0_FTL | 447 FTGMAC100_RXDES0_RUNT | 448 FTGMAC100_RXDES0_RX_ODD_NB)) 449 netdev->stats.rx_length_errors++; 450 } 451 452 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 453 { 454 struct net_device *netdev = priv->netdev; 455 struct ftgmac100_rxdes *rxdes; 456 struct sk_buff *skb; 457 unsigned int pointer, size; 458 u32 status, csum_vlan; 459 dma_addr_t map; 460 461 /* Grab next RX descriptor */ 462 pointer = priv->rx_pointer; 463 rxdes = &priv->rxdes[pointer]; 464 465 /* Grab descriptor status */ 466 status = le32_to_cpu(rxdes->rxdes0); 467 468 /* Do we have a packet ? */ 469 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY)) 470 return false; 471 472 /* Order subsequent reads with the test for the ready bit */ 473 dma_rmb(); 474 475 /* We don't cope with fragmented RX packets */ 476 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) || 477 !(status & FTGMAC100_RXDES0_LRS))) 478 goto drop; 479 480 /* Grab received size and csum vlan field in the descriptor */ 481 size = status & FTGMAC100_RXDES0_VDBC; 482 csum_vlan = le32_to_cpu(rxdes->rxdes1); 483 484 /* Any error (other than csum offload) flagged ? */ 485 if (unlikely(status & RXDES0_ANY_ERROR)) { 486 /* Correct for incorrect flagging of runt packets 487 * with vlan tags... Just accept a runt packet that 488 * has been flagged as vlan and whose size is at 489 * least 60 bytes. 490 */ 491 if ((status & FTGMAC100_RXDES0_RUNT) && 492 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) && 493 (size >= 60)) 494 status &= ~FTGMAC100_RXDES0_RUNT; 495 496 /* Any error still in there ? */ 497 if (status & RXDES0_ANY_ERROR) { 498 ftgmac100_rx_packet_error(priv, status); 499 goto drop; 500 } 501 } 502 503 /* If the packet had no skb (failed to allocate earlier) 504 * then try to allocate one and skip 505 */ 506 skb = priv->rx_skbs[pointer]; 507 if (!unlikely(skb)) { 508 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 509 goto drop; 510 } 511 512 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST)) 513 netdev->stats.multicast++; 514 515 /* If the HW found checksum errors, bounce it to software. 516 * 517 * If we didn't, we need to see if the packet was recognized 518 * by HW as one of the supported checksummed protocols before 519 * we accept the HW test results. 520 */ 521 if (netdev->features & NETIF_F_RXCSUM) { 522 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR | 523 FTGMAC100_RXDES1_UDP_CHKSUM_ERR | 524 FTGMAC100_RXDES1_IP_CHKSUM_ERR; 525 if ((csum_vlan & err_bits) || 526 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK)) 527 skb->ip_summed = CHECKSUM_NONE; 528 else 529 skb->ip_summed = CHECKSUM_UNNECESSARY; 530 } 531 532 /* Transfer received size to skb */ 533 skb_put(skb, size); 534 535 /* Extract vlan tag */ 536 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 537 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL)) 538 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 539 csum_vlan & 0xffff); 540 541 /* Tear down DMA mapping, do necessary cache management */ 542 map = le32_to_cpu(rxdes->rxdes3); 543 544 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU) 545 /* When we don't have an iommu, we can save cycles by not 546 * invalidating the cache for the part of the packet that 547 * wasn't received. 548 */ 549 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE); 550 #else 551 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 552 #endif 553 554 555 /* Resplenish rx ring */ 556 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 557 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 558 559 skb->protocol = eth_type_trans(skb, netdev); 560 561 netdev->stats.rx_packets++; 562 netdev->stats.rx_bytes += size; 563 564 /* push packet to protocol stack */ 565 if (skb->ip_summed == CHECKSUM_NONE) 566 netif_receive_skb(skb); 567 else 568 napi_gro_receive(&priv->napi, skb); 569 570 (*processed)++; 571 return true; 572 573 drop: 574 /* Clean rxdes0 (which resets own bit) */ 575 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask); 576 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 577 netdev->stats.rx_dropped++; 578 return true; 579 } 580 581 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv, 582 unsigned int index) 583 { 584 if (index == (priv->tx_q_entries - 1)) 585 return priv->txdes0_edotr_mask; 586 else 587 return 0; 588 } 589 590 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv, 591 unsigned int pointer) 592 { 593 return (pointer + 1) & (priv->tx_q_entries - 1); 594 } 595 596 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv) 597 { 598 /* Returns the number of available slots in the TX queue 599 * 600 * This always leaves one free slot so we don't have to 601 * worry about empty vs. full, and this simplifies the 602 * test for ftgmac100_tx_buf_cleanable() below 603 */ 604 return (priv->tx_clean_pointer - priv->tx_pointer - 1) & 605 (priv->tx_q_entries - 1); 606 } 607 608 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv) 609 { 610 return priv->tx_pointer != priv->tx_clean_pointer; 611 } 612 613 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv, 614 unsigned int pointer, 615 struct sk_buff *skb, 616 struct ftgmac100_txdes *txdes, 617 u32 ctl_stat) 618 { 619 dma_addr_t map = le32_to_cpu(txdes->txdes3); 620 size_t len; 621 622 if (ctl_stat & FTGMAC100_TXDES0_FTS) { 623 len = skb_headlen(skb); 624 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE); 625 } else { 626 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat); 627 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE); 628 } 629 630 /* Free SKB on last segment */ 631 if (ctl_stat & FTGMAC100_TXDES0_LTS) 632 dev_kfree_skb(skb); 633 priv->tx_skbs[pointer] = NULL; 634 } 635 636 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 637 { 638 struct net_device *netdev = priv->netdev; 639 struct ftgmac100_txdes *txdes; 640 struct sk_buff *skb; 641 unsigned int pointer; 642 u32 ctl_stat; 643 644 pointer = priv->tx_clean_pointer; 645 txdes = &priv->txdes[pointer]; 646 647 ctl_stat = le32_to_cpu(txdes->txdes0); 648 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN) 649 return false; 650 651 skb = priv->tx_skbs[pointer]; 652 netdev->stats.tx_packets++; 653 netdev->stats.tx_bytes += skb->len; 654 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 655 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 656 657 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer); 658 659 return true; 660 } 661 662 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 663 { 664 struct net_device *netdev = priv->netdev; 665 666 /* Process all completed packets */ 667 while (ftgmac100_tx_buf_cleanable(priv) && 668 ftgmac100_tx_complete_packet(priv)) 669 ; 670 671 /* Restart queue if needed */ 672 smp_mb(); 673 if (unlikely(netif_queue_stopped(netdev) && 674 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) { 675 struct netdev_queue *txq; 676 677 txq = netdev_get_tx_queue(netdev, 0); 678 __netif_tx_lock(txq, smp_processor_id()); 679 if (netif_queue_stopped(netdev) && 680 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 681 netif_wake_queue(netdev); 682 __netif_tx_unlock(txq); 683 } 684 } 685 686 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan) 687 { 688 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 689 u8 ip_proto = ip_hdr(skb)->protocol; 690 691 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM; 692 switch(ip_proto) { 693 case IPPROTO_TCP: 694 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM; 695 return true; 696 case IPPROTO_UDP: 697 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM; 698 return true; 699 case IPPROTO_IP: 700 return true; 701 } 702 } 703 return skb_checksum_help(skb) == 0; 704 } 705 706 static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb, 707 struct net_device *netdev) 708 { 709 struct ftgmac100 *priv = netdev_priv(netdev); 710 struct ftgmac100_txdes *txdes, *first; 711 unsigned int pointer, nfrags, len, i, j; 712 u32 f_ctl_stat, ctl_stat, csum_vlan; 713 dma_addr_t map; 714 715 /* The HW doesn't pad small frames */ 716 if (eth_skb_pad(skb)) { 717 netdev->stats.tx_dropped++; 718 return NETDEV_TX_OK; 719 } 720 721 /* Reject oversize packets */ 722 if (unlikely(skb->len > MAX_PKT_SIZE)) { 723 if (net_ratelimit()) 724 netdev_dbg(netdev, "tx packet too big\n"); 725 goto drop; 726 } 727 728 /* Do we have a limit on #fragments ? I yet have to get a reply 729 * from Aspeed. If there's one I haven't hit it. 730 */ 731 nfrags = skb_shinfo(skb)->nr_frags; 732 733 /* Get header len */ 734 len = skb_headlen(skb); 735 736 /* Map the packet head */ 737 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 738 if (dma_mapping_error(priv->dev, map)) { 739 if (net_ratelimit()) 740 netdev_err(netdev, "map tx packet head failed\n"); 741 goto drop; 742 } 743 744 /* Grab the next free tx descriptor */ 745 pointer = priv->tx_pointer; 746 txdes = first = &priv->txdes[pointer]; 747 748 /* Setup it up with the packet head. Don't write the head to the 749 * ring just yet 750 */ 751 priv->tx_skbs[pointer] = skb; 752 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 753 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 754 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 755 f_ctl_stat |= FTGMAC100_TXDES0_FTS; 756 if (nfrags == 0) 757 f_ctl_stat |= FTGMAC100_TXDES0_LTS; 758 txdes->txdes3 = cpu_to_le32(map); 759 760 /* Setup HW checksumming */ 761 csum_vlan = 0; 762 if (skb->ip_summed == CHECKSUM_PARTIAL && 763 !ftgmac100_prep_tx_csum(skb, &csum_vlan)) 764 goto drop; 765 766 /* Add VLAN tag */ 767 if (skb_vlan_tag_present(skb)) { 768 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG; 769 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff; 770 } 771 772 txdes->txdes1 = cpu_to_le32(csum_vlan); 773 774 /* Next descriptor */ 775 pointer = ftgmac100_next_tx_pointer(priv, pointer); 776 777 /* Add the fragments */ 778 for (i = 0; i < nfrags; i++) { 779 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 780 781 len = skb_frag_size(frag); 782 783 /* Map it */ 784 map = skb_frag_dma_map(priv->dev, frag, 0, len, 785 DMA_TO_DEVICE); 786 if (dma_mapping_error(priv->dev, map)) 787 goto dma_err; 788 789 /* Setup descriptor */ 790 priv->tx_skbs[pointer] = skb; 791 txdes = &priv->txdes[pointer]; 792 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 793 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 794 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 795 if (i == (nfrags - 1)) 796 ctl_stat |= FTGMAC100_TXDES0_LTS; 797 txdes->txdes0 = cpu_to_le32(ctl_stat); 798 txdes->txdes1 = 0; 799 txdes->txdes3 = cpu_to_le32(map); 800 801 /* Next one */ 802 pointer = ftgmac100_next_tx_pointer(priv, pointer); 803 } 804 805 /* Order the previous packet and descriptor udpates 806 * before setting the OWN bit on the first descriptor. 807 */ 808 dma_wmb(); 809 first->txdes0 = cpu_to_le32(f_ctl_stat); 810 811 /* Update next TX pointer */ 812 priv->tx_pointer = pointer; 813 814 /* If there isn't enough room for all the fragments of a new packet 815 * in the TX ring, stop the queue. The sequence below is race free 816 * vs. a concurrent restart in ftgmac100_poll() 817 */ 818 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) { 819 netif_stop_queue(netdev); 820 /* Order the queue stop with the test below */ 821 smp_mb(); 822 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 823 netif_wake_queue(netdev); 824 } 825 826 /* Poke transmitter to read the updated TX descriptors */ 827 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 828 829 return NETDEV_TX_OK; 830 831 dma_err: 832 if (net_ratelimit()) 833 netdev_err(netdev, "map tx fragment failed\n"); 834 835 /* Free head */ 836 pointer = priv->tx_pointer; 837 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat); 838 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask); 839 840 /* Then all fragments */ 841 for (j = 0; j < i; j++) { 842 pointer = ftgmac100_next_tx_pointer(priv, pointer); 843 txdes = &priv->txdes[pointer]; 844 ctl_stat = le32_to_cpu(txdes->txdes0); 845 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 846 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 847 } 848 849 /* This cannot be reached if we successfully mapped the 850 * last fragment, so we know ftgmac100_free_tx_packet() 851 * hasn't freed the skb yet. 852 */ 853 drop: 854 /* Drop the packet */ 855 dev_kfree_skb_any(skb); 856 netdev->stats.tx_dropped++; 857 858 return NETDEV_TX_OK; 859 } 860 861 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 862 { 863 int i; 864 865 /* Free all RX buffers */ 866 for (i = 0; i < priv->rx_q_entries; i++) { 867 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 868 struct sk_buff *skb = priv->rx_skbs[i]; 869 dma_addr_t map = le32_to_cpu(rxdes->rxdes3); 870 871 if (!skb) 872 continue; 873 874 priv->rx_skbs[i] = NULL; 875 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 876 dev_kfree_skb_any(skb); 877 } 878 879 /* Free all TX buffers */ 880 for (i = 0; i < priv->tx_q_entries; i++) { 881 struct ftgmac100_txdes *txdes = &priv->txdes[i]; 882 struct sk_buff *skb = priv->tx_skbs[i]; 883 884 if (!skb) 885 continue; 886 ftgmac100_free_tx_packet(priv, i, skb, txdes, 887 le32_to_cpu(txdes->txdes0)); 888 } 889 } 890 891 static void ftgmac100_free_rings(struct ftgmac100 *priv) 892 { 893 /* Free skb arrays */ 894 kfree(priv->rx_skbs); 895 kfree(priv->tx_skbs); 896 897 /* Free descriptors */ 898 if (priv->rxdes) 899 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES * 900 sizeof(struct ftgmac100_rxdes), 901 priv->rxdes, priv->rxdes_dma); 902 priv->rxdes = NULL; 903 904 if (priv->txdes) 905 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES * 906 sizeof(struct ftgmac100_txdes), 907 priv->txdes, priv->txdes_dma); 908 priv->txdes = NULL; 909 910 /* Free scratch packet buffer */ 911 if (priv->rx_scratch) 912 dma_free_coherent(priv->dev, RX_BUF_SIZE, 913 priv->rx_scratch, priv->rx_scratch_dma); 914 } 915 916 static int ftgmac100_alloc_rings(struct ftgmac100 *priv) 917 { 918 /* Allocate skb arrays */ 919 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *), 920 GFP_KERNEL); 921 if (!priv->rx_skbs) 922 return -ENOMEM; 923 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *), 924 GFP_KERNEL); 925 if (!priv->tx_skbs) 926 return -ENOMEM; 927 928 /* Allocate descriptors */ 929 priv->rxdes = dma_alloc_coherent(priv->dev, 930 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes), 931 &priv->rxdes_dma, GFP_KERNEL); 932 if (!priv->rxdes) 933 return -ENOMEM; 934 priv->txdes = dma_alloc_coherent(priv->dev, 935 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes), 936 &priv->txdes_dma, GFP_KERNEL); 937 if (!priv->txdes) 938 return -ENOMEM; 939 940 /* Allocate scratch packet buffer */ 941 priv->rx_scratch = dma_alloc_coherent(priv->dev, 942 RX_BUF_SIZE, 943 &priv->rx_scratch_dma, 944 GFP_KERNEL); 945 if (!priv->rx_scratch) 946 return -ENOMEM; 947 948 return 0; 949 } 950 951 static void ftgmac100_init_rings(struct ftgmac100 *priv) 952 { 953 struct ftgmac100_rxdes *rxdes = NULL; 954 struct ftgmac100_txdes *txdes = NULL; 955 int i; 956 957 /* Update entries counts */ 958 priv->rx_q_entries = priv->new_rx_q_entries; 959 priv->tx_q_entries = priv->new_tx_q_entries; 960 961 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES)) 962 return; 963 964 /* Initialize RX ring */ 965 for (i = 0; i < priv->rx_q_entries; i++) { 966 rxdes = &priv->rxdes[i]; 967 rxdes->rxdes0 = 0; 968 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma); 969 } 970 /* Mark the end of the ring */ 971 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); 972 973 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES)) 974 return; 975 976 /* Initialize TX ring */ 977 for (i = 0; i < priv->tx_q_entries; i++) { 978 txdes = &priv->txdes[i]; 979 txdes->txdes0 = 0; 980 } 981 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask); 982 } 983 984 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv) 985 { 986 int i; 987 988 for (i = 0; i < priv->rx_q_entries; i++) { 989 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 990 991 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL)) 992 return -ENOMEM; 993 } 994 return 0; 995 } 996 997 static void ftgmac100_adjust_link(struct net_device *netdev) 998 { 999 struct ftgmac100 *priv = netdev_priv(netdev); 1000 struct phy_device *phydev = netdev->phydev; 1001 bool tx_pause, rx_pause; 1002 int new_speed; 1003 1004 /* We store "no link" as speed 0 */ 1005 if (!phydev->link) 1006 new_speed = 0; 1007 else 1008 new_speed = phydev->speed; 1009 1010 /* Grab pause settings from PHY if configured to do so */ 1011 if (priv->aneg_pause) { 1012 rx_pause = tx_pause = phydev->pause; 1013 if (phydev->asym_pause) 1014 tx_pause = !rx_pause; 1015 } else { 1016 rx_pause = priv->rx_pause; 1017 tx_pause = priv->tx_pause; 1018 } 1019 1020 /* Link hasn't changed, do nothing */ 1021 if (phydev->speed == priv->cur_speed && 1022 phydev->duplex == priv->cur_duplex && 1023 rx_pause == priv->rx_pause && 1024 tx_pause == priv->tx_pause) 1025 return; 1026 1027 /* Print status if we have a link or we had one and just lost it, 1028 * don't print otherwise. 1029 */ 1030 if (new_speed || priv->cur_speed) 1031 phy_print_status(phydev); 1032 1033 priv->cur_speed = new_speed; 1034 priv->cur_duplex = phydev->duplex; 1035 priv->rx_pause = rx_pause; 1036 priv->tx_pause = tx_pause; 1037 1038 /* Link is down, do nothing else */ 1039 if (!new_speed) 1040 return; 1041 1042 /* Disable all interrupts */ 1043 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1044 1045 /* Reset the adapter asynchronously */ 1046 schedule_work(&priv->reset_task); 1047 } 1048 1049 static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf) 1050 { 1051 struct net_device *netdev = priv->netdev; 1052 struct phy_device *phydev; 1053 1054 phydev = phy_find_first(priv->mii_bus); 1055 if (!phydev) { 1056 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 1057 return -ENODEV; 1058 } 1059 1060 phydev = phy_connect(netdev, phydev_name(phydev), 1061 &ftgmac100_adjust_link, intf); 1062 1063 if (IS_ERR(phydev)) { 1064 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 1065 return PTR_ERR(phydev); 1066 } 1067 1068 /* Indicate that we support PAUSE frames (see comment in 1069 * Documentation/networking/phy.rst) 1070 */ 1071 phy_support_asym_pause(phydev); 1072 1073 /* Display what we found */ 1074 phy_attached_info(phydev); 1075 1076 return 0; 1077 } 1078 1079 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 1080 { 1081 struct net_device *netdev = bus->priv; 1082 struct ftgmac100 *priv = netdev_priv(netdev); 1083 unsigned int phycr; 1084 int i; 1085 1086 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1087 1088 /* preserve MDC cycle threshold */ 1089 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1090 1091 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1092 FTGMAC100_PHYCR_REGAD(regnum) | 1093 FTGMAC100_PHYCR_MIIRD; 1094 1095 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1096 1097 for (i = 0; i < 10; i++) { 1098 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1099 1100 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 1101 int data; 1102 1103 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 1104 return FTGMAC100_PHYDATA_MIIRDATA(data); 1105 } 1106 1107 udelay(100); 1108 } 1109 1110 netdev_err(netdev, "mdio read timed out\n"); 1111 return -EIO; 1112 } 1113 1114 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 1115 int regnum, u16 value) 1116 { 1117 struct net_device *netdev = bus->priv; 1118 struct ftgmac100 *priv = netdev_priv(netdev); 1119 unsigned int phycr; 1120 int data; 1121 int i; 1122 1123 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1124 1125 /* preserve MDC cycle threshold */ 1126 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1127 1128 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1129 FTGMAC100_PHYCR_REGAD(regnum) | 1130 FTGMAC100_PHYCR_MIIWR; 1131 1132 data = FTGMAC100_PHYDATA_MIIWDATA(value); 1133 1134 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 1135 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1136 1137 for (i = 0; i < 10; i++) { 1138 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1139 1140 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 1141 return 0; 1142 1143 udelay(100); 1144 } 1145 1146 netdev_err(netdev, "mdio write timed out\n"); 1147 return -EIO; 1148 } 1149 1150 static void ftgmac100_get_drvinfo(struct net_device *netdev, 1151 struct ethtool_drvinfo *info) 1152 { 1153 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1154 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1155 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); 1156 } 1157 1158 static void ftgmac100_get_ringparam(struct net_device *netdev, 1159 struct ethtool_ringparam *ering) 1160 { 1161 struct ftgmac100 *priv = netdev_priv(netdev); 1162 1163 memset(ering, 0, sizeof(*ering)); 1164 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES; 1165 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES; 1166 ering->rx_pending = priv->rx_q_entries; 1167 ering->tx_pending = priv->tx_q_entries; 1168 } 1169 1170 static int ftgmac100_set_ringparam(struct net_device *netdev, 1171 struct ethtool_ringparam *ering) 1172 { 1173 struct ftgmac100 *priv = netdev_priv(netdev); 1174 1175 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES || 1176 ering->tx_pending > MAX_TX_QUEUE_ENTRIES || 1177 ering->rx_pending < MIN_RX_QUEUE_ENTRIES || 1178 ering->tx_pending < MIN_TX_QUEUE_ENTRIES || 1179 !is_power_of_2(ering->rx_pending) || 1180 !is_power_of_2(ering->tx_pending)) 1181 return -EINVAL; 1182 1183 priv->new_rx_q_entries = ering->rx_pending; 1184 priv->new_tx_q_entries = ering->tx_pending; 1185 if (netif_running(netdev)) 1186 schedule_work(&priv->reset_task); 1187 1188 return 0; 1189 } 1190 1191 static void ftgmac100_get_pauseparam(struct net_device *netdev, 1192 struct ethtool_pauseparam *pause) 1193 { 1194 struct ftgmac100 *priv = netdev_priv(netdev); 1195 1196 pause->autoneg = priv->aneg_pause; 1197 pause->tx_pause = priv->tx_pause; 1198 pause->rx_pause = priv->rx_pause; 1199 } 1200 1201 static int ftgmac100_set_pauseparam(struct net_device *netdev, 1202 struct ethtool_pauseparam *pause) 1203 { 1204 struct ftgmac100 *priv = netdev_priv(netdev); 1205 struct phy_device *phydev = netdev->phydev; 1206 1207 priv->aneg_pause = pause->autoneg; 1208 priv->tx_pause = pause->tx_pause; 1209 priv->rx_pause = pause->rx_pause; 1210 1211 if (phydev) 1212 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); 1213 1214 if (netif_running(netdev)) { 1215 if (!(phydev && priv->aneg_pause)) 1216 ftgmac100_config_pause(priv); 1217 } 1218 1219 return 0; 1220 } 1221 1222 static const struct ethtool_ops ftgmac100_ethtool_ops = { 1223 .get_drvinfo = ftgmac100_get_drvinfo, 1224 .get_link = ethtool_op_get_link, 1225 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1226 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1227 .nway_reset = phy_ethtool_nway_reset, 1228 .get_ringparam = ftgmac100_get_ringparam, 1229 .set_ringparam = ftgmac100_set_ringparam, 1230 .get_pauseparam = ftgmac100_get_pauseparam, 1231 .set_pauseparam = ftgmac100_set_pauseparam, 1232 }; 1233 1234 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 1235 { 1236 struct net_device *netdev = dev_id; 1237 struct ftgmac100 *priv = netdev_priv(netdev); 1238 unsigned int status, new_mask = FTGMAC100_INT_BAD; 1239 1240 /* Fetch and clear interrupt bits, process abnormal ones */ 1241 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1242 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1243 if (unlikely(status & FTGMAC100_INT_BAD)) { 1244 1245 /* RX buffer unavailable */ 1246 if (status & FTGMAC100_INT_NO_RXBUF) 1247 netdev->stats.rx_over_errors++; 1248 1249 /* received packet lost due to RX FIFO full */ 1250 if (status & FTGMAC100_INT_RPKT_LOST) 1251 netdev->stats.rx_fifo_errors++; 1252 1253 /* sent packet lost due to excessive TX collision */ 1254 if (status & FTGMAC100_INT_XPKT_LOST) 1255 netdev->stats.tx_fifo_errors++; 1256 1257 /* AHB error -> Reset the chip */ 1258 if (status & FTGMAC100_INT_AHB_ERR) { 1259 if (net_ratelimit()) 1260 netdev_warn(netdev, 1261 "AHB bus error ! Resetting chip.\n"); 1262 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1263 schedule_work(&priv->reset_task); 1264 return IRQ_HANDLED; 1265 } 1266 1267 /* We may need to restart the MAC after such errors, delay 1268 * this until after we have freed some Rx buffers though 1269 */ 1270 priv->need_mac_restart = true; 1271 1272 /* Disable those errors until we restart */ 1273 new_mask &= ~status; 1274 } 1275 1276 /* Only enable "bad" interrupts while NAPI is on */ 1277 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER); 1278 1279 /* Schedule NAPI bh */ 1280 napi_schedule_irqoff(&priv->napi); 1281 1282 return IRQ_HANDLED; 1283 } 1284 1285 static bool ftgmac100_check_rx(struct ftgmac100 *priv) 1286 { 1287 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer]; 1288 1289 /* Do we have a packet ? */ 1290 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY)); 1291 } 1292 1293 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1294 { 1295 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1296 int work_done = 0; 1297 bool more; 1298 1299 /* Handle TX completions */ 1300 if (ftgmac100_tx_buf_cleanable(priv)) 1301 ftgmac100_tx_complete(priv); 1302 1303 /* Handle RX packets */ 1304 do { 1305 more = ftgmac100_rx_packet(priv, &work_done); 1306 } while (more && work_done < budget); 1307 1308 1309 /* The interrupt is telling us to kick the MAC back to life 1310 * after an RX overflow 1311 */ 1312 if (unlikely(priv->need_mac_restart)) { 1313 ftgmac100_start_hw(priv); 1314 1315 /* Re-enable "bad" interrupts */ 1316 iowrite32(FTGMAC100_INT_BAD, 1317 priv->base + FTGMAC100_OFFSET_IER); 1318 } 1319 1320 /* As long as we are waiting for transmit packets to be 1321 * completed we keep NAPI going 1322 */ 1323 if (ftgmac100_tx_buf_cleanable(priv)) 1324 work_done = budget; 1325 1326 if (work_done < budget) { 1327 /* We are about to re-enable all interrupts. However 1328 * the HW has been latching RX/TX packet interrupts while 1329 * they were masked. So we clear them first, then we need 1330 * to re-check if there's something to process 1331 */ 1332 iowrite32(FTGMAC100_INT_RXTX, 1333 priv->base + FTGMAC100_OFFSET_ISR); 1334 1335 /* Push the above (and provides a barrier vs. subsequent 1336 * reads of the descriptor). 1337 */ 1338 ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1339 1340 /* Check RX and TX descriptors for more work to do */ 1341 if (ftgmac100_check_rx(priv) || 1342 ftgmac100_tx_buf_cleanable(priv)) 1343 return budget; 1344 1345 /* deschedule NAPI */ 1346 napi_complete(napi); 1347 1348 /* enable all interrupts */ 1349 iowrite32(FTGMAC100_INT_ALL, 1350 priv->base + FTGMAC100_OFFSET_IER); 1351 } 1352 1353 return work_done; 1354 } 1355 1356 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err) 1357 { 1358 int err = 0; 1359 1360 /* Re-init descriptors (adjust queue sizes) */ 1361 ftgmac100_init_rings(priv); 1362 1363 /* Realloc rx descriptors */ 1364 err = ftgmac100_alloc_rx_buffers(priv); 1365 if (err && !ignore_alloc_err) 1366 return err; 1367 1368 /* Reinit and restart HW */ 1369 ftgmac100_init_hw(priv); 1370 ftgmac100_config_pause(priv); 1371 ftgmac100_start_hw(priv); 1372 1373 /* Re-enable the device */ 1374 napi_enable(&priv->napi); 1375 netif_start_queue(priv->netdev); 1376 1377 /* Enable all interrupts */ 1378 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER); 1379 1380 return err; 1381 } 1382 1383 static void ftgmac100_reset_task(struct work_struct *work) 1384 { 1385 struct ftgmac100 *priv = container_of(work, struct ftgmac100, 1386 reset_task); 1387 struct net_device *netdev = priv->netdev; 1388 int err; 1389 1390 netdev_dbg(netdev, "Resetting NIC...\n"); 1391 1392 /* Lock the world */ 1393 rtnl_lock(); 1394 if (netdev->phydev) 1395 mutex_lock(&netdev->phydev->lock); 1396 if (priv->mii_bus) 1397 mutex_lock(&priv->mii_bus->mdio_lock); 1398 1399 1400 /* Check if the interface is still up */ 1401 if (!netif_running(netdev)) 1402 goto bail; 1403 1404 /* Stop the network stack */ 1405 netif_trans_update(netdev); 1406 napi_disable(&priv->napi); 1407 netif_tx_disable(netdev); 1408 1409 /* Stop and reset the MAC */ 1410 ftgmac100_stop_hw(priv); 1411 err = ftgmac100_reset_and_config_mac(priv); 1412 if (err) { 1413 /* Not much we can do ... it might come back... */ 1414 netdev_err(netdev, "attempting to continue...\n"); 1415 } 1416 1417 /* Free all rx and tx buffers */ 1418 ftgmac100_free_buffers(priv); 1419 1420 /* Setup everything again and restart chip */ 1421 ftgmac100_init_all(priv, true); 1422 1423 netdev_dbg(netdev, "Reset done !\n"); 1424 bail: 1425 if (priv->mii_bus) 1426 mutex_unlock(&priv->mii_bus->mdio_lock); 1427 if (netdev->phydev) 1428 mutex_unlock(&netdev->phydev->lock); 1429 rtnl_unlock(); 1430 } 1431 1432 static int ftgmac100_open(struct net_device *netdev) 1433 { 1434 struct ftgmac100 *priv = netdev_priv(netdev); 1435 int err; 1436 1437 /* Allocate ring buffers */ 1438 err = ftgmac100_alloc_rings(priv); 1439 if (err) { 1440 netdev_err(netdev, "Failed to allocate descriptors\n"); 1441 return err; 1442 } 1443 1444 /* When using NC-SI we force the speed to 100Mbit/s full duplex, 1445 * 1446 * Otherwise we leave it set to 0 (no link), the link 1447 * message from the PHY layer will handle setting it up to 1448 * something else if needed. 1449 */ 1450 if (priv->use_ncsi) { 1451 priv->cur_duplex = DUPLEX_FULL; 1452 priv->cur_speed = SPEED_100; 1453 } else { 1454 priv->cur_duplex = 0; 1455 priv->cur_speed = 0; 1456 } 1457 1458 /* Reset the hardware */ 1459 err = ftgmac100_reset_and_config_mac(priv); 1460 if (err) 1461 goto err_hw; 1462 1463 /* Initialize NAPI */ 1464 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1465 1466 /* Grab our interrupt */ 1467 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1468 if (err) { 1469 netdev_err(netdev, "failed to request irq %d\n", netdev->irq); 1470 goto err_irq; 1471 } 1472 1473 /* Start things up */ 1474 err = ftgmac100_init_all(priv, false); 1475 if (err) { 1476 netdev_err(netdev, "Failed to allocate packet buffers\n"); 1477 goto err_alloc; 1478 } 1479 1480 if (netdev->phydev) { 1481 /* If we have a PHY, start polling */ 1482 phy_start(netdev->phydev); 1483 } else if (priv->use_ncsi) { 1484 /* If using NC-SI, set our carrier on and start the stack */ 1485 netif_carrier_on(netdev); 1486 1487 /* Start the NCSI device */ 1488 err = ncsi_start_dev(priv->ndev); 1489 if (err) 1490 goto err_ncsi; 1491 } 1492 1493 return 0; 1494 1495 err_ncsi: 1496 napi_disable(&priv->napi); 1497 netif_stop_queue(netdev); 1498 err_alloc: 1499 ftgmac100_free_buffers(priv); 1500 free_irq(netdev->irq, netdev); 1501 err_irq: 1502 netif_napi_del(&priv->napi); 1503 err_hw: 1504 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1505 ftgmac100_free_rings(priv); 1506 return err; 1507 } 1508 1509 static int ftgmac100_stop(struct net_device *netdev) 1510 { 1511 struct ftgmac100 *priv = netdev_priv(netdev); 1512 1513 /* Note about the reset task: We are called with the rtnl lock 1514 * held, so we are synchronized against the core of the reset 1515 * task. We must not try to synchronously cancel it otherwise 1516 * we can deadlock. But since it will test for netif_running() 1517 * which has already been cleared by the net core, we don't 1518 * anything special to do. 1519 */ 1520 1521 /* disable all interrupts */ 1522 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1523 1524 netif_stop_queue(netdev); 1525 napi_disable(&priv->napi); 1526 netif_napi_del(&priv->napi); 1527 if (netdev->phydev) 1528 phy_stop(netdev->phydev); 1529 else if (priv->use_ncsi) 1530 ncsi_stop_dev(priv->ndev); 1531 1532 ftgmac100_stop_hw(priv); 1533 free_irq(netdev->irq, netdev); 1534 ftgmac100_free_buffers(priv); 1535 ftgmac100_free_rings(priv); 1536 1537 return 0; 1538 } 1539 1540 /* optional */ 1541 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1542 { 1543 if (!netdev->phydev) 1544 return -ENXIO; 1545 1546 return phy_mii_ioctl(netdev->phydev, ifr, cmd); 1547 } 1548 1549 static void ftgmac100_tx_timeout(struct net_device *netdev) 1550 { 1551 struct ftgmac100 *priv = netdev_priv(netdev); 1552 1553 /* Disable all interrupts */ 1554 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1555 1556 /* Do the reset outside of interrupt context */ 1557 schedule_work(&priv->reset_task); 1558 } 1559 1560 static int ftgmac100_set_features(struct net_device *netdev, 1561 netdev_features_t features) 1562 { 1563 struct ftgmac100 *priv = netdev_priv(netdev); 1564 netdev_features_t changed = netdev->features ^ features; 1565 1566 if (!netif_running(netdev)) 1567 return 0; 1568 1569 /* Update the vlan filtering bit */ 1570 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 1571 u32 maccr; 1572 1573 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 1574 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 1575 maccr |= FTGMAC100_MACCR_RM_VLAN; 1576 else 1577 maccr &= ~FTGMAC100_MACCR_RM_VLAN; 1578 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 1579 } 1580 1581 return 0; 1582 } 1583 1584 #ifdef CONFIG_NET_POLL_CONTROLLER 1585 static void ftgmac100_poll_controller(struct net_device *netdev) 1586 { 1587 unsigned long flags; 1588 1589 local_irq_save(flags); 1590 ftgmac100_interrupt(netdev->irq, netdev); 1591 local_irq_restore(flags); 1592 } 1593 #endif 1594 1595 static const struct net_device_ops ftgmac100_netdev_ops = { 1596 .ndo_open = ftgmac100_open, 1597 .ndo_stop = ftgmac100_stop, 1598 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1599 .ndo_set_mac_address = ftgmac100_set_mac_addr, 1600 .ndo_validate_addr = eth_validate_addr, 1601 .ndo_do_ioctl = ftgmac100_do_ioctl, 1602 .ndo_tx_timeout = ftgmac100_tx_timeout, 1603 .ndo_set_rx_mode = ftgmac100_set_rx_mode, 1604 .ndo_set_features = ftgmac100_set_features, 1605 #ifdef CONFIG_NET_POLL_CONTROLLER 1606 .ndo_poll_controller = ftgmac100_poll_controller, 1607 #endif 1608 .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid, 1609 .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid, 1610 }; 1611 1612 static int ftgmac100_setup_mdio(struct net_device *netdev) 1613 { 1614 struct ftgmac100 *priv = netdev_priv(netdev); 1615 struct platform_device *pdev = to_platform_device(priv->dev); 1616 int phy_intf = PHY_INTERFACE_MODE_RGMII; 1617 struct device_node *np = pdev->dev.of_node; 1618 int i, err = 0; 1619 u32 reg; 1620 1621 /* initialize mdio bus */ 1622 priv->mii_bus = mdiobus_alloc(); 1623 if (!priv->mii_bus) 1624 return -EIO; 1625 1626 if (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1627 of_device_is_compatible(np, "aspeed,ast2500-mac")) { 1628 /* The AST2600 has a separate MDIO controller */ 1629 1630 /* For the AST2400 and AST2500 this driver only supports the 1631 * old MDIO interface 1632 */ 1633 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); 1634 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; 1635 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); 1636 } 1637 1638 /* Get PHY mode from device-tree */ 1639 if (np) { 1640 /* Default to RGMII. It's a gigabit part after all */ 1641 phy_intf = of_get_phy_mode(np); 1642 if (phy_intf < 0) 1643 phy_intf = PHY_INTERFACE_MODE_RGMII; 1644 1645 /* Aspeed only supports these. I don't know about other IP 1646 * block vendors so I'm going to just let them through for 1647 * now. Note that this is only a warning if for some obscure 1648 * reason the DT really means to lie about it or it's a newer 1649 * part we don't know about. 1650 * 1651 * On the Aspeed SoC there are additionally straps and SCU 1652 * control bits that could tell us what the interface is 1653 * (or allow us to configure it while the IP block is held 1654 * in reset). For now I chose to keep this driver away from 1655 * those SoC specific bits and assume the device-tree is 1656 * right and the SCU has been configured properly by pinmux 1657 * or the firmware. 1658 */ 1659 if (priv->is_aspeed && 1660 phy_intf != PHY_INTERFACE_MODE_RMII && 1661 phy_intf != PHY_INTERFACE_MODE_RGMII && 1662 phy_intf != PHY_INTERFACE_MODE_RGMII_ID && 1663 phy_intf != PHY_INTERFACE_MODE_RGMII_RXID && 1664 phy_intf != PHY_INTERFACE_MODE_RGMII_TXID) { 1665 netdev_warn(netdev, 1666 "Unsupported PHY mode %s !\n", 1667 phy_modes(phy_intf)); 1668 } 1669 } 1670 1671 priv->mii_bus->name = "ftgmac100_mdio"; 1672 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1673 pdev->name, pdev->id); 1674 priv->mii_bus->parent = priv->dev; 1675 priv->mii_bus->priv = priv->netdev; 1676 priv->mii_bus->read = ftgmac100_mdiobus_read; 1677 priv->mii_bus->write = ftgmac100_mdiobus_write; 1678 1679 for (i = 0; i < PHY_MAX_ADDR; i++) 1680 priv->mii_bus->irq[i] = PHY_POLL; 1681 1682 err = mdiobus_register(priv->mii_bus); 1683 if (err) { 1684 dev_err(priv->dev, "Cannot register MDIO bus!\n"); 1685 goto err_register_mdiobus; 1686 } 1687 1688 err = ftgmac100_mii_probe(priv, phy_intf); 1689 if (err) { 1690 dev_err(priv->dev, "MII Probe failed!\n"); 1691 goto err_mii_probe; 1692 } 1693 1694 return 0; 1695 1696 err_mii_probe: 1697 mdiobus_unregister(priv->mii_bus); 1698 err_register_mdiobus: 1699 mdiobus_free(priv->mii_bus); 1700 return err; 1701 } 1702 1703 static void ftgmac100_destroy_mdio(struct net_device *netdev) 1704 { 1705 struct ftgmac100 *priv = netdev_priv(netdev); 1706 1707 if (!netdev->phydev) 1708 return; 1709 1710 phy_disconnect(netdev->phydev); 1711 mdiobus_unregister(priv->mii_bus); 1712 mdiobus_free(priv->mii_bus); 1713 } 1714 1715 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) 1716 { 1717 if (unlikely(nd->state != ncsi_dev_state_functional)) 1718 return; 1719 1720 netdev_dbg(nd->dev, "NCSI interface %s\n", 1721 nd->link_up ? "up" : "down"); 1722 } 1723 1724 static int ftgmac100_setup_clk(struct ftgmac100 *priv) 1725 { 1726 struct clk *clk; 1727 int rc; 1728 1729 clk = devm_clk_get(priv->dev, NULL /* MACCLK */); 1730 if (IS_ERR(clk)) 1731 return PTR_ERR(clk); 1732 priv->clk = clk; 1733 rc = clk_prepare_enable(priv->clk); 1734 if (rc) 1735 return rc; 1736 1737 /* Aspeed specifies a 100MHz clock is required for up to 1738 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz 1739 * is sufficient 1740 */ 1741 rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ : 1742 FTGMAC_100MHZ); 1743 if (rc) 1744 goto cleanup_clk; 1745 1746 /* RCLK is for RMII, typically used for NCSI. Optional because its not 1747 * necessary if it's the AST2400 MAC, or the MAC is configured for 1748 * RGMII, or the controller is not an ASPEED-based controller. 1749 */ 1750 priv->rclk = devm_clk_get_optional(priv->dev, "RCLK"); 1751 rc = clk_prepare_enable(priv->rclk); 1752 if (!rc) 1753 return 0; 1754 1755 cleanup_clk: 1756 clk_disable_unprepare(priv->clk); 1757 1758 return rc; 1759 } 1760 1761 static int ftgmac100_probe(struct platform_device *pdev) 1762 { 1763 struct resource *res; 1764 int irq; 1765 struct net_device *netdev; 1766 struct ftgmac100 *priv; 1767 struct device_node *np; 1768 int err = 0; 1769 1770 if (!pdev) 1771 return -ENODEV; 1772 1773 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1774 if (!res) 1775 return -ENXIO; 1776 1777 irq = platform_get_irq(pdev, 0); 1778 if (irq < 0) 1779 return irq; 1780 1781 /* setup net_device */ 1782 netdev = alloc_etherdev(sizeof(*priv)); 1783 if (!netdev) { 1784 err = -ENOMEM; 1785 goto err_alloc_etherdev; 1786 } 1787 1788 SET_NETDEV_DEV(netdev, &pdev->dev); 1789 1790 netdev->ethtool_ops = &ftgmac100_ethtool_ops; 1791 netdev->netdev_ops = &ftgmac100_netdev_ops; 1792 netdev->watchdog_timeo = 5 * HZ; 1793 1794 platform_set_drvdata(pdev, netdev); 1795 1796 /* setup private data */ 1797 priv = netdev_priv(netdev); 1798 priv->netdev = netdev; 1799 priv->dev = &pdev->dev; 1800 INIT_WORK(&priv->reset_task, ftgmac100_reset_task); 1801 1802 /* map io memory */ 1803 priv->res = request_mem_region(res->start, resource_size(res), 1804 dev_name(&pdev->dev)); 1805 if (!priv->res) { 1806 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1807 err = -ENOMEM; 1808 goto err_req_mem; 1809 } 1810 1811 priv->base = ioremap(res->start, resource_size(res)); 1812 if (!priv->base) { 1813 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1814 err = -EIO; 1815 goto err_ioremap; 1816 } 1817 1818 netdev->irq = irq; 1819 1820 /* Enable pause */ 1821 priv->tx_pause = true; 1822 priv->rx_pause = true; 1823 priv->aneg_pause = true; 1824 1825 /* MAC address from chip or random one */ 1826 ftgmac100_initial_mac(priv); 1827 1828 np = pdev->dev.of_node; 1829 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1830 of_device_is_compatible(np, "aspeed,ast2500-mac") || 1831 of_device_is_compatible(np, "aspeed,ast2600-mac"))) { 1832 priv->rxdes0_edorr_mask = BIT(30); 1833 priv->txdes0_edotr_mask = BIT(30); 1834 priv->is_aspeed = true; 1835 } else { 1836 priv->rxdes0_edorr_mask = BIT(15); 1837 priv->txdes0_edotr_mask = BIT(15); 1838 } 1839 1840 if (np && of_get_property(np, "use-ncsi", NULL)) { 1841 if (!IS_ENABLED(CONFIG_NET_NCSI)) { 1842 dev_err(&pdev->dev, "NCSI stack not enabled\n"); 1843 goto err_ncsi_dev; 1844 } 1845 1846 dev_info(&pdev->dev, "Using NCSI interface\n"); 1847 priv->use_ncsi = true; 1848 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); 1849 if (!priv->ndev) 1850 goto err_ncsi_dev; 1851 } else if (np && of_get_property(np, "phy-handle", NULL)) { 1852 struct phy_device *phy; 1853 1854 phy = of_phy_get_and_connect(priv->netdev, np, 1855 &ftgmac100_adjust_link); 1856 if (!phy) { 1857 dev_err(&pdev->dev, "Failed to connect to phy\n"); 1858 goto err_setup_mdio; 1859 } 1860 1861 /* Indicate that we support PAUSE frames (see comment in 1862 * Documentation/networking/phy.txt) 1863 */ 1864 phy_support_asym_pause(phy); 1865 1866 /* Display what we found */ 1867 phy_attached_info(phy); 1868 } else if (np && !of_get_child_by_name(np, "mdio")) { 1869 /* Support legacy ASPEED devicetree descriptions that decribe a 1870 * MAC with an embedded MDIO controller but have no "mdio" 1871 * child node. Automatically scan the MDIO bus for available 1872 * PHYs. 1873 */ 1874 priv->use_ncsi = false; 1875 err = ftgmac100_setup_mdio(netdev); 1876 if (err) 1877 goto err_setup_mdio; 1878 } 1879 1880 if (priv->is_aspeed) { 1881 err = ftgmac100_setup_clk(priv); 1882 if (err) 1883 goto err_ncsi_dev; 1884 } 1885 1886 /* Default ring sizes */ 1887 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES; 1888 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES; 1889 1890 /* Base feature set */ 1891 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM | 1892 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX | 1893 NETIF_F_HW_VLAN_CTAG_TX; 1894 1895 if (priv->use_ncsi) 1896 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1897 1898 /* AST2400 doesn't have working HW checksum generation */ 1899 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac"))) 1900 netdev->hw_features &= ~NETIF_F_HW_CSUM; 1901 if (np && of_get_property(np, "no-hw-checksum", NULL)) 1902 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM); 1903 netdev->features |= netdev->hw_features; 1904 1905 /* register network device */ 1906 err = register_netdev(netdev); 1907 if (err) { 1908 dev_err(&pdev->dev, "Failed to register netdev\n"); 1909 goto err_register_netdev; 1910 } 1911 1912 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base); 1913 1914 return 0; 1915 1916 err_register_netdev: 1917 clk_disable_unprepare(priv->rclk); 1918 clk_disable_unprepare(priv->clk); 1919 err_ncsi_dev: 1920 ftgmac100_destroy_mdio(netdev); 1921 err_setup_mdio: 1922 iounmap(priv->base); 1923 err_ioremap: 1924 release_resource(priv->res); 1925 err_req_mem: 1926 free_netdev(netdev); 1927 err_alloc_etherdev: 1928 return err; 1929 } 1930 1931 static int ftgmac100_remove(struct platform_device *pdev) 1932 { 1933 struct net_device *netdev; 1934 struct ftgmac100 *priv; 1935 1936 netdev = platform_get_drvdata(pdev); 1937 priv = netdev_priv(netdev); 1938 1939 unregister_netdev(netdev); 1940 1941 clk_disable_unprepare(priv->rclk); 1942 clk_disable_unprepare(priv->clk); 1943 1944 /* There's a small chance the reset task will have been re-queued, 1945 * during stop, make sure it's gone before we free the structure. 1946 */ 1947 cancel_work_sync(&priv->reset_task); 1948 1949 ftgmac100_destroy_mdio(netdev); 1950 1951 iounmap(priv->base); 1952 release_resource(priv->res); 1953 1954 netif_napi_del(&priv->napi); 1955 free_netdev(netdev); 1956 return 0; 1957 } 1958 1959 static const struct of_device_id ftgmac100_of_match[] = { 1960 { .compatible = "faraday,ftgmac100" }, 1961 { } 1962 }; 1963 MODULE_DEVICE_TABLE(of, ftgmac100_of_match); 1964 1965 static struct platform_driver ftgmac100_driver = { 1966 .probe = ftgmac100_probe, 1967 .remove = ftgmac100_remove, 1968 .driver = { 1969 .name = DRV_NAME, 1970 .of_match_table = ftgmac100_of_match, 1971 }, 1972 }; 1973 module_platform_driver(ftgmac100_driver); 1974 1975 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1976 MODULE_DESCRIPTION("FTGMAC100 driver"); 1977 MODULE_LICENSE("GPL"); 1978