1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Faraday FTGMAC100 Gigabit Ethernet 4 * 5 * (C) Copyright 2009-2011 Faraday Technology 6 * Po-Yu Chuang <ratbert@faraday-tech.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/netdevice.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/property.h> 24 #include <linux/crc32.h> 25 #include <linux/if_vlan.h> 26 #include <linux/of_net.h> 27 #include <net/ip.h> 28 #include <net/ncsi.h> 29 30 #include "ftgmac100.h" 31 32 #define DRV_NAME "ftgmac100" 33 34 /* Arbitrary values, I am not sure the HW has limits */ 35 #define MAX_RX_QUEUE_ENTRIES 1024 36 #define MAX_TX_QUEUE_ENTRIES 1024 37 #define MIN_RX_QUEUE_ENTRIES 32 38 #define MIN_TX_QUEUE_ENTRIES 32 39 40 /* Defaults */ 41 #define DEF_RX_QUEUE_ENTRIES 128 42 #define DEF_TX_QUEUE_ENTRIES 128 43 44 #define MAX_PKT_SIZE 1536 45 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */ 46 47 /* Min number of tx ring entries before stopping queue */ 48 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1) 49 50 #define FTGMAC_100MHZ 100000000 51 #define FTGMAC_25MHZ 25000000 52 53 struct ftgmac100 { 54 /* Registers */ 55 struct resource *res; 56 void __iomem *base; 57 58 /* Rx ring */ 59 unsigned int rx_q_entries; 60 struct ftgmac100_rxdes *rxdes; 61 dma_addr_t rxdes_dma; 62 struct sk_buff **rx_skbs; 63 unsigned int rx_pointer; 64 u32 rxdes0_edorr_mask; 65 66 /* Tx ring */ 67 unsigned int tx_q_entries; 68 struct ftgmac100_txdes *txdes; 69 dma_addr_t txdes_dma; 70 struct sk_buff **tx_skbs; 71 unsigned int tx_clean_pointer; 72 unsigned int tx_pointer; 73 u32 txdes0_edotr_mask; 74 75 /* Used to signal the reset task of ring change request */ 76 unsigned int new_rx_q_entries; 77 unsigned int new_tx_q_entries; 78 79 /* Scratch page to use when rx skb alloc fails */ 80 void *rx_scratch; 81 dma_addr_t rx_scratch_dma; 82 83 /* Component structures */ 84 struct net_device *netdev; 85 struct device *dev; 86 struct ncsi_dev *ndev; 87 struct napi_struct napi; 88 struct work_struct reset_task; 89 struct mii_bus *mii_bus; 90 struct clk *clk; 91 92 /* AST2500/AST2600 RMII ref clock gate */ 93 struct clk *rclk; 94 95 /* Link management */ 96 int cur_speed; 97 int cur_duplex; 98 bool use_ncsi; 99 100 /* Multicast filter settings */ 101 u32 maht0; 102 u32 maht1; 103 104 /* Flow control settings */ 105 bool tx_pause; 106 bool rx_pause; 107 bool aneg_pause; 108 109 /* Misc */ 110 bool need_mac_restart; 111 bool is_aspeed; 112 }; 113 114 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr) 115 { 116 struct net_device *netdev = priv->netdev; 117 int i; 118 119 /* NOTE: reset clears all registers */ 120 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 121 iowrite32(maccr | FTGMAC100_MACCR_SW_RST, 122 priv->base + FTGMAC100_OFFSET_MACCR); 123 for (i = 0; i < 200; i++) { 124 unsigned int maccr; 125 126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 127 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 128 return 0; 129 130 udelay(1); 131 } 132 133 netdev_err(netdev, "Hardware reset failed\n"); 134 return -EIO; 135 } 136 137 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) 138 { 139 u32 maccr = 0; 140 141 switch (priv->cur_speed) { 142 case SPEED_10: 143 case 0: /* no link */ 144 break; 145 146 case SPEED_100: 147 maccr |= FTGMAC100_MACCR_FAST_MODE; 148 break; 149 150 case SPEED_1000: 151 maccr |= FTGMAC100_MACCR_GIGA_MODE; 152 break; 153 default: 154 netdev_err(priv->netdev, "Unknown speed %d !\n", 155 priv->cur_speed); 156 break; 157 } 158 159 /* (Re)initialize the queue pointers */ 160 priv->rx_pointer = 0; 161 priv->tx_clean_pointer = 0; 162 priv->tx_pointer = 0; 163 164 /* The doc says reset twice with 10us interval */ 165 if (ftgmac100_reset_mac(priv, maccr)) 166 return -EIO; 167 usleep_range(10, 1000); 168 return ftgmac100_reset_mac(priv, maccr); 169 } 170 171 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac) 172 { 173 unsigned int maddr = mac[0] << 8 | mac[1]; 174 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 175 176 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 177 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 178 } 179 180 static void ftgmac100_initial_mac(struct ftgmac100 *priv) 181 { 182 u8 mac[ETH_ALEN]; 183 unsigned int m; 184 unsigned int l; 185 void *addr; 186 187 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN); 188 if (addr) { 189 ether_addr_copy(priv->netdev->dev_addr, mac); 190 dev_info(priv->dev, "Read MAC address %pM from device tree\n", 191 mac); 192 return; 193 } 194 195 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); 196 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); 197 198 mac[0] = (m >> 8) & 0xff; 199 mac[1] = m & 0xff; 200 mac[2] = (l >> 24) & 0xff; 201 mac[3] = (l >> 16) & 0xff; 202 mac[4] = (l >> 8) & 0xff; 203 mac[5] = l & 0xff; 204 205 if (is_valid_ether_addr(mac)) { 206 ether_addr_copy(priv->netdev->dev_addr, mac); 207 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac); 208 } else { 209 eth_hw_addr_random(priv->netdev); 210 dev_info(priv->dev, "Generated random MAC address %pM\n", 211 priv->netdev->dev_addr); 212 } 213 } 214 215 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p) 216 { 217 int ret; 218 219 ret = eth_prepare_mac_addr_change(dev, p); 220 if (ret < 0) 221 return ret; 222 223 eth_commit_mac_addr_change(dev, p); 224 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr); 225 226 return 0; 227 } 228 229 static void ftgmac100_config_pause(struct ftgmac100 *priv) 230 { 231 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16); 232 233 /* Throttle tx queue when receiving pause frames */ 234 if (priv->rx_pause) 235 fcr |= FTGMAC100_FCR_FC_EN; 236 237 /* Enables sending pause frames when the RX queue is past a 238 * certain threshold. 239 */ 240 if (priv->tx_pause) 241 fcr |= FTGMAC100_FCR_FCTHR_EN; 242 243 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR); 244 } 245 246 static void ftgmac100_init_hw(struct ftgmac100 *priv) 247 { 248 u32 reg, rfifo_sz, tfifo_sz; 249 250 /* Clear stale interrupts */ 251 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 252 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); 253 254 /* Setup RX ring buffer base */ 255 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR); 256 257 /* Setup TX ring buffer base */ 258 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 259 260 /* Configure RX buffer size */ 261 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE), 262 priv->base + FTGMAC100_OFFSET_RBSR); 263 264 /* Set RX descriptor autopoll */ 265 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), 266 priv->base + FTGMAC100_OFFSET_APTC); 267 268 /* Write MAC address */ 269 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr); 270 271 /* Write multicast filter */ 272 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 273 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 274 275 /* Configure descriptor sizes and increase burst sizes according 276 * to values in Aspeed SDK. The FIFO arbitration is enabled and 277 * the thresholds set based on the recommended values in the 278 * AST2400 specification. 279 */ 280 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */ 281 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */ 282 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */ 283 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */ 284 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */ 285 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */ 286 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */ 287 priv->base + FTGMAC100_OFFSET_DBLAC); 288 289 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt 290 * mitigation doesn't seem to provide any benefit with NAPI so leave 291 * it at that. 292 */ 293 iowrite32(FTGMAC100_ITC_RXINT_THR(1) | 294 FTGMAC100_ITC_TXINT_THR(1), 295 priv->base + FTGMAC100_OFFSET_ITC); 296 297 /* Configure FIFO sizes in the TPAFCR register */ 298 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); 299 rfifo_sz = reg & 0x00000007; 300 tfifo_sz = (reg >> 3) & 0x00000007; 301 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); 302 reg &= ~0x3f000000; 303 reg |= (tfifo_sz << 27); 304 reg |= (rfifo_sz << 24); 305 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); 306 } 307 308 static void ftgmac100_start_hw(struct ftgmac100 *priv) 309 { 310 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 311 312 /* Keep the original GMAC and FAST bits */ 313 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE); 314 315 /* Add all the main enable bits */ 316 maccr |= FTGMAC100_MACCR_TXDMA_EN | 317 FTGMAC100_MACCR_RXDMA_EN | 318 FTGMAC100_MACCR_TXMAC_EN | 319 FTGMAC100_MACCR_RXMAC_EN | 320 FTGMAC100_MACCR_CRC_APD | 321 FTGMAC100_MACCR_PHY_LINK_LEVEL | 322 FTGMAC100_MACCR_RX_RUNT | 323 FTGMAC100_MACCR_RX_BROADPKT; 324 325 /* Add other bits as needed */ 326 if (priv->cur_duplex == DUPLEX_FULL) 327 maccr |= FTGMAC100_MACCR_FULLDUP; 328 if (priv->netdev->flags & IFF_PROMISC) 329 maccr |= FTGMAC100_MACCR_RX_ALL; 330 if (priv->netdev->flags & IFF_ALLMULTI) 331 maccr |= FTGMAC100_MACCR_RX_MULTIPKT; 332 else if (netdev_mc_count(priv->netdev)) 333 maccr |= FTGMAC100_MACCR_HT_MULTI_EN; 334 335 /* Vlan filtering enabled */ 336 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 337 maccr |= FTGMAC100_MACCR_RM_VLAN; 338 339 /* Hit the HW */ 340 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 341 } 342 343 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 344 { 345 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 346 } 347 348 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv) 349 { 350 struct netdev_hw_addr *ha; 351 352 priv->maht1 = 0; 353 priv->maht0 = 0; 354 netdev_for_each_mc_addr(ha, priv->netdev) { 355 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr); 356 357 crc_val = (~(crc_val >> 2)) & 0x3f; 358 if (crc_val >= 32) 359 priv->maht1 |= 1ul << (crc_val - 32); 360 else 361 priv->maht0 |= 1ul << (crc_val); 362 } 363 } 364 365 static void ftgmac100_set_rx_mode(struct net_device *netdev) 366 { 367 struct ftgmac100 *priv = netdev_priv(netdev); 368 369 /* Setup the hash filter */ 370 ftgmac100_calc_mc_hash(priv); 371 372 /* Interface down ? that's all there is to do */ 373 if (!netif_running(netdev)) 374 return; 375 376 /* Update the HW */ 377 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 378 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 379 380 /* Reconfigure MACCR */ 381 ftgmac100_start_hw(priv); 382 } 383 384 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry, 385 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 386 { 387 struct net_device *netdev = priv->netdev; 388 struct sk_buff *skb; 389 dma_addr_t map; 390 int err = 0; 391 392 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE); 393 if (unlikely(!skb)) { 394 if (net_ratelimit()) 395 netdev_warn(netdev, "failed to allocate rx skb\n"); 396 err = -ENOMEM; 397 map = priv->rx_scratch_dma; 398 } else { 399 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE, 400 DMA_FROM_DEVICE); 401 if (unlikely(dma_mapping_error(priv->dev, map))) { 402 if (net_ratelimit()) 403 netdev_err(netdev, "failed to map rx page\n"); 404 dev_kfree_skb_any(skb); 405 map = priv->rx_scratch_dma; 406 skb = NULL; 407 err = -ENOMEM; 408 } 409 } 410 411 /* Store skb */ 412 priv->rx_skbs[entry] = skb; 413 414 /* Store DMA address into RX desc */ 415 rxdes->rxdes3 = cpu_to_le32(map); 416 417 /* Ensure the above is ordered vs clearing the OWN bit */ 418 dma_wmb(); 419 420 /* Clean status (which resets own bit) */ 421 if (entry == (priv->rx_q_entries - 1)) 422 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask); 423 else 424 rxdes->rxdes0 = 0; 425 426 return err; 427 } 428 429 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv, 430 unsigned int pointer) 431 { 432 return (pointer + 1) & (priv->rx_q_entries - 1); 433 } 434 435 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status) 436 { 437 struct net_device *netdev = priv->netdev; 438 439 if (status & FTGMAC100_RXDES0_RX_ERR) 440 netdev->stats.rx_errors++; 441 442 if (status & FTGMAC100_RXDES0_CRC_ERR) 443 netdev->stats.rx_crc_errors++; 444 445 if (status & (FTGMAC100_RXDES0_FTL | 446 FTGMAC100_RXDES0_RUNT | 447 FTGMAC100_RXDES0_RX_ODD_NB)) 448 netdev->stats.rx_length_errors++; 449 } 450 451 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 452 { 453 struct net_device *netdev = priv->netdev; 454 struct ftgmac100_rxdes *rxdes; 455 struct sk_buff *skb; 456 unsigned int pointer, size; 457 u32 status, csum_vlan; 458 dma_addr_t map; 459 460 /* Grab next RX descriptor */ 461 pointer = priv->rx_pointer; 462 rxdes = &priv->rxdes[pointer]; 463 464 /* Grab descriptor status */ 465 status = le32_to_cpu(rxdes->rxdes0); 466 467 /* Do we have a packet ? */ 468 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY)) 469 return false; 470 471 /* Order subsequent reads with the test for the ready bit */ 472 dma_rmb(); 473 474 /* We don't cope with fragmented RX packets */ 475 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) || 476 !(status & FTGMAC100_RXDES0_LRS))) 477 goto drop; 478 479 /* Grab received size and csum vlan field in the descriptor */ 480 size = status & FTGMAC100_RXDES0_VDBC; 481 csum_vlan = le32_to_cpu(rxdes->rxdes1); 482 483 /* Any error (other than csum offload) flagged ? */ 484 if (unlikely(status & RXDES0_ANY_ERROR)) { 485 /* Correct for incorrect flagging of runt packets 486 * with vlan tags... Just accept a runt packet that 487 * has been flagged as vlan and whose size is at 488 * least 60 bytes. 489 */ 490 if ((status & FTGMAC100_RXDES0_RUNT) && 491 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) && 492 (size >= 60)) 493 status &= ~FTGMAC100_RXDES0_RUNT; 494 495 /* Any error still in there ? */ 496 if (status & RXDES0_ANY_ERROR) { 497 ftgmac100_rx_packet_error(priv, status); 498 goto drop; 499 } 500 } 501 502 /* If the packet had no skb (failed to allocate earlier) 503 * then try to allocate one and skip 504 */ 505 skb = priv->rx_skbs[pointer]; 506 if (!unlikely(skb)) { 507 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 508 goto drop; 509 } 510 511 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST)) 512 netdev->stats.multicast++; 513 514 /* If the HW found checksum errors, bounce it to software. 515 * 516 * If we didn't, we need to see if the packet was recognized 517 * by HW as one of the supported checksummed protocols before 518 * we accept the HW test results. 519 */ 520 if (netdev->features & NETIF_F_RXCSUM) { 521 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR | 522 FTGMAC100_RXDES1_UDP_CHKSUM_ERR | 523 FTGMAC100_RXDES1_IP_CHKSUM_ERR; 524 if ((csum_vlan & err_bits) || 525 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK)) 526 skb->ip_summed = CHECKSUM_NONE; 527 else 528 skb->ip_summed = CHECKSUM_UNNECESSARY; 529 } 530 531 /* Transfer received size to skb */ 532 skb_put(skb, size); 533 534 /* Extract vlan tag */ 535 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 536 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL)) 537 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 538 csum_vlan & 0xffff); 539 540 /* Tear down DMA mapping, do necessary cache management */ 541 map = le32_to_cpu(rxdes->rxdes3); 542 543 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU) 544 /* When we don't have an iommu, we can save cycles by not 545 * invalidating the cache for the part of the packet that 546 * wasn't received. 547 */ 548 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE); 549 #else 550 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 551 #endif 552 553 554 /* Resplenish rx ring */ 555 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 556 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 557 558 skb->protocol = eth_type_trans(skb, netdev); 559 560 netdev->stats.rx_packets++; 561 netdev->stats.rx_bytes += size; 562 563 /* push packet to protocol stack */ 564 if (skb->ip_summed == CHECKSUM_NONE) 565 netif_receive_skb(skb); 566 else 567 napi_gro_receive(&priv->napi, skb); 568 569 (*processed)++; 570 return true; 571 572 drop: 573 /* Clean rxdes0 (which resets own bit) */ 574 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask); 575 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 576 netdev->stats.rx_dropped++; 577 return true; 578 } 579 580 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv, 581 unsigned int index) 582 { 583 if (index == (priv->tx_q_entries - 1)) 584 return priv->txdes0_edotr_mask; 585 else 586 return 0; 587 } 588 589 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv, 590 unsigned int pointer) 591 { 592 return (pointer + 1) & (priv->tx_q_entries - 1); 593 } 594 595 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv) 596 { 597 /* Returns the number of available slots in the TX queue 598 * 599 * This always leaves one free slot so we don't have to 600 * worry about empty vs. full, and this simplifies the 601 * test for ftgmac100_tx_buf_cleanable() below 602 */ 603 return (priv->tx_clean_pointer - priv->tx_pointer - 1) & 604 (priv->tx_q_entries - 1); 605 } 606 607 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv) 608 { 609 return priv->tx_pointer != priv->tx_clean_pointer; 610 } 611 612 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv, 613 unsigned int pointer, 614 struct sk_buff *skb, 615 struct ftgmac100_txdes *txdes, 616 u32 ctl_stat) 617 { 618 dma_addr_t map = le32_to_cpu(txdes->txdes3); 619 size_t len; 620 621 if (ctl_stat & FTGMAC100_TXDES0_FTS) { 622 len = skb_headlen(skb); 623 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE); 624 } else { 625 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat); 626 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE); 627 } 628 629 /* Free SKB on last segment */ 630 if (ctl_stat & FTGMAC100_TXDES0_LTS) 631 dev_kfree_skb(skb); 632 priv->tx_skbs[pointer] = NULL; 633 } 634 635 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 636 { 637 struct net_device *netdev = priv->netdev; 638 struct ftgmac100_txdes *txdes; 639 struct sk_buff *skb; 640 unsigned int pointer; 641 u32 ctl_stat; 642 643 pointer = priv->tx_clean_pointer; 644 txdes = &priv->txdes[pointer]; 645 646 ctl_stat = le32_to_cpu(txdes->txdes0); 647 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN) 648 return false; 649 650 skb = priv->tx_skbs[pointer]; 651 netdev->stats.tx_packets++; 652 netdev->stats.tx_bytes += skb->len; 653 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 654 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 655 656 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer); 657 658 return true; 659 } 660 661 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 662 { 663 struct net_device *netdev = priv->netdev; 664 665 /* Process all completed packets */ 666 while (ftgmac100_tx_buf_cleanable(priv) && 667 ftgmac100_tx_complete_packet(priv)) 668 ; 669 670 /* Restart queue if needed */ 671 smp_mb(); 672 if (unlikely(netif_queue_stopped(netdev) && 673 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) { 674 struct netdev_queue *txq; 675 676 txq = netdev_get_tx_queue(netdev, 0); 677 __netif_tx_lock(txq, smp_processor_id()); 678 if (netif_queue_stopped(netdev) && 679 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 680 netif_wake_queue(netdev); 681 __netif_tx_unlock(txq); 682 } 683 } 684 685 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan) 686 { 687 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 688 u8 ip_proto = ip_hdr(skb)->protocol; 689 690 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM; 691 switch(ip_proto) { 692 case IPPROTO_TCP: 693 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM; 694 return true; 695 case IPPROTO_UDP: 696 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM; 697 return true; 698 case IPPROTO_IP: 699 return true; 700 } 701 } 702 return skb_checksum_help(skb) == 0; 703 } 704 705 static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb, 706 struct net_device *netdev) 707 { 708 struct ftgmac100 *priv = netdev_priv(netdev); 709 struct ftgmac100_txdes *txdes, *first; 710 unsigned int pointer, nfrags, len, i, j; 711 u32 f_ctl_stat, ctl_stat, csum_vlan; 712 dma_addr_t map; 713 714 /* The HW doesn't pad small frames */ 715 if (eth_skb_pad(skb)) { 716 netdev->stats.tx_dropped++; 717 return NETDEV_TX_OK; 718 } 719 720 /* Reject oversize packets */ 721 if (unlikely(skb->len > MAX_PKT_SIZE)) { 722 if (net_ratelimit()) 723 netdev_dbg(netdev, "tx packet too big\n"); 724 goto drop; 725 } 726 727 /* Do we have a limit on #fragments ? I yet have to get a reply 728 * from Aspeed. If there's one I haven't hit it. 729 */ 730 nfrags = skb_shinfo(skb)->nr_frags; 731 732 /* Setup HW checksumming */ 733 csum_vlan = 0; 734 if (skb->ip_summed == CHECKSUM_PARTIAL && 735 !ftgmac100_prep_tx_csum(skb, &csum_vlan)) 736 goto drop; 737 738 /* Add VLAN tag */ 739 if (skb_vlan_tag_present(skb)) { 740 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG; 741 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff; 742 } 743 744 /* Get header len */ 745 len = skb_headlen(skb); 746 747 /* Map the packet head */ 748 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 749 if (dma_mapping_error(priv->dev, map)) { 750 if (net_ratelimit()) 751 netdev_err(netdev, "map tx packet head failed\n"); 752 goto drop; 753 } 754 755 /* Grab the next free tx descriptor */ 756 pointer = priv->tx_pointer; 757 txdes = first = &priv->txdes[pointer]; 758 759 /* Setup it up with the packet head. Don't write the head to the 760 * ring just yet 761 */ 762 priv->tx_skbs[pointer] = skb; 763 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 764 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 765 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 766 f_ctl_stat |= FTGMAC100_TXDES0_FTS; 767 if (nfrags == 0) 768 f_ctl_stat |= FTGMAC100_TXDES0_LTS; 769 txdes->txdes3 = cpu_to_le32(map); 770 txdes->txdes1 = cpu_to_le32(csum_vlan); 771 772 /* Next descriptor */ 773 pointer = ftgmac100_next_tx_pointer(priv, pointer); 774 775 /* Add the fragments */ 776 for (i = 0; i < nfrags; i++) { 777 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 778 779 len = skb_frag_size(frag); 780 781 /* Map it */ 782 map = skb_frag_dma_map(priv->dev, frag, 0, len, 783 DMA_TO_DEVICE); 784 if (dma_mapping_error(priv->dev, map)) 785 goto dma_err; 786 787 /* Setup descriptor */ 788 priv->tx_skbs[pointer] = skb; 789 txdes = &priv->txdes[pointer]; 790 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 791 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 792 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 793 if (i == (nfrags - 1)) 794 ctl_stat |= FTGMAC100_TXDES0_LTS; 795 txdes->txdes0 = cpu_to_le32(ctl_stat); 796 txdes->txdes1 = 0; 797 txdes->txdes3 = cpu_to_le32(map); 798 799 /* Next one */ 800 pointer = ftgmac100_next_tx_pointer(priv, pointer); 801 } 802 803 /* Order the previous packet and descriptor udpates 804 * before setting the OWN bit on the first descriptor. 805 */ 806 dma_wmb(); 807 first->txdes0 = cpu_to_le32(f_ctl_stat); 808 809 /* Update next TX pointer */ 810 priv->tx_pointer = pointer; 811 812 /* If there isn't enough room for all the fragments of a new packet 813 * in the TX ring, stop the queue. The sequence below is race free 814 * vs. a concurrent restart in ftgmac100_poll() 815 */ 816 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) { 817 netif_stop_queue(netdev); 818 /* Order the queue stop with the test below */ 819 smp_mb(); 820 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 821 netif_wake_queue(netdev); 822 } 823 824 /* Poke transmitter to read the updated TX descriptors */ 825 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 826 827 return NETDEV_TX_OK; 828 829 dma_err: 830 if (net_ratelimit()) 831 netdev_err(netdev, "map tx fragment failed\n"); 832 833 /* Free head */ 834 pointer = priv->tx_pointer; 835 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat); 836 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask); 837 838 /* Then all fragments */ 839 for (j = 0; j < i; j++) { 840 pointer = ftgmac100_next_tx_pointer(priv, pointer); 841 txdes = &priv->txdes[pointer]; 842 ctl_stat = le32_to_cpu(txdes->txdes0); 843 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 844 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 845 } 846 847 /* This cannot be reached if we successfully mapped the 848 * last fragment, so we know ftgmac100_free_tx_packet() 849 * hasn't freed the skb yet. 850 */ 851 drop: 852 /* Drop the packet */ 853 dev_kfree_skb_any(skb); 854 netdev->stats.tx_dropped++; 855 856 return NETDEV_TX_OK; 857 } 858 859 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 860 { 861 int i; 862 863 /* Free all RX buffers */ 864 for (i = 0; i < priv->rx_q_entries; i++) { 865 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 866 struct sk_buff *skb = priv->rx_skbs[i]; 867 dma_addr_t map = le32_to_cpu(rxdes->rxdes3); 868 869 if (!skb) 870 continue; 871 872 priv->rx_skbs[i] = NULL; 873 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 874 dev_kfree_skb_any(skb); 875 } 876 877 /* Free all TX buffers */ 878 for (i = 0; i < priv->tx_q_entries; i++) { 879 struct ftgmac100_txdes *txdes = &priv->txdes[i]; 880 struct sk_buff *skb = priv->tx_skbs[i]; 881 882 if (!skb) 883 continue; 884 ftgmac100_free_tx_packet(priv, i, skb, txdes, 885 le32_to_cpu(txdes->txdes0)); 886 } 887 } 888 889 static void ftgmac100_free_rings(struct ftgmac100 *priv) 890 { 891 /* Free skb arrays */ 892 kfree(priv->rx_skbs); 893 kfree(priv->tx_skbs); 894 895 /* Free descriptors */ 896 if (priv->rxdes) 897 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES * 898 sizeof(struct ftgmac100_rxdes), 899 priv->rxdes, priv->rxdes_dma); 900 priv->rxdes = NULL; 901 902 if (priv->txdes) 903 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES * 904 sizeof(struct ftgmac100_txdes), 905 priv->txdes, priv->txdes_dma); 906 priv->txdes = NULL; 907 908 /* Free scratch packet buffer */ 909 if (priv->rx_scratch) 910 dma_free_coherent(priv->dev, RX_BUF_SIZE, 911 priv->rx_scratch, priv->rx_scratch_dma); 912 } 913 914 static int ftgmac100_alloc_rings(struct ftgmac100 *priv) 915 { 916 /* Allocate skb arrays */ 917 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *), 918 GFP_KERNEL); 919 if (!priv->rx_skbs) 920 return -ENOMEM; 921 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *), 922 GFP_KERNEL); 923 if (!priv->tx_skbs) 924 return -ENOMEM; 925 926 /* Allocate descriptors */ 927 priv->rxdes = dma_alloc_coherent(priv->dev, 928 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes), 929 &priv->rxdes_dma, GFP_KERNEL); 930 if (!priv->rxdes) 931 return -ENOMEM; 932 priv->txdes = dma_alloc_coherent(priv->dev, 933 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes), 934 &priv->txdes_dma, GFP_KERNEL); 935 if (!priv->txdes) 936 return -ENOMEM; 937 938 /* Allocate scratch packet buffer */ 939 priv->rx_scratch = dma_alloc_coherent(priv->dev, 940 RX_BUF_SIZE, 941 &priv->rx_scratch_dma, 942 GFP_KERNEL); 943 if (!priv->rx_scratch) 944 return -ENOMEM; 945 946 return 0; 947 } 948 949 static void ftgmac100_init_rings(struct ftgmac100 *priv) 950 { 951 struct ftgmac100_rxdes *rxdes = NULL; 952 struct ftgmac100_txdes *txdes = NULL; 953 int i; 954 955 /* Update entries counts */ 956 priv->rx_q_entries = priv->new_rx_q_entries; 957 priv->tx_q_entries = priv->new_tx_q_entries; 958 959 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES)) 960 return; 961 962 /* Initialize RX ring */ 963 for (i = 0; i < priv->rx_q_entries; i++) { 964 rxdes = &priv->rxdes[i]; 965 rxdes->rxdes0 = 0; 966 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma); 967 } 968 /* Mark the end of the ring */ 969 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); 970 971 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES)) 972 return; 973 974 /* Initialize TX ring */ 975 for (i = 0; i < priv->tx_q_entries; i++) { 976 txdes = &priv->txdes[i]; 977 txdes->txdes0 = 0; 978 } 979 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask); 980 } 981 982 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv) 983 { 984 int i; 985 986 for (i = 0; i < priv->rx_q_entries; i++) { 987 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 988 989 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL)) 990 return -ENOMEM; 991 } 992 return 0; 993 } 994 995 static void ftgmac100_adjust_link(struct net_device *netdev) 996 { 997 struct ftgmac100 *priv = netdev_priv(netdev); 998 struct phy_device *phydev = netdev->phydev; 999 bool tx_pause, rx_pause; 1000 int new_speed; 1001 1002 /* We store "no link" as speed 0 */ 1003 if (!phydev->link) 1004 new_speed = 0; 1005 else 1006 new_speed = phydev->speed; 1007 1008 /* Grab pause settings from PHY if configured to do so */ 1009 if (priv->aneg_pause) { 1010 rx_pause = tx_pause = phydev->pause; 1011 if (phydev->asym_pause) 1012 tx_pause = !rx_pause; 1013 } else { 1014 rx_pause = priv->rx_pause; 1015 tx_pause = priv->tx_pause; 1016 } 1017 1018 /* Link hasn't changed, do nothing */ 1019 if (phydev->speed == priv->cur_speed && 1020 phydev->duplex == priv->cur_duplex && 1021 rx_pause == priv->rx_pause && 1022 tx_pause == priv->tx_pause) 1023 return; 1024 1025 /* Print status if we have a link or we had one and just lost it, 1026 * don't print otherwise. 1027 */ 1028 if (new_speed || priv->cur_speed) 1029 phy_print_status(phydev); 1030 1031 priv->cur_speed = new_speed; 1032 priv->cur_duplex = phydev->duplex; 1033 priv->rx_pause = rx_pause; 1034 priv->tx_pause = tx_pause; 1035 1036 /* Link is down, do nothing else */ 1037 if (!new_speed) 1038 return; 1039 1040 /* Disable all interrupts */ 1041 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1042 1043 /* Reset the adapter asynchronously */ 1044 schedule_work(&priv->reset_task); 1045 } 1046 1047 static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf) 1048 { 1049 struct net_device *netdev = priv->netdev; 1050 struct phy_device *phydev; 1051 1052 phydev = phy_find_first(priv->mii_bus); 1053 if (!phydev) { 1054 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 1055 return -ENODEV; 1056 } 1057 1058 phydev = phy_connect(netdev, phydev_name(phydev), 1059 &ftgmac100_adjust_link, intf); 1060 1061 if (IS_ERR(phydev)) { 1062 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 1063 return PTR_ERR(phydev); 1064 } 1065 1066 /* Indicate that we support PAUSE frames (see comment in 1067 * Documentation/networking/phy.rst) 1068 */ 1069 phy_support_asym_pause(phydev); 1070 1071 /* Display what we found */ 1072 phy_attached_info(phydev); 1073 1074 return 0; 1075 } 1076 1077 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 1078 { 1079 struct net_device *netdev = bus->priv; 1080 struct ftgmac100 *priv = netdev_priv(netdev); 1081 unsigned int phycr; 1082 int i; 1083 1084 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1085 1086 /* preserve MDC cycle threshold */ 1087 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1088 1089 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1090 FTGMAC100_PHYCR_REGAD(regnum) | 1091 FTGMAC100_PHYCR_MIIRD; 1092 1093 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1094 1095 for (i = 0; i < 10; i++) { 1096 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1097 1098 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 1099 int data; 1100 1101 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 1102 return FTGMAC100_PHYDATA_MIIRDATA(data); 1103 } 1104 1105 udelay(100); 1106 } 1107 1108 netdev_err(netdev, "mdio read timed out\n"); 1109 return -EIO; 1110 } 1111 1112 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 1113 int regnum, u16 value) 1114 { 1115 struct net_device *netdev = bus->priv; 1116 struct ftgmac100 *priv = netdev_priv(netdev); 1117 unsigned int phycr; 1118 int data; 1119 int i; 1120 1121 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1122 1123 /* preserve MDC cycle threshold */ 1124 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1125 1126 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1127 FTGMAC100_PHYCR_REGAD(regnum) | 1128 FTGMAC100_PHYCR_MIIWR; 1129 1130 data = FTGMAC100_PHYDATA_MIIWDATA(value); 1131 1132 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 1133 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1134 1135 for (i = 0; i < 10; i++) { 1136 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1137 1138 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 1139 return 0; 1140 1141 udelay(100); 1142 } 1143 1144 netdev_err(netdev, "mdio write timed out\n"); 1145 return -EIO; 1146 } 1147 1148 static void ftgmac100_get_drvinfo(struct net_device *netdev, 1149 struct ethtool_drvinfo *info) 1150 { 1151 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1152 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); 1153 } 1154 1155 static void ftgmac100_get_ringparam(struct net_device *netdev, 1156 struct ethtool_ringparam *ering) 1157 { 1158 struct ftgmac100 *priv = netdev_priv(netdev); 1159 1160 memset(ering, 0, sizeof(*ering)); 1161 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES; 1162 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES; 1163 ering->rx_pending = priv->rx_q_entries; 1164 ering->tx_pending = priv->tx_q_entries; 1165 } 1166 1167 static int ftgmac100_set_ringparam(struct net_device *netdev, 1168 struct ethtool_ringparam *ering) 1169 { 1170 struct ftgmac100 *priv = netdev_priv(netdev); 1171 1172 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES || 1173 ering->tx_pending > MAX_TX_QUEUE_ENTRIES || 1174 ering->rx_pending < MIN_RX_QUEUE_ENTRIES || 1175 ering->tx_pending < MIN_TX_QUEUE_ENTRIES || 1176 !is_power_of_2(ering->rx_pending) || 1177 !is_power_of_2(ering->tx_pending)) 1178 return -EINVAL; 1179 1180 priv->new_rx_q_entries = ering->rx_pending; 1181 priv->new_tx_q_entries = ering->tx_pending; 1182 if (netif_running(netdev)) 1183 schedule_work(&priv->reset_task); 1184 1185 return 0; 1186 } 1187 1188 static void ftgmac100_get_pauseparam(struct net_device *netdev, 1189 struct ethtool_pauseparam *pause) 1190 { 1191 struct ftgmac100 *priv = netdev_priv(netdev); 1192 1193 pause->autoneg = priv->aneg_pause; 1194 pause->tx_pause = priv->tx_pause; 1195 pause->rx_pause = priv->rx_pause; 1196 } 1197 1198 static int ftgmac100_set_pauseparam(struct net_device *netdev, 1199 struct ethtool_pauseparam *pause) 1200 { 1201 struct ftgmac100 *priv = netdev_priv(netdev); 1202 struct phy_device *phydev = netdev->phydev; 1203 1204 priv->aneg_pause = pause->autoneg; 1205 priv->tx_pause = pause->tx_pause; 1206 priv->rx_pause = pause->rx_pause; 1207 1208 if (phydev) 1209 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); 1210 1211 if (netif_running(netdev)) { 1212 if (!(phydev && priv->aneg_pause)) 1213 ftgmac100_config_pause(priv); 1214 } 1215 1216 return 0; 1217 } 1218 1219 static const struct ethtool_ops ftgmac100_ethtool_ops = { 1220 .get_drvinfo = ftgmac100_get_drvinfo, 1221 .get_link = ethtool_op_get_link, 1222 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1223 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1224 .nway_reset = phy_ethtool_nway_reset, 1225 .get_ringparam = ftgmac100_get_ringparam, 1226 .set_ringparam = ftgmac100_set_ringparam, 1227 .get_pauseparam = ftgmac100_get_pauseparam, 1228 .set_pauseparam = ftgmac100_set_pauseparam, 1229 }; 1230 1231 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 1232 { 1233 struct net_device *netdev = dev_id; 1234 struct ftgmac100 *priv = netdev_priv(netdev); 1235 unsigned int status, new_mask = FTGMAC100_INT_BAD; 1236 1237 /* Fetch and clear interrupt bits, process abnormal ones */ 1238 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1239 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1240 if (unlikely(status & FTGMAC100_INT_BAD)) { 1241 1242 /* RX buffer unavailable */ 1243 if (status & FTGMAC100_INT_NO_RXBUF) 1244 netdev->stats.rx_over_errors++; 1245 1246 /* received packet lost due to RX FIFO full */ 1247 if (status & FTGMAC100_INT_RPKT_LOST) 1248 netdev->stats.rx_fifo_errors++; 1249 1250 /* sent packet lost due to excessive TX collision */ 1251 if (status & FTGMAC100_INT_XPKT_LOST) 1252 netdev->stats.tx_fifo_errors++; 1253 1254 /* AHB error -> Reset the chip */ 1255 if (status & FTGMAC100_INT_AHB_ERR) { 1256 if (net_ratelimit()) 1257 netdev_warn(netdev, 1258 "AHB bus error ! Resetting chip.\n"); 1259 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1260 schedule_work(&priv->reset_task); 1261 return IRQ_HANDLED; 1262 } 1263 1264 /* We may need to restart the MAC after such errors, delay 1265 * this until after we have freed some Rx buffers though 1266 */ 1267 priv->need_mac_restart = true; 1268 1269 /* Disable those errors until we restart */ 1270 new_mask &= ~status; 1271 } 1272 1273 /* Only enable "bad" interrupts while NAPI is on */ 1274 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER); 1275 1276 /* Schedule NAPI bh */ 1277 napi_schedule_irqoff(&priv->napi); 1278 1279 return IRQ_HANDLED; 1280 } 1281 1282 static bool ftgmac100_check_rx(struct ftgmac100 *priv) 1283 { 1284 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer]; 1285 1286 /* Do we have a packet ? */ 1287 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY)); 1288 } 1289 1290 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1291 { 1292 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1293 int work_done = 0; 1294 bool more; 1295 1296 /* Handle TX completions */ 1297 if (ftgmac100_tx_buf_cleanable(priv)) 1298 ftgmac100_tx_complete(priv); 1299 1300 /* Handle RX packets */ 1301 do { 1302 more = ftgmac100_rx_packet(priv, &work_done); 1303 } while (more && work_done < budget); 1304 1305 1306 /* The interrupt is telling us to kick the MAC back to life 1307 * after an RX overflow 1308 */ 1309 if (unlikely(priv->need_mac_restart)) { 1310 ftgmac100_start_hw(priv); 1311 1312 /* Re-enable "bad" interrupts */ 1313 iowrite32(FTGMAC100_INT_BAD, 1314 priv->base + FTGMAC100_OFFSET_IER); 1315 } 1316 1317 /* As long as we are waiting for transmit packets to be 1318 * completed we keep NAPI going 1319 */ 1320 if (ftgmac100_tx_buf_cleanable(priv)) 1321 work_done = budget; 1322 1323 if (work_done < budget) { 1324 /* We are about to re-enable all interrupts. However 1325 * the HW has been latching RX/TX packet interrupts while 1326 * they were masked. So we clear them first, then we need 1327 * to re-check if there's something to process 1328 */ 1329 iowrite32(FTGMAC100_INT_RXTX, 1330 priv->base + FTGMAC100_OFFSET_ISR); 1331 1332 /* Push the above (and provides a barrier vs. subsequent 1333 * reads of the descriptor). 1334 */ 1335 ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1336 1337 /* Check RX and TX descriptors for more work to do */ 1338 if (ftgmac100_check_rx(priv) || 1339 ftgmac100_tx_buf_cleanable(priv)) 1340 return budget; 1341 1342 /* deschedule NAPI */ 1343 napi_complete(napi); 1344 1345 /* enable all interrupts */ 1346 iowrite32(FTGMAC100_INT_ALL, 1347 priv->base + FTGMAC100_OFFSET_IER); 1348 } 1349 1350 return work_done; 1351 } 1352 1353 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err) 1354 { 1355 int err = 0; 1356 1357 /* Re-init descriptors (adjust queue sizes) */ 1358 ftgmac100_init_rings(priv); 1359 1360 /* Realloc rx descriptors */ 1361 err = ftgmac100_alloc_rx_buffers(priv); 1362 if (err && !ignore_alloc_err) 1363 return err; 1364 1365 /* Reinit and restart HW */ 1366 ftgmac100_init_hw(priv); 1367 ftgmac100_config_pause(priv); 1368 ftgmac100_start_hw(priv); 1369 1370 /* Re-enable the device */ 1371 napi_enable(&priv->napi); 1372 netif_start_queue(priv->netdev); 1373 1374 /* Enable all interrupts */ 1375 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER); 1376 1377 return err; 1378 } 1379 1380 static void ftgmac100_reset_task(struct work_struct *work) 1381 { 1382 struct ftgmac100 *priv = container_of(work, struct ftgmac100, 1383 reset_task); 1384 struct net_device *netdev = priv->netdev; 1385 int err; 1386 1387 netdev_dbg(netdev, "Resetting NIC...\n"); 1388 1389 /* Lock the world */ 1390 rtnl_lock(); 1391 if (netdev->phydev) 1392 mutex_lock(&netdev->phydev->lock); 1393 if (priv->mii_bus) 1394 mutex_lock(&priv->mii_bus->mdio_lock); 1395 1396 1397 /* Check if the interface is still up */ 1398 if (!netif_running(netdev)) 1399 goto bail; 1400 1401 /* Stop the network stack */ 1402 netif_trans_update(netdev); 1403 napi_disable(&priv->napi); 1404 netif_tx_disable(netdev); 1405 1406 /* Stop and reset the MAC */ 1407 ftgmac100_stop_hw(priv); 1408 err = ftgmac100_reset_and_config_mac(priv); 1409 if (err) { 1410 /* Not much we can do ... it might come back... */ 1411 netdev_err(netdev, "attempting to continue...\n"); 1412 } 1413 1414 /* Free all rx and tx buffers */ 1415 ftgmac100_free_buffers(priv); 1416 1417 /* Setup everything again and restart chip */ 1418 ftgmac100_init_all(priv, true); 1419 1420 netdev_dbg(netdev, "Reset done !\n"); 1421 bail: 1422 if (priv->mii_bus) 1423 mutex_unlock(&priv->mii_bus->mdio_lock); 1424 if (netdev->phydev) 1425 mutex_unlock(&netdev->phydev->lock); 1426 rtnl_unlock(); 1427 } 1428 1429 static int ftgmac100_open(struct net_device *netdev) 1430 { 1431 struct ftgmac100 *priv = netdev_priv(netdev); 1432 int err; 1433 1434 /* Allocate ring buffers */ 1435 err = ftgmac100_alloc_rings(priv); 1436 if (err) { 1437 netdev_err(netdev, "Failed to allocate descriptors\n"); 1438 return err; 1439 } 1440 1441 /* When using NC-SI we force the speed to 100Mbit/s full duplex, 1442 * 1443 * Otherwise we leave it set to 0 (no link), the link 1444 * message from the PHY layer will handle setting it up to 1445 * something else if needed. 1446 */ 1447 if (priv->use_ncsi) { 1448 priv->cur_duplex = DUPLEX_FULL; 1449 priv->cur_speed = SPEED_100; 1450 } else { 1451 priv->cur_duplex = 0; 1452 priv->cur_speed = 0; 1453 } 1454 1455 /* Reset the hardware */ 1456 err = ftgmac100_reset_and_config_mac(priv); 1457 if (err) 1458 goto err_hw; 1459 1460 /* Initialize NAPI */ 1461 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1462 1463 /* Grab our interrupt */ 1464 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1465 if (err) { 1466 netdev_err(netdev, "failed to request irq %d\n", netdev->irq); 1467 goto err_irq; 1468 } 1469 1470 /* Start things up */ 1471 err = ftgmac100_init_all(priv, false); 1472 if (err) { 1473 netdev_err(netdev, "Failed to allocate packet buffers\n"); 1474 goto err_alloc; 1475 } 1476 1477 if (netdev->phydev) { 1478 /* If we have a PHY, start polling */ 1479 phy_start(netdev->phydev); 1480 } else if (priv->use_ncsi) { 1481 /* If using NC-SI, set our carrier on and start the stack */ 1482 netif_carrier_on(netdev); 1483 1484 /* Start the NCSI device */ 1485 err = ncsi_start_dev(priv->ndev); 1486 if (err) 1487 goto err_ncsi; 1488 } 1489 1490 return 0; 1491 1492 err_ncsi: 1493 napi_disable(&priv->napi); 1494 netif_stop_queue(netdev); 1495 err_alloc: 1496 ftgmac100_free_buffers(priv); 1497 free_irq(netdev->irq, netdev); 1498 err_irq: 1499 netif_napi_del(&priv->napi); 1500 err_hw: 1501 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1502 ftgmac100_free_rings(priv); 1503 return err; 1504 } 1505 1506 static int ftgmac100_stop(struct net_device *netdev) 1507 { 1508 struct ftgmac100 *priv = netdev_priv(netdev); 1509 1510 /* Note about the reset task: We are called with the rtnl lock 1511 * held, so we are synchronized against the core of the reset 1512 * task. We must not try to synchronously cancel it otherwise 1513 * we can deadlock. But since it will test for netif_running() 1514 * which has already been cleared by the net core, we don't 1515 * anything special to do. 1516 */ 1517 1518 /* disable all interrupts */ 1519 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1520 1521 netif_stop_queue(netdev); 1522 napi_disable(&priv->napi); 1523 netif_napi_del(&priv->napi); 1524 if (netdev->phydev) 1525 phy_stop(netdev->phydev); 1526 else if (priv->use_ncsi) 1527 ncsi_stop_dev(priv->ndev); 1528 1529 ftgmac100_stop_hw(priv); 1530 free_irq(netdev->irq, netdev); 1531 ftgmac100_free_buffers(priv); 1532 ftgmac100_free_rings(priv); 1533 1534 return 0; 1535 } 1536 1537 static void ftgmac100_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1538 { 1539 struct ftgmac100 *priv = netdev_priv(netdev); 1540 1541 /* Disable all interrupts */ 1542 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1543 1544 /* Do the reset outside of interrupt context */ 1545 schedule_work(&priv->reset_task); 1546 } 1547 1548 static int ftgmac100_set_features(struct net_device *netdev, 1549 netdev_features_t features) 1550 { 1551 struct ftgmac100 *priv = netdev_priv(netdev); 1552 netdev_features_t changed = netdev->features ^ features; 1553 1554 if (!netif_running(netdev)) 1555 return 0; 1556 1557 /* Update the vlan filtering bit */ 1558 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 1559 u32 maccr; 1560 1561 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 1562 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 1563 maccr |= FTGMAC100_MACCR_RM_VLAN; 1564 else 1565 maccr &= ~FTGMAC100_MACCR_RM_VLAN; 1566 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 1567 } 1568 1569 return 0; 1570 } 1571 1572 #ifdef CONFIG_NET_POLL_CONTROLLER 1573 static void ftgmac100_poll_controller(struct net_device *netdev) 1574 { 1575 unsigned long flags; 1576 1577 local_irq_save(flags); 1578 ftgmac100_interrupt(netdev->irq, netdev); 1579 local_irq_restore(flags); 1580 } 1581 #endif 1582 1583 static const struct net_device_ops ftgmac100_netdev_ops = { 1584 .ndo_open = ftgmac100_open, 1585 .ndo_stop = ftgmac100_stop, 1586 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1587 .ndo_set_mac_address = ftgmac100_set_mac_addr, 1588 .ndo_validate_addr = eth_validate_addr, 1589 .ndo_do_ioctl = phy_do_ioctl, 1590 .ndo_tx_timeout = ftgmac100_tx_timeout, 1591 .ndo_set_rx_mode = ftgmac100_set_rx_mode, 1592 .ndo_set_features = ftgmac100_set_features, 1593 #ifdef CONFIG_NET_POLL_CONTROLLER 1594 .ndo_poll_controller = ftgmac100_poll_controller, 1595 #endif 1596 .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid, 1597 .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid, 1598 }; 1599 1600 static int ftgmac100_setup_mdio(struct net_device *netdev) 1601 { 1602 struct ftgmac100 *priv = netdev_priv(netdev); 1603 struct platform_device *pdev = to_platform_device(priv->dev); 1604 phy_interface_t phy_intf = PHY_INTERFACE_MODE_RGMII; 1605 struct device_node *np = pdev->dev.of_node; 1606 int i, err = 0; 1607 u32 reg; 1608 1609 /* initialize mdio bus */ 1610 priv->mii_bus = mdiobus_alloc(); 1611 if (!priv->mii_bus) 1612 return -EIO; 1613 1614 if (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1615 of_device_is_compatible(np, "aspeed,ast2500-mac")) { 1616 /* The AST2600 has a separate MDIO controller */ 1617 1618 /* For the AST2400 and AST2500 this driver only supports the 1619 * old MDIO interface 1620 */ 1621 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); 1622 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; 1623 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); 1624 } 1625 1626 /* Get PHY mode from device-tree */ 1627 if (np) { 1628 /* Default to RGMII. It's a gigabit part after all */ 1629 err = of_get_phy_mode(np, &phy_intf); 1630 if (err) 1631 phy_intf = PHY_INTERFACE_MODE_RGMII; 1632 1633 /* Aspeed only supports these. I don't know about other IP 1634 * block vendors so I'm going to just let them through for 1635 * now. Note that this is only a warning if for some obscure 1636 * reason the DT really means to lie about it or it's a newer 1637 * part we don't know about. 1638 * 1639 * On the Aspeed SoC there are additionally straps and SCU 1640 * control bits that could tell us what the interface is 1641 * (or allow us to configure it while the IP block is held 1642 * in reset). For now I chose to keep this driver away from 1643 * those SoC specific bits and assume the device-tree is 1644 * right and the SCU has been configured properly by pinmux 1645 * or the firmware. 1646 */ 1647 if (priv->is_aspeed && 1648 phy_intf != PHY_INTERFACE_MODE_RMII && 1649 phy_intf != PHY_INTERFACE_MODE_RGMII && 1650 phy_intf != PHY_INTERFACE_MODE_RGMII_ID && 1651 phy_intf != PHY_INTERFACE_MODE_RGMII_RXID && 1652 phy_intf != PHY_INTERFACE_MODE_RGMII_TXID) { 1653 netdev_warn(netdev, 1654 "Unsupported PHY mode %s !\n", 1655 phy_modes(phy_intf)); 1656 } 1657 } 1658 1659 priv->mii_bus->name = "ftgmac100_mdio"; 1660 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1661 pdev->name, pdev->id); 1662 priv->mii_bus->parent = priv->dev; 1663 priv->mii_bus->priv = priv->netdev; 1664 priv->mii_bus->read = ftgmac100_mdiobus_read; 1665 priv->mii_bus->write = ftgmac100_mdiobus_write; 1666 1667 for (i = 0; i < PHY_MAX_ADDR; i++) 1668 priv->mii_bus->irq[i] = PHY_POLL; 1669 1670 err = mdiobus_register(priv->mii_bus); 1671 if (err) { 1672 dev_err(priv->dev, "Cannot register MDIO bus!\n"); 1673 goto err_register_mdiobus; 1674 } 1675 1676 err = ftgmac100_mii_probe(priv, phy_intf); 1677 if (err) { 1678 dev_err(priv->dev, "MII Probe failed!\n"); 1679 goto err_mii_probe; 1680 } 1681 1682 return 0; 1683 1684 err_mii_probe: 1685 mdiobus_unregister(priv->mii_bus); 1686 err_register_mdiobus: 1687 mdiobus_free(priv->mii_bus); 1688 return err; 1689 } 1690 1691 static void ftgmac100_destroy_mdio(struct net_device *netdev) 1692 { 1693 struct ftgmac100 *priv = netdev_priv(netdev); 1694 1695 if (!netdev->phydev) 1696 return; 1697 1698 phy_disconnect(netdev->phydev); 1699 mdiobus_unregister(priv->mii_bus); 1700 mdiobus_free(priv->mii_bus); 1701 } 1702 1703 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) 1704 { 1705 if (unlikely(nd->state != ncsi_dev_state_functional)) 1706 return; 1707 1708 netdev_dbg(nd->dev, "NCSI interface %s\n", 1709 nd->link_up ? "up" : "down"); 1710 } 1711 1712 static int ftgmac100_setup_clk(struct ftgmac100 *priv) 1713 { 1714 struct clk *clk; 1715 int rc; 1716 1717 clk = devm_clk_get(priv->dev, NULL /* MACCLK */); 1718 if (IS_ERR(clk)) 1719 return PTR_ERR(clk); 1720 priv->clk = clk; 1721 rc = clk_prepare_enable(priv->clk); 1722 if (rc) 1723 return rc; 1724 1725 /* Aspeed specifies a 100MHz clock is required for up to 1726 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz 1727 * is sufficient 1728 */ 1729 rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ : 1730 FTGMAC_100MHZ); 1731 if (rc) 1732 goto cleanup_clk; 1733 1734 /* RCLK is for RMII, typically used for NCSI. Optional because it's not 1735 * necessary if it's the AST2400 MAC, or the MAC is configured for 1736 * RGMII, or the controller is not an ASPEED-based controller. 1737 */ 1738 priv->rclk = devm_clk_get_optional(priv->dev, "RCLK"); 1739 rc = clk_prepare_enable(priv->rclk); 1740 if (!rc) 1741 return 0; 1742 1743 cleanup_clk: 1744 clk_disable_unprepare(priv->clk); 1745 1746 return rc; 1747 } 1748 1749 static int ftgmac100_probe(struct platform_device *pdev) 1750 { 1751 struct resource *res; 1752 int irq; 1753 struct net_device *netdev; 1754 struct ftgmac100 *priv; 1755 struct device_node *np; 1756 int err = 0; 1757 1758 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1759 if (!res) 1760 return -ENXIO; 1761 1762 irq = platform_get_irq(pdev, 0); 1763 if (irq < 0) 1764 return irq; 1765 1766 /* setup net_device */ 1767 netdev = alloc_etherdev(sizeof(*priv)); 1768 if (!netdev) { 1769 err = -ENOMEM; 1770 goto err_alloc_etherdev; 1771 } 1772 1773 SET_NETDEV_DEV(netdev, &pdev->dev); 1774 1775 netdev->ethtool_ops = &ftgmac100_ethtool_ops; 1776 netdev->netdev_ops = &ftgmac100_netdev_ops; 1777 netdev->watchdog_timeo = 5 * HZ; 1778 1779 platform_set_drvdata(pdev, netdev); 1780 1781 /* setup private data */ 1782 priv = netdev_priv(netdev); 1783 priv->netdev = netdev; 1784 priv->dev = &pdev->dev; 1785 INIT_WORK(&priv->reset_task, ftgmac100_reset_task); 1786 1787 /* map io memory */ 1788 priv->res = request_mem_region(res->start, resource_size(res), 1789 dev_name(&pdev->dev)); 1790 if (!priv->res) { 1791 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1792 err = -ENOMEM; 1793 goto err_req_mem; 1794 } 1795 1796 priv->base = ioremap(res->start, resource_size(res)); 1797 if (!priv->base) { 1798 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1799 err = -EIO; 1800 goto err_ioremap; 1801 } 1802 1803 netdev->irq = irq; 1804 1805 /* Enable pause */ 1806 priv->tx_pause = true; 1807 priv->rx_pause = true; 1808 priv->aneg_pause = true; 1809 1810 /* MAC address from chip or random one */ 1811 ftgmac100_initial_mac(priv); 1812 1813 np = pdev->dev.of_node; 1814 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1815 of_device_is_compatible(np, "aspeed,ast2500-mac") || 1816 of_device_is_compatible(np, "aspeed,ast2600-mac"))) { 1817 priv->rxdes0_edorr_mask = BIT(30); 1818 priv->txdes0_edotr_mask = BIT(30); 1819 priv->is_aspeed = true; 1820 /* Disable ast2600 problematic HW arbitration */ 1821 if (of_device_is_compatible(np, "aspeed,ast2600-mac")) { 1822 iowrite32(FTGMAC100_TM_DEFAULT, 1823 priv->base + FTGMAC100_OFFSET_TM); 1824 } 1825 } else { 1826 priv->rxdes0_edorr_mask = BIT(15); 1827 priv->txdes0_edotr_mask = BIT(15); 1828 } 1829 1830 if (np && of_get_property(np, "use-ncsi", NULL)) { 1831 if (!IS_ENABLED(CONFIG_NET_NCSI)) { 1832 dev_err(&pdev->dev, "NCSI stack not enabled\n"); 1833 goto err_ncsi_dev; 1834 } 1835 1836 dev_info(&pdev->dev, "Using NCSI interface\n"); 1837 priv->use_ncsi = true; 1838 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); 1839 if (!priv->ndev) 1840 goto err_ncsi_dev; 1841 } else if (np && of_get_property(np, "phy-handle", NULL)) { 1842 struct phy_device *phy; 1843 1844 phy = of_phy_get_and_connect(priv->netdev, np, 1845 &ftgmac100_adjust_link); 1846 if (!phy) { 1847 dev_err(&pdev->dev, "Failed to connect to phy\n"); 1848 goto err_setup_mdio; 1849 } 1850 1851 /* Indicate that we support PAUSE frames (see comment in 1852 * Documentation/networking/phy.rst) 1853 */ 1854 phy_support_asym_pause(phy); 1855 1856 /* Display what we found */ 1857 phy_attached_info(phy); 1858 } else if (np && !of_get_child_by_name(np, "mdio")) { 1859 /* Support legacy ASPEED devicetree descriptions that decribe a 1860 * MAC with an embedded MDIO controller but have no "mdio" 1861 * child node. Automatically scan the MDIO bus for available 1862 * PHYs. 1863 */ 1864 priv->use_ncsi = false; 1865 err = ftgmac100_setup_mdio(netdev); 1866 if (err) 1867 goto err_setup_mdio; 1868 } 1869 1870 if (priv->is_aspeed) { 1871 err = ftgmac100_setup_clk(priv); 1872 if (err) 1873 goto err_ncsi_dev; 1874 } 1875 1876 /* Default ring sizes */ 1877 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES; 1878 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES; 1879 1880 /* Base feature set */ 1881 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM | 1882 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX | 1883 NETIF_F_HW_VLAN_CTAG_TX; 1884 1885 if (priv->use_ncsi) 1886 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1887 1888 /* AST2400 doesn't have working HW checksum generation */ 1889 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac"))) 1890 netdev->hw_features &= ~NETIF_F_HW_CSUM; 1891 if (np && of_get_property(np, "no-hw-checksum", NULL)) 1892 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM); 1893 netdev->features |= netdev->hw_features; 1894 1895 /* register network device */ 1896 err = register_netdev(netdev); 1897 if (err) { 1898 dev_err(&pdev->dev, "Failed to register netdev\n"); 1899 goto err_register_netdev; 1900 } 1901 1902 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base); 1903 1904 return 0; 1905 1906 err_register_netdev: 1907 clk_disable_unprepare(priv->rclk); 1908 clk_disable_unprepare(priv->clk); 1909 err_ncsi_dev: 1910 if (priv->ndev) 1911 ncsi_unregister_dev(priv->ndev); 1912 ftgmac100_destroy_mdio(netdev); 1913 err_setup_mdio: 1914 iounmap(priv->base); 1915 err_ioremap: 1916 release_resource(priv->res); 1917 err_req_mem: 1918 free_netdev(netdev); 1919 err_alloc_etherdev: 1920 return err; 1921 } 1922 1923 static int ftgmac100_remove(struct platform_device *pdev) 1924 { 1925 struct net_device *netdev; 1926 struct ftgmac100 *priv; 1927 1928 netdev = platform_get_drvdata(pdev); 1929 priv = netdev_priv(netdev); 1930 1931 if (priv->ndev) 1932 ncsi_unregister_dev(priv->ndev); 1933 unregister_netdev(netdev); 1934 1935 clk_disable_unprepare(priv->rclk); 1936 clk_disable_unprepare(priv->clk); 1937 1938 /* There's a small chance the reset task will have been re-queued, 1939 * during stop, make sure it's gone before we free the structure. 1940 */ 1941 cancel_work_sync(&priv->reset_task); 1942 1943 ftgmac100_destroy_mdio(netdev); 1944 1945 iounmap(priv->base); 1946 release_resource(priv->res); 1947 1948 netif_napi_del(&priv->napi); 1949 free_netdev(netdev); 1950 return 0; 1951 } 1952 1953 static const struct of_device_id ftgmac100_of_match[] = { 1954 { .compatible = "faraday,ftgmac100" }, 1955 { } 1956 }; 1957 MODULE_DEVICE_TABLE(of, ftgmac100_of_match); 1958 1959 static struct platform_driver ftgmac100_driver = { 1960 .probe = ftgmac100_probe, 1961 .remove = ftgmac100_remove, 1962 .driver = { 1963 .name = DRV_NAME, 1964 .of_match_table = ftgmac100_of_match, 1965 }, 1966 }; 1967 module_platform_driver(ftgmac100_driver); 1968 1969 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1970 MODULE_DESCRIPTION("FTGMAC100 driver"); 1971 MODULE_LICENSE("GPL"); 1972