1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * (C) Copyright 2009-2011 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/dma-mapping.h> 25 #include <linux/etherdevice.h> 26 #include <linux/ethtool.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/phy.h> 32 #include <linux/platform_device.h> 33 #include <net/ip.h> 34 #include <net/ncsi.h> 35 36 #include "ftgmac100.h" 37 38 #define DRV_NAME "ftgmac100" 39 #define DRV_VERSION "0.7" 40 41 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */ 42 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */ 43 44 #define MAX_PKT_SIZE 1518 45 #define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */ 46 47 /****************************************************************************** 48 * private data 49 *****************************************************************************/ 50 struct ftgmac100_descs { 51 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES]; 52 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES]; 53 }; 54 55 struct ftgmac100 { 56 struct resource *res; 57 void __iomem *base; 58 int irq; 59 60 struct ftgmac100_descs *descs; 61 dma_addr_t descs_dma_addr; 62 63 struct page *rx_pages[RX_QUEUE_ENTRIES]; 64 65 unsigned int rx_pointer; 66 unsigned int tx_clean_pointer; 67 unsigned int tx_pointer; 68 unsigned int tx_pending; 69 70 spinlock_t tx_lock; 71 72 struct net_device *netdev; 73 struct device *dev; 74 struct ncsi_dev *ndev; 75 struct napi_struct napi; 76 77 struct mii_bus *mii_bus; 78 int old_speed; 79 int int_mask_all; 80 bool use_ncsi; 81 bool enabled; 82 83 u32 rxdes0_edorr_mask; 84 u32 txdes0_edotr_mask; 85 }; 86 87 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, 88 struct ftgmac100_rxdes *rxdes, gfp_t gfp); 89 90 /****************************************************************************** 91 * internal functions (hardware register access) 92 *****************************************************************************/ 93 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr) 94 { 95 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR); 96 } 97 98 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv, 99 unsigned int size) 100 { 101 size = FTGMAC100_RBSR_SIZE(size); 102 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR); 103 } 104 105 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv, 106 dma_addr_t addr) 107 { 108 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 109 } 110 111 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv) 112 { 113 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 114 } 115 116 static int ftgmac100_reset_hw(struct ftgmac100 *priv) 117 { 118 struct net_device *netdev = priv->netdev; 119 int i; 120 121 /* NOTE: reset clears all registers */ 122 iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR); 123 for (i = 0; i < 5; i++) { 124 unsigned int maccr; 125 126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 127 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 128 return 0; 129 130 udelay(1000); 131 } 132 133 netdev_err(netdev, "software reset failed\n"); 134 return -EIO; 135 } 136 137 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac) 138 { 139 unsigned int maddr = mac[0] << 8 | mac[1]; 140 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 141 142 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 143 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 144 } 145 146 static void ftgmac100_setup_mac(struct ftgmac100 *priv) 147 { 148 u8 mac[ETH_ALEN]; 149 unsigned int m; 150 unsigned int l; 151 void *addr; 152 153 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN); 154 if (addr) { 155 ether_addr_copy(priv->netdev->dev_addr, mac); 156 dev_info(priv->dev, "Read MAC address %pM from device tree\n", 157 mac); 158 return; 159 } 160 161 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); 162 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); 163 164 mac[0] = (m >> 8) & 0xff; 165 mac[1] = m & 0xff; 166 mac[2] = (l >> 24) & 0xff; 167 mac[3] = (l >> 16) & 0xff; 168 mac[4] = (l >> 8) & 0xff; 169 mac[5] = l & 0xff; 170 171 if (is_valid_ether_addr(mac)) { 172 ether_addr_copy(priv->netdev->dev_addr, mac); 173 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac); 174 } else { 175 eth_hw_addr_random(priv->netdev); 176 dev_info(priv->dev, "Generated random MAC address %pM\n", 177 priv->netdev->dev_addr); 178 } 179 } 180 181 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p) 182 { 183 int ret; 184 185 ret = eth_prepare_mac_addr_change(dev, p); 186 if (ret < 0) 187 return ret; 188 189 eth_commit_mac_addr_change(dev, p); 190 ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr); 191 192 return 0; 193 } 194 195 static void ftgmac100_init_hw(struct ftgmac100 *priv) 196 { 197 /* setup ring buffer base registers */ 198 ftgmac100_set_rx_ring_base(priv, 199 priv->descs_dma_addr + 200 offsetof(struct ftgmac100_descs, rxdes)); 201 ftgmac100_set_normal_prio_tx_ring_base(priv, 202 priv->descs_dma_addr + 203 offsetof(struct ftgmac100_descs, txdes)); 204 205 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE); 206 207 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC); 208 209 ftgmac100_set_mac(priv, priv->netdev->dev_addr); 210 } 211 212 #define MACCR_ENABLE_ALL (FTGMAC100_MACCR_TXDMA_EN | \ 213 FTGMAC100_MACCR_RXDMA_EN | \ 214 FTGMAC100_MACCR_TXMAC_EN | \ 215 FTGMAC100_MACCR_RXMAC_EN | \ 216 FTGMAC100_MACCR_FULLDUP | \ 217 FTGMAC100_MACCR_CRC_APD | \ 218 FTGMAC100_MACCR_RX_RUNT | \ 219 FTGMAC100_MACCR_RX_BROADPKT) 220 221 static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed) 222 { 223 int maccr = MACCR_ENABLE_ALL; 224 225 switch (speed) { 226 default: 227 case 10: 228 break; 229 230 case 100: 231 maccr |= FTGMAC100_MACCR_FAST_MODE; 232 break; 233 234 case 1000: 235 maccr |= FTGMAC100_MACCR_GIGA_MODE; 236 break; 237 } 238 239 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 240 } 241 242 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 243 { 244 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 245 } 246 247 /****************************************************************************** 248 * internal functions (receive descriptor) 249 *****************************************************************************/ 250 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes) 251 { 252 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS); 253 } 254 255 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes) 256 { 257 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS); 258 } 259 260 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes) 261 { 262 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY); 263 } 264 265 static void ftgmac100_rxdes_set_dma_own(const struct ftgmac100 *priv, 266 struct ftgmac100_rxdes *rxdes) 267 { 268 /* clear status bits */ 269 rxdes->rxdes0 &= cpu_to_le32(priv->rxdes0_edorr_mask); 270 } 271 272 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes) 273 { 274 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR); 275 } 276 277 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes) 278 { 279 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR); 280 } 281 282 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes) 283 { 284 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL); 285 } 286 287 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes) 288 { 289 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT); 290 } 291 292 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes) 293 { 294 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB); 295 } 296 297 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes) 298 { 299 return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC; 300 } 301 302 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes) 303 { 304 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST); 305 } 306 307 static void ftgmac100_rxdes_set_end_of_ring(const struct ftgmac100 *priv, 308 struct ftgmac100_rxdes *rxdes) 309 { 310 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); 311 } 312 313 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes, 314 dma_addr_t addr) 315 { 316 rxdes->rxdes3 = cpu_to_le32(addr); 317 } 318 319 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes) 320 { 321 return le32_to_cpu(rxdes->rxdes3); 322 } 323 324 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes) 325 { 326 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == 327 cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP); 328 } 329 330 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes) 331 { 332 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == 333 cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP); 334 } 335 336 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes) 337 { 338 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR); 339 } 340 341 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes) 342 { 343 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR); 344 } 345 346 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes) 347 { 348 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR); 349 } 350 351 static inline struct page **ftgmac100_rxdes_page_slot(struct ftgmac100 *priv, 352 struct ftgmac100_rxdes *rxdes) 353 { 354 return &priv->rx_pages[rxdes - priv->descs->rxdes]; 355 } 356 357 /* 358 * rxdes2 is not used by hardware. We use it to keep track of page. 359 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). 360 */ 361 static void ftgmac100_rxdes_set_page(struct ftgmac100 *priv, 362 struct ftgmac100_rxdes *rxdes, 363 struct page *page) 364 { 365 *ftgmac100_rxdes_page_slot(priv, rxdes) = page; 366 } 367 368 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100 *priv, 369 struct ftgmac100_rxdes *rxdes) 370 { 371 return *ftgmac100_rxdes_page_slot(priv, rxdes); 372 } 373 374 /****************************************************************************** 375 * internal functions (receive) 376 *****************************************************************************/ 377 static int ftgmac100_next_rx_pointer(int pointer) 378 { 379 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1); 380 } 381 382 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv) 383 { 384 priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer); 385 } 386 387 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv) 388 { 389 return &priv->descs->rxdes[priv->rx_pointer]; 390 } 391 392 static struct ftgmac100_rxdes * 393 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv) 394 { 395 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); 396 397 while (ftgmac100_rxdes_packet_ready(rxdes)) { 398 if (ftgmac100_rxdes_first_segment(rxdes)) 399 return rxdes; 400 401 ftgmac100_rxdes_set_dma_own(priv, rxdes); 402 ftgmac100_rx_pointer_advance(priv); 403 rxdes = ftgmac100_current_rxdes(priv); 404 } 405 406 return NULL; 407 } 408 409 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv, 410 struct ftgmac100_rxdes *rxdes) 411 { 412 struct net_device *netdev = priv->netdev; 413 bool error = false; 414 415 if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) { 416 if (net_ratelimit()) 417 netdev_info(netdev, "rx err\n"); 418 419 netdev->stats.rx_errors++; 420 error = true; 421 } 422 423 if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) { 424 if (net_ratelimit()) 425 netdev_info(netdev, "rx crc err\n"); 426 427 netdev->stats.rx_crc_errors++; 428 error = true; 429 } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) { 430 if (net_ratelimit()) 431 netdev_info(netdev, "rx IP checksum err\n"); 432 433 error = true; 434 } 435 436 if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) { 437 if (net_ratelimit()) 438 netdev_info(netdev, "rx frame too long\n"); 439 440 netdev->stats.rx_length_errors++; 441 error = true; 442 } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) { 443 if (net_ratelimit()) 444 netdev_info(netdev, "rx runt\n"); 445 446 netdev->stats.rx_length_errors++; 447 error = true; 448 } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) { 449 if (net_ratelimit()) 450 netdev_info(netdev, "rx odd nibble\n"); 451 452 netdev->stats.rx_length_errors++; 453 error = true; 454 } 455 456 return error; 457 } 458 459 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv) 460 { 461 struct net_device *netdev = priv->netdev; 462 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); 463 bool done = false; 464 465 if (net_ratelimit()) 466 netdev_dbg(netdev, "drop packet %p\n", rxdes); 467 468 do { 469 if (ftgmac100_rxdes_last_segment(rxdes)) 470 done = true; 471 472 ftgmac100_rxdes_set_dma_own(priv, rxdes); 473 ftgmac100_rx_pointer_advance(priv); 474 rxdes = ftgmac100_current_rxdes(priv); 475 } while (!done && ftgmac100_rxdes_packet_ready(rxdes)); 476 477 netdev->stats.rx_dropped++; 478 } 479 480 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 481 { 482 struct net_device *netdev = priv->netdev; 483 struct ftgmac100_rxdes *rxdes; 484 struct sk_buff *skb; 485 bool done = false; 486 487 rxdes = ftgmac100_rx_locate_first_segment(priv); 488 if (!rxdes) 489 return false; 490 491 if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) { 492 ftgmac100_rx_drop_packet(priv); 493 return true; 494 } 495 496 /* start processing */ 497 skb = netdev_alloc_skb_ip_align(netdev, 128); 498 if (unlikely(!skb)) { 499 if (net_ratelimit()) 500 netdev_err(netdev, "rx skb alloc failed\n"); 501 502 ftgmac100_rx_drop_packet(priv); 503 return true; 504 } 505 506 if (unlikely(ftgmac100_rxdes_multicast(rxdes))) 507 netdev->stats.multicast++; 508 509 /* 510 * It seems that HW does checksum incorrectly with fragmented packets, 511 * so we are conservative here - if HW checksum error, let software do 512 * the checksum again. 513 */ 514 if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) || 515 (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes))) 516 skb->ip_summed = CHECKSUM_UNNECESSARY; 517 518 do { 519 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); 520 struct page *page = ftgmac100_rxdes_get_page(priv, rxdes); 521 unsigned int size; 522 523 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 524 525 size = ftgmac100_rxdes_data_length(rxdes); 526 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size); 527 528 skb->len += size; 529 skb->data_len += size; 530 skb->truesize += PAGE_SIZE; 531 532 if (ftgmac100_rxdes_last_segment(rxdes)) 533 done = true; 534 535 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC); 536 537 ftgmac100_rx_pointer_advance(priv); 538 rxdes = ftgmac100_current_rxdes(priv); 539 } while (!done); 540 541 /* Small frames are copied into linear part of skb to free one page */ 542 if (skb->len <= 128) { 543 skb->truesize -= PAGE_SIZE; 544 __pskb_pull_tail(skb, skb->len); 545 } else { 546 /* We pull the minimum amount into linear part */ 547 __pskb_pull_tail(skb, ETH_HLEN); 548 } 549 skb->protocol = eth_type_trans(skb, netdev); 550 551 netdev->stats.rx_packets++; 552 netdev->stats.rx_bytes += skb->len; 553 554 /* push packet to protocol stack */ 555 napi_gro_receive(&priv->napi, skb); 556 557 (*processed)++; 558 return true; 559 } 560 561 /****************************************************************************** 562 * internal functions (transmit descriptor) 563 *****************************************************************************/ 564 static void ftgmac100_txdes_reset(const struct ftgmac100 *priv, 565 struct ftgmac100_txdes *txdes) 566 { 567 /* clear all except end of ring bit */ 568 txdes->txdes0 &= cpu_to_le32(priv->txdes0_edotr_mask); 569 txdes->txdes1 = 0; 570 txdes->txdes2 = 0; 571 txdes->txdes3 = 0; 572 } 573 574 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes) 575 { 576 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); 577 } 578 579 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes) 580 { 581 /* 582 * Make sure dma own bit will not be set before any other 583 * descriptor fields. 584 */ 585 wmb(); 586 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); 587 } 588 589 static void ftgmac100_txdes_set_end_of_ring(const struct ftgmac100 *priv, 590 struct ftgmac100_txdes *txdes) 591 { 592 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask); 593 } 594 595 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes) 596 { 597 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS); 598 } 599 600 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes) 601 { 602 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS); 603 } 604 605 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes, 606 unsigned int len) 607 { 608 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len)); 609 } 610 611 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes) 612 { 613 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC); 614 } 615 616 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes) 617 { 618 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM); 619 } 620 621 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes) 622 { 623 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM); 624 } 625 626 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes) 627 { 628 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM); 629 } 630 631 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes, 632 dma_addr_t addr) 633 { 634 txdes->txdes3 = cpu_to_le32(addr); 635 } 636 637 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes) 638 { 639 return le32_to_cpu(txdes->txdes3); 640 } 641 642 /* 643 * txdes2 is not used by hardware. We use it to keep track of socket buffer. 644 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). 645 */ 646 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes, 647 struct sk_buff *skb) 648 { 649 txdes->txdes2 = (unsigned int)skb; 650 } 651 652 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes) 653 { 654 return (struct sk_buff *)txdes->txdes2; 655 } 656 657 /****************************************************************************** 658 * internal functions (transmit) 659 *****************************************************************************/ 660 static int ftgmac100_next_tx_pointer(int pointer) 661 { 662 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1); 663 } 664 665 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv) 666 { 667 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer); 668 } 669 670 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv) 671 { 672 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer); 673 } 674 675 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv) 676 { 677 return &priv->descs->txdes[priv->tx_pointer]; 678 } 679 680 static struct ftgmac100_txdes * 681 ftgmac100_current_clean_txdes(struct ftgmac100 *priv) 682 { 683 return &priv->descs->txdes[priv->tx_clean_pointer]; 684 } 685 686 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 687 { 688 struct net_device *netdev = priv->netdev; 689 struct ftgmac100_txdes *txdes; 690 struct sk_buff *skb; 691 dma_addr_t map; 692 693 if (priv->tx_pending == 0) 694 return false; 695 696 txdes = ftgmac100_current_clean_txdes(priv); 697 698 if (ftgmac100_txdes_owned_by_dma(txdes)) 699 return false; 700 701 skb = ftgmac100_txdes_get_skb(txdes); 702 map = ftgmac100_txdes_get_dma_addr(txdes); 703 704 netdev->stats.tx_packets++; 705 netdev->stats.tx_bytes += skb->len; 706 707 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); 708 709 dev_kfree_skb(skb); 710 711 ftgmac100_txdes_reset(priv, txdes); 712 713 ftgmac100_tx_clean_pointer_advance(priv); 714 715 spin_lock(&priv->tx_lock); 716 priv->tx_pending--; 717 spin_unlock(&priv->tx_lock); 718 netif_wake_queue(netdev); 719 720 return true; 721 } 722 723 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 724 { 725 while (ftgmac100_tx_complete_packet(priv)) 726 ; 727 } 728 729 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb, 730 dma_addr_t map) 731 { 732 struct net_device *netdev = priv->netdev; 733 struct ftgmac100_txdes *txdes; 734 unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len; 735 736 txdes = ftgmac100_current_txdes(priv); 737 ftgmac100_tx_pointer_advance(priv); 738 739 /* setup TX descriptor */ 740 ftgmac100_txdes_set_skb(txdes, skb); 741 ftgmac100_txdes_set_dma_addr(txdes, map); 742 ftgmac100_txdes_set_buffer_size(txdes, len); 743 744 ftgmac100_txdes_set_first_segment(txdes); 745 ftgmac100_txdes_set_last_segment(txdes); 746 ftgmac100_txdes_set_txint(txdes); 747 if (skb->ip_summed == CHECKSUM_PARTIAL) { 748 __be16 protocol = skb->protocol; 749 750 if (protocol == cpu_to_be16(ETH_P_IP)) { 751 u8 ip_proto = ip_hdr(skb)->protocol; 752 753 ftgmac100_txdes_set_ipcs(txdes); 754 if (ip_proto == IPPROTO_TCP) 755 ftgmac100_txdes_set_tcpcs(txdes); 756 else if (ip_proto == IPPROTO_UDP) 757 ftgmac100_txdes_set_udpcs(txdes); 758 } 759 } 760 761 spin_lock(&priv->tx_lock); 762 priv->tx_pending++; 763 if (priv->tx_pending == TX_QUEUE_ENTRIES) 764 netif_stop_queue(netdev); 765 766 /* start transmit */ 767 ftgmac100_txdes_set_dma_own(txdes); 768 spin_unlock(&priv->tx_lock); 769 770 ftgmac100_txdma_normal_prio_start_polling(priv); 771 772 return NETDEV_TX_OK; 773 } 774 775 /****************************************************************************** 776 * internal functions (buffer) 777 *****************************************************************************/ 778 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, 779 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 780 { 781 struct net_device *netdev = priv->netdev; 782 struct page *page; 783 dma_addr_t map; 784 785 page = alloc_page(gfp); 786 if (!page) { 787 if (net_ratelimit()) 788 netdev_err(netdev, "failed to allocate rx page\n"); 789 return -ENOMEM; 790 } 791 792 map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE); 793 if (unlikely(dma_mapping_error(priv->dev, map))) { 794 if (net_ratelimit()) 795 netdev_err(netdev, "failed to map rx page\n"); 796 __free_page(page); 797 return -ENOMEM; 798 } 799 800 ftgmac100_rxdes_set_page(priv, rxdes, page); 801 ftgmac100_rxdes_set_dma_addr(rxdes, map); 802 ftgmac100_rxdes_set_dma_own(priv, rxdes); 803 return 0; 804 } 805 806 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 807 { 808 int i; 809 810 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 811 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 812 struct page *page = ftgmac100_rxdes_get_page(priv, rxdes); 813 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); 814 815 if (!page) 816 continue; 817 818 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 819 __free_page(page); 820 } 821 822 for (i = 0; i < TX_QUEUE_ENTRIES; i++) { 823 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i]; 824 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes); 825 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes); 826 827 if (!skb) 828 continue; 829 830 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); 831 kfree_skb(skb); 832 } 833 834 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs), 835 priv->descs, priv->descs_dma_addr); 836 } 837 838 static int ftgmac100_alloc_buffers(struct ftgmac100 *priv) 839 { 840 int i; 841 842 priv->descs = dma_zalloc_coherent(priv->dev, 843 sizeof(struct ftgmac100_descs), 844 &priv->descs_dma_addr, GFP_KERNEL); 845 if (!priv->descs) 846 return -ENOMEM; 847 848 /* initialize RX ring */ 849 ftgmac100_rxdes_set_end_of_ring(priv, 850 &priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); 851 852 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 853 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 854 855 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL)) 856 goto err; 857 } 858 859 /* initialize TX ring */ 860 ftgmac100_txdes_set_end_of_ring(priv, 861 &priv->descs->txdes[TX_QUEUE_ENTRIES - 1]); 862 return 0; 863 864 err: 865 ftgmac100_free_buffers(priv); 866 return -ENOMEM; 867 } 868 869 /****************************************************************************** 870 * internal functions (mdio) 871 *****************************************************************************/ 872 static void ftgmac100_adjust_link(struct net_device *netdev) 873 { 874 struct ftgmac100 *priv = netdev_priv(netdev); 875 struct phy_device *phydev = netdev->phydev; 876 int ier; 877 878 if (phydev->speed == priv->old_speed) 879 return; 880 881 priv->old_speed = phydev->speed; 882 883 ier = ioread32(priv->base + FTGMAC100_OFFSET_IER); 884 885 /* disable all interrupts */ 886 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 887 888 netif_stop_queue(netdev); 889 ftgmac100_stop_hw(priv); 890 891 netif_start_queue(netdev); 892 ftgmac100_init_hw(priv); 893 ftgmac100_start_hw(priv, phydev->speed); 894 895 /* re-enable interrupts */ 896 iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER); 897 } 898 899 static int ftgmac100_mii_probe(struct ftgmac100 *priv) 900 { 901 struct net_device *netdev = priv->netdev; 902 struct phy_device *phydev; 903 904 phydev = phy_find_first(priv->mii_bus); 905 if (!phydev) { 906 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 907 return -ENODEV; 908 } 909 910 phydev = phy_connect(netdev, phydev_name(phydev), 911 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII); 912 913 if (IS_ERR(phydev)) { 914 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 915 return PTR_ERR(phydev); 916 } 917 918 return 0; 919 } 920 921 /****************************************************************************** 922 * struct mii_bus functions 923 *****************************************************************************/ 924 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 925 { 926 struct net_device *netdev = bus->priv; 927 struct ftgmac100 *priv = netdev_priv(netdev); 928 unsigned int phycr; 929 int i; 930 931 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 932 933 /* preserve MDC cycle threshold */ 934 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 935 936 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 937 FTGMAC100_PHYCR_REGAD(regnum) | 938 FTGMAC100_PHYCR_MIIRD; 939 940 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 941 942 for (i = 0; i < 10; i++) { 943 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 944 945 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 946 int data; 947 948 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 949 return FTGMAC100_PHYDATA_MIIRDATA(data); 950 } 951 952 udelay(100); 953 } 954 955 netdev_err(netdev, "mdio read timed out\n"); 956 return -EIO; 957 } 958 959 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 960 int regnum, u16 value) 961 { 962 struct net_device *netdev = bus->priv; 963 struct ftgmac100 *priv = netdev_priv(netdev); 964 unsigned int phycr; 965 int data; 966 int i; 967 968 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 969 970 /* preserve MDC cycle threshold */ 971 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 972 973 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 974 FTGMAC100_PHYCR_REGAD(regnum) | 975 FTGMAC100_PHYCR_MIIWR; 976 977 data = FTGMAC100_PHYDATA_MIIWDATA(value); 978 979 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 980 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 981 982 for (i = 0; i < 10; i++) { 983 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 984 985 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 986 return 0; 987 988 udelay(100); 989 } 990 991 netdev_err(netdev, "mdio write timed out\n"); 992 return -EIO; 993 } 994 995 /****************************************************************************** 996 * struct ethtool_ops functions 997 *****************************************************************************/ 998 static void ftgmac100_get_drvinfo(struct net_device *netdev, 999 struct ethtool_drvinfo *info) 1000 { 1001 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1002 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1003 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); 1004 } 1005 1006 static const struct ethtool_ops ftgmac100_ethtool_ops = { 1007 .get_drvinfo = ftgmac100_get_drvinfo, 1008 .get_link = ethtool_op_get_link, 1009 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1010 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1011 }; 1012 1013 /****************************************************************************** 1014 * interrupt handler 1015 *****************************************************************************/ 1016 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 1017 { 1018 struct net_device *netdev = dev_id; 1019 struct ftgmac100 *priv = netdev_priv(netdev); 1020 1021 /* When running in NCSI mode, the interface should be ready for 1022 * receiving or transmitting NCSI packets before it's opened. 1023 */ 1024 if (likely(priv->use_ncsi || netif_running(netdev))) { 1025 /* Disable interrupts for polling */ 1026 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1027 napi_schedule(&priv->napi); 1028 } 1029 1030 return IRQ_HANDLED; 1031 } 1032 1033 /****************************************************************************** 1034 * struct napi_struct functions 1035 *****************************************************************************/ 1036 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1037 { 1038 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1039 struct net_device *netdev = priv->netdev; 1040 unsigned int status; 1041 bool completed = true; 1042 int rx = 0; 1043 1044 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1045 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1046 1047 if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) { 1048 /* 1049 * FTGMAC100_INT_RPKT_BUF: 1050 * RX DMA has received packets into RX buffer successfully 1051 * 1052 * FTGMAC100_INT_NO_RXBUF: 1053 * RX buffer unavailable 1054 */ 1055 bool retry; 1056 1057 do { 1058 retry = ftgmac100_rx_packet(priv, &rx); 1059 } while (retry && rx < budget); 1060 1061 if (retry && rx == budget) 1062 completed = false; 1063 } 1064 1065 if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) { 1066 /* 1067 * FTGMAC100_INT_XPKT_ETH: 1068 * packet transmitted to ethernet successfully 1069 * 1070 * FTGMAC100_INT_XPKT_LOST: 1071 * packet transmitted to ethernet lost due to late 1072 * collision or excessive collision 1073 */ 1074 ftgmac100_tx_complete(priv); 1075 } 1076 1077 if (status & priv->int_mask_all & (FTGMAC100_INT_NO_RXBUF | 1078 FTGMAC100_INT_RPKT_LOST | FTGMAC100_INT_AHB_ERR)) { 1079 if (net_ratelimit()) 1080 netdev_info(netdev, "[ISR] = 0x%x: %s%s%s\n", status, 1081 status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "", 1082 status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "", 1083 status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : ""); 1084 1085 if (status & FTGMAC100_INT_NO_RXBUF) { 1086 /* RX buffer unavailable */ 1087 netdev->stats.rx_over_errors++; 1088 } 1089 1090 if (status & FTGMAC100_INT_RPKT_LOST) { 1091 /* received packet lost due to RX FIFO full */ 1092 netdev->stats.rx_fifo_errors++; 1093 } 1094 } 1095 1096 if (completed) { 1097 napi_complete(napi); 1098 1099 /* enable all interrupts */ 1100 iowrite32(priv->int_mask_all, 1101 priv->base + FTGMAC100_OFFSET_IER); 1102 } 1103 1104 return rx; 1105 } 1106 1107 /****************************************************************************** 1108 * struct net_device_ops functions 1109 *****************************************************************************/ 1110 static int ftgmac100_open(struct net_device *netdev) 1111 { 1112 struct ftgmac100 *priv = netdev_priv(netdev); 1113 unsigned int status; 1114 int err; 1115 1116 err = ftgmac100_alloc_buffers(priv); 1117 if (err) { 1118 netdev_err(netdev, "failed to allocate buffers\n"); 1119 goto err_alloc; 1120 } 1121 1122 err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1123 if (err) { 1124 netdev_err(netdev, "failed to request irq %d\n", priv->irq); 1125 goto err_irq; 1126 } 1127 1128 priv->rx_pointer = 0; 1129 priv->tx_clean_pointer = 0; 1130 priv->tx_pointer = 0; 1131 priv->tx_pending = 0; 1132 1133 err = ftgmac100_reset_hw(priv); 1134 if (err) 1135 goto err_hw; 1136 1137 ftgmac100_init_hw(priv); 1138 ftgmac100_start_hw(priv, priv->use_ncsi ? 100 : 10); 1139 1140 /* Clear stale interrupts */ 1141 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1142 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1143 1144 if (netdev->phydev) 1145 phy_start(netdev->phydev); 1146 else if (priv->use_ncsi) 1147 netif_carrier_on(netdev); 1148 1149 napi_enable(&priv->napi); 1150 netif_start_queue(netdev); 1151 1152 /* enable all interrupts */ 1153 iowrite32(priv->int_mask_all, priv->base + FTGMAC100_OFFSET_IER); 1154 1155 /* Start the NCSI device */ 1156 if (priv->use_ncsi) { 1157 err = ncsi_start_dev(priv->ndev); 1158 if (err) 1159 goto err_ncsi; 1160 } 1161 1162 priv->enabled = true; 1163 1164 return 0; 1165 1166 err_ncsi: 1167 napi_disable(&priv->napi); 1168 netif_stop_queue(netdev); 1169 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1170 err_hw: 1171 free_irq(priv->irq, netdev); 1172 err_irq: 1173 ftgmac100_free_buffers(priv); 1174 err_alloc: 1175 return err; 1176 } 1177 1178 static int ftgmac100_stop(struct net_device *netdev) 1179 { 1180 struct ftgmac100 *priv = netdev_priv(netdev); 1181 1182 if (!priv->enabled) 1183 return 0; 1184 1185 /* disable all interrupts */ 1186 priv->enabled = false; 1187 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1188 1189 netif_stop_queue(netdev); 1190 napi_disable(&priv->napi); 1191 if (netdev->phydev) 1192 phy_stop(netdev->phydev); 1193 else if (priv->use_ncsi) 1194 ncsi_stop_dev(priv->ndev); 1195 1196 ftgmac100_stop_hw(priv); 1197 free_irq(priv->irq, netdev); 1198 ftgmac100_free_buffers(priv); 1199 1200 return 0; 1201 } 1202 1203 static int ftgmac100_hard_start_xmit(struct sk_buff *skb, 1204 struct net_device *netdev) 1205 { 1206 struct ftgmac100 *priv = netdev_priv(netdev); 1207 dma_addr_t map; 1208 1209 if (unlikely(skb->len > MAX_PKT_SIZE)) { 1210 if (net_ratelimit()) 1211 netdev_dbg(netdev, "tx packet too big\n"); 1212 1213 netdev->stats.tx_dropped++; 1214 kfree_skb(skb); 1215 return NETDEV_TX_OK; 1216 } 1217 1218 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 1219 if (unlikely(dma_mapping_error(priv->dev, map))) { 1220 /* drop packet */ 1221 if (net_ratelimit()) 1222 netdev_err(netdev, "map socket buffer failed\n"); 1223 1224 netdev->stats.tx_dropped++; 1225 kfree_skb(skb); 1226 return NETDEV_TX_OK; 1227 } 1228 1229 return ftgmac100_xmit(priv, skb, map); 1230 } 1231 1232 /* optional */ 1233 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1234 { 1235 if (!netdev->phydev) 1236 return -ENXIO; 1237 1238 return phy_mii_ioctl(netdev->phydev, ifr, cmd); 1239 } 1240 1241 static const struct net_device_ops ftgmac100_netdev_ops = { 1242 .ndo_open = ftgmac100_open, 1243 .ndo_stop = ftgmac100_stop, 1244 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1245 .ndo_set_mac_address = ftgmac100_set_mac_addr, 1246 .ndo_validate_addr = eth_validate_addr, 1247 .ndo_do_ioctl = ftgmac100_do_ioctl, 1248 }; 1249 1250 static int ftgmac100_setup_mdio(struct net_device *netdev) 1251 { 1252 struct ftgmac100 *priv = netdev_priv(netdev); 1253 struct platform_device *pdev = to_platform_device(priv->dev); 1254 int i, err = 0; 1255 u32 reg; 1256 1257 /* initialize mdio bus */ 1258 priv->mii_bus = mdiobus_alloc(); 1259 if (!priv->mii_bus) 1260 return -EIO; 1261 1262 if (of_machine_is_compatible("aspeed,ast2400") || 1263 of_machine_is_compatible("aspeed,ast2500")) { 1264 /* This driver supports the old MDIO interface */ 1265 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); 1266 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; 1267 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); 1268 }; 1269 1270 priv->mii_bus->name = "ftgmac100_mdio"; 1271 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1272 pdev->name, pdev->id); 1273 priv->mii_bus->priv = priv->netdev; 1274 priv->mii_bus->read = ftgmac100_mdiobus_read; 1275 priv->mii_bus->write = ftgmac100_mdiobus_write; 1276 1277 for (i = 0; i < PHY_MAX_ADDR; i++) 1278 priv->mii_bus->irq[i] = PHY_POLL; 1279 1280 err = mdiobus_register(priv->mii_bus); 1281 if (err) { 1282 dev_err(priv->dev, "Cannot register MDIO bus!\n"); 1283 goto err_register_mdiobus; 1284 } 1285 1286 err = ftgmac100_mii_probe(priv); 1287 if (err) { 1288 dev_err(priv->dev, "MII Probe failed!\n"); 1289 goto err_mii_probe; 1290 } 1291 1292 return 0; 1293 1294 err_mii_probe: 1295 mdiobus_unregister(priv->mii_bus); 1296 err_register_mdiobus: 1297 mdiobus_free(priv->mii_bus); 1298 return err; 1299 } 1300 1301 static void ftgmac100_destroy_mdio(struct net_device *netdev) 1302 { 1303 struct ftgmac100 *priv = netdev_priv(netdev); 1304 1305 if (!netdev->phydev) 1306 return; 1307 1308 phy_disconnect(netdev->phydev); 1309 mdiobus_unregister(priv->mii_bus); 1310 mdiobus_free(priv->mii_bus); 1311 } 1312 1313 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) 1314 { 1315 if (unlikely(nd->state != ncsi_dev_state_functional)) 1316 return; 1317 1318 netdev_info(nd->dev, "NCSI interface %s\n", 1319 nd->link_up ? "up" : "down"); 1320 } 1321 1322 /****************************************************************************** 1323 * struct platform_driver functions 1324 *****************************************************************************/ 1325 static int ftgmac100_probe(struct platform_device *pdev) 1326 { 1327 struct resource *res; 1328 int irq; 1329 struct net_device *netdev; 1330 struct ftgmac100 *priv; 1331 int err = 0; 1332 1333 if (!pdev) 1334 return -ENODEV; 1335 1336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1337 if (!res) 1338 return -ENXIO; 1339 1340 irq = platform_get_irq(pdev, 0); 1341 if (irq < 0) 1342 return irq; 1343 1344 /* setup net_device */ 1345 netdev = alloc_etherdev(sizeof(*priv)); 1346 if (!netdev) { 1347 err = -ENOMEM; 1348 goto err_alloc_etherdev; 1349 } 1350 1351 SET_NETDEV_DEV(netdev, &pdev->dev); 1352 1353 netdev->ethtool_ops = &ftgmac100_ethtool_ops; 1354 netdev->netdev_ops = &ftgmac100_netdev_ops; 1355 1356 platform_set_drvdata(pdev, netdev); 1357 1358 /* setup private data */ 1359 priv = netdev_priv(netdev); 1360 priv->netdev = netdev; 1361 priv->dev = &pdev->dev; 1362 1363 spin_lock_init(&priv->tx_lock); 1364 1365 /* initialize NAPI */ 1366 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1367 1368 /* map io memory */ 1369 priv->res = request_mem_region(res->start, resource_size(res), 1370 dev_name(&pdev->dev)); 1371 if (!priv->res) { 1372 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1373 err = -ENOMEM; 1374 goto err_req_mem; 1375 } 1376 1377 priv->base = ioremap(res->start, resource_size(res)); 1378 if (!priv->base) { 1379 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1380 err = -EIO; 1381 goto err_ioremap; 1382 } 1383 1384 priv->irq = irq; 1385 1386 /* MAC address from chip or random one */ 1387 ftgmac100_setup_mac(priv); 1388 1389 priv->int_mask_all = (FTGMAC100_INT_RPKT_LOST | 1390 FTGMAC100_INT_XPKT_ETH | 1391 FTGMAC100_INT_XPKT_LOST | 1392 FTGMAC100_INT_AHB_ERR | 1393 FTGMAC100_INT_RPKT_BUF | 1394 FTGMAC100_INT_NO_RXBUF); 1395 1396 if (of_machine_is_compatible("aspeed,ast2400") || 1397 of_machine_is_compatible("aspeed,ast2500")) { 1398 priv->rxdes0_edorr_mask = BIT(30); 1399 priv->txdes0_edotr_mask = BIT(30); 1400 } else { 1401 priv->rxdes0_edorr_mask = BIT(15); 1402 priv->txdes0_edotr_mask = BIT(15); 1403 } 1404 1405 if (pdev->dev.of_node && 1406 of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) { 1407 if (!IS_ENABLED(CONFIG_NET_NCSI)) { 1408 dev_err(&pdev->dev, "NCSI stack not enabled\n"); 1409 goto err_ncsi_dev; 1410 } 1411 1412 dev_info(&pdev->dev, "Using NCSI interface\n"); 1413 priv->use_ncsi = true; 1414 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); 1415 if (!priv->ndev) 1416 goto err_ncsi_dev; 1417 } else { 1418 priv->use_ncsi = false; 1419 err = ftgmac100_setup_mdio(netdev); 1420 if (err) 1421 goto err_setup_mdio; 1422 } 1423 1424 /* We have to disable on-chip IP checksum functionality 1425 * when NCSI is enabled on the interface. It doesn't work 1426 * in that case. 1427 */ 1428 netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO; 1429 if (priv->use_ncsi && 1430 of_get_property(pdev->dev.of_node, "no-hw-checksum", NULL)) 1431 netdev->features &= ~NETIF_F_IP_CSUM; 1432 1433 1434 /* register network device */ 1435 err = register_netdev(netdev); 1436 if (err) { 1437 dev_err(&pdev->dev, "Failed to register netdev\n"); 1438 goto err_register_netdev; 1439 } 1440 1441 netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base); 1442 1443 return 0; 1444 1445 err_ncsi_dev: 1446 err_register_netdev: 1447 ftgmac100_destroy_mdio(netdev); 1448 err_setup_mdio: 1449 iounmap(priv->base); 1450 err_ioremap: 1451 release_resource(priv->res); 1452 err_req_mem: 1453 netif_napi_del(&priv->napi); 1454 free_netdev(netdev); 1455 err_alloc_etherdev: 1456 return err; 1457 } 1458 1459 static int ftgmac100_remove(struct platform_device *pdev) 1460 { 1461 struct net_device *netdev; 1462 struct ftgmac100 *priv; 1463 1464 netdev = platform_get_drvdata(pdev); 1465 priv = netdev_priv(netdev); 1466 1467 unregister_netdev(netdev); 1468 ftgmac100_destroy_mdio(netdev); 1469 1470 iounmap(priv->base); 1471 release_resource(priv->res); 1472 1473 netif_napi_del(&priv->napi); 1474 free_netdev(netdev); 1475 return 0; 1476 } 1477 1478 static const struct of_device_id ftgmac100_of_match[] = { 1479 { .compatible = "faraday,ftgmac100" }, 1480 { } 1481 }; 1482 MODULE_DEVICE_TABLE(of, ftgmac100_of_match); 1483 1484 static struct platform_driver ftgmac100_driver = { 1485 .probe = ftgmac100_probe, 1486 .remove = ftgmac100_remove, 1487 .driver = { 1488 .name = DRV_NAME, 1489 .of_match_table = ftgmac100_of_match, 1490 }, 1491 }; 1492 module_platform_driver(ftgmac100_driver); 1493 1494 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1495 MODULE_DESCRIPTION("FTGMAC100 driver"); 1496 MODULE_LICENSE("GPL"); 1497