1 /*
2  * Faraday FTGMAC100 Gigabit Ethernet
3  *
4  * (C) Copyright 2009-2011 Faraday Technology
5  * Po-Yu Chuang <ratbert@faraday-tech.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21 
22 #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
23 
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/of.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
35 #include <linux/crc32.h>
36 #include <linux/if_vlan.h>
37 #include <linux/of_net.h>
38 #include <net/ip.h>
39 #include <net/ncsi.h>
40 
41 #include "ftgmac100.h"
42 
43 #define DRV_NAME	"ftgmac100"
44 #define DRV_VERSION	"0.7"
45 
46 /* Arbitrary values, I am not sure the HW has limits */
47 #define MAX_RX_QUEUE_ENTRIES	1024
48 #define MAX_TX_QUEUE_ENTRIES	1024
49 #define MIN_RX_QUEUE_ENTRIES	32
50 #define MIN_TX_QUEUE_ENTRIES	32
51 
52 /* Defaults */
53 #define DEF_RX_QUEUE_ENTRIES	128
54 #define DEF_TX_QUEUE_ENTRIES	128
55 
56 #define MAX_PKT_SIZE		1536
57 #define RX_BUF_SIZE		MAX_PKT_SIZE	/* must be smaller than 0x3fff */
58 
59 /* Min number of tx ring entries before stopping queue */
60 #define TX_THRESHOLD		(MAX_SKB_FRAGS + 1)
61 
62 struct ftgmac100 {
63 	/* Registers */
64 	struct resource *res;
65 	void __iomem *base;
66 
67 	/* Rx ring */
68 	unsigned int rx_q_entries;
69 	struct ftgmac100_rxdes *rxdes;
70 	dma_addr_t rxdes_dma;
71 	struct sk_buff **rx_skbs;
72 	unsigned int rx_pointer;
73 	u32 rxdes0_edorr_mask;
74 
75 	/* Tx ring */
76 	unsigned int tx_q_entries;
77 	struct ftgmac100_txdes *txdes;
78 	dma_addr_t txdes_dma;
79 	struct sk_buff **tx_skbs;
80 	unsigned int tx_clean_pointer;
81 	unsigned int tx_pointer;
82 	u32 txdes0_edotr_mask;
83 
84 	/* Used to signal the reset task of ring change request */
85 	unsigned int new_rx_q_entries;
86 	unsigned int new_tx_q_entries;
87 
88 	/* Scratch page to use when rx skb alloc fails */
89 	void *rx_scratch;
90 	dma_addr_t rx_scratch_dma;
91 
92 	/* Component structures */
93 	struct net_device *netdev;
94 	struct device *dev;
95 	struct ncsi_dev *ndev;
96 	struct napi_struct napi;
97 	struct work_struct reset_task;
98 	struct mii_bus *mii_bus;
99 
100 	/* Link management */
101 	int cur_speed;
102 	int cur_duplex;
103 	bool use_ncsi;
104 
105 	/* Multicast filter settings */
106 	u32 maht0;
107 	u32 maht1;
108 
109 	/* Flow control settings */
110 	bool tx_pause;
111 	bool rx_pause;
112 	bool aneg_pause;
113 
114 	/* Misc */
115 	bool need_mac_restart;
116 	bool is_aspeed;
117 };
118 
119 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
120 {
121 	struct net_device *netdev = priv->netdev;
122 	int i;
123 
124 	/* NOTE: reset clears all registers */
125 	iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
126 	iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
127 		  priv->base + FTGMAC100_OFFSET_MACCR);
128 	for (i = 0; i < 50; i++) {
129 		unsigned int maccr;
130 
131 		maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
132 		if (!(maccr & FTGMAC100_MACCR_SW_RST))
133 			return 0;
134 
135 		udelay(1);
136 	}
137 
138 	netdev_err(netdev, "Hardware reset failed\n");
139 	return -EIO;
140 }
141 
142 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
143 {
144 	u32 maccr = 0;
145 
146 	switch (priv->cur_speed) {
147 	case SPEED_10:
148 	case 0: /* no link */
149 		break;
150 
151 	case SPEED_100:
152 		maccr |= FTGMAC100_MACCR_FAST_MODE;
153 		break;
154 
155 	case SPEED_1000:
156 		maccr |= FTGMAC100_MACCR_GIGA_MODE;
157 		break;
158 	default:
159 		netdev_err(priv->netdev, "Unknown speed %d !\n",
160 			   priv->cur_speed);
161 		break;
162 	}
163 
164 	/* (Re)initialize the queue pointers */
165 	priv->rx_pointer = 0;
166 	priv->tx_clean_pointer = 0;
167 	priv->tx_pointer = 0;
168 
169 	/* The doc says reset twice with 10us interval */
170 	if (ftgmac100_reset_mac(priv, maccr))
171 		return -EIO;
172 	usleep_range(10, 1000);
173 	return ftgmac100_reset_mac(priv, maccr);
174 }
175 
176 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
177 {
178 	unsigned int maddr = mac[0] << 8 | mac[1];
179 	unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
180 
181 	iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
182 	iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
183 }
184 
185 static void ftgmac100_initial_mac(struct ftgmac100 *priv)
186 {
187 	u8 mac[ETH_ALEN];
188 	unsigned int m;
189 	unsigned int l;
190 	void *addr;
191 
192 	addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
193 	if (addr) {
194 		ether_addr_copy(priv->netdev->dev_addr, mac);
195 		dev_info(priv->dev, "Read MAC address %pM from device tree\n",
196 			 mac);
197 		return;
198 	}
199 
200 	m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
201 	l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
202 
203 	mac[0] = (m >> 8) & 0xff;
204 	mac[1] = m & 0xff;
205 	mac[2] = (l >> 24) & 0xff;
206 	mac[3] = (l >> 16) & 0xff;
207 	mac[4] = (l >> 8) & 0xff;
208 	mac[5] = l & 0xff;
209 
210 	if (is_valid_ether_addr(mac)) {
211 		ether_addr_copy(priv->netdev->dev_addr, mac);
212 		dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
213 	} else {
214 		eth_hw_addr_random(priv->netdev);
215 		dev_info(priv->dev, "Generated random MAC address %pM\n",
216 			 priv->netdev->dev_addr);
217 	}
218 }
219 
220 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
221 {
222 	int ret;
223 
224 	ret = eth_prepare_mac_addr_change(dev, p);
225 	if (ret < 0)
226 		return ret;
227 
228 	eth_commit_mac_addr_change(dev, p);
229 	ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
230 
231 	return 0;
232 }
233 
234 static void ftgmac100_config_pause(struct ftgmac100 *priv)
235 {
236 	u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
237 
238 	/* Throttle tx queue when receiving pause frames */
239 	if (priv->rx_pause)
240 		fcr |= FTGMAC100_FCR_FC_EN;
241 
242 	/* Enables sending pause frames when the RX queue is past a
243 	 * certain threshold.
244 	 */
245 	if (priv->tx_pause)
246 		fcr |= FTGMAC100_FCR_FCTHR_EN;
247 
248 	iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
249 }
250 
251 static void ftgmac100_init_hw(struct ftgmac100 *priv)
252 {
253 	u32 reg, rfifo_sz, tfifo_sz;
254 
255 	/* Clear stale interrupts */
256 	reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
257 	iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
258 
259 	/* Setup RX ring buffer base */
260 	iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
261 
262 	/* Setup TX ring buffer base */
263 	iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
264 
265 	/* Configure RX buffer size */
266 	iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
267 		  priv->base + FTGMAC100_OFFSET_RBSR);
268 
269 	/* Set RX descriptor autopoll */
270 	iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
271 		  priv->base + FTGMAC100_OFFSET_APTC);
272 
273 	/* Write MAC address */
274 	ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
275 
276 	/* Write multicast filter */
277 	iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
278 	iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
279 
280 	/* Configure descriptor sizes and increase burst sizes according
281 	 * to values in Aspeed SDK. The FIFO arbitration is enabled and
282 	 * the thresholds set based on the recommended values in the
283 	 * AST2400 specification.
284 	 */
285 	iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) |   /* 2*8 bytes RX descs */
286 		  FTGMAC100_DBLAC_TXDES_SIZE(2) |   /* 2*8 bytes TX descs */
287 		  FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
288 		  FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
289 		  FTGMAC100_DBLAC_RX_THR_EN |       /* Enable fifo threshold arb */
290 		  FTGMAC100_DBLAC_RXFIFO_HTHR(6) |  /* 6/8 of FIFO high threshold */
291 		  FTGMAC100_DBLAC_RXFIFO_LTHR(2),   /* 2/8 of FIFO low threshold */
292 		  priv->base + FTGMAC100_OFFSET_DBLAC);
293 
294 	/* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
295 	 * mitigation doesn't seem to provide any benefit with NAPI so leave
296 	 * it at that.
297 	 */
298 	iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
299 		  FTGMAC100_ITC_TXINT_THR(1),
300 		  priv->base + FTGMAC100_OFFSET_ITC);
301 
302 	/* Configure FIFO sizes in the TPAFCR register */
303 	reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
304 	rfifo_sz = reg & 0x00000007;
305 	tfifo_sz = (reg >> 3) & 0x00000007;
306 	reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
307 	reg &= ~0x3f000000;
308 	reg |= (tfifo_sz << 27);
309 	reg |= (rfifo_sz << 24);
310 	iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
311 }
312 
313 static void ftgmac100_start_hw(struct ftgmac100 *priv)
314 {
315 	u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
316 
317 	/* Keep the original GMAC and FAST bits */
318 	maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
319 
320 	/* Add all the main enable bits */
321 	maccr |= FTGMAC100_MACCR_TXDMA_EN	|
322 		 FTGMAC100_MACCR_RXDMA_EN	|
323 		 FTGMAC100_MACCR_TXMAC_EN	|
324 		 FTGMAC100_MACCR_RXMAC_EN	|
325 		 FTGMAC100_MACCR_CRC_APD	|
326 		 FTGMAC100_MACCR_PHY_LINK_LEVEL	|
327 		 FTGMAC100_MACCR_RX_RUNT	|
328 		 FTGMAC100_MACCR_RX_BROADPKT;
329 
330 	/* Add other bits as needed */
331 	if (priv->cur_duplex == DUPLEX_FULL)
332 		maccr |= FTGMAC100_MACCR_FULLDUP;
333 	if (priv->netdev->flags & IFF_PROMISC)
334 		maccr |= FTGMAC100_MACCR_RX_ALL;
335 	if (priv->netdev->flags & IFF_ALLMULTI)
336 		maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
337 	else if (netdev_mc_count(priv->netdev))
338 		maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
339 
340 	/* Vlan filtering enabled */
341 	if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
342 		maccr |= FTGMAC100_MACCR_RM_VLAN;
343 
344 	/* Hit the HW */
345 	iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
346 }
347 
348 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
349 {
350 	iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
351 }
352 
353 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
354 {
355 	struct netdev_hw_addr *ha;
356 
357 	priv->maht1 = 0;
358 	priv->maht0 = 0;
359 	netdev_for_each_mc_addr(ha, priv->netdev) {
360 		u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
361 
362 		crc_val = (~(crc_val >> 2)) & 0x3f;
363 		if (crc_val >= 32)
364 			priv->maht1 |= 1ul << (crc_val - 32);
365 		else
366 			priv->maht0 |= 1ul << (crc_val);
367 	}
368 }
369 
370 static void ftgmac100_set_rx_mode(struct net_device *netdev)
371 {
372 	struct ftgmac100 *priv = netdev_priv(netdev);
373 
374 	/* Setup the hash filter */
375 	ftgmac100_calc_mc_hash(priv);
376 
377 	/* Interface down ? that's all there is to do */
378 	if (!netif_running(netdev))
379 		return;
380 
381 	/* Update the HW */
382 	iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
383 	iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
384 
385 	/* Reconfigure MACCR */
386 	ftgmac100_start_hw(priv);
387 }
388 
389 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
390 				  struct ftgmac100_rxdes *rxdes, gfp_t gfp)
391 {
392 	struct net_device *netdev = priv->netdev;
393 	struct sk_buff *skb;
394 	dma_addr_t map;
395 	int err;
396 
397 	skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
398 	if (unlikely(!skb)) {
399 		if (net_ratelimit())
400 			netdev_warn(netdev, "failed to allocate rx skb\n");
401 		err = -ENOMEM;
402 		map = priv->rx_scratch_dma;
403 	} else {
404 		map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
405 				     DMA_FROM_DEVICE);
406 		if (unlikely(dma_mapping_error(priv->dev, map))) {
407 			if (net_ratelimit())
408 				netdev_err(netdev, "failed to map rx page\n");
409 			dev_kfree_skb_any(skb);
410 			map = priv->rx_scratch_dma;
411 			skb = NULL;
412 			err = -ENOMEM;
413 		}
414 	}
415 
416 	/* Store skb */
417 	priv->rx_skbs[entry] = skb;
418 
419 	/* Store DMA address into RX desc */
420 	rxdes->rxdes3 = cpu_to_le32(map);
421 
422 	/* Ensure the above is ordered vs clearing the OWN bit */
423 	dma_wmb();
424 
425 	/* Clean status (which resets own bit) */
426 	if (entry == (priv->rx_q_entries - 1))
427 		rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
428 	else
429 		rxdes->rxdes0 = 0;
430 
431 	return 0;
432 }
433 
434 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
435 					      unsigned int pointer)
436 {
437 	return (pointer + 1) & (priv->rx_q_entries - 1);
438 }
439 
440 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
441 {
442 	struct net_device *netdev = priv->netdev;
443 
444 	if (status & FTGMAC100_RXDES0_RX_ERR)
445 		netdev->stats.rx_errors++;
446 
447 	if (status & FTGMAC100_RXDES0_CRC_ERR)
448 		netdev->stats.rx_crc_errors++;
449 
450 	if (status & (FTGMAC100_RXDES0_FTL |
451 		      FTGMAC100_RXDES0_RUNT |
452 		      FTGMAC100_RXDES0_RX_ODD_NB))
453 		netdev->stats.rx_length_errors++;
454 }
455 
456 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
457 {
458 	struct net_device *netdev = priv->netdev;
459 	struct ftgmac100_rxdes *rxdes;
460 	struct sk_buff *skb;
461 	unsigned int pointer, size;
462 	u32 status, csum_vlan;
463 	dma_addr_t map;
464 
465 	/* Grab next RX descriptor */
466 	pointer = priv->rx_pointer;
467 	rxdes = &priv->rxdes[pointer];
468 
469 	/* Grab descriptor status */
470 	status = le32_to_cpu(rxdes->rxdes0);
471 
472 	/* Do we have a packet ? */
473 	if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
474 		return false;
475 
476 	/* Order subsequent reads with the test for the ready bit */
477 	dma_rmb();
478 
479 	/* We don't cope with fragmented RX packets */
480 	if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
481 		     !(status & FTGMAC100_RXDES0_LRS)))
482 		goto drop;
483 
484 	/* Grab received size and csum vlan field in the descriptor */
485 	size = status & FTGMAC100_RXDES0_VDBC;
486 	csum_vlan = le32_to_cpu(rxdes->rxdes1);
487 
488 	/* Any error (other than csum offload) flagged ? */
489 	if (unlikely(status & RXDES0_ANY_ERROR)) {
490 		/* Correct for incorrect flagging of runt packets
491 		 * with vlan tags... Just accept a runt packet that
492 		 * has been flagged as vlan and whose size is at
493 		 * least 60 bytes.
494 		 */
495 		if ((status & FTGMAC100_RXDES0_RUNT) &&
496 		    (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
497 		    (size >= 60))
498 			status &= ~FTGMAC100_RXDES0_RUNT;
499 
500 		/* Any error still in there ? */
501 		if (status & RXDES0_ANY_ERROR) {
502 			ftgmac100_rx_packet_error(priv, status);
503 			goto drop;
504 		}
505 	}
506 
507 	/* If the packet had no skb (failed to allocate earlier)
508 	 * then try to allocate one and skip
509 	 */
510 	skb = priv->rx_skbs[pointer];
511 	if (!unlikely(skb)) {
512 		ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
513 		goto drop;
514 	}
515 
516 	if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
517 		netdev->stats.multicast++;
518 
519 	/* If the HW found checksum errors, bounce it to software.
520 	 *
521 	 * If we didn't, we need to see if the packet was recognized
522 	 * by HW as one of the supported checksummed protocols before
523 	 * we accept the HW test results.
524 	 */
525 	if (netdev->features & NETIF_F_RXCSUM) {
526 		u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
527 			FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
528 			FTGMAC100_RXDES1_IP_CHKSUM_ERR;
529 		if ((csum_vlan & err_bits) ||
530 		    !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
531 			skb->ip_summed = CHECKSUM_NONE;
532 		else
533 			skb->ip_summed = CHECKSUM_UNNECESSARY;
534 	}
535 
536 	/* Transfer received size to skb */
537 	skb_put(skb, size);
538 
539 	/* Extract vlan tag */
540 	if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
541 	    (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
542 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
543 				       csum_vlan & 0xffff);
544 
545 	/* Tear down DMA mapping, do necessary cache management */
546 	map = le32_to_cpu(rxdes->rxdes3);
547 
548 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
549 	/* When we don't have an iommu, we can save cycles by not
550 	 * invalidating the cache for the part of the packet that
551 	 * wasn't received.
552 	 */
553 	dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
554 #else
555 	dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
556 #endif
557 
558 
559 	/* Resplenish rx ring */
560 	ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
561 	priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
562 
563 	skb->protocol = eth_type_trans(skb, netdev);
564 
565 	netdev->stats.rx_packets++;
566 	netdev->stats.rx_bytes += size;
567 
568 	/* push packet to protocol stack */
569 	if (skb->ip_summed == CHECKSUM_NONE)
570 		netif_receive_skb(skb);
571 	else
572 		napi_gro_receive(&priv->napi, skb);
573 
574 	(*processed)++;
575 	return true;
576 
577  drop:
578 	/* Clean rxdes0 (which resets own bit) */
579 	rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
580 	priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
581 	netdev->stats.rx_dropped++;
582 	return true;
583 }
584 
585 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
586 				     unsigned int index)
587 {
588 	if (index == (priv->tx_q_entries - 1))
589 		return priv->txdes0_edotr_mask;
590 	else
591 		return 0;
592 }
593 
594 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
595 					      unsigned int pointer)
596 {
597 	return (pointer + 1) & (priv->tx_q_entries - 1);
598 }
599 
600 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
601 {
602 	/* Returns the number of available slots in the TX queue
603 	 *
604 	 * This always leaves one free slot so we don't have to
605 	 * worry about empty vs. full, and this simplifies the
606 	 * test for ftgmac100_tx_buf_cleanable() below
607 	 */
608 	return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
609 		(priv->tx_q_entries - 1);
610 }
611 
612 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
613 {
614 	return priv->tx_pointer != priv->tx_clean_pointer;
615 }
616 
617 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
618 				     unsigned int pointer,
619 				     struct sk_buff *skb,
620 				     struct ftgmac100_txdes *txdes,
621 				     u32 ctl_stat)
622 {
623 	dma_addr_t map = le32_to_cpu(txdes->txdes3);
624 	size_t len;
625 
626 	if (ctl_stat & FTGMAC100_TXDES0_FTS) {
627 		len = skb_headlen(skb);
628 		dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
629 	} else {
630 		len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
631 		dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
632 	}
633 
634 	/* Free SKB on last segment */
635 	if (ctl_stat & FTGMAC100_TXDES0_LTS)
636 		dev_kfree_skb(skb);
637 	priv->tx_skbs[pointer] = NULL;
638 }
639 
640 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
641 {
642 	struct net_device *netdev = priv->netdev;
643 	struct ftgmac100_txdes *txdes;
644 	struct sk_buff *skb;
645 	unsigned int pointer;
646 	u32 ctl_stat;
647 
648 	pointer = priv->tx_clean_pointer;
649 	txdes = &priv->txdes[pointer];
650 
651 	ctl_stat = le32_to_cpu(txdes->txdes0);
652 	if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
653 		return false;
654 
655 	skb = priv->tx_skbs[pointer];
656 	netdev->stats.tx_packets++;
657 	netdev->stats.tx_bytes += skb->len;
658 	ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
659 	txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
660 
661 	priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
662 
663 	return true;
664 }
665 
666 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
667 {
668 	struct net_device *netdev = priv->netdev;
669 
670 	/* Process all completed packets */
671 	while (ftgmac100_tx_buf_cleanable(priv) &&
672 	       ftgmac100_tx_complete_packet(priv))
673 		;
674 
675 	/* Restart queue if needed */
676 	smp_mb();
677 	if (unlikely(netif_queue_stopped(netdev) &&
678 		     ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
679 		struct netdev_queue *txq;
680 
681 		txq = netdev_get_tx_queue(netdev, 0);
682 		__netif_tx_lock(txq, smp_processor_id());
683 		if (netif_queue_stopped(netdev) &&
684 		    ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
685 			netif_wake_queue(netdev);
686 		__netif_tx_unlock(txq);
687 	}
688 }
689 
690 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
691 {
692 	if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
693 		u8 ip_proto = ip_hdr(skb)->protocol;
694 
695 		*csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
696 		switch(ip_proto) {
697 		case IPPROTO_TCP:
698 			*csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
699 			return true;
700 		case IPPROTO_UDP:
701 			*csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
702 			return true;
703 		case IPPROTO_IP:
704 			return true;
705 		}
706 	}
707 	return skb_checksum_help(skb) == 0;
708 }
709 
710 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
711 				     struct net_device *netdev)
712 {
713 	struct ftgmac100 *priv = netdev_priv(netdev);
714 	struct ftgmac100_txdes *txdes, *first;
715 	unsigned int pointer, nfrags, len, i, j;
716 	u32 f_ctl_stat, ctl_stat, csum_vlan;
717 	dma_addr_t map;
718 
719 	/* The HW doesn't pad small frames */
720 	if (eth_skb_pad(skb)) {
721 		netdev->stats.tx_dropped++;
722 		return NETDEV_TX_OK;
723 	}
724 
725 	/* Reject oversize packets */
726 	if (unlikely(skb->len > MAX_PKT_SIZE)) {
727 		if (net_ratelimit())
728 			netdev_dbg(netdev, "tx packet too big\n");
729 		goto drop;
730 	}
731 
732 	/* Do we have a limit on #fragments ? I yet have to get a reply
733 	 * from Aspeed. If there's one I haven't hit it.
734 	 */
735 	nfrags = skb_shinfo(skb)->nr_frags;
736 
737 	/* Get header len */
738 	len = skb_headlen(skb);
739 
740 	/* Map the packet head */
741 	map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
742 	if (dma_mapping_error(priv->dev, map)) {
743 		if (net_ratelimit())
744 			netdev_err(netdev, "map tx packet head failed\n");
745 		goto drop;
746 	}
747 
748 	/* Grab the next free tx descriptor */
749 	pointer = priv->tx_pointer;
750 	txdes = first = &priv->txdes[pointer];
751 
752 	/* Setup it up with the packet head. Don't write the head to the
753 	 * ring just yet
754 	 */
755 	priv->tx_skbs[pointer] = skb;
756 	f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
757 	f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
758 	f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
759 	f_ctl_stat |= FTGMAC100_TXDES0_FTS;
760 	if (nfrags == 0)
761 		f_ctl_stat |= FTGMAC100_TXDES0_LTS;
762 	txdes->txdes3 = cpu_to_le32(map);
763 
764 	/* Setup HW checksumming */
765 	csum_vlan = 0;
766 	if (skb->ip_summed == CHECKSUM_PARTIAL &&
767 	    !ftgmac100_prep_tx_csum(skb, &csum_vlan))
768 		goto drop;
769 
770 	/* Add VLAN tag */
771 	if (skb_vlan_tag_present(skb)) {
772 		csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
773 		csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
774 	}
775 
776 	txdes->txdes1 = cpu_to_le32(csum_vlan);
777 
778 	/* Next descriptor */
779 	pointer = ftgmac100_next_tx_pointer(priv, pointer);
780 
781 	/* Add the fragments */
782 	for (i = 0; i < nfrags; i++) {
783 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
784 
785 		len = frag->size;
786 
787 		/* Map it */
788 		map = skb_frag_dma_map(priv->dev, frag, 0, len,
789 				       DMA_TO_DEVICE);
790 		if (dma_mapping_error(priv->dev, map))
791 			goto dma_err;
792 
793 		/* Setup descriptor */
794 		priv->tx_skbs[pointer] = skb;
795 		txdes = &priv->txdes[pointer];
796 		ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
797 		ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
798 		ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
799 		if (i == (nfrags - 1))
800 			ctl_stat |= FTGMAC100_TXDES0_LTS;
801 		txdes->txdes0 = cpu_to_le32(ctl_stat);
802 		txdes->txdes1 = 0;
803 		txdes->txdes3 = cpu_to_le32(map);
804 
805 		/* Next one */
806 		pointer = ftgmac100_next_tx_pointer(priv, pointer);
807 	}
808 
809 	/* Order the previous packet and descriptor udpates
810 	 * before setting the OWN bit on the first descriptor.
811 	 */
812 	dma_wmb();
813 	first->txdes0 = cpu_to_le32(f_ctl_stat);
814 
815 	/* Update next TX pointer */
816 	priv->tx_pointer = pointer;
817 
818 	/* If there isn't enough room for all the fragments of a new packet
819 	 * in the TX ring, stop the queue. The sequence below is race free
820 	 * vs. a concurrent restart in ftgmac100_poll()
821 	 */
822 	if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
823 		netif_stop_queue(netdev);
824 		/* Order the queue stop with the test below */
825 		smp_mb();
826 		if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
827 			netif_wake_queue(netdev);
828 	}
829 
830 	/* Poke transmitter to read the updated TX descriptors */
831 	iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
832 
833 	return NETDEV_TX_OK;
834 
835  dma_err:
836 	if (net_ratelimit())
837 		netdev_err(netdev, "map tx fragment failed\n");
838 
839 	/* Free head */
840 	pointer = priv->tx_pointer;
841 	ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
842 	first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
843 
844 	/* Then all fragments */
845 	for (j = 0; j < i; j++) {
846 		pointer = ftgmac100_next_tx_pointer(priv, pointer);
847 		txdes = &priv->txdes[pointer];
848 		ctl_stat = le32_to_cpu(txdes->txdes0);
849 		ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
850 		txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
851 	}
852 
853 	/* This cannot be reached if we successfully mapped the
854 	 * last fragment, so we know ftgmac100_free_tx_packet()
855 	 * hasn't freed the skb yet.
856 	 */
857  drop:
858 	/* Drop the packet */
859 	dev_kfree_skb_any(skb);
860 	netdev->stats.tx_dropped++;
861 
862 	return NETDEV_TX_OK;
863 }
864 
865 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
866 {
867 	int i;
868 
869 	/* Free all RX buffers */
870 	for (i = 0; i < priv->rx_q_entries; i++) {
871 		struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
872 		struct sk_buff *skb = priv->rx_skbs[i];
873 		dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
874 
875 		if (!skb)
876 			continue;
877 
878 		priv->rx_skbs[i] = NULL;
879 		dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
880 		dev_kfree_skb_any(skb);
881 	}
882 
883 	/* Free all TX buffers */
884 	for (i = 0; i < priv->tx_q_entries; i++) {
885 		struct ftgmac100_txdes *txdes = &priv->txdes[i];
886 		struct sk_buff *skb = priv->tx_skbs[i];
887 
888 		if (!skb)
889 			continue;
890 		ftgmac100_free_tx_packet(priv, i, skb, txdes,
891 					 le32_to_cpu(txdes->txdes0));
892 	}
893 }
894 
895 static void ftgmac100_free_rings(struct ftgmac100 *priv)
896 {
897 	/* Free skb arrays */
898 	kfree(priv->rx_skbs);
899 	kfree(priv->tx_skbs);
900 
901 	/* Free descriptors */
902 	if (priv->rxdes)
903 		dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
904 				  sizeof(struct ftgmac100_rxdes),
905 				  priv->rxdes, priv->rxdes_dma);
906 	priv->rxdes = NULL;
907 
908 	if (priv->txdes)
909 		dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
910 				  sizeof(struct ftgmac100_txdes),
911 				  priv->txdes, priv->txdes_dma);
912 	priv->txdes = NULL;
913 
914 	/* Free scratch packet buffer */
915 	if (priv->rx_scratch)
916 		dma_free_coherent(priv->dev, RX_BUF_SIZE,
917 				  priv->rx_scratch, priv->rx_scratch_dma);
918 }
919 
920 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
921 {
922 	/* Allocate skb arrays */
923 	priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
924 				GFP_KERNEL);
925 	if (!priv->rx_skbs)
926 		return -ENOMEM;
927 	priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
928 				GFP_KERNEL);
929 	if (!priv->tx_skbs)
930 		return -ENOMEM;
931 
932 	/* Allocate descriptors */
933 	priv->rxdes = dma_zalloc_coherent(priv->dev,
934 					  MAX_RX_QUEUE_ENTRIES *
935 					  sizeof(struct ftgmac100_rxdes),
936 					  &priv->rxdes_dma, GFP_KERNEL);
937 	if (!priv->rxdes)
938 		return -ENOMEM;
939 	priv->txdes = dma_zalloc_coherent(priv->dev,
940 					  MAX_TX_QUEUE_ENTRIES *
941 					  sizeof(struct ftgmac100_txdes),
942 					  &priv->txdes_dma, GFP_KERNEL);
943 	if (!priv->txdes)
944 		return -ENOMEM;
945 
946 	/* Allocate scratch packet buffer */
947 	priv->rx_scratch = dma_alloc_coherent(priv->dev,
948 					      RX_BUF_SIZE,
949 					      &priv->rx_scratch_dma,
950 					      GFP_KERNEL);
951 	if (!priv->rx_scratch)
952 		return -ENOMEM;
953 
954 	return 0;
955 }
956 
957 static void ftgmac100_init_rings(struct ftgmac100 *priv)
958 {
959 	struct ftgmac100_rxdes *rxdes = NULL;
960 	struct ftgmac100_txdes *txdes = NULL;
961 	int i;
962 
963 	/* Update entries counts */
964 	priv->rx_q_entries = priv->new_rx_q_entries;
965 	priv->tx_q_entries = priv->new_tx_q_entries;
966 
967 	if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
968 		return;
969 
970 	/* Initialize RX ring */
971 	for (i = 0; i < priv->rx_q_entries; i++) {
972 		rxdes = &priv->rxdes[i];
973 		rxdes->rxdes0 = 0;
974 		rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
975 	}
976 	/* Mark the end of the ring */
977 	rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
978 
979 	if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
980 		return;
981 
982 	/* Initialize TX ring */
983 	for (i = 0; i < priv->tx_q_entries; i++) {
984 		txdes = &priv->txdes[i];
985 		txdes->txdes0 = 0;
986 	}
987 	txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
988 }
989 
990 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
991 {
992 	int i;
993 
994 	for (i = 0; i < priv->rx_q_entries; i++) {
995 		struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
996 
997 		if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
998 			return -ENOMEM;
999 	}
1000 	return 0;
1001 }
1002 
1003 static void ftgmac100_adjust_link(struct net_device *netdev)
1004 {
1005 	struct ftgmac100 *priv = netdev_priv(netdev);
1006 	struct phy_device *phydev = netdev->phydev;
1007 	bool tx_pause, rx_pause;
1008 	int new_speed;
1009 
1010 	/* We store "no link" as speed 0 */
1011 	if (!phydev->link)
1012 		new_speed = 0;
1013 	else
1014 		new_speed = phydev->speed;
1015 
1016 	/* Grab pause settings from PHY if configured to do so */
1017 	if (priv->aneg_pause) {
1018 		rx_pause = tx_pause = phydev->pause;
1019 		if (phydev->asym_pause)
1020 			tx_pause = !rx_pause;
1021 	} else {
1022 		rx_pause = priv->rx_pause;
1023 		tx_pause = priv->tx_pause;
1024 	}
1025 
1026 	/* Link hasn't changed, do nothing */
1027 	if (phydev->speed == priv->cur_speed &&
1028 	    phydev->duplex == priv->cur_duplex &&
1029 	    rx_pause == priv->rx_pause &&
1030 	    tx_pause == priv->tx_pause)
1031 		return;
1032 
1033 	/* Print status if we have a link or we had one and just lost it,
1034 	 * don't print otherwise.
1035 	 */
1036 	if (new_speed || priv->cur_speed)
1037 		phy_print_status(phydev);
1038 
1039 	priv->cur_speed = new_speed;
1040 	priv->cur_duplex = phydev->duplex;
1041 	priv->rx_pause = rx_pause;
1042 	priv->tx_pause = tx_pause;
1043 
1044 	/* Link is down, do nothing else */
1045 	if (!new_speed)
1046 		return;
1047 
1048 	/* Disable all interrupts */
1049 	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1050 
1051 	/* Reset the adapter asynchronously */
1052 	schedule_work(&priv->reset_task);
1053 }
1054 
1055 static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf)
1056 {
1057 	struct net_device *netdev = priv->netdev;
1058 	struct phy_device *phydev;
1059 
1060 	phydev = phy_find_first(priv->mii_bus);
1061 	if (!phydev) {
1062 		netdev_info(netdev, "%s: no PHY found\n", netdev->name);
1063 		return -ENODEV;
1064 	}
1065 
1066 	phydev = phy_connect(netdev, phydev_name(phydev),
1067 			     &ftgmac100_adjust_link, intf);
1068 
1069 	if (IS_ERR(phydev)) {
1070 		netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1071 		return PTR_ERR(phydev);
1072 	}
1073 
1074 	/* Indicate that we support PAUSE frames (see comment in
1075 	 * Documentation/networking/phy.txt)
1076 	 */
1077 	phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1078 	phydev->advertising = phydev->supported;
1079 
1080 	/* Display what we found */
1081 	phy_attached_info(phydev);
1082 
1083 	return 0;
1084 }
1085 
1086 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1087 {
1088 	struct net_device *netdev = bus->priv;
1089 	struct ftgmac100 *priv = netdev_priv(netdev);
1090 	unsigned int phycr;
1091 	int i;
1092 
1093 	phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1094 
1095 	/* preserve MDC cycle threshold */
1096 	phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1097 
1098 	phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1099 		 FTGMAC100_PHYCR_REGAD(regnum) |
1100 		 FTGMAC100_PHYCR_MIIRD;
1101 
1102 	iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1103 
1104 	for (i = 0; i < 10; i++) {
1105 		phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1106 
1107 		if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1108 			int data;
1109 
1110 			data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1111 			return FTGMAC100_PHYDATA_MIIRDATA(data);
1112 		}
1113 
1114 		udelay(100);
1115 	}
1116 
1117 	netdev_err(netdev, "mdio read timed out\n");
1118 	return -EIO;
1119 }
1120 
1121 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1122 				   int regnum, u16 value)
1123 {
1124 	struct net_device *netdev = bus->priv;
1125 	struct ftgmac100 *priv = netdev_priv(netdev);
1126 	unsigned int phycr;
1127 	int data;
1128 	int i;
1129 
1130 	phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1131 
1132 	/* preserve MDC cycle threshold */
1133 	phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1134 
1135 	phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1136 		 FTGMAC100_PHYCR_REGAD(regnum) |
1137 		 FTGMAC100_PHYCR_MIIWR;
1138 
1139 	data = FTGMAC100_PHYDATA_MIIWDATA(value);
1140 
1141 	iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1142 	iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1143 
1144 	for (i = 0; i < 10; i++) {
1145 		phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1146 
1147 		if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1148 			return 0;
1149 
1150 		udelay(100);
1151 	}
1152 
1153 	netdev_err(netdev, "mdio write timed out\n");
1154 	return -EIO;
1155 }
1156 
1157 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1158 				  struct ethtool_drvinfo *info)
1159 {
1160 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1161 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1162 	strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1163 }
1164 
1165 static void ftgmac100_get_ringparam(struct net_device *netdev,
1166 				    struct ethtool_ringparam *ering)
1167 {
1168 	struct ftgmac100 *priv = netdev_priv(netdev);
1169 
1170 	memset(ering, 0, sizeof(*ering));
1171 	ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1172 	ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1173 	ering->rx_pending = priv->rx_q_entries;
1174 	ering->tx_pending = priv->tx_q_entries;
1175 }
1176 
1177 static int ftgmac100_set_ringparam(struct net_device *netdev,
1178 				   struct ethtool_ringparam *ering)
1179 {
1180 	struct ftgmac100 *priv = netdev_priv(netdev);
1181 
1182 	if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1183 	    ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1184 	    ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1185 	    ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1186 	    !is_power_of_2(ering->rx_pending) ||
1187 	    !is_power_of_2(ering->tx_pending))
1188 		return -EINVAL;
1189 
1190 	priv->new_rx_q_entries = ering->rx_pending;
1191 	priv->new_tx_q_entries = ering->tx_pending;
1192 	if (netif_running(netdev))
1193 		schedule_work(&priv->reset_task);
1194 
1195 	return 0;
1196 }
1197 
1198 static void ftgmac100_get_pauseparam(struct net_device *netdev,
1199 				     struct ethtool_pauseparam *pause)
1200 {
1201 	struct ftgmac100 *priv = netdev_priv(netdev);
1202 
1203 	pause->autoneg = priv->aneg_pause;
1204 	pause->tx_pause = priv->tx_pause;
1205 	pause->rx_pause = priv->rx_pause;
1206 }
1207 
1208 static int ftgmac100_set_pauseparam(struct net_device *netdev,
1209 				    struct ethtool_pauseparam *pause)
1210 {
1211 	struct ftgmac100 *priv = netdev_priv(netdev);
1212 	struct phy_device *phydev = netdev->phydev;
1213 
1214 	priv->aneg_pause = pause->autoneg;
1215 	priv->tx_pause = pause->tx_pause;
1216 	priv->rx_pause = pause->rx_pause;
1217 
1218 	if (phydev) {
1219 		phydev->advertising &= ~ADVERTISED_Pause;
1220 		phydev->advertising &= ~ADVERTISED_Asym_Pause;
1221 
1222 		if (pause->rx_pause) {
1223 			phydev->advertising |= ADVERTISED_Pause;
1224 			phydev->advertising |= ADVERTISED_Asym_Pause;
1225 		}
1226 
1227 		if (pause->tx_pause)
1228 			phydev->advertising ^= ADVERTISED_Asym_Pause;
1229 	}
1230 	if (netif_running(netdev)) {
1231 		if (phydev && priv->aneg_pause)
1232 			phy_start_aneg(phydev);
1233 		else
1234 			ftgmac100_config_pause(priv);
1235 	}
1236 
1237 	return 0;
1238 }
1239 
1240 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1241 	.get_drvinfo		= ftgmac100_get_drvinfo,
1242 	.get_link		= ethtool_op_get_link,
1243 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
1244 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
1245 	.nway_reset		= phy_ethtool_nway_reset,
1246 	.get_ringparam		= ftgmac100_get_ringparam,
1247 	.set_ringparam		= ftgmac100_set_ringparam,
1248 	.get_pauseparam		= ftgmac100_get_pauseparam,
1249 	.set_pauseparam		= ftgmac100_set_pauseparam,
1250 };
1251 
1252 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1253 {
1254 	struct net_device *netdev = dev_id;
1255 	struct ftgmac100 *priv = netdev_priv(netdev);
1256 	unsigned int status, new_mask = FTGMAC100_INT_BAD;
1257 
1258 	/* Fetch and clear interrupt bits, process abnormal ones */
1259 	status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1260 	iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1261 	if (unlikely(status & FTGMAC100_INT_BAD)) {
1262 
1263 		/* RX buffer unavailable */
1264 		if (status & FTGMAC100_INT_NO_RXBUF)
1265 			netdev->stats.rx_over_errors++;
1266 
1267 		/* received packet lost due to RX FIFO full */
1268 		if (status & FTGMAC100_INT_RPKT_LOST)
1269 			netdev->stats.rx_fifo_errors++;
1270 
1271 		/* sent packet lost due to excessive TX collision */
1272 		if (status & FTGMAC100_INT_XPKT_LOST)
1273 			netdev->stats.tx_fifo_errors++;
1274 
1275 		/* AHB error -> Reset the chip */
1276 		if (status & FTGMAC100_INT_AHB_ERR) {
1277 			if (net_ratelimit())
1278 				netdev_warn(netdev,
1279 					   "AHB bus error ! Resetting chip.\n");
1280 			iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1281 			schedule_work(&priv->reset_task);
1282 			return IRQ_HANDLED;
1283 		}
1284 
1285 		/* We may need to restart the MAC after such errors, delay
1286 		 * this until after we have freed some Rx buffers though
1287 		 */
1288 		priv->need_mac_restart = true;
1289 
1290 		/* Disable those errors until we restart */
1291 		new_mask &= ~status;
1292 	}
1293 
1294 	/* Only enable "bad" interrupts while NAPI is on */
1295 	iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1296 
1297 	/* Schedule NAPI bh */
1298 	napi_schedule_irqoff(&priv->napi);
1299 
1300 	return IRQ_HANDLED;
1301 }
1302 
1303 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1304 {
1305 	struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1306 
1307 	/* Do we have a packet ? */
1308 	return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1309 }
1310 
1311 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1312 {
1313 	struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1314 	int work_done = 0;
1315 	bool more;
1316 
1317 	/* Handle TX completions */
1318 	if (ftgmac100_tx_buf_cleanable(priv))
1319 		ftgmac100_tx_complete(priv);
1320 
1321 	/* Handle RX packets */
1322 	do {
1323 		more = ftgmac100_rx_packet(priv, &work_done);
1324 	} while (more && work_done < budget);
1325 
1326 
1327 	/* The interrupt is telling us to kick the MAC back to life
1328 	 * after an RX overflow
1329 	 */
1330 	if (unlikely(priv->need_mac_restart)) {
1331 		ftgmac100_start_hw(priv);
1332 
1333 		/* Re-enable "bad" interrupts */
1334 		iowrite32(FTGMAC100_INT_BAD,
1335 			  priv->base + FTGMAC100_OFFSET_IER);
1336 	}
1337 
1338 	/* As long as we are waiting for transmit packets to be
1339 	 * completed we keep NAPI going
1340 	 */
1341 	if (ftgmac100_tx_buf_cleanable(priv))
1342 		work_done = budget;
1343 
1344 	if (work_done < budget) {
1345 		/* We are about to re-enable all interrupts. However
1346 		 * the HW has been latching RX/TX packet interrupts while
1347 		 * they were masked. So we clear them first, then we need
1348 		 * to re-check if there's something to process
1349 		 */
1350 		iowrite32(FTGMAC100_INT_RXTX,
1351 			  priv->base + FTGMAC100_OFFSET_ISR);
1352 
1353 		/* Push the above (and provides a barrier vs. subsequent
1354 		 * reads of the descriptor).
1355 		 */
1356 		ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1357 
1358 		/* Check RX and TX descriptors for more work to do */
1359 		if (ftgmac100_check_rx(priv) ||
1360 		    ftgmac100_tx_buf_cleanable(priv))
1361 			return budget;
1362 
1363 		/* deschedule NAPI */
1364 		napi_complete(napi);
1365 
1366 		/* enable all interrupts */
1367 		iowrite32(FTGMAC100_INT_ALL,
1368 			  priv->base + FTGMAC100_OFFSET_IER);
1369 	}
1370 
1371 	return work_done;
1372 }
1373 
1374 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1375 {
1376 	int err = 0;
1377 
1378 	/* Re-init descriptors (adjust queue sizes) */
1379 	ftgmac100_init_rings(priv);
1380 
1381 	/* Realloc rx descriptors */
1382 	err = ftgmac100_alloc_rx_buffers(priv);
1383 	if (err && !ignore_alloc_err)
1384 		return err;
1385 
1386 	/* Reinit and restart HW */
1387 	ftgmac100_init_hw(priv);
1388 	ftgmac100_config_pause(priv);
1389 	ftgmac100_start_hw(priv);
1390 
1391 	/* Re-enable the device */
1392 	napi_enable(&priv->napi);
1393 	netif_start_queue(priv->netdev);
1394 
1395 	/* Enable all interrupts */
1396 	iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1397 
1398 	return err;
1399 }
1400 
1401 static void ftgmac100_reset_task(struct work_struct *work)
1402 {
1403 	struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1404 					      reset_task);
1405 	struct net_device *netdev = priv->netdev;
1406 	int err;
1407 
1408 	netdev_dbg(netdev, "Resetting NIC...\n");
1409 
1410 	/* Lock the world */
1411 	rtnl_lock();
1412 	if (netdev->phydev)
1413 		mutex_lock(&netdev->phydev->lock);
1414 	if (priv->mii_bus)
1415 		mutex_lock(&priv->mii_bus->mdio_lock);
1416 
1417 
1418 	/* Check if the interface is still up */
1419 	if (!netif_running(netdev))
1420 		goto bail;
1421 
1422 	/* Stop the network stack */
1423 	netif_trans_update(netdev);
1424 	napi_disable(&priv->napi);
1425 	netif_tx_disable(netdev);
1426 
1427 	/* Stop and reset the MAC */
1428 	ftgmac100_stop_hw(priv);
1429 	err = ftgmac100_reset_and_config_mac(priv);
1430 	if (err) {
1431 		/* Not much we can do ... it might come back... */
1432 		netdev_err(netdev, "attempting to continue...\n");
1433 	}
1434 
1435 	/* Free all rx and tx buffers */
1436 	ftgmac100_free_buffers(priv);
1437 
1438 	/* Setup everything again and restart chip */
1439 	ftgmac100_init_all(priv, true);
1440 
1441 	netdev_dbg(netdev, "Reset done !\n");
1442  bail:
1443 	if (priv->mii_bus)
1444 		mutex_unlock(&priv->mii_bus->mdio_lock);
1445 	if (netdev->phydev)
1446 		mutex_unlock(&netdev->phydev->lock);
1447 	rtnl_unlock();
1448 }
1449 
1450 static int ftgmac100_open(struct net_device *netdev)
1451 {
1452 	struct ftgmac100 *priv = netdev_priv(netdev);
1453 	int err;
1454 
1455 	/* Allocate ring buffers  */
1456 	err = ftgmac100_alloc_rings(priv);
1457 	if (err) {
1458 		netdev_err(netdev, "Failed to allocate descriptors\n");
1459 		return err;
1460 	}
1461 
1462 	/* When using NC-SI we force the speed to 100Mbit/s full duplex,
1463 	 *
1464 	 * Otherwise we leave it set to 0 (no link), the link
1465 	 * message from the PHY layer will handle setting it up to
1466 	 * something else if needed.
1467 	 */
1468 	if (priv->use_ncsi) {
1469 		priv->cur_duplex = DUPLEX_FULL;
1470 		priv->cur_speed = SPEED_100;
1471 	} else {
1472 		priv->cur_duplex = 0;
1473 		priv->cur_speed = 0;
1474 	}
1475 
1476 	/* Reset the hardware */
1477 	err = ftgmac100_reset_and_config_mac(priv);
1478 	if (err)
1479 		goto err_hw;
1480 
1481 	/* Initialize NAPI */
1482 	netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1483 
1484 	/* Grab our interrupt */
1485 	err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1486 	if (err) {
1487 		netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1488 		goto err_irq;
1489 	}
1490 
1491 	/* Start things up */
1492 	err = ftgmac100_init_all(priv, false);
1493 	if (err) {
1494 		netdev_err(netdev, "Failed to allocate packet buffers\n");
1495 		goto err_alloc;
1496 	}
1497 
1498 	if (netdev->phydev) {
1499 		/* If we have a PHY, start polling */
1500 		phy_start(netdev->phydev);
1501 	} else if (priv->use_ncsi) {
1502 		/* If using NC-SI, set our carrier on and start the stack */
1503 		netif_carrier_on(netdev);
1504 
1505 		/* Start the NCSI device */
1506 		err = ncsi_start_dev(priv->ndev);
1507 		if (err)
1508 			goto err_ncsi;
1509 	}
1510 
1511 	return 0;
1512 
1513  err_ncsi:
1514 	napi_disable(&priv->napi);
1515 	netif_stop_queue(netdev);
1516  err_alloc:
1517 	ftgmac100_free_buffers(priv);
1518 	free_irq(netdev->irq, netdev);
1519  err_irq:
1520 	netif_napi_del(&priv->napi);
1521  err_hw:
1522 	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1523 	ftgmac100_free_rings(priv);
1524 	return err;
1525 }
1526 
1527 static int ftgmac100_stop(struct net_device *netdev)
1528 {
1529 	struct ftgmac100 *priv = netdev_priv(netdev);
1530 
1531 	/* Note about the reset task: We are called with the rtnl lock
1532 	 * held, so we are synchronized against the core of the reset
1533 	 * task. We must not try to synchronously cancel it otherwise
1534 	 * we can deadlock. But since it will test for netif_running()
1535 	 * which has already been cleared by the net core, we don't
1536 	 * anything special to do.
1537 	 */
1538 
1539 	/* disable all interrupts */
1540 	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1541 
1542 	netif_stop_queue(netdev);
1543 	napi_disable(&priv->napi);
1544 	netif_napi_del(&priv->napi);
1545 	if (netdev->phydev)
1546 		phy_stop(netdev->phydev);
1547 	else if (priv->use_ncsi)
1548 		ncsi_stop_dev(priv->ndev);
1549 
1550 	ftgmac100_stop_hw(priv);
1551 	free_irq(netdev->irq, netdev);
1552 	ftgmac100_free_buffers(priv);
1553 	ftgmac100_free_rings(priv);
1554 
1555 	return 0;
1556 }
1557 
1558 /* optional */
1559 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1560 {
1561 	if (!netdev->phydev)
1562 		return -ENXIO;
1563 
1564 	return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1565 }
1566 
1567 static void ftgmac100_tx_timeout(struct net_device *netdev)
1568 {
1569 	struct ftgmac100 *priv = netdev_priv(netdev);
1570 
1571 	/* Disable all interrupts */
1572 	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1573 
1574 	/* Do the reset outside of interrupt context */
1575 	schedule_work(&priv->reset_task);
1576 }
1577 
1578 static int ftgmac100_set_features(struct net_device *netdev,
1579 				  netdev_features_t features)
1580 {
1581 	struct ftgmac100 *priv = netdev_priv(netdev);
1582 	netdev_features_t changed = netdev->features ^ features;
1583 
1584 	if (!netif_running(netdev))
1585 		return 0;
1586 
1587 	/* Update the vlan filtering bit */
1588 	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
1589 		u32 maccr;
1590 
1591 		maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
1592 		if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1593 			maccr |= FTGMAC100_MACCR_RM_VLAN;
1594 		else
1595 			maccr &= ~FTGMAC100_MACCR_RM_VLAN;
1596 		iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
1597 	}
1598 
1599 	return 0;
1600 }
1601 
1602 #ifdef CONFIG_NET_POLL_CONTROLLER
1603 static void ftgmac100_poll_controller(struct net_device *netdev)
1604 {
1605 	unsigned long flags;
1606 
1607 	local_irq_save(flags);
1608 	ftgmac100_interrupt(netdev->irq, netdev);
1609 	local_irq_restore(flags);
1610 }
1611 #endif
1612 
1613 static const struct net_device_ops ftgmac100_netdev_ops = {
1614 	.ndo_open		= ftgmac100_open,
1615 	.ndo_stop		= ftgmac100_stop,
1616 	.ndo_start_xmit		= ftgmac100_hard_start_xmit,
1617 	.ndo_set_mac_address	= ftgmac100_set_mac_addr,
1618 	.ndo_validate_addr	= eth_validate_addr,
1619 	.ndo_do_ioctl		= ftgmac100_do_ioctl,
1620 	.ndo_tx_timeout		= ftgmac100_tx_timeout,
1621 	.ndo_set_rx_mode	= ftgmac100_set_rx_mode,
1622 	.ndo_set_features	= ftgmac100_set_features,
1623 #ifdef CONFIG_NET_POLL_CONTROLLER
1624 	.ndo_poll_controller	= ftgmac100_poll_controller,
1625 #endif
1626 };
1627 
1628 static int ftgmac100_setup_mdio(struct net_device *netdev)
1629 {
1630 	struct ftgmac100 *priv = netdev_priv(netdev);
1631 	struct platform_device *pdev = to_platform_device(priv->dev);
1632 	int phy_intf = PHY_INTERFACE_MODE_RGMII;
1633 	struct device_node *np = pdev->dev.of_node;
1634 	int i, err = 0;
1635 	u32 reg;
1636 
1637 	/* initialize mdio bus */
1638 	priv->mii_bus = mdiobus_alloc();
1639 	if (!priv->mii_bus)
1640 		return -EIO;
1641 
1642 	if (priv->is_aspeed) {
1643 		/* This driver supports the old MDIO interface */
1644 		reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1645 		reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1646 		iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1647 	};
1648 
1649 	/* Get PHY mode from device-tree */
1650 	if (np) {
1651 		/* Default to RGMII. It's a gigabit part after all */
1652 		phy_intf = of_get_phy_mode(np);
1653 		if (phy_intf < 0)
1654 			phy_intf = PHY_INTERFACE_MODE_RGMII;
1655 
1656 		/* Aspeed only supports these. I don't know about other IP
1657 		 * block vendors so I'm going to just let them through for
1658 		 * now. Note that this is only a warning if for some obscure
1659 		 * reason the DT really means to lie about it or it's a newer
1660 		 * part we don't know about.
1661 		 *
1662 		 * On the Aspeed SoC there are additionally straps and SCU
1663 		 * control bits that could tell us what the interface is
1664 		 * (or allow us to configure it while the IP block is held
1665 		 * in reset). For now I chose to keep this driver away from
1666 		 * those SoC specific bits and assume the device-tree is
1667 		 * right and the SCU has been configured properly by pinmux
1668 		 * or the firmware.
1669 		 */
1670 		if (priv->is_aspeed &&
1671 		    phy_intf != PHY_INTERFACE_MODE_RMII &&
1672 		    phy_intf != PHY_INTERFACE_MODE_RGMII &&
1673 		    phy_intf != PHY_INTERFACE_MODE_RGMII_ID &&
1674 		    phy_intf != PHY_INTERFACE_MODE_RGMII_RXID &&
1675 		    phy_intf != PHY_INTERFACE_MODE_RGMII_TXID) {
1676 			netdev_warn(netdev,
1677 				   "Unsupported PHY mode %s !\n",
1678 				   phy_modes(phy_intf));
1679 		}
1680 	}
1681 
1682 	priv->mii_bus->name = "ftgmac100_mdio";
1683 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1684 		 pdev->name, pdev->id);
1685 	priv->mii_bus->priv = priv->netdev;
1686 	priv->mii_bus->read = ftgmac100_mdiobus_read;
1687 	priv->mii_bus->write = ftgmac100_mdiobus_write;
1688 
1689 	for (i = 0; i < PHY_MAX_ADDR; i++)
1690 		priv->mii_bus->irq[i] = PHY_POLL;
1691 
1692 	err = mdiobus_register(priv->mii_bus);
1693 	if (err) {
1694 		dev_err(priv->dev, "Cannot register MDIO bus!\n");
1695 		goto err_register_mdiobus;
1696 	}
1697 
1698 	err = ftgmac100_mii_probe(priv, phy_intf);
1699 	if (err) {
1700 		dev_err(priv->dev, "MII Probe failed!\n");
1701 		goto err_mii_probe;
1702 	}
1703 
1704 	return 0;
1705 
1706 err_mii_probe:
1707 	mdiobus_unregister(priv->mii_bus);
1708 err_register_mdiobus:
1709 	mdiobus_free(priv->mii_bus);
1710 	return err;
1711 }
1712 
1713 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1714 {
1715 	struct ftgmac100 *priv = netdev_priv(netdev);
1716 
1717 	if (!netdev->phydev)
1718 		return;
1719 
1720 	phy_disconnect(netdev->phydev);
1721 	mdiobus_unregister(priv->mii_bus);
1722 	mdiobus_free(priv->mii_bus);
1723 }
1724 
1725 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1726 {
1727 	if (unlikely(nd->state != ncsi_dev_state_functional))
1728 		return;
1729 
1730 	netdev_info(nd->dev, "NCSI interface %s\n",
1731 		    nd->link_up ? "up" : "down");
1732 }
1733 
1734 static int ftgmac100_probe(struct platform_device *pdev)
1735 {
1736 	struct resource *res;
1737 	int irq;
1738 	struct net_device *netdev;
1739 	struct ftgmac100 *priv;
1740 	struct device_node *np;
1741 	int err = 0;
1742 
1743 	if (!pdev)
1744 		return -ENODEV;
1745 
1746 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1747 	if (!res)
1748 		return -ENXIO;
1749 
1750 	irq = platform_get_irq(pdev, 0);
1751 	if (irq < 0)
1752 		return irq;
1753 
1754 	/* setup net_device */
1755 	netdev = alloc_etherdev(sizeof(*priv));
1756 	if (!netdev) {
1757 		err = -ENOMEM;
1758 		goto err_alloc_etherdev;
1759 	}
1760 
1761 	SET_NETDEV_DEV(netdev, &pdev->dev);
1762 
1763 	netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1764 	netdev->netdev_ops = &ftgmac100_netdev_ops;
1765 	netdev->watchdog_timeo = 5 * HZ;
1766 
1767 	platform_set_drvdata(pdev, netdev);
1768 
1769 	/* setup private data */
1770 	priv = netdev_priv(netdev);
1771 	priv->netdev = netdev;
1772 	priv->dev = &pdev->dev;
1773 	INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1774 
1775 	/* map io memory */
1776 	priv->res = request_mem_region(res->start, resource_size(res),
1777 				       dev_name(&pdev->dev));
1778 	if (!priv->res) {
1779 		dev_err(&pdev->dev, "Could not reserve memory region\n");
1780 		err = -ENOMEM;
1781 		goto err_req_mem;
1782 	}
1783 
1784 	priv->base = ioremap(res->start, resource_size(res));
1785 	if (!priv->base) {
1786 		dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1787 		err = -EIO;
1788 		goto err_ioremap;
1789 	}
1790 
1791 	netdev->irq = irq;
1792 
1793 	/* Enable pause */
1794 	priv->tx_pause = true;
1795 	priv->rx_pause = true;
1796 	priv->aneg_pause = true;
1797 
1798 	/* MAC address from chip or random one */
1799 	ftgmac100_initial_mac(priv);
1800 
1801 	np = pdev->dev.of_node;
1802 	if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1803 		   of_device_is_compatible(np, "aspeed,ast2500-mac"))) {
1804 		priv->rxdes0_edorr_mask = BIT(30);
1805 		priv->txdes0_edotr_mask = BIT(30);
1806 		priv->is_aspeed = true;
1807 	} else {
1808 		priv->rxdes0_edorr_mask = BIT(15);
1809 		priv->txdes0_edotr_mask = BIT(15);
1810 	}
1811 
1812 	if (np && of_get_property(np, "use-ncsi", NULL)) {
1813 		if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1814 			dev_err(&pdev->dev, "NCSI stack not enabled\n");
1815 			goto err_ncsi_dev;
1816 		}
1817 
1818 		dev_info(&pdev->dev, "Using NCSI interface\n");
1819 		priv->use_ncsi = true;
1820 		priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1821 		if (!priv->ndev)
1822 			goto err_ncsi_dev;
1823 	} else {
1824 		priv->use_ncsi = false;
1825 		err = ftgmac100_setup_mdio(netdev);
1826 		if (err)
1827 			goto err_setup_mdio;
1828 	}
1829 
1830 	/* Default ring sizes */
1831 	priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1832 	priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1833 
1834 	/* Base feature set */
1835 	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1836 		NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX |
1837 		NETIF_F_HW_VLAN_CTAG_TX;
1838 
1839 	/* AST2400  doesn't have working HW checksum generation */
1840 	if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1841 		netdev->hw_features &= ~NETIF_F_HW_CSUM;
1842 	if (np && of_get_property(np, "no-hw-checksum", NULL))
1843 		netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
1844 	netdev->features |= netdev->hw_features;
1845 
1846 	/* register network device */
1847 	err = register_netdev(netdev);
1848 	if (err) {
1849 		dev_err(&pdev->dev, "Failed to register netdev\n");
1850 		goto err_register_netdev;
1851 	}
1852 
1853 	netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1854 
1855 	return 0;
1856 
1857 err_ncsi_dev:
1858 err_register_netdev:
1859 	ftgmac100_destroy_mdio(netdev);
1860 err_setup_mdio:
1861 	iounmap(priv->base);
1862 err_ioremap:
1863 	release_resource(priv->res);
1864 err_req_mem:
1865 	netif_napi_del(&priv->napi);
1866 	free_netdev(netdev);
1867 err_alloc_etherdev:
1868 	return err;
1869 }
1870 
1871 static int ftgmac100_remove(struct platform_device *pdev)
1872 {
1873 	struct net_device *netdev;
1874 	struct ftgmac100 *priv;
1875 
1876 	netdev = platform_get_drvdata(pdev);
1877 	priv = netdev_priv(netdev);
1878 
1879 	unregister_netdev(netdev);
1880 
1881 	/* There's a small chance the reset task will have been re-queued,
1882 	 * during stop, make sure it's gone before we free the structure.
1883 	 */
1884 	cancel_work_sync(&priv->reset_task);
1885 
1886 	ftgmac100_destroy_mdio(netdev);
1887 
1888 	iounmap(priv->base);
1889 	release_resource(priv->res);
1890 
1891 	netif_napi_del(&priv->napi);
1892 	free_netdev(netdev);
1893 	return 0;
1894 }
1895 
1896 static const struct of_device_id ftgmac100_of_match[] = {
1897 	{ .compatible = "faraday,ftgmac100" },
1898 	{ }
1899 };
1900 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1901 
1902 static struct platform_driver ftgmac100_driver = {
1903 	.probe	= ftgmac100_probe,
1904 	.remove	= ftgmac100_remove,
1905 	.driver	= {
1906 		.name		= DRV_NAME,
1907 		.of_match_table	= ftgmac100_of_match,
1908 	},
1909 };
1910 module_platform_driver(ftgmac100_driver);
1911 
1912 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1913 MODULE_DESCRIPTION("FTGMAC100 driver");
1914 MODULE_LICENSE("GPL");
1915