1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * (C) Copyright 2009-2011 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/dma-mapping.h> 25 #include <linux/etherdevice.h> 26 #include <linux/ethtool.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/of.h> 32 #include <linux/phy.h> 33 #include <linux/platform_device.h> 34 #include <linux/property.h> 35 #include <net/ip.h> 36 #include <net/ncsi.h> 37 38 #include "ftgmac100.h" 39 40 #define DRV_NAME "ftgmac100" 41 #define DRV_VERSION "0.7" 42 43 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */ 44 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */ 45 46 #define MAX_PKT_SIZE 1536 47 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */ 48 49 /* Min number of tx ring entries before stopping queue */ 50 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1) 51 52 struct ftgmac100_descs { 53 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES]; 54 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES]; 55 }; 56 57 struct ftgmac100 { 58 /* Registers */ 59 struct resource *res; 60 void __iomem *base; 61 62 struct ftgmac100_descs *descs; 63 dma_addr_t descs_dma_addr; 64 65 /* Rx ring */ 66 struct sk_buff *rx_skbs[RX_QUEUE_ENTRIES]; 67 unsigned int rx_pointer; 68 u32 rxdes0_edorr_mask; 69 70 /* Tx ring */ 71 struct sk_buff *tx_skbs[TX_QUEUE_ENTRIES]; 72 unsigned int tx_clean_pointer; 73 unsigned int tx_pointer; 74 u32 txdes0_edotr_mask; 75 76 /* Scratch page to use when rx skb alloc fails */ 77 void *rx_scratch; 78 dma_addr_t rx_scratch_dma; 79 80 /* Component structures */ 81 struct net_device *netdev; 82 struct device *dev; 83 struct ncsi_dev *ndev; 84 struct napi_struct napi; 85 struct work_struct reset_task; 86 struct mii_bus *mii_bus; 87 88 /* Link management */ 89 int cur_speed; 90 int cur_duplex; 91 bool use_ncsi; 92 93 /* Misc */ 94 bool need_mac_restart; 95 bool is_aspeed; 96 }; 97 98 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr) 99 { 100 struct net_device *netdev = priv->netdev; 101 int i; 102 103 /* NOTE: reset clears all registers */ 104 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 105 iowrite32(maccr | FTGMAC100_MACCR_SW_RST, 106 priv->base + FTGMAC100_OFFSET_MACCR); 107 for (i = 0; i < 50; i++) { 108 unsigned int maccr; 109 110 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 111 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 112 return 0; 113 114 udelay(1); 115 } 116 117 netdev_err(netdev, "Hardware reset failed\n"); 118 return -EIO; 119 } 120 121 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) 122 { 123 u32 maccr = 0; 124 125 switch (priv->cur_speed) { 126 case SPEED_10: 127 case 0: /* no link */ 128 break; 129 130 case SPEED_100: 131 maccr |= FTGMAC100_MACCR_FAST_MODE; 132 break; 133 134 case SPEED_1000: 135 maccr |= FTGMAC100_MACCR_GIGA_MODE; 136 break; 137 default: 138 netdev_err(priv->netdev, "Unknown speed %d !\n", 139 priv->cur_speed); 140 break; 141 } 142 143 /* (Re)initialize the queue pointers */ 144 priv->rx_pointer = 0; 145 priv->tx_clean_pointer = 0; 146 priv->tx_pointer = 0; 147 148 /* The doc says reset twice with 10us interval */ 149 if (ftgmac100_reset_mac(priv, maccr)) 150 return -EIO; 151 usleep_range(10, 1000); 152 return ftgmac100_reset_mac(priv, maccr); 153 } 154 155 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac) 156 { 157 unsigned int maddr = mac[0] << 8 | mac[1]; 158 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 159 160 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 161 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 162 } 163 164 static void ftgmac100_initial_mac(struct ftgmac100 *priv) 165 { 166 u8 mac[ETH_ALEN]; 167 unsigned int m; 168 unsigned int l; 169 void *addr; 170 171 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN); 172 if (addr) { 173 ether_addr_copy(priv->netdev->dev_addr, mac); 174 dev_info(priv->dev, "Read MAC address %pM from device tree\n", 175 mac); 176 return; 177 } 178 179 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); 180 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); 181 182 mac[0] = (m >> 8) & 0xff; 183 mac[1] = m & 0xff; 184 mac[2] = (l >> 24) & 0xff; 185 mac[3] = (l >> 16) & 0xff; 186 mac[4] = (l >> 8) & 0xff; 187 mac[5] = l & 0xff; 188 189 if (is_valid_ether_addr(mac)) { 190 ether_addr_copy(priv->netdev->dev_addr, mac); 191 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac); 192 } else { 193 eth_hw_addr_random(priv->netdev); 194 dev_info(priv->dev, "Generated random MAC address %pM\n", 195 priv->netdev->dev_addr); 196 } 197 } 198 199 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p) 200 { 201 int ret; 202 203 ret = eth_prepare_mac_addr_change(dev, p); 204 if (ret < 0) 205 return ret; 206 207 eth_commit_mac_addr_change(dev, p); 208 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr); 209 210 return 0; 211 } 212 213 static void ftgmac100_init_hw(struct ftgmac100 *priv) 214 { 215 u32 reg, rfifo_sz, tfifo_sz; 216 217 /* Clear stale interrupts */ 218 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 219 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); 220 221 /* Setup RX ring buffer base */ 222 iowrite32(priv->descs_dma_addr + 223 offsetof(struct ftgmac100_descs, rxdes), 224 priv->base + FTGMAC100_OFFSET_RXR_BADR); 225 226 /* Setup TX ring buffer base */ 227 iowrite32(priv->descs_dma_addr + 228 offsetof(struct ftgmac100_descs, txdes), 229 priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 230 231 /* Configure RX buffer size */ 232 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE), 233 priv->base + FTGMAC100_OFFSET_RBSR); 234 235 /* Set RX descriptor autopoll */ 236 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), 237 priv->base + FTGMAC100_OFFSET_APTC); 238 239 /* Write MAC address */ 240 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr); 241 242 /* Configure descriptor sizes and increase burst sizes according 243 * to values in Aspeed SDK. The FIFO arbitration is enabled and 244 * the thresholds set based on the recommended values in the 245 * AST2400 specification. 246 */ 247 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */ 248 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */ 249 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */ 250 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */ 251 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */ 252 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */ 253 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */ 254 priv->base + FTGMAC100_OFFSET_DBLAC); 255 256 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt 257 * mitigation doesn't seem to provide any benefit with NAPI so leave 258 * it at that. 259 */ 260 iowrite32(FTGMAC100_ITC_RXINT_THR(1) | 261 FTGMAC100_ITC_TXINT_THR(1), 262 priv->base + FTGMAC100_OFFSET_ITC); 263 264 /* Configure FIFO sizes in the TPAFCR register */ 265 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); 266 rfifo_sz = reg & 0x00000007; 267 tfifo_sz = (reg >> 3) & 0x00000007; 268 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); 269 reg &= ~0x3f000000; 270 reg |= (tfifo_sz << 27); 271 reg |= (rfifo_sz << 24); 272 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); 273 } 274 275 static void ftgmac100_start_hw(struct ftgmac100 *priv) 276 { 277 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 278 279 /* Keep the original GMAC and FAST bits */ 280 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE); 281 282 /* Add all the main enable bits */ 283 maccr |= FTGMAC100_MACCR_TXDMA_EN | 284 FTGMAC100_MACCR_RXDMA_EN | 285 FTGMAC100_MACCR_TXMAC_EN | 286 FTGMAC100_MACCR_RXMAC_EN | 287 FTGMAC100_MACCR_CRC_APD | 288 FTGMAC100_MACCR_PHY_LINK_LEVEL | 289 FTGMAC100_MACCR_RX_RUNT | 290 FTGMAC100_MACCR_RX_BROADPKT; 291 292 /* Add other bits as needed */ 293 if (priv->cur_duplex == DUPLEX_FULL) 294 maccr |= FTGMAC100_MACCR_FULLDUP; 295 296 /* Hit the HW */ 297 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 298 } 299 300 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 301 { 302 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 303 } 304 305 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry, 306 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 307 { 308 struct net_device *netdev = priv->netdev; 309 struct sk_buff *skb; 310 dma_addr_t map; 311 int err; 312 313 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE); 314 if (unlikely(!skb)) { 315 if (net_ratelimit()) 316 netdev_warn(netdev, "failed to allocate rx skb\n"); 317 err = -ENOMEM; 318 map = priv->rx_scratch_dma; 319 } else { 320 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE, 321 DMA_FROM_DEVICE); 322 if (unlikely(dma_mapping_error(priv->dev, map))) { 323 if (net_ratelimit()) 324 netdev_err(netdev, "failed to map rx page\n"); 325 dev_kfree_skb_any(skb); 326 map = priv->rx_scratch_dma; 327 skb = NULL; 328 err = -ENOMEM; 329 } 330 } 331 332 /* Store skb */ 333 priv->rx_skbs[entry] = skb; 334 335 /* Store DMA address into RX desc */ 336 rxdes->rxdes3 = cpu_to_le32(map); 337 338 /* Ensure the above is ordered vs clearing the OWN bit */ 339 dma_wmb(); 340 341 /* Clean status (which resets own bit) */ 342 if (entry == (RX_QUEUE_ENTRIES - 1)) 343 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask); 344 else 345 rxdes->rxdes0 = 0; 346 347 return 0; 348 } 349 350 static int ftgmac100_next_rx_pointer(int pointer) 351 { 352 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1); 353 } 354 355 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status) 356 { 357 struct net_device *netdev = priv->netdev; 358 359 if (status & FTGMAC100_RXDES0_RX_ERR) 360 netdev->stats.rx_errors++; 361 362 if (status & FTGMAC100_RXDES0_CRC_ERR) 363 netdev->stats.rx_crc_errors++; 364 365 if (status & (FTGMAC100_RXDES0_FTL | 366 FTGMAC100_RXDES0_RUNT | 367 FTGMAC100_RXDES0_RX_ODD_NB)) 368 netdev->stats.rx_length_errors++; 369 } 370 371 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 372 { 373 struct net_device *netdev = priv->netdev; 374 struct ftgmac100_rxdes *rxdes; 375 struct sk_buff *skb; 376 unsigned int pointer, size; 377 u32 status, csum_vlan; 378 dma_addr_t map; 379 380 /* Grab next RX descriptor */ 381 pointer = priv->rx_pointer; 382 rxdes = &priv->descs->rxdes[pointer]; 383 384 /* Grab descriptor status */ 385 status = le32_to_cpu(rxdes->rxdes0); 386 387 /* Do we have a packet ? */ 388 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY)) 389 return false; 390 391 /* Order subsequent reads with the test for the ready bit */ 392 dma_rmb(); 393 394 /* We don't cope with fragmented RX packets */ 395 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) || 396 !(status & FTGMAC100_RXDES0_LRS))) 397 goto drop; 398 399 /* Grab received size and csum vlan field in the descriptor */ 400 size = status & FTGMAC100_RXDES0_VDBC; 401 csum_vlan = le32_to_cpu(rxdes->rxdes1); 402 403 /* Any error (other than csum offload) flagged ? */ 404 if (unlikely(status & RXDES0_ANY_ERROR)) { 405 /* Correct for incorrect flagging of runt packets 406 * with vlan tags... Just accept a runt packet that 407 * has been flagged as vlan and whose size is at 408 * least 60 bytes. 409 */ 410 if ((status & FTGMAC100_RXDES0_RUNT) && 411 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) && 412 (size >= 60)) 413 status &= ~FTGMAC100_RXDES0_RUNT; 414 415 /* Any error still in there ? */ 416 if (status & RXDES0_ANY_ERROR) { 417 ftgmac100_rx_packet_error(priv, status); 418 goto drop; 419 } 420 } 421 422 /* If the packet had no skb (failed to allocate earlier) 423 * then try to allocate one and skip 424 */ 425 skb = priv->rx_skbs[pointer]; 426 if (!unlikely(skb)) { 427 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 428 goto drop; 429 } 430 431 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST)) 432 netdev->stats.multicast++; 433 434 /* If the HW found checksum errors, bounce it to software. 435 * 436 * If we didn't, we need to see if the packet was recognized 437 * by HW as one of the supported checksummed protocols before 438 * we accept the HW test results. 439 */ 440 if (netdev->features & NETIF_F_RXCSUM) { 441 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR | 442 FTGMAC100_RXDES1_UDP_CHKSUM_ERR | 443 FTGMAC100_RXDES1_IP_CHKSUM_ERR; 444 if ((csum_vlan & err_bits) || 445 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK)) 446 skb->ip_summed = CHECKSUM_NONE; 447 else 448 skb->ip_summed = CHECKSUM_UNNECESSARY; 449 } 450 451 /* Transfer received size to skb */ 452 skb_put(skb, size); 453 454 /* Tear down DMA mapping, do necessary cache management */ 455 map = le32_to_cpu(rxdes->rxdes3); 456 457 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU) 458 /* When we don't have an iommu, we can save cycles by not 459 * invalidating the cache for the part of the packet that 460 * wasn't received. 461 */ 462 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE); 463 #else 464 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 465 #endif 466 467 468 /* Resplenish rx ring */ 469 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 470 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer); 471 472 skb->protocol = eth_type_trans(skb, netdev); 473 474 netdev->stats.rx_packets++; 475 netdev->stats.rx_bytes += size; 476 477 /* push packet to protocol stack */ 478 if (skb->ip_summed == CHECKSUM_NONE) 479 netif_receive_skb(skb); 480 else 481 napi_gro_receive(&priv->napi, skb); 482 483 (*processed)++; 484 return true; 485 486 drop: 487 /* Clean rxdes0 (which resets own bit) */ 488 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask); 489 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer); 490 netdev->stats.rx_dropped++; 491 return true; 492 } 493 494 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv, 495 unsigned int index) 496 { 497 if (index == (TX_QUEUE_ENTRIES - 1)) 498 return priv->txdes0_edotr_mask; 499 else 500 return 0; 501 } 502 503 static int ftgmac100_next_tx_pointer(int pointer) 504 { 505 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1); 506 } 507 508 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv) 509 { 510 /* Returns the number of available slots in the TX queue 511 * 512 * This always leaves one free slot so we don't have to 513 * worry about empty vs. full, and this simplifies the 514 * test for ftgmac100_tx_buf_cleanable() below 515 */ 516 return (priv->tx_clean_pointer - priv->tx_pointer - 1) & 517 (TX_QUEUE_ENTRIES - 1); 518 } 519 520 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv) 521 { 522 return priv->tx_pointer != priv->tx_clean_pointer; 523 } 524 525 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv, 526 unsigned int pointer, 527 struct sk_buff *skb, 528 struct ftgmac100_txdes *txdes, 529 u32 ctl_stat) 530 { 531 dma_addr_t map = le32_to_cpu(txdes->txdes3); 532 size_t len; 533 534 if (ctl_stat & FTGMAC100_TXDES0_FTS) { 535 len = skb_headlen(skb); 536 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE); 537 } else { 538 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat); 539 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE); 540 } 541 542 /* Free SKB on last segment */ 543 if (ctl_stat & FTGMAC100_TXDES0_LTS) 544 dev_kfree_skb(skb); 545 priv->tx_skbs[pointer] = NULL; 546 } 547 548 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 549 { 550 struct net_device *netdev = priv->netdev; 551 struct ftgmac100_txdes *txdes; 552 struct sk_buff *skb; 553 unsigned int pointer; 554 u32 ctl_stat; 555 556 pointer = priv->tx_clean_pointer; 557 txdes = &priv->descs->txdes[pointer]; 558 559 ctl_stat = le32_to_cpu(txdes->txdes0); 560 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN) 561 return false; 562 563 skb = priv->tx_skbs[pointer]; 564 netdev->stats.tx_packets++; 565 netdev->stats.tx_bytes += skb->len; 566 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 567 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 568 569 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(pointer); 570 571 return true; 572 } 573 574 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 575 { 576 struct net_device *netdev = priv->netdev; 577 578 /* Process all completed packets */ 579 while (ftgmac100_tx_buf_cleanable(priv) && 580 ftgmac100_tx_complete_packet(priv)) 581 ; 582 583 /* Restart queue if needed */ 584 smp_mb(); 585 if (unlikely(netif_queue_stopped(netdev) && 586 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) { 587 struct netdev_queue *txq; 588 589 txq = netdev_get_tx_queue(netdev, 0); 590 __netif_tx_lock(txq, smp_processor_id()); 591 if (netif_queue_stopped(netdev) && 592 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 593 netif_wake_queue(netdev); 594 __netif_tx_unlock(txq); 595 } 596 } 597 598 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan) 599 { 600 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 601 u8 ip_proto = ip_hdr(skb)->protocol; 602 603 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM; 604 switch(ip_proto) { 605 case IPPROTO_TCP: 606 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM; 607 return true; 608 case IPPROTO_UDP: 609 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM; 610 return true; 611 case IPPROTO_IP: 612 return true; 613 } 614 } 615 return skb_checksum_help(skb) == 0; 616 } 617 618 static int ftgmac100_hard_start_xmit(struct sk_buff *skb, 619 struct net_device *netdev) 620 { 621 struct ftgmac100 *priv = netdev_priv(netdev); 622 struct ftgmac100_txdes *txdes, *first; 623 unsigned int pointer, nfrags, len, i, j; 624 u32 f_ctl_stat, ctl_stat, csum_vlan; 625 dma_addr_t map; 626 627 /* The HW doesn't pad small frames */ 628 if (eth_skb_pad(skb)) { 629 netdev->stats.tx_dropped++; 630 return NETDEV_TX_OK; 631 } 632 633 /* Reject oversize packets */ 634 if (unlikely(skb->len > MAX_PKT_SIZE)) { 635 if (net_ratelimit()) 636 netdev_dbg(netdev, "tx packet too big\n"); 637 goto drop; 638 } 639 640 /* Do we have a limit on #fragments ? I yet have to get a reply 641 * from Aspeed. If there's one I haven't hit it. 642 */ 643 nfrags = skb_shinfo(skb)->nr_frags; 644 645 /* Get header len */ 646 len = skb_headlen(skb); 647 648 /* Map the packet head */ 649 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 650 if (dma_mapping_error(priv->dev, map)) { 651 if (net_ratelimit()) 652 netdev_err(netdev, "map tx packet head failed\n"); 653 goto drop; 654 } 655 656 /* Grab the next free tx descriptor */ 657 pointer = priv->tx_pointer; 658 txdes = first = &priv->descs->txdes[pointer]; 659 660 /* Setup it up with the packet head. Don't write the head to the 661 * ring just yet 662 */ 663 priv->tx_skbs[pointer] = skb; 664 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 665 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 666 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 667 f_ctl_stat |= FTGMAC100_TXDES0_FTS; 668 if (nfrags == 0) 669 f_ctl_stat |= FTGMAC100_TXDES0_LTS; 670 txdes->txdes3 = cpu_to_le32(map); 671 672 /* Setup HW checksumming */ 673 csum_vlan = 0; 674 if (skb->ip_summed == CHECKSUM_PARTIAL && 675 !ftgmac100_prep_tx_csum(skb, &csum_vlan)) 676 goto drop; 677 txdes->txdes1 = cpu_to_le32(csum_vlan); 678 679 /* Next descriptor */ 680 pointer = ftgmac100_next_tx_pointer(pointer); 681 682 /* Add the fragments */ 683 for (i = 0; i < nfrags; i++) { 684 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 685 686 len = frag->size; 687 688 /* Map it */ 689 map = skb_frag_dma_map(priv->dev, frag, 0, len, 690 DMA_TO_DEVICE); 691 if (dma_mapping_error(priv->dev, map)) 692 goto dma_err; 693 694 /* Setup descriptor */ 695 priv->tx_skbs[pointer] = skb; 696 txdes = &priv->descs->txdes[pointer]; 697 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 698 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 699 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 700 if (i == (nfrags - 1)) 701 ctl_stat |= FTGMAC100_TXDES0_LTS; 702 txdes->txdes0 = cpu_to_le32(ctl_stat); 703 txdes->txdes1 = 0; 704 txdes->txdes3 = cpu_to_le32(map); 705 706 /* Next one */ 707 pointer = ftgmac100_next_tx_pointer(pointer); 708 } 709 710 /* Order the previous packet and descriptor udpates 711 * before setting the OWN bit on the first descriptor. 712 */ 713 dma_wmb(); 714 first->txdes0 = cpu_to_le32(f_ctl_stat); 715 716 /* Update next TX pointer */ 717 priv->tx_pointer = pointer; 718 719 /* If there isn't enough room for all the fragments of a new packet 720 * in the TX ring, stop the queue. The sequence below is race free 721 * vs. a concurrent restart in ftgmac100_poll() 722 */ 723 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) { 724 netif_stop_queue(netdev); 725 /* Order the queue stop with the test below */ 726 smp_mb(); 727 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 728 netif_wake_queue(netdev); 729 } 730 731 /* Poke transmitter to read the updated TX descriptors */ 732 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 733 734 return NETDEV_TX_OK; 735 736 dma_err: 737 if (net_ratelimit()) 738 netdev_err(netdev, "map tx fragment failed\n"); 739 740 /* Free head */ 741 pointer = priv->tx_pointer; 742 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat); 743 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask); 744 745 /* Then all fragments */ 746 for (j = 0; j < i; j++) { 747 pointer = ftgmac100_next_tx_pointer(pointer); 748 txdes = &priv->descs->txdes[pointer]; 749 ctl_stat = le32_to_cpu(txdes->txdes0); 750 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 751 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 752 } 753 754 /* This cannot be reached if we successfully mapped the 755 * last fragment, so we know ftgmac100_free_tx_packet() 756 * hasn't freed the skb yet. 757 */ 758 drop: 759 /* Drop the packet */ 760 dev_kfree_skb_any(skb); 761 netdev->stats.tx_dropped++; 762 763 return NETDEV_TX_OK; 764 } 765 766 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 767 { 768 int i; 769 770 /* Free all RX buffers */ 771 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 772 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 773 struct sk_buff *skb = priv->rx_skbs[i]; 774 dma_addr_t map = le32_to_cpu(rxdes->rxdes3); 775 776 if (!skb) 777 continue; 778 779 priv->rx_skbs[i] = NULL; 780 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 781 dev_kfree_skb_any(skb); 782 } 783 784 /* Free all TX buffers */ 785 for (i = 0; i < TX_QUEUE_ENTRIES; i++) { 786 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i]; 787 struct sk_buff *skb = priv->tx_skbs[i]; 788 789 if (!skb) 790 continue; 791 ftgmac100_free_tx_packet(priv, i, skb, txdes, 792 le32_to_cpu(txdes->txdes0)); 793 } 794 } 795 796 static void ftgmac100_free_rings(struct ftgmac100 *priv) 797 { 798 /* Free descriptors */ 799 if (priv->descs) 800 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs), 801 priv->descs, priv->descs_dma_addr); 802 803 /* Free scratch packet buffer */ 804 if (priv->rx_scratch) 805 dma_free_coherent(priv->dev, RX_BUF_SIZE, 806 priv->rx_scratch, priv->rx_scratch_dma); 807 } 808 809 static int ftgmac100_alloc_rings(struct ftgmac100 *priv) 810 { 811 /* Allocate descriptors */ 812 priv->descs = dma_zalloc_coherent(priv->dev, 813 sizeof(struct ftgmac100_descs), 814 &priv->descs_dma_addr, GFP_KERNEL); 815 if (!priv->descs) 816 return -ENOMEM; 817 818 /* Allocate scratch packet buffer */ 819 priv->rx_scratch = dma_alloc_coherent(priv->dev, 820 RX_BUF_SIZE, 821 &priv->rx_scratch_dma, 822 GFP_KERNEL); 823 if (!priv->rx_scratch) 824 return -ENOMEM; 825 826 return 0; 827 } 828 829 static void ftgmac100_init_rings(struct ftgmac100 *priv) 830 { 831 struct ftgmac100_rxdes *rxdes; 832 struct ftgmac100_txdes *txdes; 833 int i; 834 835 /* Initialize RX ring */ 836 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 837 rxdes = &priv->descs->rxdes[i]; 838 rxdes->rxdes0 = 0; 839 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma); 840 } 841 /* Mark the end of the ring */ 842 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); 843 844 /* Initialize TX ring */ 845 for (i = 0; i < TX_QUEUE_ENTRIES; i++) { 846 txdes = &priv->descs->txdes[i]; 847 txdes->txdes0 = 0; 848 } 849 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask); 850 } 851 852 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv) 853 { 854 int i; 855 856 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 857 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 858 859 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL)) 860 return -ENOMEM; 861 } 862 return 0; 863 } 864 865 static void ftgmac100_adjust_link(struct net_device *netdev) 866 { 867 struct ftgmac100 *priv = netdev_priv(netdev); 868 struct phy_device *phydev = netdev->phydev; 869 int new_speed; 870 871 /* We store "no link" as speed 0 */ 872 if (!phydev->link) 873 new_speed = 0; 874 else 875 new_speed = phydev->speed; 876 877 if (phydev->speed == priv->cur_speed && 878 phydev->duplex == priv->cur_duplex) 879 return; 880 881 /* Print status if we have a link or we had one and just lost it, 882 * don't print otherwise. 883 */ 884 if (new_speed || priv->cur_speed) 885 phy_print_status(phydev); 886 887 priv->cur_speed = new_speed; 888 priv->cur_duplex = phydev->duplex; 889 890 /* Link is down, do nothing else */ 891 if (!new_speed) 892 return; 893 894 /* Disable all interrupts */ 895 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 896 897 /* Reset the adapter asynchronously */ 898 schedule_work(&priv->reset_task); 899 } 900 901 static int ftgmac100_mii_probe(struct ftgmac100 *priv) 902 { 903 struct net_device *netdev = priv->netdev; 904 struct phy_device *phydev; 905 906 phydev = phy_find_first(priv->mii_bus); 907 if (!phydev) { 908 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 909 return -ENODEV; 910 } 911 912 phydev = phy_connect(netdev, phydev_name(phydev), 913 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII); 914 915 if (IS_ERR(phydev)) { 916 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 917 return PTR_ERR(phydev); 918 } 919 920 return 0; 921 } 922 923 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 924 { 925 struct net_device *netdev = bus->priv; 926 struct ftgmac100 *priv = netdev_priv(netdev); 927 unsigned int phycr; 928 int i; 929 930 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 931 932 /* preserve MDC cycle threshold */ 933 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 934 935 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 936 FTGMAC100_PHYCR_REGAD(regnum) | 937 FTGMAC100_PHYCR_MIIRD; 938 939 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 940 941 for (i = 0; i < 10; i++) { 942 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 943 944 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 945 int data; 946 947 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 948 return FTGMAC100_PHYDATA_MIIRDATA(data); 949 } 950 951 udelay(100); 952 } 953 954 netdev_err(netdev, "mdio read timed out\n"); 955 return -EIO; 956 } 957 958 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 959 int regnum, u16 value) 960 { 961 struct net_device *netdev = bus->priv; 962 struct ftgmac100 *priv = netdev_priv(netdev); 963 unsigned int phycr; 964 int data; 965 int i; 966 967 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 968 969 /* preserve MDC cycle threshold */ 970 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 971 972 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 973 FTGMAC100_PHYCR_REGAD(regnum) | 974 FTGMAC100_PHYCR_MIIWR; 975 976 data = FTGMAC100_PHYDATA_MIIWDATA(value); 977 978 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 979 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 980 981 for (i = 0; i < 10; i++) { 982 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 983 984 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 985 return 0; 986 987 udelay(100); 988 } 989 990 netdev_err(netdev, "mdio write timed out\n"); 991 return -EIO; 992 } 993 994 static void ftgmac100_get_drvinfo(struct net_device *netdev, 995 struct ethtool_drvinfo *info) 996 { 997 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 998 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 999 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); 1000 } 1001 1002 static const struct ethtool_ops ftgmac100_ethtool_ops = { 1003 .get_drvinfo = ftgmac100_get_drvinfo, 1004 .get_link = ethtool_op_get_link, 1005 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1006 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1007 }; 1008 1009 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 1010 { 1011 struct net_device *netdev = dev_id; 1012 struct ftgmac100 *priv = netdev_priv(netdev); 1013 unsigned int status, new_mask = FTGMAC100_INT_BAD; 1014 1015 /* Fetch and clear interrupt bits, process abnormal ones */ 1016 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1017 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1018 if (unlikely(status & FTGMAC100_INT_BAD)) { 1019 1020 /* RX buffer unavailable */ 1021 if (status & FTGMAC100_INT_NO_RXBUF) 1022 netdev->stats.rx_over_errors++; 1023 1024 /* received packet lost due to RX FIFO full */ 1025 if (status & FTGMAC100_INT_RPKT_LOST) 1026 netdev->stats.rx_fifo_errors++; 1027 1028 /* sent packet lost due to excessive TX collision */ 1029 if (status & FTGMAC100_INT_XPKT_LOST) 1030 netdev->stats.tx_fifo_errors++; 1031 1032 /* AHB error -> Reset the chip */ 1033 if (status & FTGMAC100_INT_AHB_ERR) { 1034 if (net_ratelimit()) 1035 netdev_warn(netdev, 1036 "AHB bus error ! Resetting chip.\n"); 1037 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1038 schedule_work(&priv->reset_task); 1039 return IRQ_HANDLED; 1040 } 1041 1042 /* We may need to restart the MAC after such errors, delay 1043 * this until after we have freed some Rx buffers though 1044 */ 1045 priv->need_mac_restart = true; 1046 1047 /* Disable those errors until we restart */ 1048 new_mask &= ~status; 1049 } 1050 1051 /* Only enable "bad" interrupts while NAPI is on */ 1052 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER); 1053 1054 /* Schedule NAPI bh */ 1055 napi_schedule_irqoff(&priv->napi); 1056 1057 return IRQ_HANDLED; 1058 } 1059 1060 static bool ftgmac100_check_rx(struct ftgmac100 *priv) 1061 { 1062 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[priv->rx_pointer]; 1063 1064 /* Do we have a packet ? */ 1065 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY)); 1066 } 1067 1068 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1069 { 1070 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1071 int work_done = 0; 1072 bool more; 1073 1074 /* Handle TX completions */ 1075 if (ftgmac100_tx_buf_cleanable(priv)) 1076 ftgmac100_tx_complete(priv); 1077 1078 /* Handle RX packets */ 1079 do { 1080 more = ftgmac100_rx_packet(priv, &work_done); 1081 } while (more && work_done < budget); 1082 1083 1084 /* The interrupt is telling us to kick the MAC back to life 1085 * after an RX overflow 1086 */ 1087 if (unlikely(priv->need_mac_restart)) { 1088 ftgmac100_start_hw(priv); 1089 1090 /* Re-enable "bad" interrupts */ 1091 iowrite32(FTGMAC100_INT_BAD, 1092 priv->base + FTGMAC100_OFFSET_IER); 1093 } 1094 1095 /* As long as we are waiting for transmit packets to be 1096 * completed we keep NAPI going 1097 */ 1098 if (ftgmac100_tx_buf_cleanable(priv)) 1099 work_done = budget; 1100 1101 if (work_done < budget) { 1102 /* We are about to re-enable all interrupts. However 1103 * the HW has been latching RX/TX packet interrupts while 1104 * they were masked. So we clear them first, then we need 1105 * to re-check if there's something to process 1106 */ 1107 iowrite32(FTGMAC100_INT_RXTX, 1108 priv->base + FTGMAC100_OFFSET_ISR); 1109 if (ftgmac100_check_rx(priv) || 1110 ftgmac100_tx_buf_cleanable(priv)) 1111 return budget; 1112 1113 /* deschedule NAPI */ 1114 napi_complete(napi); 1115 1116 /* enable all interrupts */ 1117 iowrite32(FTGMAC100_INT_ALL, 1118 priv->base + FTGMAC100_OFFSET_IER); 1119 } 1120 1121 return work_done; 1122 } 1123 1124 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err) 1125 { 1126 int err = 0; 1127 1128 /* Re-init descriptors (adjust queue sizes) */ 1129 ftgmac100_init_rings(priv); 1130 1131 /* Realloc rx descriptors */ 1132 err = ftgmac100_alloc_rx_buffers(priv); 1133 if (err && !ignore_alloc_err) 1134 return err; 1135 1136 /* Reinit and restart HW */ 1137 ftgmac100_init_hw(priv); 1138 ftgmac100_start_hw(priv); 1139 1140 /* Re-enable the device */ 1141 napi_enable(&priv->napi); 1142 netif_start_queue(priv->netdev); 1143 1144 /* Enable all interrupts */ 1145 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER); 1146 1147 return err; 1148 } 1149 1150 static void ftgmac100_reset_task(struct work_struct *work) 1151 { 1152 struct ftgmac100 *priv = container_of(work, struct ftgmac100, 1153 reset_task); 1154 struct net_device *netdev = priv->netdev; 1155 int err; 1156 1157 netdev_dbg(netdev, "Resetting NIC...\n"); 1158 1159 /* Lock the world */ 1160 rtnl_lock(); 1161 if (netdev->phydev) 1162 mutex_lock(&netdev->phydev->lock); 1163 if (priv->mii_bus) 1164 mutex_lock(&priv->mii_bus->mdio_lock); 1165 1166 1167 /* Check if the interface is still up */ 1168 if (!netif_running(netdev)) 1169 goto bail; 1170 1171 /* Stop the network stack */ 1172 netif_trans_update(netdev); 1173 napi_disable(&priv->napi); 1174 netif_tx_disable(netdev); 1175 1176 /* Stop and reset the MAC */ 1177 ftgmac100_stop_hw(priv); 1178 err = ftgmac100_reset_and_config_mac(priv); 1179 if (err) { 1180 /* Not much we can do ... it might come back... */ 1181 netdev_err(netdev, "attempting to continue...\n"); 1182 } 1183 1184 /* Free all rx and tx buffers */ 1185 ftgmac100_free_buffers(priv); 1186 1187 /* Setup everything again and restart chip */ 1188 ftgmac100_init_all(priv, true); 1189 1190 netdev_dbg(netdev, "Reset done !\n"); 1191 bail: 1192 if (priv->mii_bus) 1193 mutex_unlock(&priv->mii_bus->mdio_lock); 1194 if (netdev->phydev) 1195 mutex_unlock(&netdev->phydev->lock); 1196 rtnl_unlock(); 1197 } 1198 1199 static int ftgmac100_open(struct net_device *netdev) 1200 { 1201 struct ftgmac100 *priv = netdev_priv(netdev); 1202 int err; 1203 1204 /* Allocate ring buffers */ 1205 err = ftgmac100_alloc_rings(priv); 1206 if (err) { 1207 netdev_err(netdev, "Failed to allocate descriptors\n"); 1208 return err; 1209 } 1210 1211 /* When using NC-SI we force the speed to 100Mbit/s full duplex, 1212 * 1213 * Otherwise we leave it set to 0 (no link), the link 1214 * message from the PHY layer will handle setting it up to 1215 * something else if needed. 1216 */ 1217 if (priv->use_ncsi) { 1218 priv->cur_duplex = DUPLEX_FULL; 1219 priv->cur_speed = SPEED_100; 1220 } else { 1221 priv->cur_duplex = 0; 1222 priv->cur_speed = 0; 1223 } 1224 1225 /* Reset the hardware */ 1226 err = ftgmac100_reset_and_config_mac(priv); 1227 if (err) 1228 goto err_hw; 1229 1230 /* Initialize NAPI */ 1231 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1232 1233 /* Grab our interrupt */ 1234 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1235 if (err) { 1236 netdev_err(netdev, "failed to request irq %d\n", netdev->irq); 1237 goto err_irq; 1238 } 1239 1240 /* Start things up */ 1241 err = ftgmac100_init_all(priv, false); 1242 if (err) { 1243 netdev_err(netdev, "Failed to allocate packet buffers\n"); 1244 goto err_alloc; 1245 } 1246 1247 if (netdev->phydev) { 1248 /* If we have a PHY, start polling */ 1249 phy_start(netdev->phydev); 1250 } else if (priv->use_ncsi) { 1251 /* If using NC-SI, set our carrier on and start the stack */ 1252 netif_carrier_on(netdev); 1253 1254 /* Start the NCSI device */ 1255 err = ncsi_start_dev(priv->ndev); 1256 if (err) 1257 goto err_ncsi; 1258 } 1259 1260 return 0; 1261 1262 err_ncsi: 1263 napi_disable(&priv->napi); 1264 netif_stop_queue(netdev); 1265 err_alloc: 1266 ftgmac100_free_buffers(priv); 1267 free_irq(netdev->irq, netdev); 1268 err_irq: 1269 netif_napi_del(&priv->napi); 1270 err_hw: 1271 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1272 ftgmac100_free_rings(priv); 1273 return err; 1274 } 1275 1276 static int ftgmac100_stop(struct net_device *netdev) 1277 { 1278 struct ftgmac100 *priv = netdev_priv(netdev); 1279 1280 /* Note about the reset task: We are called with the rtnl lock 1281 * held, so we are synchronized against the core of the reset 1282 * task. We must not try to synchronously cancel it otherwise 1283 * we can deadlock. But since it will test for netif_running() 1284 * which has already been cleared by the net core, we don't 1285 * anything special to do. 1286 */ 1287 1288 /* disable all interrupts */ 1289 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1290 1291 netif_stop_queue(netdev); 1292 napi_disable(&priv->napi); 1293 netif_napi_del(&priv->napi); 1294 if (netdev->phydev) 1295 phy_stop(netdev->phydev); 1296 else if (priv->use_ncsi) 1297 ncsi_stop_dev(priv->ndev); 1298 1299 ftgmac100_stop_hw(priv); 1300 free_irq(netdev->irq, netdev); 1301 ftgmac100_free_buffers(priv); 1302 ftgmac100_free_rings(priv); 1303 1304 return 0; 1305 } 1306 1307 /* optional */ 1308 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1309 { 1310 if (!netdev->phydev) 1311 return -ENXIO; 1312 1313 return phy_mii_ioctl(netdev->phydev, ifr, cmd); 1314 } 1315 1316 static void ftgmac100_tx_timeout(struct net_device *netdev) 1317 { 1318 struct ftgmac100 *priv = netdev_priv(netdev); 1319 1320 /* Disable all interrupts */ 1321 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1322 1323 /* Do the reset outside of interrupt context */ 1324 schedule_work(&priv->reset_task); 1325 } 1326 1327 static const struct net_device_ops ftgmac100_netdev_ops = { 1328 .ndo_open = ftgmac100_open, 1329 .ndo_stop = ftgmac100_stop, 1330 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1331 .ndo_set_mac_address = ftgmac100_set_mac_addr, 1332 .ndo_validate_addr = eth_validate_addr, 1333 .ndo_do_ioctl = ftgmac100_do_ioctl, 1334 .ndo_tx_timeout = ftgmac100_tx_timeout, 1335 }; 1336 1337 static int ftgmac100_setup_mdio(struct net_device *netdev) 1338 { 1339 struct ftgmac100 *priv = netdev_priv(netdev); 1340 struct platform_device *pdev = to_platform_device(priv->dev); 1341 int i, err = 0; 1342 u32 reg; 1343 1344 /* initialize mdio bus */ 1345 priv->mii_bus = mdiobus_alloc(); 1346 if (!priv->mii_bus) 1347 return -EIO; 1348 1349 if (priv->is_aspeed) { 1350 /* This driver supports the old MDIO interface */ 1351 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); 1352 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; 1353 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); 1354 }; 1355 1356 priv->mii_bus->name = "ftgmac100_mdio"; 1357 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1358 pdev->name, pdev->id); 1359 priv->mii_bus->priv = priv->netdev; 1360 priv->mii_bus->read = ftgmac100_mdiobus_read; 1361 priv->mii_bus->write = ftgmac100_mdiobus_write; 1362 1363 for (i = 0; i < PHY_MAX_ADDR; i++) 1364 priv->mii_bus->irq[i] = PHY_POLL; 1365 1366 err = mdiobus_register(priv->mii_bus); 1367 if (err) { 1368 dev_err(priv->dev, "Cannot register MDIO bus!\n"); 1369 goto err_register_mdiobus; 1370 } 1371 1372 err = ftgmac100_mii_probe(priv); 1373 if (err) { 1374 dev_err(priv->dev, "MII Probe failed!\n"); 1375 goto err_mii_probe; 1376 } 1377 1378 return 0; 1379 1380 err_mii_probe: 1381 mdiobus_unregister(priv->mii_bus); 1382 err_register_mdiobus: 1383 mdiobus_free(priv->mii_bus); 1384 return err; 1385 } 1386 1387 static void ftgmac100_destroy_mdio(struct net_device *netdev) 1388 { 1389 struct ftgmac100 *priv = netdev_priv(netdev); 1390 1391 if (!netdev->phydev) 1392 return; 1393 1394 phy_disconnect(netdev->phydev); 1395 mdiobus_unregister(priv->mii_bus); 1396 mdiobus_free(priv->mii_bus); 1397 } 1398 1399 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) 1400 { 1401 if (unlikely(nd->state != ncsi_dev_state_functional)) 1402 return; 1403 1404 netdev_info(nd->dev, "NCSI interface %s\n", 1405 nd->link_up ? "up" : "down"); 1406 } 1407 1408 static int ftgmac100_probe(struct platform_device *pdev) 1409 { 1410 struct resource *res; 1411 int irq; 1412 struct net_device *netdev; 1413 struct ftgmac100 *priv; 1414 struct device_node *np; 1415 int err = 0; 1416 1417 if (!pdev) 1418 return -ENODEV; 1419 1420 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1421 if (!res) 1422 return -ENXIO; 1423 1424 irq = platform_get_irq(pdev, 0); 1425 if (irq < 0) 1426 return irq; 1427 1428 /* setup net_device */ 1429 netdev = alloc_etherdev(sizeof(*priv)); 1430 if (!netdev) { 1431 err = -ENOMEM; 1432 goto err_alloc_etherdev; 1433 } 1434 1435 SET_NETDEV_DEV(netdev, &pdev->dev); 1436 1437 netdev->ethtool_ops = &ftgmac100_ethtool_ops; 1438 netdev->netdev_ops = &ftgmac100_netdev_ops; 1439 netdev->watchdog_timeo = 5 * HZ; 1440 1441 platform_set_drvdata(pdev, netdev); 1442 1443 /* setup private data */ 1444 priv = netdev_priv(netdev); 1445 priv->netdev = netdev; 1446 priv->dev = &pdev->dev; 1447 INIT_WORK(&priv->reset_task, ftgmac100_reset_task); 1448 1449 /* map io memory */ 1450 priv->res = request_mem_region(res->start, resource_size(res), 1451 dev_name(&pdev->dev)); 1452 if (!priv->res) { 1453 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1454 err = -ENOMEM; 1455 goto err_req_mem; 1456 } 1457 1458 priv->base = ioremap(res->start, resource_size(res)); 1459 if (!priv->base) { 1460 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1461 err = -EIO; 1462 goto err_ioremap; 1463 } 1464 1465 netdev->irq = irq; 1466 1467 /* MAC address from chip or random one */ 1468 ftgmac100_initial_mac(priv); 1469 1470 np = pdev->dev.of_node; 1471 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1472 of_device_is_compatible(np, "aspeed,ast2500-mac"))) { 1473 priv->rxdes0_edorr_mask = BIT(30); 1474 priv->txdes0_edotr_mask = BIT(30); 1475 priv->is_aspeed = true; 1476 } else { 1477 priv->rxdes0_edorr_mask = BIT(15); 1478 priv->txdes0_edotr_mask = BIT(15); 1479 } 1480 1481 if (np && of_get_property(np, "use-ncsi", NULL)) { 1482 if (!IS_ENABLED(CONFIG_NET_NCSI)) { 1483 dev_err(&pdev->dev, "NCSI stack not enabled\n"); 1484 goto err_ncsi_dev; 1485 } 1486 1487 dev_info(&pdev->dev, "Using NCSI interface\n"); 1488 priv->use_ncsi = true; 1489 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); 1490 if (!priv->ndev) 1491 goto err_ncsi_dev; 1492 } else { 1493 priv->use_ncsi = false; 1494 err = ftgmac100_setup_mdio(netdev); 1495 if (err) 1496 goto err_setup_mdio; 1497 } 1498 1499 /* Base feature set */ 1500 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM | 1501 NETIF_F_GRO | NETIF_F_SG; 1502 1503 /* AST2400 doesn't have working HW checksum generation */ 1504 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac"))) 1505 netdev->hw_features &= ~NETIF_F_HW_CSUM; 1506 if (np && of_get_property(np, "no-hw-checksum", NULL)) 1507 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM); 1508 netdev->features |= netdev->hw_features; 1509 1510 /* register network device */ 1511 err = register_netdev(netdev); 1512 if (err) { 1513 dev_err(&pdev->dev, "Failed to register netdev\n"); 1514 goto err_register_netdev; 1515 } 1516 1517 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base); 1518 1519 return 0; 1520 1521 err_ncsi_dev: 1522 err_register_netdev: 1523 ftgmac100_destroy_mdio(netdev); 1524 err_setup_mdio: 1525 iounmap(priv->base); 1526 err_ioremap: 1527 release_resource(priv->res); 1528 err_req_mem: 1529 netif_napi_del(&priv->napi); 1530 free_netdev(netdev); 1531 err_alloc_etherdev: 1532 return err; 1533 } 1534 1535 static int ftgmac100_remove(struct platform_device *pdev) 1536 { 1537 struct net_device *netdev; 1538 struct ftgmac100 *priv; 1539 1540 netdev = platform_get_drvdata(pdev); 1541 priv = netdev_priv(netdev); 1542 1543 unregister_netdev(netdev); 1544 1545 /* There's a small chance the reset task will have been re-queued, 1546 * during stop, make sure it's gone before we free the structure. 1547 */ 1548 cancel_work_sync(&priv->reset_task); 1549 1550 ftgmac100_destroy_mdio(netdev); 1551 1552 iounmap(priv->base); 1553 release_resource(priv->res); 1554 1555 netif_napi_del(&priv->napi); 1556 free_netdev(netdev); 1557 return 0; 1558 } 1559 1560 static const struct of_device_id ftgmac100_of_match[] = { 1561 { .compatible = "faraday,ftgmac100" }, 1562 { } 1563 }; 1564 MODULE_DEVICE_TABLE(of, ftgmac100_of_match); 1565 1566 static struct platform_driver ftgmac100_driver = { 1567 .probe = ftgmac100_probe, 1568 .remove = ftgmac100_remove, 1569 .driver = { 1570 .name = DRV_NAME, 1571 .of_match_table = ftgmac100_of_match, 1572 }, 1573 }; 1574 module_platform_driver(ftgmac100_driver); 1575 1576 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1577 MODULE_DESCRIPTION("FTGMAC100 driver"); 1578 MODULE_LICENSE("GPL"); 1579