1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * (C) Copyright 2009-2011 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/dma-mapping.h> 25 #include <linux/etherdevice.h> 26 #include <linux/ethtool.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/of.h> 32 #include <linux/phy.h> 33 #include <linux/platform_device.h> 34 #include <linux/property.h> 35 #include <linux/crc32.h> 36 #include <linux/if_vlan.h> 37 #include <net/ip.h> 38 #include <net/ncsi.h> 39 40 #include "ftgmac100.h" 41 42 #define DRV_NAME "ftgmac100" 43 #define DRV_VERSION "0.7" 44 45 /* Arbitrary values, I am not sure the HW has limits */ 46 #define MAX_RX_QUEUE_ENTRIES 1024 47 #define MAX_TX_QUEUE_ENTRIES 1024 48 #define MIN_RX_QUEUE_ENTRIES 32 49 #define MIN_TX_QUEUE_ENTRIES 32 50 51 /* Defaults */ 52 #define DEF_RX_QUEUE_ENTRIES 128 53 #define DEF_TX_QUEUE_ENTRIES 128 54 55 #define MAX_PKT_SIZE 1536 56 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */ 57 58 /* Min number of tx ring entries before stopping queue */ 59 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1) 60 61 struct ftgmac100 { 62 /* Registers */ 63 struct resource *res; 64 void __iomem *base; 65 66 /* Rx ring */ 67 unsigned int rx_q_entries; 68 struct ftgmac100_rxdes *rxdes; 69 dma_addr_t rxdes_dma; 70 struct sk_buff **rx_skbs; 71 unsigned int rx_pointer; 72 u32 rxdes0_edorr_mask; 73 74 /* Tx ring */ 75 unsigned int tx_q_entries; 76 struct ftgmac100_txdes *txdes; 77 dma_addr_t txdes_dma; 78 struct sk_buff **tx_skbs; 79 unsigned int tx_clean_pointer; 80 unsigned int tx_pointer; 81 u32 txdes0_edotr_mask; 82 83 /* Used to signal the reset task of ring change request */ 84 unsigned int new_rx_q_entries; 85 unsigned int new_tx_q_entries; 86 87 /* Scratch page to use when rx skb alloc fails */ 88 void *rx_scratch; 89 dma_addr_t rx_scratch_dma; 90 91 /* Component structures */ 92 struct net_device *netdev; 93 struct device *dev; 94 struct ncsi_dev *ndev; 95 struct napi_struct napi; 96 struct work_struct reset_task; 97 struct mii_bus *mii_bus; 98 99 /* Link management */ 100 int cur_speed; 101 int cur_duplex; 102 bool use_ncsi; 103 104 /* Multicast filter settings */ 105 u32 maht0; 106 u32 maht1; 107 108 /* Flow control settings */ 109 bool tx_pause; 110 bool rx_pause; 111 bool aneg_pause; 112 113 /* Misc */ 114 bool need_mac_restart; 115 bool is_aspeed; 116 }; 117 118 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr) 119 { 120 struct net_device *netdev = priv->netdev; 121 int i; 122 123 /* NOTE: reset clears all registers */ 124 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 125 iowrite32(maccr | FTGMAC100_MACCR_SW_RST, 126 priv->base + FTGMAC100_OFFSET_MACCR); 127 for (i = 0; i < 50; i++) { 128 unsigned int maccr; 129 130 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 131 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 132 return 0; 133 134 udelay(1); 135 } 136 137 netdev_err(netdev, "Hardware reset failed\n"); 138 return -EIO; 139 } 140 141 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) 142 { 143 u32 maccr = 0; 144 145 switch (priv->cur_speed) { 146 case SPEED_10: 147 case 0: /* no link */ 148 break; 149 150 case SPEED_100: 151 maccr |= FTGMAC100_MACCR_FAST_MODE; 152 break; 153 154 case SPEED_1000: 155 maccr |= FTGMAC100_MACCR_GIGA_MODE; 156 break; 157 default: 158 netdev_err(priv->netdev, "Unknown speed %d !\n", 159 priv->cur_speed); 160 break; 161 } 162 163 /* (Re)initialize the queue pointers */ 164 priv->rx_pointer = 0; 165 priv->tx_clean_pointer = 0; 166 priv->tx_pointer = 0; 167 168 /* The doc says reset twice with 10us interval */ 169 if (ftgmac100_reset_mac(priv, maccr)) 170 return -EIO; 171 usleep_range(10, 1000); 172 return ftgmac100_reset_mac(priv, maccr); 173 } 174 175 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac) 176 { 177 unsigned int maddr = mac[0] << 8 | mac[1]; 178 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 179 180 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 181 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 182 } 183 184 static void ftgmac100_initial_mac(struct ftgmac100 *priv) 185 { 186 u8 mac[ETH_ALEN]; 187 unsigned int m; 188 unsigned int l; 189 void *addr; 190 191 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN); 192 if (addr) { 193 ether_addr_copy(priv->netdev->dev_addr, mac); 194 dev_info(priv->dev, "Read MAC address %pM from device tree\n", 195 mac); 196 return; 197 } 198 199 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); 200 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); 201 202 mac[0] = (m >> 8) & 0xff; 203 mac[1] = m & 0xff; 204 mac[2] = (l >> 24) & 0xff; 205 mac[3] = (l >> 16) & 0xff; 206 mac[4] = (l >> 8) & 0xff; 207 mac[5] = l & 0xff; 208 209 if (is_valid_ether_addr(mac)) { 210 ether_addr_copy(priv->netdev->dev_addr, mac); 211 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac); 212 } else { 213 eth_hw_addr_random(priv->netdev); 214 dev_info(priv->dev, "Generated random MAC address %pM\n", 215 priv->netdev->dev_addr); 216 } 217 } 218 219 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p) 220 { 221 int ret; 222 223 ret = eth_prepare_mac_addr_change(dev, p); 224 if (ret < 0) 225 return ret; 226 227 eth_commit_mac_addr_change(dev, p); 228 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr); 229 230 return 0; 231 } 232 233 static void ftgmac100_config_pause(struct ftgmac100 *priv) 234 { 235 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16); 236 237 /* Throttle tx queue when receiving pause frames */ 238 if (priv->rx_pause) 239 fcr |= FTGMAC100_FCR_FC_EN; 240 241 /* Enables sending pause frames when the RX queue is past a 242 * certain threshold. 243 */ 244 if (priv->tx_pause) 245 fcr |= FTGMAC100_FCR_FCTHR_EN; 246 247 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR); 248 } 249 250 static void ftgmac100_init_hw(struct ftgmac100 *priv) 251 { 252 u32 reg, rfifo_sz, tfifo_sz; 253 254 /* Clear stale interrupts */ 255 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 256 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); 257 258 /* Setup RX ring buffer base */ 259 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR); 260 261 /* Setup TX ring buffer base */ 262 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 263 264 /* Configure RX buffer size */ 265 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE), 266 priv->base + FTGMAC100_OFFSET_RBSR); 267 268 /* Set RX descriptor autopoll */ 269 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), 270 priv->base + FTGMAC100_OFFSET_APTC); 271 272 /* Write MAC address */ 273 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr); 274 275 /* Write multicast filter */ 276 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 277 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 278 279 /* Configure descriptor sizes and increase burst sizes according 280 * to values in Aspeed SDK. The FIFO arbitration is enabled and 281 * the thresholds set based on the recommended values in the 282 * AST2400 specification. 283 */ 284 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */ 285 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */ 286 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */ 287 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */ 288 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */ 289 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */ 290 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */ 291 priv->base + FTGMAC100_OFFSET_DBLAC); 292 293 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt 294 * mitigation doesn't seem to provide any benefit with NAPI so leave 295 * it at that. 296 */ 297 iowrite32(FTGMAC100_ITC_RXINT_THR(1) | 298 FTGMAC100_ITC_TXINT_THR(1), 299 priv->base + FTGMAC100_OFFSET_ITC); 300 301 /* Configure FIFO sizes in the TPAFCR register */ 302 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); 303 rfifo_sz = reg & 0x00000007; 304 tfifo_sz = (reg >> 3) & 0x00000007; 305 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); 306 reg &= ~0x3f000000; 307 reg |= (tfifo_sz << 27); 308 reg |= (rfifo_sz << 24); 309 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); 310 } 311 312 static void ftgmac100_start_hw(struct ftgmac100 *priv) 313 { 314 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 315 316 /* Keep the original GMAC and FAST bits */ 317 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE); 318 319 /* Add all the main enable bits */ 320 maccr |= FTGMAC100_MACCR_TXDMA_EN | 321 FTGMAC100_MACCR_RXDMA_EN | 322 FTGMAC100_MACCR_TXMAC_EN | 323 FTGMAC100_MACCR_RXMAC_EN | 324 FTGMAC100_MACCR_CRC_APD | 325 FTGMAC100_MACCR_PHY_LINK_LEVEL | 326 FTGMAC100_MACCR_RX_RUNT | 327 FTGMAC100_MACCR_RX_BROADPKT; 328 329 /* Add other bits as needed */ 330 if (priv->cur_duplex == DUPLEX_FULL) 331 maccr |= FTGMAC100_MACCR_FULLDUP; 332 if (priv->netdev->flags & IFF_PROMISC) 333 maccr |= FTGMAC100_MACCR_RX_ALL; 334 if (priv->netdev->flags & IFF_ALLMULTI) 335 maccr |= FTGMAC100_MACCR_RX_MULTIPKT; 336 else if (netdev_mc_count(priv->netdev)) 337 maccr |= FTGMAC100_MACCR_HT_MULTI_EN; 338 339 /* Vlan filtering enabled */ 340 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 341 maccr |= FTGMAC100_MACCR_RM_VLAN; 342 343 /* Hit the HW */ 344 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 345 } 346 347 static void ftgmac100_stop_hw(struct ftgmac100 *priv) 348 { 349 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 350 } 351 352 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv) 353 { 354 struct netdev_hw_addr *ha; 355 356 priv->maht1 = 0; 357 priv->maht0 = 0; 358 netdev_for_each_mc_addr(ha, priv->netdev) { 359 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr); 360 361 crc_val = (~(crc_val >> 2)) & 0x3f; 362 if (crc_val >= 32) 363 priv->maht1 |= 1ul << (crc_val - 32); 364 else 365 priv->maht0 |= 1ul << (crc_val); 366 } 367 } 368 369 static void ftgmac100_set_rx_mode(struct net_device *netdev) 370 { 371 struct ftgmac100 *priv = netdev_priv(netdev); 372 373 /* Setup the hash filter */ 374 ftgmac100_calc_mc_hash(priv); 375 376 /* Interface down ? that's all there is to do */ 377 if (!netif_running(netdev)) 378 return; 379 380 /* Update the HW */ 381 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); 382 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); 383 384 /* Reconfigure MACCR */ 385 ftgmac100_start_hw(priv); 386 } 387 388 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry, 389 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 390 { 391 struct net_device *netdev = priv->netdev; 392 struct sk_buff *skb; 393 dma_addr_t map; 394 int err; 395 396 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE); 397 if (unlikely(!skb)) { 398 if (net_ratelimit()) 399 netdev_warn(netdev, "failed to allocate rx skb\n"); 400 err = -ENOMEM; 401 map = priv->rx_scratch_dma; 402 } else { 403 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE, 404 DMA_FROM_DEVICE); 405 if (unlikely(dma_mapping_error(priv->dev, map))) { 406 if (net_ratelimit()) 407 netdev_err(netdev, "failed to map rx page\n"); 408 dev_kfree_skb_any(skb); 409 map = priv->rx_scratch_dma; 410 skb = NULL; 411 err = -ENOMEM; 412 } 413 } 414 415 /* Store skb */ 416 priv->rx_skbs[entry] = skb; 417 418 /* Store DMA address into RX desc */ 419 rxdes->rxdes3 = cpu_to_le32(map); 420 421 /* Ensure the above is ordered vs clearing the OWN bit */ 422 dma_wmb(); 423 424 /* Clean status (which resets own bit) */ 425 if (entry == (priv->rx_q_entries - 1)) 426 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask); 427 else 428 rxdes->rxdes0 = 0; 429 430 return 0; 431 } 432 433 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv, 434 unsigned int pointer) 435 { 436 return (pointer + 1) & (priv->rx_q_entries - 1); 437 } 438 439 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status) 440 { 441 struct net_device *netdev = priv->netdev; 442 443 if (status & FTGMAC100_RXDES0_RX_ERR) 444 netdev->stats.rx_errors++; 445 446 if (status & FTGMAC100_RXDES0_CRC_ERR) 447 netdev->stats.rx_crc_errors++; 448 449 if (status & (FTGMAC100_RXDES0_FTL | 450 FTGMAC100_RXDES0_RUNT | 451 FTGMAC100_RXDES0_RX_ODD_NB)) 452 netdev->stats.rx_length_errors++; 453 } 454 455 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 456 { 457 struct net_device *netdev = priv->netdev; 458 struct ftgmac100_rxdes *rxdes; 459 struct sk_buff *skb; 460 unsigned int pointer, size; 461 u32 status, csum_vlan; 462 dma_addr_t map; 463 464 /* Grab next RX descriptor */ 465 pointer = priv->rx_pointer; 466 rxdes = &priv->rxdes[pointer]; 467 468 /* Grab descriptor status */ 469 status = le32_to_cpu(rxdes->rxdes0); 470 471 /* Do we have a packet ? */ 472 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY)) 473 return false; 474 475 /* Order subsequent reads with the test for the ready bit */ 476 dma_rmb(); 477 478 /* We don't cope with fragmented RX packets */ 479 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) || 480 !(status & FTGMAC100_RXDES0_LRS))) 481 goto drop; 482 483 /* Grab received size and csum vlan field in the descriptor */ 484 size = status & FTGMAC100_RXDES0_VDBC; 485 csum_vlan = le32_to_cpu(rxdes->rxdes1); 486 487 /* Any error (other than csum offload) flagged ? */ 488 if (unlikely(status & RXDES0_ANY_ERROR)) { 489 /* Correct for incorrect flagging of runt packets 490 * with vlan tags... Just accept a runt packet that 491 * has been flagged as vlan and whose size is at 492 * least 60 bytes. 493 */ 494 if ((status & FTGMAC100_RXDES0_RUNT) && 495 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) && 496 (size >= 60)) 497 status &= ~FTGMAC100_RXDES0_RUNT; 498 499 /* Any error still in there ? */ 500 if (status & RXDES0_ANY_ERROR) { 501 ftgmac100_rx_packet_error(priv, status); 502 goto drop; 503 } 504 } 505 506 /* If the packet had no skb (failed to allocate earlier) 507 * then try to allocate one and skip 508 */ 509 skb = priv->rx_skbs[pointer]; 510 if (!unlikely(skb)) { 511 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 512 goto drop; 513 } 514 515 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST)) 516 netdev->stats.multicast++; 517 518 /* If the HW found checksum errors, bounce it to software. 519 * 520 * If we didn't, we need to see if the packet was recognized 521 * by HW as one of the supported checksummed protocols before 522 * we accept the HW test results. 523 */ 524 if (netdev->features & NETIF_F_RXCSUM) { 525 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR | 526 FTGMAC100_RXDES1_UDP_CHKSUM_ERR | 527 FTGMAC100_RXDES1_IP_CHKSUM_ERR; 528 if ((csum_vlan & err_bits) || 529 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK)) 530 skb->ip_summed = CHECKSUM_NONE; 531 else 532 skb->ip_summed = CHECKSUM_UNNECESSARY; 533 } 534 535 /* Transfer received size to skb */ 536 skb_put(skb, size); 537 538 /* Extract vlan tag */ 539 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 540 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL)) 541 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 542 csum_vlan & 0xffff); 543 544 /* Tear down DMA mapping, do necessary cache management */ 545 map = le32_to_cpu(rxdes->rxdes3); 546 547 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU) 548 /* When we don't have an iommu, we can save cycles by not 549 * invalidating the cache for the part of the packet that 550 * wasn't received. 551 */ 552 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE); 553 #else 554 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 555 #endif 556 557 558 /* Resplenish rx ring */ 559 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); 560 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 561 562 skb->protocol = eth_type_trans(skb, netdev); 563 564 netdev->stats.rx_packets++; 565 netdev->stats.rx_bytes += size; 566 567 /* push packet to protocol stack */ 568 if (skb->ip_summed == CHECKSUM_NONE) 569 netif_receive_skb(skb); 570 else 571 napi_gro_receive(&priv->napi, skb); 572 573 (*processed)++; 574 return true; 575 576 drop: 577 /* Clean rxdes0 (which resets own bit) */ 578 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask); 579 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); 580 netdev->stats.rx_dropped++; 581 return true; 582 } 583 584 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv, 585 unsigned int index) 586 { 587 if (index == (priv->tx_q_entries - 1)) 588 return priv->txdes0_edotr_mask; 589 else 590 return 0; 591 } 592 593 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv, 594 unsigned int pointer) 595 { 596 return (pointer + 1) & (priv->tx_q_entries - 1); 597 } 598 599 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv) 600 { 601 /* Returns the number of available slots in the TX queue 602 * 603 * This always leaves one free slot so we don't have to 604 * worry about empty vs. full, and this simplifies the 605 * test for ftgmac100_tx_buf_cleanable() below 606 */ 607 return (priv->tx_clean_pointer - priv->tx_pointer - 1) & 608 (priv->tx_q_entries - 1); 609 } 610 611 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv) 612 { 613 return priv->tx_pointer != priv->tx_clean_pointer; 614 } 615 616 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv, 617 unsigned int pointer, 618 struct sk_buff *skb, 619 struct ftgmac100_txdes *txdes, 620 u32 ctl_stat) 621 { 622 dma_addr_t map = le32_to_cpu(txdes->txdes3); 623 size_t len; 624 625 if (ctl_stat & FTGMAC100_TXDES0_FTS) { 626 len = skb_headlen(skb); 627 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE); 628 } else { 629 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat); 630 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE); 631 } 632 633 /* Free SKB on last segment */ 634 if (ctl_stat & FTGMAC100_TXDES0_LTS) 635 dev_kfree_skb(skb); 636 priv->tx_skbs[pointer] = NULL; 637 } 638 639 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 640 { 641 struct net_device *netdev = priv->netdev; 642 struct ftgmac100_txdes *txdes; 643 struct sk_buff *skb; 644 unsigned int pointer; 645 u32 ctl_stat; 646 647 pointer = priv->tx_clean_pointer; 648 txdes = &priv->txdes[pointer]; 649 650 ctl_stat = le32_to_cpu(txdes->txdes0); 651 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN) 652 return false; 653 654 skb = priv->tx_skbs[pointer]; 655 netdev->stats.tx_packets++; 656 netdev->stats.tx_bytes += skb->len; 657 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 658 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 659 660 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer); 661 662 return true; 663 } 664 665 static void ftgmac100_tx_complete(struct ftgmac100 *priv) 666 { 667 struct net_device *netdev = priv->netdev; 668 669 /* Process all completed packets */ 670 while (ftgmac100_tx_buf_cleanable(priv) && 671 ftgmac100_tx_complete_packet(priv)) 672 ; 673 674 /* Restart queue if needed */ 675 smp_mb(); 676 if (unlikely(netif_queue_stopped(netdev) && 677 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) { 678 struct netdev_queue *txq; 679 680 txq = netdev_get_tx_queue(netdev, 0); 681 __netif_tx_lock(txq, smp_processor_id()); 682 if (netif_queue_stopped(netdev) && 683 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 684 netif_wake_queue(netdev); 685 __netif_tx_unlock(txq); 686 } 687 } 688 689 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan) 690 { 691 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 692 u8 ip_proto = ip_hdr(skb)->protocol; 693 694 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM; 695 switch(ip_proto) { 696 case IPPROTO_TCP: 697 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM; 698 return true; 699 case IPPROTO_UDP: 700 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM; 701 return true; 702 case IPPROTO_IP: 703 return true; 704 } 705 } 706 return skb_checksum_help(skb) == 0; 707 } 708 709 static int ftgmac100_hard_start_xmit(struct sk_buff *skb, 710 struct net_device *netdev) 711 { 712 struct ftgmac100 *priv = netdev_priv(netdev); 713 struct ftgmac100_txdes *txdes, *first; 714 unsigned int pointer, nfrags, len, i, j; 715 u32 f_ctl_stat, ctl_stat, csum_vlan; 716 dma_addr_t map; 717 718 /* The HW doesn't pad small frames */ 719 if (eth_skb_pad(skb)) { 720 netdev->stats.tx_dropped++; 721 return NETDEV_TX_OK; 722 } 723 724 /* Reject oversize packets */ 725 if (unlikely(skb->len > MAX_PKT_SIZE)) { 726 if (net_ratelimit()) 727 netdev_dbg(netdev, "tx packet too big\n"); 728 goto drop; 729 } 730 731 /* Do we have a limit on #fragments ? I yet have to get a reply 732 * from Aspeed. If there's one I haven't hit it. 733 */ 734 nfrags = skb_shinfo(skb)->nr_frags; 735 736 /* Get header len */ 737 len = skb_headlen(skb); 738 739 /* Map the packet head */ 740 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 741 if (dma_mapping_error(priv->dev, map)) { 742 if (net_ratelimit()) 743 netdev_err(netdev, "map tx packet head failed\n"); 744 goto drop; 745 } 746 747 /* Grab the next free tx descriptor */ 748 pointer = priv->tx_pointer; 749 txdes = first = &priv->txdes[pointer]; 750 751 /* Setup it up with the packet head. Don't write the head to the 752 * ring just yet 753 */ 754 priv->tx_skbs[pointer] = skb; 755 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 756 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 757 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 758 f_ctl_stat |= FTGMAC100_TXDES0_FTS; 759 if (nfrags == 0) 760 f_ctl_stat |= FTGMAC100_TXDES0_LTS; 761 txdes->txdes3 = cpu_to_le32(map); 762 763 /* Setup HW checksumming */ 764 csum_vlan = 0; 765 if (skb->ip_summed == CHECKSUM_PARTIAL && 766 !ftgmac100_prep_tx_csum(skb, &csum_vlan)) 767 goto drop; 768 769 /* Add VLAN tag */ 770 if (skb_vlan_tag_present(skb)) { 771 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG; 772 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff; 773 } 774 775 txdes->txdes1 = cpu_to_le32(csum_vlan); 776 777 /* Next descriptor */ 778 pointer = ftgmac100_next_tx_pointer(priv, pointer); 779 780 /* Add the fragments */ 781 for (i = 0; i < nfrags; i++) { 782 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 783 784 len = frag->size; 785 786 /* Map it */ 787 map = skb_frag_dma_map(priv->dev, frag, 0, len, 788 DMA_TO_DEVICE); 789 if (dma_mapping_error(priv->dev, map)) 790 goto dma_err; 791 792 /* Setup descriptor */ 793 priv->tx_skbs[pointer] = skb; 794 txdes = &priv->txdes[pointer]; 795 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); 796 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; 797 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); 798 if (i == (nfrags - 1)) 799 ctl_stat |= FTGMAC100_TXDES0_LTS; 800 txdes->txdes0 = cpu_to_le32(ctl_stat); 801 txdes->txdes1 = 0; 802 txdes->txdes3 = cpu_to_le32(map); 803 804 /* Next one */ 805 pointer = ftgmac100_next_tx_pointer(priv, pointer); 806 } 807 808 /* Order the previous packet and descriptor udpates 809 * before setting the OWN bit on the first descriptor. 810 */ 811 dma_wmb(); 812 first->txdes0 = cpu_to_le32(f_ctl_stat); 813 814 /* Update next TX pointer */ 815 priv->tx_pointer = pointer; 816 817 /* If there isn't enough room for all the fragments of a new packet 818 * in the TX ring, stop the queue. The sequence below is race free 819 * vs. a concurrent restart in ftgmac100_poll() 820 */ 821 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) { 822 netif_stop_queue(netdev); 823 /* Order the queue stop with the test below */ 824 smp_mb(); 825 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) 826 netif_wake_queue(netdev); 827 } 828 829 /* Poke transmitter to read the updated TX descriptors */ 830 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 831 832 return NETDEV_TX_OK; 833 834 dma_err: 835 if (net_ratelimit()) 836 netdev_err(netdev, "map tx fragment failed\n"); 837 838 /* Free head */ 839 pointer = priv->tx_pointer; 840 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat); 841 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask); 842 843 /* Then all fragments */ 844 for (j = 0; j < i; j++) { 845 pointer = ftgmac100_next_tx_pointer(priv, pointer); 846 txdes = &priv->txdes[pointer]; 847 ctl_stat = le32_to_cpu(txdes->txdes0); 848 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); 849 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); 850 } 851 852 /* This cannot be reached if we successfully mapped the 853 * last fragment, so we know ftgmac100_free_tx_packet() 854 * hasn't freed the skb yet. 855 */ 856 drop: 857 /* Drop the packet */ 858 dev_kfree_skb_any(skb); 859 netdev->stats.tx_dropped++; 860 861 return NETDEV_TX_OK; 862 } 863 864 static void ftgmac100_free_buffers(struct ftgmac100 *priv) 865 { 866 int i; 867 868 /* Free all RX buffers */ 869 for (i = 0; i < priv->rx_q_entries; i++) { 870 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 871 struct sk_buff *skb = priv->rx_skbs[i]; 872 dma_addr_t map = le32_to_cpu(rxdes->rxdes3); 873 874 if (!skb) 875 continue; 876 877 priv->rx_skbs[i] = NULL; 878 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 879 dev_kfree_skb_any(skb); 880 } 881 882 /* Free all TX buffers */ 883 for (i = 0; i < priv->tx_q_entries; i++) { 884 struct ftgmac100_txdes *txdes = &priv->txdes[i]; 885 struct sk_buff *skb = priv->tx_skbs[i]; 886 887 if (!skb) 888 continue; 889 ftgmac100_free_tx_packet(priv, i, skb, txdes, 890 le32_to_cpu(txdes->txdes0)); 891 } 892 } 893 894 static void ftgmac100_free_rings(struct ftgmac100 *priv) 895 { 896 /* Free skb arrays */ 897 kfree(priv->rx_skbs); 898 kfree(priv->tx_skbs); 899 900 /* Free descriptors */ 901 if (priv->rxdes) 902 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES * 903 sizeof(struct ftgmac100_rxdes), 904 priv->rxdes, priv->rxdes_dma); 905 priv->rxdes = NULL; 906 907 if (priv->txdes) 908 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES * 909 sizeof(struct ftgmac100_txdes), 910 priv->txdes, priv->txdes_dma); 911 priv->txdes = NULL; 912 913 /* Free scratch packet buffer */ 914 if (priv->rx_scratch) 915 dma_free_coherent(priv->dev, RX_BUF_SIZE, 916 priv->rx_scratch, priv->rx_scratch_dma); 917 } 918 919 static int ftgmac100_alloc_rings(struct ftgmac100 *priv) 920 { 921 /* Allocate skb arrays */ 922 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *), 923 GFP_KERNEL); 924 if (!priv->rx_skbs) 925 return -ENOMEM; 926 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *), 927 GFP_KERNEL); 928 if (!priv->tx_skbs) 929 return -ENOMEM; 930 931 /* Allocate descriptors */ 932 priv->rxdes = dma_zalloc_coherent(priv->dev, 933 MAX_RX_QUEUE_ENTRIES * 934 sizeof(struct ftgmac100_rxdes), 935 &priv->rxdes_dma, GFP_KERNEL); 936 if (!priv->rxdes) 937 return -ENOMEM; 938 priv->txdes = dma_zalloc_coherent(priv->dev, 939 MAX_TX_QUEUE_ENTRIES * 940 sizeof(struct ftgmac100_txdes), 941 &priv->txdes_dma, GFP_KERNEL); 942 if (!priv->txdes) 943 return -ENOMEM; 944 945 /* Allocate scratch packet buffer */ 946 priv->rx_scratch = dma_alloc_coherent(priv->dev, 947 RX_BUF_SIZE, 948 &priv->rx_scratch_dma, 949 GFP_KERNEL); 950 if (!priv->rx_scratch) 951 return -ENOMEM; 952 953 return 0; 954 } 955 956 static void ftgmac100_init_rings(struct ftgmac100 *priv) 957 { 958 struct ftgmac100_rxdes *rxdes = NULL; 959 struct ftgmac100_txdes *txdes = NULL; 960 int i; 961 962 /* Update entries counts */ 963 priv->rx_q_entries = priv->new_rx_q_entries; 964 priv->tx_q_entries = priv->new_tx_q_entries; 965 966 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES)) 967 return; 968 969 /* Initialize RX ring */ 970 for (i = 0; i < priv->rx_q_entries; i++) { 971 rxdes = &priv->rxdes[i]; 972 rxdes->rxdes0 = 0; 973 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma); 974 } 975 /* Mark the end of the ring */ 976 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); 977 978 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES)) 979 return; 980 981 /* Initialize TX ring */ 982 for (i = 0; i < priv->tx_q_entries; i++) { 983 txdes = &priv->txdes[i]; 984 txdes->txdes0 = 0; 985 } 986 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask); 987 } 988 989 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv) 990 { 991 int i; 992 993 for (i = 0; i < priv->rx_q_entries; i++) { 994 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; 995 996 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL)) 997 return -ENOMEM; 998 } 999 return 0; 1000 } 1001 1002 static void ftgmac100_adjust_link(struct net_device *netdev) 1003 { 1004 struct ftgmac100 *priv = netdev_priv(netdev); 1005 struct phy_device *phydev = netdev->phydev; 1006 bool tx_pause, rx_pause; 1007 int new_speed; 1008 1009 /* We store "no link" as speed 0 */ 1010 if (!phydev->link) 1011 new_speed = 0; 1012 else 1013 new_speed = phydev->speed; 1014 1015 /* Grab pause settings from PHY if configured to do so */ 1016 if (priv->aneg_pause) { 1017 rx_pause = tx_pause = phydev->pause; 1018 if (phydev->asym_pause) 1019 tx_pause = !rx_pause; 1020 } else { 1021 rx_pause = priv->rx_pause; 1022 tx_pause = priv->tx_pause; 1023 } 1024 1025 /* Link hasn't changed, do nothing */ 1026 if (phydev->speed == priv->cur_speed && 1027 phydev->duplex == priv->cur_duplex && 1028 rx_pause == priv->rx_pause && 1029 tx_pause == priv->tx_pause) 1030 return; 1031 1032 /* Print status if we have a link or we had one and just lost it, 1033 * don't print otherwise. 1034 */ 1035 if (new_speed || priv->cur_speed) 1036 phy_print_status(phydev); 1037 1038 priv->cur_speed = new_speed; 1039 priv->cur_duplex = phydev->duplex; 1040 priv->rx_pause = rx_pause; 1041 priv->tx_pause = tx_pause; 1042 1043 /* Link is down, do nothing else */ 1044 if (!new_speed) 1045 return; 1046 1047 /* Disable all interrupts */ 1048 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1049 1050 /* Reset the adapter asynchronously */ 1051 schedule_work(&priv->reset_task); 1052 } 1053 1054 static int ftgmac100_mii_probe(struct ftgmac100 *priv) 1055 { 1056 struct net_device *netdev = priv->netdev; 1057 struct phy_device *phydev; 1058 1059 phydev = phy_find_first(priv->mii_bus); 1060 if (!phydev) { 1061 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 1062 return -ENODEV; 1063 } 1064 1065 phydev = phy_connect(netdev, phydev_name(phydev), 1066 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII); 1067 1068 if (IS_ERR(phydev)) { 1069 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 1070 return PTR_ERR(phydev); 1071 } 1072 1073 /* Indicate that we support PAUSE frames (see comment in 1074 * Documentation/networking/phy.txt) 1075 */ 1076 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 1077 phydev->advertising = phydev->supported; 1078 1079 return 0; 1080 } 1081 1082 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 1083 { 1084 struct net_device *netdev = bus->priv; 1085 struct ftgmac100 *priv = netdev_priv(netdev); 1086 unsigned int phycr; 1087 int i; 1088 1089 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1090 1091 /* preserve MDC cycle threshold */ 1092 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1093 1094 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1095 FTGMAC100_PHYCR_REGAD(regnum) | 1096 FTGMAC100_PHYCR_MIIRD; 1097 1098 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1099 1100 for (i = 0; i < 10; i++) { 1101 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1102 1103 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 1104 int data; 1105 1106 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 1107 return FTGMAC100_PHYDATA_MIIRDATA(data); 1108 } 1109 1110 udelay(100); 1111 } 1112 1113 netdev_err(netdev, "mdio read timed out\n"); 1114 return -EIO; 1115 } 1116 1117 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 1118 int regnum, u16 value) 1119 { 1120 struct net_device *netdev = bus->priv; 1121 struct ftgmac100 *priv = netdev_priv(netdev); 1122 unsigned int phycr; 1123 int data; 1124 int i; 1125 1126 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1127 1128 /* preserve MDC cycle threshold */ 1129 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 1130 1131 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 1132 FTGMAC100_PHYCR_REGAD(regnum) | 1133 FTGMAC100_PHYCR_MIIWR; 1134 1135 data = FTGMAC100_PHYDATA_MIIWDATA(value); 1136 1137 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 1138 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 1139 1140 for (i = 0; i < 10; i++) { 1141 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 1142 1143 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 1144 return 0; 1145 1146 udelay(100); 1147 } 1148 1149 netdev_err(netdev, "mdio write timed out\n"); 1150 return -EIO; 1151 } 1152 1153 static void ftgmac100_get_drvinfo(struct net_device *netdev, 1154 struct ethtool_drvinfo *info) 1155 { 1156 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1157 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1158 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); 1159 } 1160 1161 static void ftgmac100_get_ringparam(struct net_device *netdev, 1162 struct ethtool_ringparam *ering) 1163 { 1164 struct ftgmac100 *priv = netdev_priv(netdev); 1165 1166 memset(ering, 0, sizeof(*ering)); 1167 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES; 1168 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES; 1169 ering->rx_pending = priv->rx_q_entries; 1170 ering->tx_pending = priv->tx_q_entries; 1171 } 1172 1173 static int ftgmac100_set_ringparam(struct net_device *netdev, 1174 struct ethtool_ringparam *ering) 1175 { 1176 struct ftgmac100 *priv = netdev_priv(netdev); 1177 1178 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES || 1179 ering->tx_pending > MAX_TX_QUEUE_ENTRIES || 1180 ering->rx_pending < MIN_RX_QUEUE_ENTRIES || 1181 ering->tx_pending < MIN_TX_QUEUE_ENTRIES || 1182 !is_power_of_2(ering->rx_pending) || 1183 !is_power_of_2(ering->tx_pending)) 1184 return -EINVAL; 1185 1186 priv->new_rx_q_entries = ering->rx_pending; 1187 priv->new_tx_q_entries = ering->tx_pending; 1188 if (netif_running(netdev)) 1189 schedule_work(&priv->reset_task); 1190 1191 return 0; 1192 } 1193 1194 static void ftgmac100_get_pauseparam(struct net_device *netdev, 1195 struct ethtool_pauseparam *pause) 1196 { 1197 struct ftgmac100 *priv = netdev_priv(netdev); 1198 1199 pause->autoneg = priv->aneg_pause; 1200 pause->tx_pause = priv->tx_pause; 1201 pause->rx_pause = priv->rx_pause; 1202 } 1203 1204 static int ftgmac100_set_pauseparam(struct net_device *netdev, 1205 struct ethtool_pauseparam *pause) 1206 { 1207 struct ftgmac100 *priv = netdev_priv(netdev); 1208 struct phy_device *phydev = netdev->phydev; 1209 1210 priv->aneg_pause = pause->autoneg; 1211 priv->tx_pause = pause->tx_pause; 1212 priv->rx_pause = pause->rx_pause; 1213 1214 if (phydev) { 1215 phydev->advertising &= ~ADVERTISED_Pause; 1216 phydev->advertising &= ~ADVERTISED_Asym_Pause; 1217 1218 if (pause->rx_pause) { 1219 phydev->advertising |= ADVERTISED_Pause; 1220 phydev->advertising |= ADVERTISED_Asym_Pause; 1221 } 1222 1223 if (pause->tx_pause) 1224 phydev->advertising ^= ADVERTISED_Asym_Pause; 1225 } 1226 if (netif_running(netdev)) { 1227 if (phydev && priv->aneg_pause) 1228 phy_start_aneg(phydev); 1229 else 1230 ftgmac100_config_pause(priv); 1231 } 1232 1233 return 0; 1234 } 1235 1236 static const struct ethtool_ops ftgmac100_ethtool_ops = { 1237 .get_drvinfo = ftgmac100_get_drvinfo, 1238 .get_link = ethtool_op_get_link, 1239 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1240 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1241 .nway_reset = phy_ethtool_nway_reset, 1242 .get_ringparam = ftgmac100_get_ringparam, 1243 .set_ringparam = ftgmac100_set_ringparam, 1244 .get_pauseparam = ftgmac100_get_pauseparam, 1245 .set_pauseparam = ftgmac100_set_pauseparam, 1246 }; 1247 1248 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 1249 { 1250 struct net_device *netdev = dev_id; 1251 struct ftgmac100 *priv = netdev_priv(netdev); 1252 unsigned int status, new_mask = FTGMAC100_INT_BAD; 1253 1254 /* Fetch and clear interrupt bits, process abnormal ones */ 1255 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1256 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1257 if (unlikely(status & FTGMAC100_INT_BAD)) { 1258 1259 /* RX buffer unavailable */ 1260 if (status & FTGMAC100_INT_NO_RXBUF) 1261 netdev->stats.rx_over_errors++; 1262 1263 /* received packet lost due to RX FIFO full */ 1264 if (status & FTGMAC100_INT_RPKT_LOST) 1265 netdev->stats.rx_fifo_errors++; 1266 1267 /* sent packet lost due to excessive TX collision */ 1268 if (status & FTGMAC100_INT_XPKT_LOST) 1269 netdev->stats.tx_fifo_errors++; 1270 1271 /* AHB error -> Reset the chip */ 1272 if (status & FTGMAC100_INT_AHB_ERR) { 1273 if (net_ratelimit()) 1274 netdev_warn(netdev, 1275 "AHB bus error ! Resetting chip.\n"); 1276 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1277 schedule_work(&priv->reset_task); 1278 return IRQ_HANDLED; 1279 } 1280 1281 /* We may need to restart the MAC after such errors, delay 1282 * this until after we have freed some Rx buffers though 1283 */ 1284 priv->need_mac_restart = true; 1285 1286 /* Disable those errors until we restart */ 1287 new_mask &= ~status; 1288 } 1289 1290 /* Only enable "bad" interrupts while NAPI is on */ 1291 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER); 1292 1293 /* Schedule NAPI bh */ 1294 napi_schedule_irqoff(&priv->napi); 1295 1296 return IRQ_HANDLED; 1297 } 1298 1299 static bool ftgmac100_check_rx(struct ftgmac100 *priv) 1300 { 1301 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer]; 1302 1303 /* Do we have a packet ? */ 1304 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY)); 1305 } 1306 1307 static int ftgmac100_poll(struct napi_struct *napi, int budget) 1308 { 1309 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1310 int work_done = 0; 1311 bool more; 1312 1313 /* Handle TX completions */ 1314 if (ftgmac100_tx_buf_cleanable(priv)) 1315 ftgmac100_tx_complete(priv); 1316 1317 /* Handle RX packets */ 1318 do { 1319 more = ftgmac100_rx_packet(priv, &work_done); 1320 } while (more && work_done < budget); 1321 1322 1323 /* The interrupt is telling us to kick the MAC back to life 1324 * after an RX overflow 1325 */ 1326 if (unlikely(priv->need_mac_restart)) { 1327 ftgmac100_start_hw(priv); 1328 1329 /* Re-enable "bad" interrupts */ 1330 iowrite32(FTGMAC100_INT_BAD, 1331 priv->base + FTGMAC100_OFFSET_IER); 1332 } 1333 1334 /* As long as we are waiting for transmit packets to be 1335 * completed we keep NAPI going 1336 */ 1337 if (ftgmac100_tx_buf_cleanable(priv)) 1338 work_done = budget; 1339 1340 if (work_done < budget) { 1341 /* We are about to re-enable all interrupts. However 1342 * the HW has been latching RX/TX packet interrupts while 1343 * they were masked. So we clear them first, then we need 1344 * to re-check if there's something to process 1345 */ 1346 iowrite32(FTGMAC100_INT_RXTX, 1347 priv->base + FTGMAC100_OFFSET_ISR); 1348 if (ftgmac100_check_rx(priv) || 1349 ftgmac100_tx_buf_cleanable(priv)) 1350 return budget; 1351 1352 /* deschedule NAPI */ 1353 napi_complete(napi); 1354 1355 /* enable all interrupts */ 1356 iowrite32(FTGMAC100_INT_ALL, 1357 priv->base + FTGMAC100_OFFSET_IER); 1358 } 1359 1360 return work_done; 1361 } 1362 1363 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err) 1364 { 1365 int err = 0; 1366 1367 /* Re-init descriptors (adjust queue sizes) */ 1368 ftgmac100_init_rings(priv); 1369 1370 /* Realloc rx descriptors */ 1371 err = ftgmac100_alloc_rx_buffers(priv); 1372 if (err && !ignore_alloc_err) 1373 return err; 1374 1375 /* Reinit and restart HW */ 1376 ftgmac100_init_hw(priv); 1377 ftgmac100_config_pause(priv); 1378 ftgmac100_start_hw(priv); 1379 1380 /* Re-enable the device */ 1381 napi_enable(&priv->napi); 1382 netif_start_queue(priv->netdev); 1383 1384 /* Enable all interrupts */ 1385 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER); 1386 1387 return err; 1388 } 1389 1390 static void ftgmac100_reset_task(struct work_struct *work) 1391 { 1392 struct ftgmac100 *priv = container_of(work, struct ftgmac100, 1393 reset_task); 1394 struct net_device *netdev = priv->netdev; 1395 int err; 1396 1397 netdev_dbg(netdev, "Resetting NIC...\n"); 1398 1399 /* Lock the world */ 1400 rtnl_lock(); 1401 if (netdev->phydev) 1402 mutex_lock(&netdev->phydev->lock); 1403 if (priv->mii_bus) 1404 mutex_lock(&priv->mii_bus->mdio_lock); 1405 1406 1407 /* Check if the interface is still up */ 1408 if (!netif_running(netdev)) 1409 goto bail; 1410 1411 /* Stop the network stack */ 1412 netif_trans_update(netdev); 1413 napi_disable(&priv->napi); 1414 netif_tx_disable(netdev); 1415 1416 /* Stop and reset the MAC */ 1417 ftgmac100_stop_hw(priv); 1418 err = ftgmac100_reset_and_config_mac(priv); 1419 if (err) { 1420 /* Not much we can do ... it might come back... */ 1421 netdev_err(netdev, "attempting to continue...\n"); 1422 } 1423 1424 /* Free all rx and tx buffers */ 1425 ftgmac100_free_buffers(priv); 1426 1427 /* Setup everything again and restart chip */ 1428 ftgmac100_init_all(priv, true); 1429 1430 netdev_dbg(netdev, "Reset done !\n"); 1431 bail: 1432 if (priv->mii_bus) 1433 mutex_unlock(&priv->mii_bus->mdio_lock); 1434 if (netdev->phydev) 1435 mutex_unlock(&netdev->phydev->lock); 1436 rtnl_unlock(); 1437 } 1438 1439 static int ftgmac100_open(struct net_device *netdev) 1440 { 1441 struct ftgmac100 *priv = netdev_priv(netdev); 1442 int err; 1443 1444 /* Allocate ring buffers */ 1445 err = ftgmac100_alloc_rings(priv); 1446 if (err) { 1447 netdev_err(netdev, "Failed to allocate descriptors\n"); 1448 return err; 1449 } 1450 1451 /* When using NC-SI we force the speed to 100Mbit/s full duplex, 1452 * 1453 * Otherwise we leave it set to 0 (no link), the link 1454 * message from the PHY layer will handle setting it up to 1455 * something else if needed. 1456 */ 1457 if (priv->use_ncsi) { 1458 priv->cur_duplex = DUPLEX_FULL; 1459 priv->cur_speed = SPEED_100; 1460 } else { 1461 priv->cur_duplex = 0; 1462 priv->cur_speed = 0; 1463 } 1464 1465 /* Reset the hardware */ 1466 err = ftgmac100_reset_and_config_mac(priv); 1467 if (err) 1468 goto err_hw; 1469 1470 /* Initialize NAPI */ 1471 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1472 1473 /* Grab our interrupt */ 1474 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1475 if (err) { 1476 netdev_err(netdev, "failed to request irq %d\n", netdev->irq); 1477 goto err_irq; 1478 } 1479 1480 /* Start things up */ 1481 err = ftgmac100_init_all(priv, false); 1482 if (err) { 1483 netdev_err(netdev, "Failed to allocate packet buffers\n"); 1484 goto err_alloc; 1485 } 1486 1487 if (netdev->phydev) { 1488 /* If we have a PHY, start polling */ 1489 phy_start(netdev->phydev); 1490 } else if (priv->use_ncsi) { 1491 /* If using NC-SI, set our carrier on and start the stack */ 1492 netif_carrier_on(netdev); 1493 1494 /* Start the NCSI device */ 1495 err = ncsi_start_dev(priv->ndev); 1496 if (err) 1497 goto err_ncsi; 1498 } 1499 1500 return 0; 1501 1502 err_ncsi: 1503 napi_disable(&priv->napi); 1504 netif_stop_queue(netdev); 1505 err_alloc: 1506 ftgmac100_free_buffers(priv); 1507 free_irq(netdev->irq, netdev); 1508 err_irq: 1509 netif_napi_del(&priv->napi); 1510 err_hw: 1511 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1512 ftgmac100_free_rings(priv); 1513 return err; 1514 } 1515 1516 static int ftgmac100_stop(struct net_device *netdev) 1517 { 1518 struct ftgmac100 *priv = netdev_priv(netdev); 1519 1520 /* Note about the reset task: We are called with the rtnl lock 1521 * held, so we are synchronized against the core of the reset 1522 * task. We must not try to synchronously cancel it otherwise 1523 * we can deadlock. But since it will test for netif_running() 1524 * which has already been cleared by the net core, we don't 1525 * anything special to do. 1526 */ 1527 1528 /* disable all interrupts */ 1529 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1530 1531 netif_stop_queue(netdev); 1532 napi_disable(&priv->napi); 1533 netif_napi_del(&priv->napi); 1534 if (netdev->phydev) 1535 phy_stop(netdev->phydev); 1536 else if (priv->use_ncsi) 1537 ncsi_stop_dev(priv->ndev); 1538 1539 ftgmac100_stop_hw(priv); 1540 free_irq(netdev->irq, netdev); 1541 ftgmac100_free_buffers(priv); 1542 ftgmac100_free_rings(priv); 1543 1544 return 0; 1545 } 1546 1547 /* optional */ 1548 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1549 { 1550 if (!netdev->phydev) 1551 return -ENXIO; 1552 1553 return phy_mii_ioctl(netdev->phydev, ifr, cmd); 1554 } 1555 1556 static void ftgmac100_tx_timeout(struct net_device *netdev) 1557 { 1558 struct ftgmac100 *priv = netdev_priv(netdev); 1559 1560 /* Disable all interrupts */ 1561 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1562 1563 /* Do the reset outside of interrupt context */ 1564 schedule_work(&priv->reset_task); 1565 } 1566 1567 static int ftgmac100_set_features(struct net_device *netdev, 1568 netdev_features_t features) 1569 { 1570 struct ftgmac100 *priv = netdev_priv(netdev); 1571 netdev_features_t changed = netdev->features ^ features; 1572 1573 if (!netif_running(netdev)) 1574 return 0; 1575 1576 /* Update the vlan filtering bit */ 1577 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 1578 u32 maccr; 1579 1580 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 1581 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 1582 maccr |= FTGMAC100_MACCR_RM_VLAN; 1583 else 1584 maccr &= ~FTGMAC100_MACCR_RM_VLAN; 1585 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 1586 } 1587 1588 return 0; 1589 } 1590 1591 #ifdef CONFIG_NET_POLL_CONTROLLER 1592 static void ftgmac100_poll_controller(struct net_device *netdev) 1593 { 1594 unsigned long flags; 1595 1596 local_irq_save(flags); 1597 ftgmac100_interrupt(netdev->irq, netdev); 1598 local_irq_restore(flags); 1599 } 1600 #endif 1601 1602 static const struct net_device_ops ftgmac100_netdev_ops = { 1603 .ndo_open = ftgmac100_open, 1604 .ndo_stop = ftgmac100_stop, 1605 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1606 .ndo_set_mac_address = ftgmac100_set_mac_addr, 1607 .ndo_validate_addr = eth_validate_addr, 1608 .ndo_do_ioctl = ftgmac100_do_ioctl, 1609 .ndo_tx_timeout = ftgmac100_tx_timeout, 1610 .ndo_set_rx_mode = ftgmac100_set_rx_mode, 1611 .ndo_set_features = ftgmac100_set_features, 1612 #ifdef CONFIG_NET_POLL_CONTROLLER 1613 .ndo_poll_controller = ftgmac100_poll_controller, 1614 #endif 1615 }; 1616 1617 static int ftgmac100_setup_mdio(struct net_device *netdev) 1618 { 1619 struct ftgmac100 *priv = netdev_priv(netdev); 1620 struct platform_device *pdev = to_platform_device(priv->dev); 1621 int i, err = 0; 1622 u32 reg; 1623 1624 /* initialize mdio bus */ 1625 priv->mii_bus = mdiobus_alloc(); 1626 if (!priv->mii_bus) 1627 return -EIO; 1628 1629 if (priv->is_aspeed) { 1630 /* This driver supports the old MDIO interface */ 1631 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); 1632 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; 1633 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); 1634 }; 1635 1636 priv->mii_bus->name = "ftgmac100_mdio"; 1637 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1638 pdev->name, pdev->id); 1639 priv->mii_bus->priv = priv->netdev; 1640 priv->mii_bus->read = ftgmac100_mdiobus_read; 1641 priv->mii_bus->write = ftgmac100_mdiobus_write; 1642 1643 for (i = 0; i < PHY_MAX_ADDR; i++) 1644 priv->mii_bus->irq[i] = PHY_POLL; 1645 1646 err = mdiobus_register(priv->mii_bus); 1647 if (err) { 1648 dev_err(priv->dev, "Cannot register MDIO bus!\n"); 1649 goto err_register_mdiobus; 1650 } 1651 1652 err = ftgmac100_mii_probe(priv); 1653 if (err) { 1654 dev_err(priv->dev, "MII Probe failed!\n"); 1655 goto err_mii_probe; 1656 } 1657 1658 return 0; 1659 1660 err_mii_probe: 1661 mdiobus_unregister(priv->mii_bus); 1662 err_register_mdiobus: 1663 mdiobus_free(priv->mii_bus); 1664 return err; 1665 } 1666 1667 static void ftgmac100_destroy_mdio(struct net_device *netdev) 1668 { 1669 struct ftgmac100 *priv = netdev_priv(netdev); 1670 1671 if (!netdev->phydev) 1672 return; 1673 1674 phy_disconnect(netdev->phydev); 1675 mdiobus_unregister(priv->mii_bus); 1676 mdiobus_free(priv->mii_bus); 1677 } 1678 1679 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) 1680 { 1681 if (unlikely(nd->state != ncsi_dev_state_functional)) 1682 return; 1683 1684 netdev_info(nd->dev, "NCSI interface %s\n", 1685 nd->link_up ? "up" : "down"); 1686 } 1687 1688 static int ftgmac100_probe(struct platform_device *pdev) 1689 { 1690 struct resource *res; 1691 int irq; 1692 struct net_device *netdev; 1693 struct ftgmac100 *priv; 1694 struct device_node *np; 1695 int err = 0; 1696 1697 if (!pdev) 1698 return -ENODEV; 1699 1700 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1701 if (!res) 1702 return -ENXIO; 1703 1704 irq = platform_get_irq(pdev, 0); 1705 if (irq < 0) 1706 return irq; 1707 1708 /* setup net_device */ 1709 netdev = alloc_etherdev(sizeof(*priv)); 1710 if (!netdev) { 1711 err = -ENOMEM; 1712 goto err_alloc_etherdev; 1713 } 1714 1715 SET_NETDEV_DEV(netdev, &pdev->dev); 1716 1717 netdev->ethtool_ops = &ftgmac100_ethtool_ops; 1718 netdev->netdev_ops = &ftgmac100_netdev_ops; 1719 netdev->watchdog_timeo = 5 * HZ; 1720 1721 platform_set_drvdata(pdev, netdev); 1722 1723 /* setup private data */ 1724 priv = netdev_priv(netdev); 1725 priv->netdev = netdev; 1726 priv->dev = &pdev->dev; 1727 INIT_WORK(&priv->reset_task, ftgmac100_reset_task); 1728 1729 /* map io memory */ 1730 priv->res = request_mem_region(res->start, resource_size(res), 1731 dev_name(&pdev->dev)); 1732 if (!priv->res) { 1733 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1734 err = -ENOMEM; 1735 goto err_req_mem; 1736 } 1737 1738 priv->base = ioremap(res->start, resource_size(res)); 1739 if (!priv->base) { 1740 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1741 err = -EIO; 1742 goto err_ioremap; 1743 } 1744 1745 netdev->irq = irq; 1746 1747 /* Enable pause */ 1748 priv->tx_pause = true; 1749 priv->rx_pause = true; 1750 priv->aneg_pause = true; 1751 1752 /* MAC address from chip or random one */ 1753 ftgmac100_initial_mac(priv); 1754 1755 np = pdev->dev.of_node; 1756 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || 1757 of_device_is_compatible(np, "aspeed,ast2500-mac"))) { 1758 priv->rxdes0_edorr_mask = BIT(30); 1759 priv->txdes0_edotr_mask = BIT(30); 1760 priv->is_aspeed = true; 1761 } else { 1762 priv->rxdes0_edorr_mask = BIT(15); 1763 priv->txdes0_edotr_mask = BIT(15); 1764 } 1765 1766 if (np && of_get_property(np, "use-ncsi", NULL)) { 1767 if (!IS_ENABLED(CONFIG_NET_NCSI)) { 1768 dev_err(&pdev->dev, "NCSI stack not enabled\n"); 1769 goto err_ncsi_dev; 1770 } 1771 1772 dev_info(&pdev->dev, "Using NCSI interface\n"); 1773 priv->use_ncsi = true; 1774 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); 1775 if (!priv->ndev) 1776 goto err_ncsi_dev; 1777 } else { 1778 priv->use_ncsi = false; 1779 err = ftgmac100_setup_mdio(netdev); 1780 if (err) 1781 goto err_setup_mdio; 1782 } 1783 1784 /* Default ring sizes */ 1785 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES; 1786 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES; 1787 1788 /* Base feature set */ 1789 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM | 1790 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX | 1791 NETIF_F_HW_VLAN_CTAG_TX; 1792 1793 /* AST2400 doesn't have working HW checksum generation */ 1794 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac"))) 1795 netdev->hw_features &= ~NETIF_F_HW_CSUM; 1796 if (np && of_get_property(np, "no-hw-checksum", NULL)) 1797 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM); 1798 netdev->features |= netdev->hw_features; 1799 1800 /* register network device */ 1801 err = register_netdev(netdev); 1802 if (err) { 1803 dev_err(&pdev->dev, "Failed to register netdev\n"); 1804 goto err_register_netdev; 1805 } 1806 1807 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base); 1808 1809 return 0; 1810 1811 err_ncsi_dev: 1812 err_register_netdev: 1813 ftgmac100_destroy_mdio(netdev); 1814 err_setup_mdio: 1815 iounmap(priv->base); 1816 err_ioremap: 1817 release_resource(priv->res); 1818 err_req_mem: 1819 netif_napi_del(&priv->napi); 1820 free_netdev(netdev); 1821 err_alloc_etherdev: 1822 return err; 1823 } 1824 1825 static int ftgmac100_remove(struct platform_device *pdev) 1826 { 1827 struct net_device *netdev; 1828 struct ftgmac100 *priv; 1829 1830 netdev = platform_get_drvdata(pdev); 1831 priv = netdev_priv(netdev); 1832 1833 unregister_netdev(netdev); 1834 1835 /* There's a small chance the reset task will have been re-queued, 1836 * during stop, make sure it's gone before we free the structure. 1837 */ 1838 cancel_work_sync(&priv->reset_task); 1839 1840 ftgmac100_destroy_mdio(netdev); 1841 1842 iounmap(priv->base); 1843 release_resource(priv->res); 1844 1845 netif_napi_del(&priv->napi); 1846 free_netdev(netdev); 1847 return 0; 1848 } 1849 1850 static const struct of_device_id ftgmac100_of_match[] = { 1851 { .compatible = "faraday,ftgmac100" }, 1852 { } 1853 }; 1854 MODULE_DEVICE_TABLE(of, ftgmac100_of_match); 1855 1856 static struct platform_driver ftgmac100_driver = { 1857 .probe = ftgmac100_probe, 1858 .remove = ftgmac100_remove, 1859 .driver = { 1860 .name = DRV_NAME, 1861 .of_match_table = ftgmac100_of_match, 1862 }, 1863 }; 1864 module_platform_driver(ftgmac100_driver); 1865 1866 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1867 MODULE_DESCRIPTION("FTGMAC100 driver"); 1868 MODULE_LICENSE("GPL"); 1869