1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 36 37 #include <linux/bitmap.h> 38 #include <linux/crc32.h> 39 #include <linux/ctype.h> 40 #include <linux/debugfs.h> 41 #include <linux/err.h> 42 #include <linux/etherdevice.h> 43 #include <linux/firmware.h> 44 #include <linux/if.h> 45 #include <linux/if_vlan.h> 46 #include <linux/init.h> 47 #include <linux/log2.h> 48 #include <linux/mdio.h> 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/mutex.h> 52 #include <linux/netdevice.h> 53 #include <linux/pci.h> 54 #include <linux/aer.h> 55 #include <linux/rtnetlink.h> 56 #include <linux/sched.h> 57 #include <linux/seq_file.h> 58 #include <linux/sockios.h> 59 #include <linux/vmalloc.h> 60 #include <linux/workqueue.h> 61 #include <net/neighbour.h> 62 #include <net/netevent.h> 63 #include <net/addrconf.h> 64 #include <net/bonding.h> 65 #include <net/addrconf.h> 66 #include <asm/uaccess.h> 67 68 #include "cxgb4.h" 69 #include "t4_regs.h" 70 #include "t4_values.h" 71 #include "t4_msg.h" 72 #include "t4fw_api.h" 73 #include "t4fw_version.h" 74 #include "cxgb4_dcb.h" 75 #include "cxgb4_debugfs.h" 76 #include "clip_tbl.h" 77 #include "l2t.h" 78 79 char cxgb4_driver_name[] = KBUILD_MODNAME; 80 81 #ifdef DRV_VERSION 82 #undef DRV_VERSION 83 #endif 84 #define DRV_VERSION "2.0.0-ko" 85 const char cxgb4_driver_version[] = DRV_VERSION; 86 #define DRV_DESC "Chelsio T4/T5 Network Driver" 87 88 /* Host shadow copy of ingress filter entry. This is in host native format 89 * and doesn't match the ordering or bit order, etc. of the hardware of the 90 * firmware command. The use of bit-field structure elements is purely to 91 * remind ourselves of the field size limitations and save memory in the case 92 * where the filter table is large. 93 */ 94 struct filter_entry { 95 /* Administrative fields for filter. 96 */ 97 u32 valid:1; /* filter allocated and valid */ 98 u32 locked:1; /* filter is administratively locked */ 99 100 u32 pending:1; /* filter action is pending firmware reply */ 101 u32 smtidx:8; /* Source MAC Table index for smac */ 102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 103 104 /* The filter itself. Most of this is a straight copy of information 105 * provided by the extended ioctl(). Some fields are translated to 106 * internal forms -- for instance the Ingress Queue ID passed in from 107 * the ioctl() is translated into the Absolute Ingress Queue ID. 108 */ 109 struct ch_filter_specification fs; 110 }; 111 112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 115 116 /* Macros needed to support the PCI Device ID Table ... 117 */ 118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 119 static const struct pci_device_id cxgb4_pci_tbl[] = { 120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 121 122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is 123 * called for both. 124 */ 125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 126 127 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 128 {PCI_VDEVICE(CHELSIO, (devid)), 4} 129 130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 131 { 0, } \ 132 } 133 134 #include "t4_pci_id_tbl.h" 135 136 #define FW4_FNAME "cxgb4/t4fw.bin" 137 #define FW5_FNAME "cxgb4/t5fw.bin" 138 #define FW6_FNAME "cxgb4/t6fw.bin" 139 #define FW4_CFNAME "cxgb4/t4-config.txt" 140 #define FW5_CFNAME "cxgb4/t5-config.txt" 141 #define FW6_CFNAME "cxgb4/t6-config.txt" 142 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 143 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 144 #define PHY_AQ1202_DEVICEID 0x4409 145 #define PHY_BCM84834_DEVICEID 0x4486 146 147 MODULE_DESCRIPTION(DRV_DESC); 148 MODULE_AUTHOR("Chelsio Communications"); 149 MODULE_LICENSE("Dual BSD/GPL"); 150 MODULE_VERSION(DRV_VERSION); 151 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); 152 MODULE_FIRMWARE(FW4_FNAME); 153 MODULE_FIRMWARE(FW5_FNAME); 154 155 /* 156 * Normally we're willing to become the firmware's Master PF but will be happy 157 * if another PF has already become the Master and initialized the adapter. 158 * Setting "force_init" will cause this driver to forcibly establish itself as 159 * the Master PF and initialize the adapter. 160 */ 161 static uint force_init; 162 163 module_param(force_init, uint, 0644); 164 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter"); 165 166 /* 167 * Normally if the firmware we connect to has Configuration File support, we 168 * use that and only fall back to the old Driver-based initialization if the 169 * Configuration File fails for some reason. If force_old_init is set, then 170 * we'll always use the old Driver-based initialization sequence. 171 */ 172 static uint force_old_init; 173 174 module_param(force_old_init, uint, 0644); 175 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated" 176 " parameter"); 177 178 static int dflt_msg_enable = DFLT_MSG_ENABLE; 179 180 module_param(dflt_msg_enable, int, 0644); 181 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap"); 182 183 /* 184 * The driver uses the best interrupt scheme available on a platform in the 185 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which 186 * of these schemes the driver may consider as follows: 187 * 188 * msi = 2: choose from among all three options 189 * msi = 1: only consider MSI and INTx interrupts 190 * msi = 0: force INTx interrupts 191 */ 192 static int msi = 2; 193 194 module_param(msi, int, 0644); 195 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); 196 197 /* 198 * Queue interrupt hold-off timer values. Queues default to the first of these 199 * upon creation. 200 */ 201 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 }; 202 203 module_param_array(intr_holdoff, uint, NULL, 0644); 204 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers " 205 "0..4 in microseconds, deprecated parameter"); 206 207 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 }; 208 209 module_param_array(intr_cnt, uint, NULL, 0644); 210 MODULE_PARM_DESC(intr_cnt, 211 "thresholds 1..3 for queue interrupt packet counters, " 212 "deprecated parameter"); 213 214 /* 215 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers 216 * offset by 2 bytes in order to have the IP headers line up on 4-byte 217 * boundaries. This is a requirement for many architectures which will throw 218 * a machine check fault if an attempt is made to access one of the 4-byte IP 219 * header fields on a non-4-byte boundary. And it's a major performance issue 220 * even on some architectures which allow it like some implementations of the 221 * x86 ISA. However, some architectures don't mind this and for some very 222 * edge-case performance sensitive applications (like forwarding large volumes 223 * of small packets), setting this DMA offset to 0 will decrease the number of 224 * PCI-E Bus transfers enough to measurably affect performance. 225 */ 226 static int rx_dma_offset = 2; 227 228 static bool vf_acls; 229 230 #ifdef CONFIG_PCI_IOV 231 module_param(vf_acls, bool, 0644); 232 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, " 233 "deprecated parameter"); 234 235 /* Configure the number of PCI-E Virtual Function which are to be instantiated 236 * on SR-IOV Capable Physical Functions. 237 */ 238 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV]; 239 240 module_param_array(num_vf, uint, NULL, 0644); 241 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3"); 242 #endif 243 244 /* TX Queue select used to determine what algorithm to use for selecting TX 245 * queue. Select between the kernel provided function (select_queue=0) or user 246 * cxgb_select_queue function (select_queue=1) 247 * 248 * Default: select_queue=0 249 */ 250 static int select_queue; 251 module_param(select_queue, int, 0644); 252 MODULE_PARM_DESC(select_queue, 253 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); 254 255 static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC; 256 257 module_param(tp_vlan_pri_map, uint, 0644); 258 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, " 259 "deprecated parameter"); 260 261 static struct dentry *cxgb4_debugfs_root; 262 263 static LIST_HEAD(adapter_list); 264 static DEFINE_MUTEX(uld_mutex); 265 /* Adapter list to be accessed from atomic context */ 266 static LIST_HEAD(adap_rcu_list); 267 static DEFINE_SPINLOCK(adap_rcu_lock); 268 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX]; 269 static const char *uld_str[] = { "RDMA", "iSCSI" }; 270 271 static void link_report(struct net_device *dev) 272 { 273 if (!netif_carrier_ok(dev)) 274 netdev_info(dev, "link down\n"); 275 else { 276 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; 277 278 const char *s = "10Mbps"; 279 const struct port_info *p = netdev_priv(dev); 280 281 switch (p->link_cfg.speed) { 282 case 10000: 283 s = "10Gbps"; 284 break; 285 case 1000: 286 s = "1000Mbps"; 287 break; 288 case 100: 289 s = "100Mbps"; 290 break; 291 case 40000: 292 s = "40Gbps"; 293 break; 294 } 295 296 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, 297 fc[p->link_cfg.fc]); 298 } 299 } 300 301 #ifdef CONFIG_CHELSIO_T4_DCB 302 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ 303 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) 304 { 305 struct port_info *pi = netdev_priv(dev); 306 struct adapter *adap = pi->adapter; 307 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; 308 int i; 309 310 /* We use a simple mapping of Port TX Queue Index to DCB 311 * Priority when we're enabling DCB. 312 */ 313 for (i = 0; i < pi->nqsets; i++, txq++) { 314 u32 name, value; 315 int err; 316 317 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 318 FW_PARAMS_PARAM_X_V( 319 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | 320 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); 321 value = enable ? i : 0xffffffff; 322 323 /* Since we can be called while atomic (from "interrupt 324 * level") we need to issue the Set Parameters Commannd 325 * without sleeping (timeout < 0). 326 */ 327 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 328 &name, &value, 329 -FW_CMD_MAX_TIMEOUT); 330 331 if (err) 332 dev_err(adap->pdev_dev, 333 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", 334 enable ? "set" : "unset", pi->port_id, i, -err); 335 else 336 txq->dcb_prio = value; 337 } 338 } 339 #endif /* CONFIG_CHELSIO_T4_DCB */ 340 341 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) 342 { 343 struct net_device *dev = adapter->port[port_id]; 344 345 /* Skip changes from disabled ports. */ 346 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { 347 if (link_stat) 348 netif_carrier_on(dev); 349 else { 350 #ifdef CONFIG_CHELSIO_T4_DCB 351 cxgb4_dcb_state_init(dev); 352 dcb_tx_queue_prio_enable(dev, false); 353 #endif /* CONFIG_CHELSIO_T4_DCB */ 354 netif_carrier_off(dev); 355 } 356 357 link_report(dev); 358 } 359 } 360 361 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 362 { 363 static const char *mod_str[] = { 364 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 365 }; 366 367 const struct net_device *dev = adap->port[port_id]; 368 const struct port_info *pi = netdev_priv(dev); 369 370 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 371 netdev_info(dev, "port module unplugged\n"); 372 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 373 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); 374 } 375 376 /* 377 * Configure the exact and hash address filters to handle a port's multicast 378 * and secondary unicast MAC addresses. 379 */ 380 static int set_addr_filters(const struct net_device *dev, bool sleep) 381 { 382 u64 mhash = 0; 383 u64 uhash = 0; 384 bool free = true; 385 u16 filt_idx[7]; 386 const u8 *addr[7]; 387 int ret, naddr = 0; 388 const struct netdev_hw_addr *ha; 389 int uc_cnt = netdev_uc_count(dev); 390 int mc_cnt = netdev_mc_count(dev); 391 const struct port_info *pi = netdev_priv(dev); 392 unsigned int mb = pi->adapter->pf; 393 394 /* first do the secondary unicast addresses */ 395 netdev_for_each_uc_addr(ha, dev) { 396 addr[naddr++] = ha->addr; 397 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) { 398 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free, 399 naddr, addr, filt_idx, &uhash, sleep); 400 if (ret < 0) 401 return ret; 402 403 free = false; 404 naddr = 0; 405 } 406 } 407 408 /* next set up the multicast addresses */ 409 netdev_for_each_mc_addr(ha, dev) { 410 addr[naddr++] = ha->addr; 411 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) { 412 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free, 413 naddr, addr, filt_idx, &mhash, sleep); 414 if (ret < 0) 415 return ret; 416 417 free = false; 418 naddr = 0; 419 } 420 } 421 422 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0, 423 uhash | mhash, sleep); 424 } 425 426 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ 427 module_param(dbfifo_int_thresh, int, 0644); 428 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); 429 430 /* 431 * usecs to sleep while draining the dbfifo 432 */ 433 static int dbfifo_drain_delay = 1000; 434 module_param(dbfifo_drain_delay, int, 0644); 435 MODULE_PARM_DESC(dbfifo_drain_delay, 436 "usecs to sleep while draining the dbfifo"); 437 438 /* 439 * Set Rx properties of a port, such as promiscruity, address filters, and MTU. 440 * If @mtu is -1 it is left unchanged. 441 */ 442 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) 443 { 444 int ret; 445 struct port_info *pi = netdev_priv(dev); 446 447 ret = set_addr_filters(dev, sleep_ok); 448 if (ret == 0) 449 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu, 450 (dev->flags & IFF_PROMISC) ? 1 : 0, 451 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, 452 sleep_ok); 453 return ret; 454 } 455 456 /** 457 * link_start - enable a port 458 * @dev: the port to enable 459 * 460 * Performs the MAC and PHY actions needed to enable a port. 461 */ 462 static int link_start(struct net_device *dev) 463 { 464 int ret; 465 struct port_info *pi = netdev_priv(dev); 466 unsigned int mb = pi->adapter->pf; 467 468 /* 469 * We do not set address filters and promiscuity here, the stack does 470 * that step explicitly. 471 */ 472 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, 473 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 474 if (ret == 0) { 475 ret = t4_change_mac(pi->adapter, mb, pi->viid, 476 pi->xact_addr_filt, dev->dev_addr, true, 477 true); 478 if (ret >= 0) { 479 pi->xact_addr_filt = ret; 480 ret = 0; 481 } 482 } 483 if (ret == 0) 484 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, 485 &pi->link_cfg); 486 if (ret == 0) { 487 local_bh_disable(); 488 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true, 489 true, CXGB4_DCB_ENABLED); 490 local_bh_enable(); 491 } 492 493 return ret; 494 } 495 496 int cxgb4_dcb_enabled(const struct net_device *dev) 497 { 498 #ifdef CONFIG_CHELSIO_T4_DCB 499 struct port_info *pi = netdev_priv(dev); 500 501 if (!pi->dcb.enabled) 502 return 0; 503 504 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || 505 (pi->dcb.state == CXGB4_DCB_STATE_HOST)); 506 #else 507 return 0; 508 #endif 509 } 510 EXPORT_SYMBOL(cxgb4_dcb_enabled); 511 512 #ifdef CONFIG_CHELSIO_T4_DCB 513 /* Handle a Data Center Bridging update message from the firmware. */ 514 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) 515 { 516 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); 517 struct net_device *dev = adap->port[port]; 518 int old_dcb_enabled = cxgb4_dcb_enabled(dev); 519 int new_dcb_enabled; 520 521 cxgb4_dcb_handle_fw_update(adap, pcmd); 522 new_dcb_enabled = cxgb4_dcb_enabled(dev); 523 524 /* If the DCB has become enabled or disabled on the port then we're 525 * going to need to set up/tear down DCB Priority parameters for the 526 * TX Queues associated with the port. 527 */ 528 if (new_dcb_enabled != old_dcb_enabled) 529 dcb_tx_queue_prio_enable(dev, new_dcb_enabled); 530 } 531 #endif /* CONFIG_CHELSIO_T4_DCB */ 532 533 /* Clear a filter and release any of its resources that we own. This also 534 * clears the filter's "pending" status. 535 */ 536 static void clear_filter(struct adapter *adap, struct filter_entry *f) 537 { 538 /* If the new or old filter have loopback rewriteing rules then we'll 539 * need to free any existing Layer Two Table (L2T) entries of the old 540 * filter rule. The firmware will handle freeing up any Source MAC 541 * Table (SMT) entries used for rewriting Source MAC Addresses in 542 * loopback rules. 543 */ 544 if (f->l2t) 545 cxgb4_l2t_release(f->l2t); 546 547 /* The zeroing of the filter rule below clears the filter valid, 548 * pending, locked flags, l2t pointer, etc. so it's all we need for 549 * this operation. 550 */ 551 memset(f, 0, sizeof(*f)); 552 } 553 554 /* Handle a filter write/deletion reply. 555 */ 556 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl) 557 { 558 unsigned int idx = GET_TID(rpl); 559 unsigned int nidx = idx - adap->tids.ftid_base; 560 unsigned int ret; 561 struct filter_entry *f; 562 563 if (idx >= adap->tids.ftid_base && nidx < 564 (adap->tids.nftids + adap->tids.nsftids)) { 565 idx = nidx; 566 ret = TCB_COOKIE_G(rpl->cookie); 567 f = &adap->tids.ftid_tab[idx]; 568 569 if (ret == FW_FILTER_WR_FLT_DELETED) { 570 /* Clear the filter when we get confirmation from the 571 * hardware that the filter has been deleted. 572 */ 573 clear_filter(adap, f); 574 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) { 575 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n", 576 idx); 577 clear_filter(adap, f); 578 } else if (ret == FW_FILTER_WR_FLT_ADDED) { 579 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff; 580 f->pending = 0; /* asynchronous setup completed */ 581 f->valid = 1; 582 } else { 583 /* Something went wrong. Issue a warning about the 584 * problem and clear everything out. 585 */ 586 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n", 587 idx, ret); 588 clear_filter(adap, f); 589 } 590 } 591 } 592 593 /* Response queue handler for the FW event queue. 594 */ 595 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 596 const struct pkt_gl *gl) 597 { 598 u8 opcode = ((const struct rss_header *)rsp)->opcode; 599 600 rsp++; /* skip RSS header */ 601 602 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 603 */ 604 if (unlikely(opcode == CPL_FW4_MSG && 605 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { 606 rsp++; 607 opcode = ((const struct rss_header *)rsp)->opcode; 608 rsp++; 609 if (opcode != CPL_SGE_EGR_UPDATE) { 610 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" 611 , opcode); 612 goto out; 613 } 614 } 615 616 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 617 const struct cpl_sge_egr_update *p = (void *)rsp; 618 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); 619 struct sge_txq *txq; 620 621 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; 622 txq->restarts++; 623 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) { 624 struct sge_eth_txq *eq; 625 626 eq = container_of(txq, struct sge_eth_txq, q); 627 netif_tx_wake_queue(eq->txq); 628 } else { 629 struct sge_ofld_txq *oq; 630 631 oq = container_of(txq, struct sge_ofld_txq, q); 632 tasklet_schedule(&oq->qresume_tsk); 633 } 634 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 635 const struct cpl_fw6_msg *p = (void *)rsp; 636 637 #ifdef CONFIG_CHELSIO_T4_DCB 638 const struct fw_port_cmd *pcmd = (const void *)p->data; 639 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); 640 unsigned int action = 641 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); 642 643 if (cmd == FW_PORT_CMD && 644 action == FW_PORT_ACTION_GET_PORT_INFO) { 645 int port = FW_PORT_CMD_PORTID_G( 646 be32_to_cpu(pcmd->op_to_portid)); 647 struct net_device *dev = q->adap->port[port]; 648 int state_input = ((pcmd->u.info.dcbxdis_pkd & 649 FW_PORT_CMD_DCBXDIS_F) 650 ? CXGB4_DCB_INPUT_FW_DISABLED 651 : CXGB4_DCB_INPUT_FW_ENABLED); 652 653 cxgb4_dcb_state_fsm(dev, state_input); 654 } 655 656 if (cmd == FW_PORT_CMD && 657 action == FW_PORT_ACTION_L2_DCB_CFG) 658 dcb_rpl(q->adap, pcmd); 659 else 660 #endif 661 if (p->type == 0) 662 t4_handle_fw_rpl(q->adap, p->data); 663 } else if (opcode == CPL_L2T_WRITE_RPL) { 664 const struct cpl_l2t_write_rpl *p = (void *)rsp; 665 666 do_l2t_write_rpl(q->adap, p); 667 } else if (opcode == CPL_SET_TCB_RPL) { 668 const struct cpl_set_tcb_rpl *p = (void *)rsp; 669 670 filter_rpl(q->adap, p); 671 } else 672 dev_err(q->adap->pdev_dev, 673 "unexpected CPL %#x on FW event queue\n", opcode); 674 out: 675 return 0; 676 } 677 678 /** 679 * uldrx_handler - response queue handler for ULD queues 680 * @q: the response queue that received the packet 681 * @rsp: the response queue descriptor holding the offload message 682 * @gl: the gather list of packet fragments 683 * 684 * Deliver an ingress offload packet to a ULD. All processing is done by 685 * the ULD, we just maintain statistics. 686 */ 687 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp, 688 const struct pkt_gl *gl) 689 { 690 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq); 691 692 /* FW can send CPLs encapsulated in a CPL_FW4_MSG. 693 */ 694 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG && 695 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL) 696 rsp += 2; 697 698 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) { 699 rxq->stats.nomem++; 700 return -1; 701 } 702 if (gl == NULL) 703 rxq->stats.imm++; 704 else if (gl == CXGB4_MSG_AN) 705 rxq->stats.an++; 706 else 707 rxq->stats.pkts++; 708 return 0; 709 } 710 711 static void disable_msi(struct adapter *adapter) 712 { 713 if (adapter->flags & USING_MSIX) { 714 pci_disable_msix(adapter->pdev); 715 adapter->flags &= ~USING_MSIX; 716 } else if (adapter->flags & USING_MSI) { 717 pci_disable_msi(adapter->pdev); 718 adapter->flags &= ~USING_MSI; 719 } 720 } 721 722 /* 723 * Interrupt handler for non-data events used with MSI-X. 724 */ 725 static irqreturn_t t4_nondata_intr(int irq, void *cookie) 726 { 727 struct adapter *adap = cookie; 728 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); 729 730 if (v & PFSW_F) { 731 adap->swintr = 1; 732 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); 733 } 734 if (adap->flags & MASTER_PF) 735 t4_slow_intr_handler(adap); 736 return IRQ_HANDLED; 737 } 738 739 /* 740 * Name the MSI-X interrupts. 741 */ 742 static void name_msix_vecs(struct adapter *adap) 743 { 744 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); 745 746 /* non-data interrupts */ 747 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); 748 749 /* FW events */ 750 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", 751 adap->port[0]->name); 752 753 /* Ethernet queues */ 754 for_each_port(adap, j) { 755 struct net_device *d = adap->port[j]; 756 const struct port_info *pi = netdev_priv(d); 757 758 for (i = 0; i < pi->nqsets; i++, msi_idx++) 759 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", 760 d->name, i); 761 } 762 763 /* offload queues */ 764 for_each_ofldrxq(&adap->sge, i) 765 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d", 766 adap->port[0]->name, i); 767 768 for_each_rdmarxq(&adap->sge, i) 769 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d", 770 adap->port[0]->name, i); 771 772 for_each_rdmaciq(&adap->sge, i) 773 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d", 774 adap->port[0]->name, i); 775 } 776 777 static int request_msix_queue_irqs(struct adapter *adap) 778 { 779 struct sge *s = &adap->sge; 780 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0; 781 int msi_index = 2; 782 783 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, 784 adap->msix_info[1].desc, &s->fw_evtq); 785 if (err) 786 return err; 787 788 for_each_ethrxq(s, ethqidx) { 789 err = request_irq(adap->msix_info[msi_index].vec, 790 t4_sge_intr_msix, 0, 791 adap->msix_info[msi_index].desc, 792 &s->ethrxq[ethqidx].rspq); 793 if (err) 794 goto unwind; 795 msi_index++; 796 } 797 for_each_ofldrxq(s, ofldqidx) { 798 err = request_irq(adap->msix_info[msi_index].vec, 799 t4_sge_intr_msix, 0, 800 adap->msix_info[msi_index].desc, 801 &s->ofldrxq[ofldqidx].rspq); 802 if (err) 803 goto unwind; 804 msi_index++; 805 } 806 for_each_rdmarxq(s, rdmaqidx) { 807 err = request_irq(adap->msix_info[msi_index].vec, 808 t4_sge_intr_msix, 0, 809 adap->msix_info[msi_index].desc, 810 &s->rdmarxq[rdmaqidx].rspq); 811 if (err) 812 goto unwind; 813 msi_index++; 814 } 815 for_each_rdmaciq(s, rdmaciqqidx) { 816 err = request_irq(adap->msix_info[msi_index].vec, 817 t4_sge_intr_msix, 0, 818 adap->msix_info[msi_index].desc, 819 &s->rdmaciq[rdmaciqqidx].rspq); 820 if (err) 821 goto unwind; 822 msi_index++; 823 } 824 return 0; 825 826 unwind: 827 while (--rdmaciqqidx >= 0) 828 free_irq(adap->msix_info[--msi_index].vec, 829 &s->rdmaciq[rdmaciqqidx].rspq); 830 while (--rdmaqidx >= 0) 831 free_irq(adap->msix_info[--msi_index].vec, 832 &s->rdmarxq[rdmaqidx].rspq); 833 while (--ofldqidx >= 0) 834 free_irq(adap->msix_info[--msi_index].vec, 835 &s->ofldrxq[ofldqidx].rspq); 836 while (--ethqidx >= 0) 837 free_irq(adap->msix_info[--msi_index].vec, 838 &s->ethrxq[ethqidx].rspq); 839 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 840 return err; 841 } 842 843 static void free_msix_queue_irqs(struct adapter *adap) 844 { 845 int i, msi_index = 2; 846 struct sge *s = &adap->sge; 847 848 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 849 for_each_ethrxq(s, i) 850 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); 851 for_each_ofldrxq(s, i) 852 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq); 853 for_each_rdmarxq(s, i) 854 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq); 855 for_each_rdmaciq(s, i) 856 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq); 857 } 858 859 /** 860 * cxgb4_write_rss - write the RSS table for a given port 861 * @pi: the port 862 * @queues: array of queue indices for RSS 863 * 864 * Sets up the portion of the HW RSS table for the port's VI to distribute 865 * packets to the Rx queues in @queues. 866 * Should never be called before setting up sge eth rx queues 867 */ 868 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 869 { 870 u16 *rss; 871 int i, err; 872 struct adapter *adapter = pi->adapter; 873 const struct sge_eth_rxq *rxq; 874 875 rxq = &adapter->sge.ethrxq[pi->first_qset]; 876 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL); 877 if (!rss) 878 return -ENOMEM; 879 880 /* map the queue indices to queue ids */ 881 for (i = 0; i < pi->rss_size; i++, queues++) 882 rss[i] = rxq[*queues].rspq.abs_id; 883 884 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 885 pi->rss_size, rss, pi->rss_size); 886 /* If Tunnel All Lookup isn't specified in the global RSS 887 * Configuration, then we need to specify a default Ingress 888 * Queue for any ingress packets which aren't hashed. We'll 889 * use our first ingress queue ... 890 */ 891 if (!err) 892 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 893 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | 894 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | 895 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | 896 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | 897 FW_RSS_VI_CONFIG_CMD_UDPEN_F, 898 rss[0]); 899 kfree(rss); 900 return err; 901 } 902 903 /** 904 * setup_rss - configure RSS 905 * @adap: the adapter 906 * 907 * Sets up RSS for each port. 908 */ 909 static int setup_rss(struct adapter *adap) 910 { 911 int i, j, err; 912 913 for_each_port(adap, i) { 914 const struct port_info *pi = adap2pinfo(adap, i); 915 916 /* Fill default values with equal distribution */ 917 for (j = 0; j < pi->rss_size; j++) 918 pi->rss[j] = j % pi->nqsets; 919 920 err = cxgb4_write_rss(pi, pi->rss); 921 if (err) 922 return err; 923 } 924 return 0; 925 } 926 927 /* 928 * Return the channel of the ingress queue with the given qid. 929 */ 930 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) 931 { 932 qid -= p->ingr_start; 933 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; 934 } 935 936 /* 937 * Wait until all NAPI handlers are descheduled. 938 */ 939 static void quiesce_rx(struct adapter *adap) 940 { 941 int i; 942 943 for (i = 0; i < adap->sge.ingr_sz; i++) { 944 struct sge_rspq *q = adap->sge.ingr_map[i]; 945 946 if (q && q->handler) { 947 napi_disable(&q->napi); 948 local_bh_disable(); 949 while (!cxgb_poll_lock_napi(q)) 950 mdelay(1); 951 local_bh_enable(); 952 } 953 954 } 955 } 956 957 /* Disable interrupt and napi handler */ 958 static void disable_interrupts(struct adapter *adap) 959 { 960 if (adap->flags & FULL_INIT_DONE) { 961 t4_intr_disable(adap); 962 if (adap->flags & USING_MSIX) { 963 free_msix_queue_irqs(adap); 964 free_irq(adap->msix_info[0].vec, adap); 965 } else { 966 free_irq(adap->pdev->irq, adap); 967 } 968 quiesce_rx(adap); 969 } 970 } 971 972 /* 973 * Enable NAPI scheduling and interrupt generation for all Rx queues. 974 */ 975 static void enable_rx(struct adapter *adap) 976 { 977 int i; 978 979 for (i = 0; i < adap->sge.ingr_sz; i++) { 980 struct sge_rspq *q = adap->sge.ingr_map[i]; 981 982 if (!q) 983 continue; 984 if (q->handler) { 985 cxgb_busy_poll_init_lock(q); 986 napi_enable(&q->napi); 987 } 988 /* 0-increment GTS to start the timer and enable interrupts */ 989 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 990 SEINTARM_V(q->intr_params) | 991 INGRESSQID_V(q->cntxt_id)); 992 } 993 } 994 995 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q, 996 unsigned int nq, unsigned int per_chan, int msi_idx, 997 u16 *ids) 998 { 999 int i, err; 1000 1001 for (i = 0; i < nq; i++, q++) { 1002 if (msi_idx > 0) 1003 msi_idx++; 1004 err = t4_sge_alloc_rxq(adap, &q->rspq, false, 1005 adap->port[i / per_chan], 1006 msi_idx, q->fl.size ? &q->fl : NULL, 1007 uldrx_handler, 0); 1008 if (err) 1009 return err; 1010 memset(&q->stats, 0, sizeof(q->stats)); 1011 if (ids) 1012 ids[i] = q->rspq.abs_id; 1013 } 1014 return 0; 1015 } 1016 1017 /** 1018 * setup_sge_queues - configure SGE Tx/Rx/response queues 1019 * @adap: the adapter 1020 * 1021 * Determines how many sets of SGE queues to use and initializes them. 1022 * We support multiple queue sets per port if we have MSI-X, otherwise 1023 * just one queue set per port. 1024 */ 1025 static int setup_sge_queues(struct adapter *adap) 1026 { 1027 int err, msi_idx, i, j; 1028 struct sge *s = &adap->sge; 1029 1030 bitmap_zero(s->starving_fl, s->egr_sz); 1031 bitmap_zero(s->txq_maperr, s->egr_sz); 1032 1033 if (adap->flags & USING_MSIX) 1034 msi_idx = 1; /* vector 0 is for non-queue interrupts */ 1035 else { 1036 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, 1037 NULL, NULL, -1); 1038 if (err) 1039 return err; 1040 msi_idx = -((int)s->intrq.abs_id + 1); 1041 } 1042 1043 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here, 1044 * don't forget to update the following which need to be 1045 * synchronized to and changes here. 1046 * 1047 * 1. The calculations of MAX_INGQ in cxgb4.h. 1048 * 1049 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs 1050 * to accommodate any new/deleted Ingress Queues 1051 * which need MSI-X Vectors. 1052 * 1053 * 3. Update sge_qinfo_show() to include information on the 1054 * new/deleted queues. 1055 */ 1056 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], 1057 msi_idx, NULL, fwevtq_handler, -1); 1058 if (err) { 1059 freeout: t4_free_sge_resources(adap); 1060 return err; 1061 } 1062 1063 for_each_port(adap, i) { 1064 struct net_device *dev = adap->port[i]; 1065 struct port_info *pi = netdev_priv(dev); 1066 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; 1067 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; 1068 1069 for (j = 0; j < pi->nqsets; j++, q++) { 1070 if (msi_idx > 0) 1071 msi_idx++; 1072 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, 1073 msi_idx, &q->fl, 1074 t4_ethrx_handler, 1075 t4_get_mps_bg_map(adap, 1076 pi->tx_chan)); 1077 if (err) 1078 goto freeout; 1079 q->rspq.idx = j; 1080 memset(&q->stats, 0, sizeof(q->stats)); 1081 } 1082 for (j = 0; j < pi->nqsets; j++, t++) { 1083 err = t4_sge_alloc_eth_txq(adap, t, dev, 1084 netdev_get_tx_queue(dev, j), 1085 s->fw_evtq.cntxt_id); 1086 if (err) 1087 goto freeout; 1088 } 1089 } 1090 1091 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */ 1092 for_each_ofldrxq(s, i) { 1093 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], 1094 adap->port[i / j], 1095 s->fw_evtq.cntxt_id); 1096 if (err) 1097 goto freeout; 1098 } 1099 1100 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \ 1101 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \ 1102 if (err) \ 1103 goto freeout; \ 1104 if (msi_idx > 0) \ 1105 msi_idx += nq; \ 1106 } while (0) 1107 1108 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq); 1109 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq); 1110 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */ 1111 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq); 1112 1113 #undef ALLOC_OFLD_RXQS 1114 1115 for_each_port(adap, i) { 1116 /* 1117 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't 1118 * have RDMA queues, and that's the right value. 1119 */ 1120 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], 1121 s->fw_evtq.cntxt_id, 1122 s->rdmarxq[i].rspq.cntxt_id); 1123 if (err) 1124 goto freeout; 1125 } 1126 1127 t4_write_reg(adap, is_t4(adap->params.chip) ? 1128 MPS_TRC_RSS_CONTROL_A : 1129 MPS_T5_TRC_RSS_CONTROL_A, 1130 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | 1131 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); 1132 return 0; 1133 } 1134 1135 /* 1136 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc. 1137 * The allocated memory is cleared. 1138 */ 1139 void *t4_alloc_mem(size_t size) 1140 { 1141 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 1142 1143 if (!p) 1144 p = vzalloc(size); 1145 return p; 1146 } 1147 1148 /* 1149 * Free memory allocated through alloc_mem(). 1150 */ 1151 void t4_free_mem(void *addr) 1152 { 1153 kvfree(addr); 1154 } 1155 1156 /* Send a Work Request to write the filter at a specified index. We construct 1157 * a Firmware Filter Work Request to have the work done and put the indicated 1158 * filter into "pending" mode which will prevent any further actions against 1159 * it till we get a reply from the firmware on the completion status of the 1160 * request. 1161 */ 1162 static int set_filter_wr(struct adapter *adapter, int fidx) 1163 { 1164 struct filter_entry *f = &adapter->tids.ftid_tab[fidx]; 1165 struct sk_buff *skb; 1166 struct fw_filter_wr *fwr; 1167 unsigned int ftid; 1168 1169 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL); 1170 if (!skb) 1171 return -ENOMEM; 1172 1173 /* If the new filter requires loopback Destination MAC and/or VLAN 1174 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for 1175 * the filter. 1176 */ 1177 if (f->fs.newdmac || f->fs.newvlan) { 1178 /* allocate L2T entry for new filter */ 1179 f->l2t = t4_l2t_alloc_switching(adapter->l2t); 1180 if (f->l2t == NULL) { 1181 kfree_skb(skb); 1182 return -EAGAIN; 1183 } 1184 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan, 1185 f->fs.eport, f->fs.dmac)) { 1186 cxgb4_l2t_release(f->l2t); 1187 f->l2t = NULL; 1188 kfree_skb(skb); 1189 return -ENOMEM; 1190 } 1191 } 1192 1193 ftid = adapter->tids.ftid_base + fidx; 1194 1195 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr)); 1196 memset(fwr, 0, sizeof(*fwr)); 1197 1198 /* It would be nice to put most of the following in t4_hw.c but most 1199 * of the work is translating the cxgbtool ch_filter_specification 1200 * into the Work Request and the definition of that structure is 1201 * currently in cxgbtool.h which isn't appropriate to pull into the 1202 * common code. We may eventually try to come up with a more neutral 1203 * filter specification structure but for now it's easiest to simply 1204 * put this fairly direct code in line ... 1205 */ 1206 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR)); 1207 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16)); 1208 fwr->tid_to_iq = 1209 htonl(FW_FILTER_WR_TID_V(ftid) | 1210 FW_FILTER_WR_RQTYPE_V(f->fs.type) | 1211 FW_FILTER_WR_NOREPLY_V(0) | 1212 FW_FILTER_WR_IQ_V(f->fs.iq)); 1213 fwr->del_filter_to_l2tix = 1214 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) | 1215 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) | 1216 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) | 1217 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) | 1218 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) | 1219 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) | 1220 FW_FILTER_WR_DMAC_V(f->fs.newdmac) | 1221 FW_FILTER_WR_SMAC_V(f->fs.newsmac) | 1222 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT || 1223 f->fs.newvlan == VLAN_REWRITE) | 1224 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE || 1225 f->fs.newvlan == VLAN_REWRITE) | 1226 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) | 1227 FW_FILTER_WR_TXCHAN_V(f->fs.eport) | 1228 FW_FILTER_WR_PRIO_V(f->fs.prio) | 1229 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0)); 1230 fwr->ethtype = htons(f->fs.val.ethtype); 1231 fwr->ethtypem = htons(f->fs.mask.ethtype); 1232 fwr->frag_to_ovlan_vldm = 1233 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) | 1234 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) | 1235 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) | 1236 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) | 1237 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) | 1238 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld)); 1239 fwr->smac_sel = 0; 1240 fwr->rx_chan_rx_rpl_iq = 1241 htons(FW_FILTER_WR_RX_CHAN_V(0) | 1242 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id)); 1243 fwr->maci_to_matchtypem = 1244 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) | 1245 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) | 1246 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) | 1247 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) | 1248 FW_FILTER_WR_PORT_V(f->fs.val.iport) | 1249 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) | 1250 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) | 1251 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype)); 1252 fwr->ptcl = f->fs.val.proto; 1253 fwr->ptclm = f->fs.mask.proto; 1254 fwr->ttyp = f->fs.val.tos; 1255 fwr->ttypm = f->fs.mask.tos; 1256 fwr->ivlan = htons(f->fs.val.ivlan); 1257 fwr->ivlanm = htons(f->fs.mask.ivlan); 1258 fwr->ovlan = htons(f->fs.val.ovlan); 1259 fwr->ovlanm = htons(f->fs.mask.ovlan); 1260 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip)); 1261 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm)); 1262 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip)); 1263 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm)); 1264 fwr->lp = htons(f->fs.val.lport); 1265 fwr->lpm = htons(f->fs.mask.lport); 1266 fwr->fp = htons(f->fs.val.fport); 1267 fwr->fpm = htons(f->fs.mask.fport); 1268 if (f->fs.newsmac) 1269 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma)); 1270 1271 /* Mark the filter as "pending" and ship off the Filter Work Request. 1272 * When we get the Work Request Reply we'll clear the pending status. 1273 */ 1274 f->pending = 1; 1275 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); 1276 t4_ofld_send(adapter, skb); 1277 return 0; 1278 } 1279 1280 /* Delete the filter at a specified index. 1281 */ 1282 static int del_filter_wr(struct adapter *adapter, int fidx) 1283 { 1284 struct filter_entry *f = &adapter->tids.ftid_tab[fidx]; 1285 struct sk_buff *skb; 1286 struct fw_filter_wr *fwr; 1287 unsigned int len, ftid; 1288 1289 len = sizeof(*fwr); 1290 ftid = adapter->tids.ftid_base + fidx; 1291 1292 skb = alloc_skb(len, GFP_KERNEL); 1293 if (!skb) 1294 return -ENOMEM; 1295 1296 fwr = (struct fw_filter_wr *)__skb_put(skb, len); 1297 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id); 1298 1299 /* Mark the filter as "pending" and ship off the Filter Work Request. 1300 * When we get the Work Request Reply we'll clear the pending status. 1301 */ 1302 f->pending = 1; 1303 t4_mgmt_tx(adapter, skb); 1304 return 0; 1305 } 1306 1307 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, 1308 void *accel_priv, select_queue_fallback_t fallback) 1309 { 1310 int txq; 1311 1312 #ifdef CONFIG_CHELSIO_T4_DCB 1313 /* If a Data Center Bridging has been successfully negotiated on this 1314 * link then we'll use the skb's priority to map it to a TX Queue. 1315 * The skb's priority is determined via the VLAN Tag Priority Code 1316 * Point field. 1317 */ 1318 if (cxgb4_dcb_enabled(dev)) { 1319 u16 vlan_tci; 1320 int err; 1321 1322 err = vlan_get_tag(skb, &vlan_tci); 1323 if (unlikely(err)) { 1324 if (net_ratelimit()) 1325 netdev_warn(dev, 1326 "TX Packet without VLAN Tag on DCB Link\n"); 1327 txq = 0; 1328 } else { 1329 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 1330 #ifdef CONFIG_CHELSIO_T4_FCOE 1331 if (skb->protocol == htons(ETH_P_FCOE)) 1332 txq = skb->priority & 0x7; 1333 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1334 } 1335 return txq; 1336 } 1337 #endif /* CONFIG_CHELSIO_T4_DCB */ 1338 1339 if (select_queue) { 1340 txq = (skb_rx_queue_recorded(skb) 1341 ? skb_get_rx_queue(skb) 1342 : smp_processor_id()); 1343 1344 while (unlikely(txq >= dev->real_num_tx_queues)) 1345 txq -= dev->real_num_tx_queues; 1346 1347 return txq; 1348 } 1349 1350 return fallback(dev, skb) % dev->real_num_tx_queues; 1351 } 1352 1353 static int closest_timer(const struct sge *s, int time) 1354 { 1355 int i, delta, match = 0, min_delta = INT_MAX; 1356 1357 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 1358 delta = time - s->timer_val[i]; 1359 if (delta < 0) 1360 delta = -delta; 1361 if (delta < min_delta) { 1362 min_delta = delta; 1363 match = i; 1364 } 1365 } 1366 return match; 1367 } 1368 1369 static int closest_thres(const struct sge *s, int thres) 1370 { 1371 int i, delta, match = 0, min_delta = INT_MAX; 1372 1373 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 1374 delta = thres - s->counter_val[i]; 1375 if (delta < 0) 1376 delta = -delta; 1377 if (delta < min_delta) { 1378 min_delta = delta; 1379 match = i; 1380 } 1381 } 1382 return match; 1383 } 1384 1385 /** 1386 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 1387 * @q: the Rx queue 1388 * @us: the hold-off time in us, or 0 to disable timer 1389 * @cnt: the hold-off packet count, or 0 to disable counter 1390 * 1391 * Sets an Rx queue's interrupt hold-off time and packet count. At least 1392 * one of the two needs to be enabled for the queue to generate interrupts. 1393 */ 1394 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, 1395 unsigned int us, unsigned int cnt) 1396 { 1397 struct adapter *adap = q->adap; 1398 1399 if ((us | cnt) == 0) 1400 cnt = 1; 1401 1402 if (cnt) { 1403 int err; 1404 u32 v, new_idx; 1405 1406 new_idx = closest_thres(&adap->sge, cnt); 1407 if (q->desc && q->pktcnt_idx != new_idx) { 1408 /* the queue has already been created, update it */ 1409 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 1410 FW_PARAMS_PARAM_X_V( 1411 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 1412 FW_PARAMS_PARAM_YZ_V(q->cntxt_id); 1413 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 1414 &v, &new_idx); 1415 if (err) 1416 return err; 1417 } 1418 q->pktcnt_idx = new_idx; 1419 } 1420 1421 us = us == 0 ? 6 : closest_timer(&adap->sge, us); 1422 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); 1423 return 0; 1424 } 1425 1426 static int cxgb_set_features(struct net_device *dev, netdev_features_t features) 1427 { 1428 const struct port_info *pi = netdev_priv(dev); 1429 netdev_features_t changed = dev->features ^ features; 1430 int err; 1431 1432 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) 1433 return 0; 1434 1435 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, 1436 -1, -1, -1, 1437 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); 1438 if (unlikely(err)) 1439 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; 1440 return err; 1441 } 1442 1443 static int setup_debugfs(struct adapter *adap) 1444 { 1445 if (IS_ERR_OR_NULL(adap->debugfs_root)) 1446 return -1; 1447 1448 #ifdef CONFIG_DEBUG_FS 1449 t4_setup_debugfs(adap); 1450 #endif 1451 return 0; 1452 } 1453 1454 /* 1455 * upper-layer driver support 1456 */ 1457 1458 /* 1459 * Allocate an active-open TID and set it to the supplied value. 1460 */ 1461 int cxgb4_alloc_atid(struct tid_info *t, void *data) 1462 { 1463 int atid = -1; 1464 1465 spin_lock_bh(&t->atid_lock); 1466 if (t->afree) { 1467 union aopen_entry *p = t->afree; 1468 1469 atid = (p - t->atid_tab) + t->atid_base; 1470 t->afree = p->next; 1471 p->data = data; 1472 t->atids_in_use++; 1473 } 1474 spin_unlock_bh(&t->atid_lock); 1475 return atid; 1476 } 1477 EXPORT_SYMBOL(cxgb4_alloc_atid); 1478 1479 /* 1480 * Release an active-open TID. 1481 */ 1482 void cxgb4_free_atid(struct tid_info *t, unsigned int atid) 1483 { 1484 union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; 1485 1486 spin_lock_bh(&t->atid_lock); 1487 p->next = t->afree; 1488 t->afree = p; 1489 t->atids_in_use--; 1490 spin_unlock_bh(&t->atid_lock); 1491 } 1492 EXPORT_SYMBOL(cxgb4_free_atid); 1493 1494 /* 1495 * Allocate a server TID and set it to the supplied value. 1496 */ 1497 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) 1498 { 1499 int stid; 1500 1501 spin_lock_bh(&t->stid_lock); 1502 if (family == PF_INET) { 1503 stid = find_first_zero_bit(t->stid_bmap, t->nstids); 1504 if (stid < t->nstids) 1505 __set_bit(stid, t->stid_bmap); 1506 else 1507 stid = -1; 1508 } else { 1509 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2); 1510 if (stid < 0) 1511 stid = -1; 1512 } 1513 if (stid >= 0) { 1514 t->stid_tab[stid].data = data; 1515 stid += t->stid_base; 1516 /* IPv6 requires max of 520 bits or 16 cells in TCAM 1517 * This is equivalent to 4 TIDs. With CLIP enabled it 1518 * needs 2 TIDs. 1519 */ 1520 if (family == PF_INET) 1521 t->stids_in_use++; 1522 else 1523 t->stids_in_use += 4; 1524 } 1525 spin_unlock_bh(&t->stid_lock); 1526 return stid; 1527 } 1528 EXPORT_SYMBOL(cxgb4_alloc_stid); 1529 1530 /* Allocate a server filter TID and set it to the supplied value. 1531 */ 1532 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) 1533 { 1534 int stid; 1535 1536 spin_lock_bh(&t->stid_lock); 1537 if (family == PF_INET) { 1538 stid = find_next_zero_bit(t->stid_bmap, 1539 t->nstids + t->nsftids, t->nstids); 1540 if (stid < (t->nstids + t->nsftids)) 1541 __set_bit(stid, t->stid_bmap); 1542 else 1543 stid = -1; 1544 } else { 1545 stid = -1; 1546 } 1547 if (stid >= 0) { 1548 t->stid_tab[stid].data = data; 1549 stid -= t->nstids; 1550 stid += t->sftid_base; 1551 t->stids_in_use++; 1552 } 1553 spin_unlock_bh(&t->stid_lock); 1554 return stid; 1555 } 1556 EXPORT_SYMBOL(cxgb4_alloc_sftid); 1557 1558 /* Release a server TID. 1559 */ 1560 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) 1561 { 1562 /* Is it a server filter TID? */ 1563 if (t->nsftids && (stid >= t->sftid_base)) { 1564 stid -= t->sftid_base; 1565 stid += t->nstids; 1566 } else { 1567 stid -= t->stid_base; 1568 } 1569 1570 spin_lock_bh(&t->stid_lock); 1571 if (family == PF_INET) 1572 __clear_bit(stid, t->stid_bmap); 1573 else 1574 bitmap_release_region(t->stid_bmap, stid, 2); 1575 t->stid_tab[stid].data = NULL; 1576 if (family == PF_INET) 1577 t->stids_in_use--; 1578 else 1579 t->stids_in_use -= 4; 1580 spin_unlock_bh(&t->stid_lock); 1581 } 1582 EXPORT_SYMBOL(cxgb4_free_stid); 1583 1584 /* 1585 * Populate a TID_RELEASE WR. Caller must properly size the skb. 1586 */ 1587 static void mk_tid_release(struct sk_buff *skb, unsigned int chan, 1588 unsigned int tid) 1589 { 1590 struct cpl_tid_release *req; 1591 1592 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); 1593 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req)); 1594 INIT_TP_WR(req, tid); 1595 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); 1596 } 1597 1598 /* 1599 * Queue a TID release request and if necessary schedule a work queue to 1600 * process it. 1601 */ 1602 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, 1603 unsigned int tid) 1604 { 1605 void **p = &t->tid_tab[tid]; 1606 struct adapter *adap = container_of(t, struct adapter, tids); 1607 1608 spin_lock_bh(&adap->tid_release_lock); 1609 *p = adap->tid_release_head; 1610 /* Low 2 bits encode the Tx channel number */ 1611 adap->tid_release_head = (void **)((uintptr_t)p | chan); 1612 if (!adap->tid_release_task_busy) { 1613 adap->tid_release_task_busy = true; 1614 queue_work(adap->workq, &adap->tid_release_task); 1615 } 1616 spin_unlock_bh(&adap->tid_release_lock); 1617 } 1618 1619 /* 1620 * Process the list of pending TID release requests. 1621 */ 1622 static void process_tid_release_list(struct work_struct *work) 1623 { 1624 struct sk_buff *skb; 1625 struct adapter *adap; 1626 1627 adap = container_of(work, struct adapter, tid_release_task); 1628 1629 spin_lock_bh(&adap->tid_release_lock); 1630 while (adap->tid_release_head) { 1631 void **p = adap->tid_release_head; 1632 unsigned int chan = (uintptr_t)p & 3; 1633 p = (void *)p - chan; 1634 1635 adap->tid_release_head = *p; 1636 *p = NULL; 1637 spin_unlock_bh(&adap->tid_release_lock); 1638 1639 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), 1640 GFP_KERNEL))) 1641 schedule_timeout_uninterruptible(1); 1642 1643 mk_tid_release(skb, chan, p - adap->tids.tid_tab); 1644 t4_ofld_send(adap, skb); 1645 spin_lock_bh(&adap->tid_release_lock); 1646 } 1647 adap->tid_release_task_busy = false; 1648 spin_unlock_bh(&adap->tid_release_lock); 1649 } 1650 1651 /* 1652 * Release a TID and inform HW. If we are unable to allocate the release 1653 * message we defer to a work queue. 1654 */ 1655 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid) 1656 { 1657 void *old; 1658 struct sk_buff *skb; 1659 struct adapter *adap = container_of(t, struct adapter, tids); 1660 1661 old = t->tid_tab[tid]; 1662 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); 1663 if (likely(skb)) { 1664 t->tid_tab[tid] = NULL; 1665 mk_tid_release(skb, chan, tid); 1666 t4_ofld_send(adap, skb); 1667 } else 1668 cxgb4_queue_tid_release(t, chan, tid); 1669 if (old) 1670 atomic_dec(&t->tids_in_use); 1671 } 1672 EXPORT_SYMBOL(cxgb4_remove_tid); 1673 1674 /* 1675 * Allocate and initialize the TID tables. Returns 0 on success. 1676 */ 1677 static int tid_init(struct tid_info *t) 1678 { 1679 size_t size; 1680 unsigned int stid_bmap_size; 1681 unsigned int natids = t->natids; 1682 struct adapter *adap = container_of(t, struct adapter, tids); 1683 1684 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); 1685 size = t->ntids * sizeof(*t->tid_tab) + 1686 natids * sizeof(*t->atid_tab) + 1687 t->nstids * sizeof(*t->stid_tab) + 1688 t->nsftids * sizeof(*t->stid_tab) + 1689 stid_bmap_size * sizeof(long) + 1690 t->nftids * sizeof(*t->ftid_tab) + 1691 t->nsftids * sizeof(*t->ftid_tab); 1692 1693 t->tid_tab = t4_alloc_mem(size); 1694 if (!t->tid_tab) 1695 return -ENOMEM; 1696 1697 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 1698 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; 1699 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; 1700 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; 1701 spin_lock_init(&t->stid_lock); 1702 spin_lock_init(&t->atid_lock); 1703 1704 t->stids_in_use = 0; 1705 t->afree = NULL; 1706 t->atids_in_use = 0; 1707 atomic_set(&t->tids_in_use, 0); 1708 1709 /* Setup the free list for atid_tab and clear the stid bitmap. */ 1710 if (natids) { 1711 while (--natids) 1712 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 1713 t->afree = t->atid_tab; 1714 } 1715 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1716 /* Reserve stid 0 for T4/T5 adapters */ 1717 if (!t->stid_base && 1718 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)) 1719 __set_bit(0, t->stid_bmap); 1720 1721 return 0; 1722 } 1723 1724 /** 1725 * cxgb4_create_server - create an IP server 1726 * @dev: the device 1727 * @stid: the server TID 1728 * @sip: local IP address to bind server to 1729 * @sport: the server's TCP port 1730 * @queue: queue to direct messages from this server to 1731 * 1732 * Create an IP server for the given port and address. 1733 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1734 */ 1735 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 1736 __be32 sip, __be16 sport, __be16 vlan, 1737 unsigned int queue) 1738 { 1739 unsigned int chan; 1740 struct sk_buff *skb; 1741 struct adapter *adap; 1742 struct cpl_pass_open_req *req; 1743 int ret; 1744 1745 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1746 if (!skb) 1747 return -ENOMEM; 1748 1749 adap = netdev2adap(dev); 1750 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req)); 1751 INIT_TP_WR(req, 0); 1752 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); 1753 req->local_port = sport; 1754 req->peer_port = htons(0); 1755 req->local_ip = sip; 1756 req->peer_ip = htonl(0); 1757 chan = rxq_to_chan(&adap->sge, queue); 1758 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1759 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1760 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1761 ret = t4_mgmt_tx(adap, skb); 1762 return net_xmit_eval(ret); 1763 } 1764 EXPORT_SYMBOL(cxgb4_create_server); 1765 1766 /* cxgb4_create_server6 - create an IPv6 server 1767 * @dev: the device 1768 * @stid: the server TID 1769 * @sip: local IPv6 address to bind server to 1770 * @sport: the server's TCP port 1771 * @queue: queue to direct messages from this server to 1772 * 1773 * Create an IPv6 server for the given port and address. 1774 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1775 */ 1776 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 1777 const struct in6_addr *sip, __be16 sport, 1778 unsigned int queue) 1779 { 1780 unsigned int chan; 1781 struct sk_buff *skb; 1782 struct adapter *adap; 1783 struct cpl_pass_open_req6 *req; 1784 int ret; 1785 1786 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1787 if (!skb) 1788 return -ENOMEM; 1789 1790 adap = netdev2adap(dev); 1791 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req)); 1792 INIT_TP_WR(req, 0); 1793 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); 1794 req->local_port = sport; 1795 req->peer_port = htons(0); 1796 req->local_ip_hi = *(__be64 *)(sip->s6_addr); 1797 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); 1798 req->peer_ip_hi = cpu_to_be64(0); 1799 req->peer_ip_lo = cpu_to_be64(0); 1800 chan = rxq_to_chan(&adap->sge, queue); 1801 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1802 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1803 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1804 ret = t4_mgmt_tx(adap, skb); 1805 return net_xmit_eval(ret); 1806 } 1807 EXPORT_SYMBOL(cxgb4_create_server6); 1808 1809 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 1810 unsigned int queue, bool ipv6) 1811 { 1812 struct sk_buff *skb; 1813 struct adapter *adap; 1814 struct cpl_close_listsvr_req *req; 1815 int ret; 1816 1817 adap = netdev2adap(dev); 1818 1819 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1820 if (!skb) 1821 return -ENOMEM; 1822 1823 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req)); 1824 INIT_TP_WR(req, 0); 1825 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); 1826 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : 1827 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); 1828 ret = t4_mgmt_tx(adap, skb); 1829 return net_xmit_eval(ret); 1830 } 1831 EXPORT_SYMBOL(cxgb4_remove_server); 1832 1833 /** 1834 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU 1835 * @mtus: the HW MTU table 1836 * @mtu: the target MTU 1837 * @idx: index of selected entry in the MTU table 1838 * 1839 * Returns the index and the value in the HW MTU table that is closest to 1840 * but does not exceed @mtu, unless @mtu is smaller than any value in the 1841 * table, in which case that smallest available value is selected. 1842 */ 1843 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 1844 unsigned int *idx) 1845 { 1846 unsigned int i = 0; 1847 1848 while (i < NMTUS - 1 && mtus[i + 1] <= mtu) 1849 ++i; 1850 if (idx) 1851 *idx = i; 1852 return mtus[i]; 1853 } 1854 EXPORT_SYMBOL(cxgb4_best_mtu); 1855 1856 /** 1857 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned 1858 * @mtus: the HW MTU table 1859 * @header_size: Header Size 1860 * @data_size_max: maximum Data Segment Size 1861 * @data_size_align: desired Data Segment Size Alignment (2^N) 1862 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) 1863 * 1864 * Similar to cxgb4_best_mtu() but instead of searching the Hardware 1865 * MTU Table based solely on a Maximum MTU parameter, we break that 1866 * parameter up into a Header Size and Maximum Data Segment Size, and 1867 * provide a desired Data Segment Size Alignment. If we find an MTU in 1868 * the Hardware MTU Table which will result in a Data Segment Size with 1869 * the requested alignment _and_ that MTU isn't "too far" from the 1870 * closest MTU, then we'll return that rather than the closest MTU. 1871 */ 1872 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 1873 unsigned short header_size, 1874 unsigned short data_size_max, 1875 unsigned short data_size_align, 1876 unsigned int *mtu_idxp) 1877 { 1878 unsigned short max_mtu = header_size + data_size_max; 1879 unsigned short data_size_align_mask = data_size_align - 1; 1880 int mtu_idx, aligned_mtu_idx; 1881 1882 /* Scan the MTU Table till we find an MTU which is larger than our 1883 * Maximum MTU or we reach the end of the table. Along the way, 1884 * record the last MTU found, if any, which will result in a Data 1885 * Segment Length matching the requested alignment. 1886 */ 1887 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { 1888 unsigned short data_size = mtus[mtu_idx] - header_size; 1889 1890 /* If this MTU minus the Header Size would result in a 1891 * Data Segment Size of the desired alignment, remember it. 1892 */ 1893 if ((data_size & data_size_align_mask) == 0) 1894 aligned_mtu_idx = mtu_idx; 1895 1896 /* If we're not at the end of the Hardware MTU Table and the 1897 * next element is larger than our Maximum MTU, drop out of 1898 * the loop. 1899 */ 1900 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) 1901 break; 1902 } 1903 1904 /* If we fell out of the loop because we ran to the end of the table, 1905 * then we just have to use the last [largest] entry. 1906 */ 1907 if (mtu_idx == NMTUS) 1908 mtu_idx--; 1909 1910 /* If we found an MTU which resulted in the requested Data Segment 1911 * Length alignment and that's "not far" from the largest MTU which is 1912 * less than or equal to the maximum MTU, then use that. 1913 */ 1914 if (aligned_mtu_idx >= 0 && 1915 mtu_idx - aligned_mtu_idx <= 1) 1916 mtu_idx = aligned_mtu_idx; 1917 1918 /* If the caller has passed in an MTU Index pointer, pass the 1919 * MTU Index back. Return the MTU value. 1920 */ 1921 if (mtu_idxp) 1922 *mtu_idxp = mtu_idx; 1923 return mtus[mtu_idx]; 1924 } 1925 EXPORT_SYMBOL(cxgb4_best_aligned_mtu); 1926 1927 /** 1928 * cxgb4_port_chan - get the HW channel of a port 1929 * @dev: the net device for the port 1930 * 1931 * Return the HW Tx channel of the given port. 1932 */ 1933 unsigned int cxgb4_port_chan(const struct net_device *dev) 1934 { 1935 return netdev2pinfo(dev)->tx_chan; 1936 } 1937 EXPORT_SYMBOL(cxgb4_port_chan); 1938 1939 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 1940 { 1941 struct adapter *adap = netdev2adap(dev); 1942 u32 v1, v2, lp_count, hp_count; 1943 1944 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1945 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1946 if (is_t4(adap->params.chip)) { 1947 lp_count = LP_COUNT_G(v1); 1948 hp_count = HP_COUNT_G(v1); 1949 } else { 1950 lp_count = LP_COUNT_T5_G(v1); 1951 hp_count = HP_COUNT_T5_G(v2); 1952 } 1953 return lpfifo ? lp_count : hp_count; 1954 } 1955 EXPORT_SYMBOL(cxgb4_dbfifo_count); 1956 1957 /** 1958 * cxgb4_port_viid - get the VI id of a port 1959 * @dev: the net device for the port 1960 * 1961 * Return the VI id of the given port. 1962 */ 1963 unsigned int cxgb4_port_viid(const struct net_device *dev) 1964 { 1965 return netdev2pinfo(dev)->viid; 1966 } 1967 EXPORT_SYMBOL(cxgb4_port_viid); 1968 1969 /** 1970 * cxgb4_port_idx - get the index of a port 1971 * @dev: the net device for the port 1972 * 1973 * Return the index of the given port. 1974 */ 1975 unsigned int cxgb4_port_idx(const struct net_device *dev) 1976 { 1977 return netdev2pinfo(dev)->port_id; 1978 } 1979 EXPORT_SYMBOL(cxgb4_port_idx); 1980 1981 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 1982 struct tp_tcp_stats *v6) 1983 { 1984 struct adapter *adap = pci_get_drvdata(pdev); 1985 1986 spin_lock(&adap->stats_lock); 1987 t4_tp_get_tcp_stats(adap, v4, v6); 1988 spin_unlock(&adap->stats_lock); 1989 } 1990 EXPORT_SYMBOL(cxgb4_get_tcp_stats); 1991 1992 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 1993 const unsigned int *pgsz_order) 1994 { 1995 struct adapter *adap = netdev2adap(dev); 1996 1997 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); 1998 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | 1999 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | 2000 HPZ3_V(pgsz_order[3])); 2001 } 2002 EXPORT_SYMBOL(cxgb4_iscsi_init); 2003 2004 int cxgb4_flush_eq_cache(struct net_device *dev) 2005 { 2006 struct adapter *adap = netdev2adap(dev); 2007 2008 return t4_sge_ctxt_flush(adap, adap->mbox); 2009 } 2010 EXPORT_SYMBOL(cxgb4_flush_eq_cache); 2011 2012 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 2013 { 2014 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; 2015 __be64 indices; 2016 int ret; 2017 2018 spin_lock(&adap->win0_lock); 2019 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, 2020 sizeof(indices), (__be32 *)&indices, 2021 T4_MEMORY_READ); 2022 spin_unlock(&adap->win0_lock); 2023 if (!ret) { 2024 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; 2025 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; 2026 } 2027 return ret; 2028 } 2029 2030 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 2031 u16 size) 2032 { 2033 struct adapter *adap = netdev2adap(dev); 2034 u16 hw_pidx, hw_cidx; 2035 int ret; 2036 2037 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); 2038 if (ret) 2039 goto out; 2040 2041 if (pidx != hw_pidx) { 2042 u16 delta; 2043 u32 val; 2044 2045 if (pidx >= hw_pidx) 2046 delta = pidx - hw_pidx; 2047 else 2048 delta = size - hw_pidx + pidx; 2049 2050 if (is_t4(adap->params.chip)) 2051 val = PIDX_V(delta); 2052 else 2053 val = PIDX_T5_V(delta); 2054 wmb(); 2055 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2056 QID_V(qid) | val); 2057 } 2058 out: 2059 return ret; 2060 } 2061 EXPORT_SYMBOL(cxgb4_sync_txq_pidx); 2062 2063 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) 2064 { 2065 struct adapter *adap; 2066 u32 offset, memtype, memaddr; 2067 u32 edc0_size, edc1_size, mc0_size, mc1_size, size; 2068 u32 edc0_end, edc1_end, mc0_end, mc1_end; 2069 int ret; 2070 2071 adap = netdev2adap(dev); 2072 2073 offset = ((stag >> 8) * 32) + adap->vres.stag.start; 2074 2075 /* Figure out where the offset lands in the Memory Type/Address scheme. 2076 * This code assumes that the memory is laid out starting at offset 0 2077 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 2078 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have 2079 * MC0, and some have both MC0 and MC1. 2080 */ 2081 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 2082 edc0_size = EDRAM0_SIZE_G(size) << 20; 2083 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 2084 edc1_size = EDRAM1_SIZE_G(size) << 20; 2085 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 2086 mc0_size = EXT_MEM0_SIZE_G(size) << 20; 2087 2088 edc0_end = edc0_size; 2089 edc1_end = edc0_end + edc1_size; 2090 mc0_end = edc1_end + mc0_size; 2091 2092 if (offset < edc0_end) { 2093 memtype = MEM_EDC0; 2094 memaddr = offset; 2095 } else if (offset < edc1_end) { 2096 memtype = MEM_EDC1; 2097 memaddr = offset - edc0_end; 2098 } else { 2099 if (offset < mc0_end) { 2100 memtype = MEM_MC0; 2101 memaddr = offset - edc1_end; 2102 } else if (is_t5(adap->params.chip)) { 2103 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 2104 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 2105 mc1_end = mc0_end + mc1_size; 2106 if (offset < mc1_end) { 2107 memtype = MEM_MC1; 2108 memaddr = offset - mc0_end; 2109 } else { 2110 /* offset beyond the end of any memory */ 2111 goto err; 2112 } 2113 } else { 2114 /* T4/T6 only has a single memory channel */ 2115 goto err; 2116 } 2117 } 2118 2119 spin_lock(&adap->win0_lock); 2120 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); 2121 spin_unlock(&adap->win0_lock); 2122 return ret; 2123 2124 err: 2125 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", 2126 stag, offset); 2127 return -EINVAL; 2128 } 2129 EXPORT_SYMBOL(cxgb4_read_tpte); 2130 2131 u64 cxgb4_read_sge_timestamp(struct net_device *dev) 2132 { 2133 u32 hi, lo; 2134 struct adapter *adap; 2135 2136 adap = netdev2adap(dev); 2137 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); 2138 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); 2139 2140 return ((u64)hi << 32) | (u64)lo; 2141 } 2142 EXPORT_SYMBOL(cxgb4_read_sge_timestamp); 2143 2144 int cxgb4_bar2_sge_qregs(struct net_device *dev, 2145 unsigned int qid, 2146 enum cxgb4_bar2_qtype qtype, 2147 int user, 2148 u64 *pbar2_qoffset, 2149 unsigned int *pbar2_qid) 2150 { 2151 return t4_bar2_sge_qregs(netdev2adap(dev), 2152 qid, 2153 (qtype == CXGB4_BAR2_QTYPE_EGRESS 2154 ? T4_BAR2_QTYPE_EGRESS 2155 : T4_BAR2_QTYPE_INGRESS), 2156 user, 2157 pbar2_qoffset, 2158 pbar2_qid); 2159 } 2160 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); 2161 2162 static struct pci_driver cxgb4_driver; 2163 2164 static void check_neigh_update(struct neighbour *neigh) 2165 { 2166 const struct device *parent; 2167 const struct net_device *netdev = neigh->dev; 2168 2169 if (netdev->priv_flags & IFF_802_1Q_VLAN) 2170 netdev = vlan_dev_real_dev(netdev); 2171 parent = netdev->dev.parent; 2172 if (parent && parent->driver == &cxgb4_driver.driver) 2173 t4_l2t_update(dev_get_drvdata(parent), neigh); 2174 } 2175 2176 static int netevent_cb(struct notifier_block *nb, unsigned long event, 2177 void *data) 2178 { 2179 switch (event) { 2180 case NETEVENT_NEIGH_UPDATE: 2181 check_neigh_update(data); 2182 break; 2183 case NETEVENT_REDIRECT: 2184 default: 2185 break; 2186 } 2187 return 0; 2188 } 2189 2190 static bool netevent_registered; 2191 static struct notifier_block cxgb4_netevent_nb = { 2192 .notifier_call = netevent_cb 2193 }; 2194 2195 static void drain_db_fifo(struct adapter *adap, int usecs) 2196 { 2197 u32 v1, v2, lp_count, hp_count; 2198 2199 do { 2200 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 2201 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 2202 if (is_t4(adap->params.chip)) { 2203 lp_count = LP_COUNT_G(v1); 2204 hp_count = HP_COUNT_G(v1); 2205 } else { 2206 lp_count = LP_COUNT_T5_G(v1); 2207 hp_count = HP_COUNT_T5_G(v2); 2208 } 2209 2210 if (lp_count == 0 && hp_count == 0) 2211 break; 2212 set_current_state(TASK_UNINTERRUPTIBLE); 2213 schedule_timeout(usecs_to_jiffies(usecs)); 2214 } while (1); 2215 } 2216 2217 static void disable_txq_db(struct sge_txq *q) 2218 { 2219 unsigned long flags; 2220 2221 spin_lock_irqsave(&q->db_lock, flags); 2222 q->db_disabled = 1; 2223 spin_unlock_irqrestore(&q->db_lock, flags); 2224 } 2225 2226 static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 2227 { 2228 spin_lock_irq(&q->db_lock); 2229 if (q->db_pidx_inc) { 2230 /* Make sure that all writes to the TX descriptors 2231 * are committed before we tell HW about them. 2232 */ 2233 wmb(); 2234 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2235 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); 2236 q->db_pidx_inc = 0; 2237 } 2238 q->db_disabled = 0; 2239 spin_unlock_irq(&q->db_lock); 2240 } 2241 2242 static void disable_dbs(struct adapter *adap) 2243 { 2244 int i; 2245 2246 for_each_ethrxq(&adap->sge, i) 2247 disable_txq_db(&adap->sge.ethtxq[i].q); 2248 for_each_ofldrxq(&adap->sge, i) 2249 disable_txq_db(&adap->sge.ofldtxq[i].q); 2250 for_each_port(adap, i) 2251 disable_txq_db(&adap->sge.ctrlq[i].q); 2252 } 2253 2254 static void enable_dbs(struct adapter *adap) 2255 { 2256 int i; 2257 2258 for_each_ethrxq(&adap->sge, i) 2259 enable_txq_db(adap, &adap->sge.ethtxq[i].q); 2260 for_each_ofldrxq(&adap->sge, i) 2261 enable_txq_db(adap, &adap->sge.ofldtxq[i].q); 2262 for_each_port(adap, i) 2263 enable_txq_db(adap, &adap->sge.ctrlq[i].q); 2264 } 2265 2266 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) 2267 { 2268 if (adap->uld_handle[CXGB4_ULD_RDMA]) 2269 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA], 2270 cmd); 2271 } 2272 2273 static void process_db_full(struct work_struct *work) 2274 { 2275 struct adapter *adap; 2276 2277 adap = container_of(work, struct adapter, db_full_task); 2278 2279 drain_db_fifo(adap, dbfifo_drain_delay); 2280 enable_dbs(adap); 2281 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2282 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2283 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2284 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 2285 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 2286 else 2287 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2288 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); 2289 } 2290 2291 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 2292 { 2293 u16 hw_pidx, hw_cidx; 2294 int ret; 2295 2296 spin_lock_irq(&q->db_lock); 2297 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); 2298 if (ret) 2299 goto out; 2300 if (q->db_pidx != hw_pidx) { 2301 u16 delta; 2302 u32 val; 2303 2304 if (q->db_pidx >= hw_pidx) 2305 delta = q->db_pidx - hw_pidx; 2306 else 2307 delta = q->size - hw_pidx + q->db_pidx; 2308 2309 if (is_t4(adap->params.chip)) 2310 val = PIDX_V(delta); 2311 else 2312 val = PIDX_T5_V(delta); 2313 wmb(); 2314 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2315 QID_V(q->cntxt_id) | val); 2316 } 2317 out: 2318 q->db_disabled = 0; 2319 q->db_pidx_inc = 0; 2320 spin_unlock_irq(&q->db_lock); 2321 if (ret) 2322 CH_WARN(adap, "DB drop recovery failed.\n"); 2323 } 2324 static void recover_all_queues(struct adapter *adap) 2325 { 2326 int i; 2327 2328 for_each_ethrxq(&adap->sge, i) 2329 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); 2330 for_each_ofldrxq(&adap->sge, i) 2331 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q); 2332 for_each_port(adap, i) 2333 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); 2334 } 2335 2336 static void process_db_drop(struct work_struct *work) 2337 { 2338 struct adapter *adap; 2339 2340 adap = container_of(work, struct adapter, db_drop_task); 2341 2342 if (is_t4(adap->params.chip)) { 2343 drain_db_fifo(adap, dbfifo_drain_delay); 2344 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); 2345 drain_db_fifo(adap, dbfifo_drain_delay); 2346 recover_all_queues(adap); 2347 drain_db_fifo(adap, dbfifo_drain_delay); 2348 enable_dbs(adap); 2349 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2350 } else if (is_t5(adap->params.chip)) { 2351 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2352 u16 qid = (dropped_db >> 15) & 0x1ffff; 2353 u16 pidx_inc = dropped_db & 0x1fff; 2354 u64 bar2_qoffset; 2355 unsigned int bar2_qid; 2356 int ret; 2357 2358 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, 2359 0, &bar2_qoffset, &bar2_qid); 2360 if (ret) 2361 dev_err(adap->pdev_dev, "doorbell drop recovery: " 2362 "qid=%d, pidx_inc=%d\n", qid, pidx_inc); 2363 else 2364 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), 2365 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); 2366 2367 /* Re-enable BAR2 WC */ 2368 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2369 } 2370 2371 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2372 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2373 } 2374 2375 void t4_db_full(struct adapter *adap) 2376 { 2377 if (is_t4(adap->params.chip)) { 2378 disable_dbs(adap); 2379 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2380 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2381 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); 2382 queue_work(adap->workq, &adap->db_full_task); 2383 } 2384 } 2385 2386 void t4_db_dropped(struct adapter *adap) 2387 { 2388 if (is_t4(adap->params.chip)) { 2389 disable_dbs(adap); 2390 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2391 } 2392 queue_work(adap->workq, &adap->db_drop_task); 2393 } 2394 2395 static void uld_attach(struct adapter *adap, unsigned int uld) 2396 { 2397 void *handle; 2398 struct cxgb4_lld_info lli; 2399 unsigned short i; 2400 2401 lli.pdev = adap->pdev; 2402 lli.pf = adap->pf; 2403 lli.l2t = adap->l2t; 2404 lli.tids = &adap->tids; 2405 lli.ports = adap->port; 2406 lli.vr = &adap->vres; 2407 lli.mtus = adap->params.mtus; 2408 if (uld == CXGB4_ULD_RDMA) { 2409 lli.rxq_ids = adap->sge.rdma_rxq; 2410 lli.ciq_ids = adap->sge.rdma_ciq; 2411 lli.nrxq = adap->sge.rdmaqs; 2412 lli.nciq = adap->sge.rdmaciqs; 2413 } else if (uld == CXGB4_ULD_ISCSI) { 2414 lli.rxq_ids = adap->sge.ofld_rxq; 2415 lli.nrxq = adap->sge.ofldqsets; 2416 } 2417 lli.ntxq = adap->sge.ofldqsets; 2418 lli.nchan = adap->params.nports; 2419 lli.nports = adap->params.nports; 2420 lli.wr_cred = adap->params.ofldq_wr_cred; 2421 lli.adapter_type = adap->params.chip; 2422 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A)); 2423 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk; 2424 lli.udb_density = 1 << adap->params.sge.eq_qpp; 2425 lli.ucq_density = 1 << adap->params.sge.iq_qpp; 2426 lli.filt_mode = adap->params.tp.vlan_pri_map; 2427 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */ 2428 for (i = 0; i < NCHAN; i++) 2429 lli.tx_modq[i] = i; 2430 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A); 2431 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A); 2432 lli.fw_vers = adap->params.fw_vers; 2433 lli.dbfifo_int_thresh = dbfifo_int_thresh; 2434 lli.sge_ingpadboundary = adap->sge.fl_align; 2435 lli.sge_egrstatuspagesize = adap->sge.stat_len; 2436 lli.sge_pktshift = adap->sge.pktshift; 2437 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN; 2438 lli.max_ordird_qp = adap->params.max_ordird_qp; 2439 lli.max_ird_adapter = adap->params.max_ird_adapter; 2440 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl; 2441 lli.nodeid = dev_to_node(adap->pdev_dev); 2442 2443 handle = ulds[uld].add(&lli); 2444 if (IS_ERR(handle)) { 2445 dev_warn(adap->pdev_dev, 2446 "could not attach to the %s driver, error %ld\n", 2447 uld_str[uld], PTR_ERR(handle)); 2448 return; 2449 } 2450 2451 adap->uld_handle[uld] = handle; 2452 2453 if (!netevent_registered) { 2454 register_netevent_notifier(&cxgb4_netevent_nb); 2455 netevent_registered = true; 2456 } 2457 2458 if (adap->flags & FULL_INIT_DONE) 2459 ulds[uld].state_change(handle, CXGB4_STATE_UP); 2460 } 2461 2462 static void attach_ulds(struct adapter *adap) 2463 { 2464 unsigned int i; 2465 2466 spin_lock(&adap_rcu_lock); 2467 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list); 2468 spin_unlock(&adap_rcu_lock); 2469 2470 mutex_lock(&uld_mutex); 2471 list_add_tail(&adap->list_node, &adapter_list); 2472 for (i = 0; i < CXGB4_ULD_MAX; i++) 2473 if (ulds[i].add) 2474 uld_attach(adap, i); 2475 mutex_unlock(&uld_mutex); 2476 } 2477 2478 static void detach_ulds(struct adapter *adap) 2479 { 2480 unsigned int i; 2481 2482 mutex_lock(&uld_mutex); 2483 list_del(&adap->list_node); 2484 for (i = 0; i < CXGB4_ULD_MAX; i++) 2485 if (adap->uld_handle[i]) { 2486 ulds[i].state_change(adap->uld_handle[i], 2487 CXGB4_STATE_DETACH); 2488 adap->uld_handle[i] = NULL; 2489 } 2490 if (netevent_registered && list_empty(&adapter_list)) { 2491 unregister_netevent_notifier(&cxgb4_netevent_nb); 2492 netevent_registered = false; 2493 } 2494 mutex_unlock(&uld_mutex); 2495 2496 spin_lock(&adap_rcu_lock); 2497 list_del_rcu(&adap->rcu_node); 2498 spin_unlock(&adap_rcu_lock); 2499 } 2500 2501 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) 2502 { 2503 unsigned int i; 2504 2505 mutex_lock(&uld_mutex); 2506 for (i = 0; i < CXGB4_ULD_MAX; i++) 2507 if (adap->uld_handle[i]) 2508 ulds[i].state_change(adap->uld_handle[i], new_state); 2509 mutex_unlock(&uld_mutex); 2510 } 2511 2512 /** 2513 * cxgb4_register_uld - register an upper-layer driver 2514 * @type: the ULD type 2515 * @p: the ULD methods 2516 * 2517 * Registers an upper-layer driver with this driver and notifies the ULD 2518 * about any presently available devices that support its type. Returns 2519 * %-EBUSY if a ULD of the same type is already registered. 2520 */ 2521 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p) 2522 { 2523 int ret = 0; 2524 struct adapter *adap; 2525 2526 if (type >= CXGB4_ULD_MAX) 2527 return -EINVAL; 2528 mutex_lock(&uld_mutex); 2529 if (ulds[type].add) { 2530 ret = -EBUSY; 2531 goto out; 2532 } 2533 ulds[type] = *p; 2534 list_for_each_entry(adap, &adapter_list, list_node) 2535 uld_attach(adap, type); 2536 out: mutex_unlock(&uld_mutex); 2537 return ret; 2538 } 2539 EXPORT_SYMBOL(cxgb4_register_uld); 2540 2541 /** 2542 * cxgb4_unregister_uld - unregister an upper-layer driver 2543 * @type: the ULD type 2544 * 2545 * Unregisters an existing upper-layer driver. 2546 */ 2547 int cxgb4_unregister_uld(enum cxgb4_uld type) 2548 { 2549 struct adapter *adap; 2550 2551 if (type >= CXGB4_ULD_MAX) 2552 return -EINVAL; 2553 mutex_lock(&uld_mutex); 2554 list_for_each_entry(adap, &adapter_list, list_node) 2555 adap->uld_handle[type] = NULL; 2556 ulds[type].add = NULL; 2557 mutex_unlock(&uld_mutex); 2558 return 0; 2559 } 2560 EXPORT_SYMBOL(cxgb4_unregister_uld); 2561 2562 #if IS_ENABLED(CONFIG_IPV6) 2563 static int cxgb4_inet6addr_handler(struct notifier_block *this, 2564 unsigned long event, void *data) 2565 { 2566 struct inet6_ifaddr *ifa = data; 2567 struct net_device *event_dev = ifa->idev->dev; 2568 const struct device *parent = NULL; 2569 #if IS_ENABLED(CONFIG_BONDING) 2570 struct adapter *adap; 2571 #endif 2572 if (event_dev->priv_flags & IFF_802_1Q_VLAN) 2573 event_dev = vlan_dev_real_dev(event_dev); 2574 #if IS_ENABLED(CONFIG_BONDING) 2575 if (event_dev->flags & IFF_MASTER) { 2576 list_for_each_entry(adap, &adapter_list, list_node) { 2577 switch (event) { 2578 case NETDEV_UP: 2579 cxgb4_clip_get(adap->port[0], 2580 (const u32 *)ifa, 1); 2581 break; 2582 case NETDEV_DOWN: 2583 cxgb4_clip_release(adap->port[0], 2584 (const u32 *)ifa, 1); 2585 break; 2586 default: 2587 break; 2588 } 2589 } 2590 return NOTIFY_OK; 2591 } 2592 #endif 2593 2594 if (event_dev) 2595 parent = event_dev->dev.parent; 2596 2597 if (parent && parent->driver == &cxgb4_driver.driver) { 2598 switch (event) { 2599 case NETDEV_UP: 2600 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); 2601 break; 2602 case NETDEV_DOWN: 2603 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); 2604 break; 2605 default: 2606 break; 2607 } 2608 } 2609 return NOTIFY_OK; 2610 } 2611 2612 static bool inet6addr_registered; 2613 static struct notifier_block cxgb4_inet6addr_notifier = { 2614 .notifier_call = cxgb4_inet6addr_handler 2615 }; 2616 2617 static void update_clip(const struct adapter *adap) 2618 { 2619 int i; 2620 struct net_device *dev; 2621 int ret; 2622 2623 rcu_read_lock(); 2624 2625 for (i = 0; i < MAX_NPORTS; i++) { 2626 dev = adap->port[i]; 2627 ret = 0; 2628 2629 if (dev) 2630 ret = cxgb4_update_root_dev_clip(dev); 2631 2632 if (ret < 0) 2633 break; 2634 } 2635 rcu_read_unlock(); 2636 } 2637 #endif /* IS_ENABLED(CONFIG_IPV6) */ 2638 2639 /** 2640 * cxgb_up - enable the adapter 2641 * @adap: adapter being enabled 2642 * 2643 * Called when the first port is enabled, this function performs the 2644 * actions necessary to make an adapter operational, such as completing 2645 * the initialization of HW modules, and enabling interrupts. 2646 * 2647 * Must be called with the rtnl lock held. 2648 */ 2649 static int cxgb_up(struct adapter *adap) 2650 { 2651 int err; 2652 2653 err = setup_sge_queues(adap); 2654 if (err) 2655 goto out; 2656 err = setup_rss(adap); 2657 if (err) 2658 goto freeq; 2659 2660 if (adap->flags & USING_MSIX) { 2661 name_msix_vecs(adap); 2662 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, 2663 adap->msix_info[0].desc, adap); 2664 if (err) 2665 goto irq_err; 2666 2667 err = request_msix_queue_irqs(adap); 2668 if (err) { 2669 free_irq(adap->msix_info[0].vec, adap); 2670 goto irq_err; 2671 } 2672 } else { 2673 err = request_irq(adap->pdev->irq, t4_intr_handler(adap), 2674 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, 2675 adap->port[0]->name, adap); 2676 if (err) 2677 goto irq_err; 2678 } 2679 enable_rx(adap); 2680 t4_sge_start(adap); 2681 t4_intr_enable(adap); 2682 adap->flags |= FULL_INIT_DONE; 2683 notify_ulds(adap, CXGB4_STATE_UP); 2684 #if IS_ENABLED(CONFIG_IPV6) 2685 update_clip(adap); 2686 #endif 2687 out: 2688 return err; 2689 irq_err: 2690 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); 2691 freeq: 2692 t4_free_sge_resources(adap); 2693 goto out; 2694 } 2695 2696 static void cxgb_down(struct adapter *adapter) 2697 { 2698 cancel_work_sync(&adapter->tid_release_task); 2699 cancel_work_sync(&adapter->db_full_task); 2700 cancel_work_sync(&adapter->db_drop_task); 2701 adapter->tid_release_task_busy = false; 2702 adapter->tid_release_head = NULL; 2703 2704 t4_sge_stop(adapter); 2705 t4_free_sge_resources(adapter); 2706 adapter->flags &= ~FULL_INIT_DONE; 2707 } 2708 2709 /* 2710 * net_device operations 2711 */ 2712 static int cxgb_open(struct net_device *dev) 2713 { 2714 int err; 2715 struct port_info *pi = netdev_priv(dev); 2716 struct adapter *adapter = pi->adapter; 2717 2718 netif_carrier_off(dev); 2719 2720 if (!(adapter->flags & FULL_INIT_DONE)) { 2721 err = cxgb_up(adapter); 2722 if (err < 0) 2723 return err; 2724 } 2725 2726 err = link_start(dev); 2727 if (!err) 2728 netif_tx_start_all_queues(dev); 2729 return err; 2730 } 2731 2732 static int cxgb_close(struct net_device *dev) 2733 { 2734 struct port_info *pi = netdev_priv(dev); 2735 struct adapter *adapter = pi->adapter; 2736 2737 netif_tx_stop_all_queues(dev); 2738 netif_carrier_off(dev); 2739 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false); 2740 } 2741 2742 /* Return an error number if the indicated filter isn't writable ... 2743 */ 2744 static int writable_filter(struct filter_entry *f) 2745 { 2746 if (f->locked) 2747 return -EPERM; 2748 if (f->pending) 2749 return -EBUSY; 2750 2751 return 0; 2752 } 2753 2754 /* Delete the filter at the specified index (if valid). The checks for all 2755 * the common problems with doing this like the filter being locked, currently 2756 * pending in another operation, etc. 2757 */ 2758 static int delete_filter(struct adapter *adapter, unsigned int fidx) 2759 { 2760 struct filter_entry *f; 2761 int ret; 2762 2763 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids) 2764 return -EINVAL; 2765 2766 f = &adapter->tids.ftid_tab[fidx]; 2767 ret = writable_filter(f); 2768 if (ret) 2769 return ret; 2770 if (f->valid) 2771 return del_filter_wr(adapter, fidx); 2772 2773 return 0; 2774 } 2775 2776 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 2777 __be32 sip, __be16 sport, __be16 vlan, 2778 unsigned int queue, unsigned char port, unsigned char mask) 2779 { 2780 int ret; 2781 struct filter_entry *f; 2782 struct adapter *adap; 2783 int i; 2784 u8 *val; 2785 2786 adap = netdev2adap(dev); 2787 2788 /* Adjust stid to correct filter index */ 2789 stid -= adap->tids.sftid_base; 2790 stid += adap->tids.nftids; 2791 2792 /* Check to make sure the filter requested is writable ... 2793 */ 2794 f = &adap->tids.ftid_tab[stid]; 2795 ret = writable_filter(f); 2796 if (ret) 2797 return ret; 2798 2799 /* Clear out any old resources being used by the filter before 2800 * we start constructing the new filter. 2801 */ 2802 if (f->valid) 2803 clear_filter(adap, f); 2804 2805 /* Clear out filter specifications */ 2806 memset(&f->fs, 0, sizeof(struct ch_filter_specification)); 2807 f->fs.val.lport = cpu_to_be16(sport); 2808 f->fs.mask.lport = ~0; 2809 val = (u8 *)&sip; 2810 if ((val[0] | val[1] | val[2] | val[3]) != 0) { 2811 for (i = 0; i < 4; i++) { 2812 f->fs.val.lip[i] = val[i]; 2813 f->fs.mask.lip[i] = ~0; 2814 } 2815 if (adap->params.tp.vlan_pri_map & PORT_F) { 2816 f->fs.val.iport = port; 2817 f->fs.mask.iport = mask; 2818 } 2819 } 2820 2821 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { 2822 f->fs.val.proto = IPPROTO_TCP; 2823 f->fs.mask.proto = ~0; 2824 } 2825 2826 f->fs.dirsteer = 1; 2827 f->fs.iq = queue; 2828 /* Mark filter as locked */ 2829 f->locked = 1; 2830 f->fs.rpttid = 1; 2831 2832 ret = set_filter_wr(adap, stid); 2833 if (ret) { 2834 clear_filter(adap, f); 2835 return ret; 2836 } 2837 2838 return 0; 2839 } 2840 EXPORT_SYMBOL(cxgb4_create_server_filter); 2841 2842 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 2843 unsigned int queue, bool ipv6) 2844 { 2845 int ret; 2846 struct filter_entry *f; 2847 struct adapter *adap; 2848 2849 adap = netdev2adap(dev); 2850 2851 /* Adjust stid to correct filter index */ 2852 stid -= adap->tids.sftid_base; 2853 stid += adap->tids.nftids; 2854 2855 f = &adap->tids.ftid_tab[stid]; 2856 /* Unlock the filter */ 2857 f->locked = 0; 2858 2859 ret = delete_filter(adap, stid); 2860 if (ret) 2861 return ret; 2862 2863 return 0; 2864 } 2865 EXPORT_SYMBOL(cxgb4_remove_server_filter); 2866 2867 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev, 2868 struct rtnl_link_stats64 *ns) 2869 { 2870 struct port_stats stats; 2871 struct port_info *p = netdev_priv(dev); 2872 struct adapter *adapter = p->adapter; 2873 2874 /* Block retrieving statistics during EEH error 2875 * recovery. Otherwise, the recovery might fail 2876 * and the PCI device will be removed permanently 2877 */ 2878 spin_lock(&adapter->stats_lock); 2879 if (!netif_device_present(dev)) { 2880 spin_unlock(&adapter->stats_lock); 2881 return ns; 2882 } 2883 t4_get_port_stats_offset(adapter, p->tx_chan, &stats, 2884 &p->stats_base); 2885 spin_unlock(&adapter->stats_lock); 2886 2887 ns->tx_bytes = stats.tx_octets; 2888 ns->tx_packets = stats.tx_frames; 2889 ns->rx_bytes = stats.rx_octets; 2890 ns->rx_packets = stats.rx_frames; 2891 ns->multicast = stats.rx_mcast_frames; 2892 2893 /* detailed rx_errors */ 2894 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + 2895 stats.rx_runt; 2896 ns->rx_over_errors = 0; 2897 ns->rx_crc_errors = stats.rx_fcs_err; 2898 ns->rx_frame_errors = stats.rx_symbol_err; 2899 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 + 2900 stats.rx_ovflow2 + stats.rx_ovflow3 + 2901 stats.rx_trunc0 + stats.rx_trunc1 + 2902 stats.rx_trunc2 + stats.rx_trunc3; 2903 ns->rx_missed_errors = 0; 2904 2905 /* detailed tx_errors */ 2906 ns->tx_aborted_errors = 0; 2907 ns->tx_carrier_errors = 0; 2908 ns->tx_fifo_errors = 0; 2909 ns->tx_heartbeat_errors = 0; 2910 ns->tx_window_errors = 0; 2911 2912 ns->tx_errors = stats.tx_error_frames; 2913 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + 2914 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; 2915 return ns; 2916 } 2917 2918 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 2919 { 2920 unsigned int mbox; 2921 int ret = 0, prtad, devad; 2922 struct port_info *pi = netdev_priv(dev); 2923 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; 2924 2925 switch (cmd) { 2926 case SIOCGMIIPHY: 2927 if (pi->mdio_addr < 0) 2928 return -EOPNOTSUPP; 2929 data->phy_id = pi->mdio_addr; 2930 break; 2931 case SIOCGMIIREG: 2932 case SIOCSMIIREG: 2933 if (mdio_phy_id_is_c45(data->phy_id)) { 2934 prtad = mdio_phy_id_prtad(data->phy_id); 2935 devad = mdio_phy_id_devad(data->phy_id); 2936 } else if (data->phy_id < 32) { 2937 prtad = data->phy_id; 2938 devad = 0; 2939 data->reg_num &= 0x1f; 2940 } else 2941 return -EINVAL; 2942 2943 mbox = pi->adapter->pf; 2944 if (cmd == SIOCGMIIREG) 2945 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, 2946 data->reg_num, &data->val_out); 2947 else 2948 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, 2949 data->reg_num, data->val_in); 2950 break; 2951 default: 2952 return -EOPNOTSUPP; 2953 } 2954 return ret; 2955 } 2956 2957 static void cxgb_set_rxmode(struct net_device *dev) 2958 { 2959 /* unfortunately we can't return errors to the stack */ 2960 set_rxmode(dev, -1, false); 2961 } 2962 2963 static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2964 { 2965 int ret; 2966 struct port_info *pi = netdev_priv(dev); 2967 2968 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */ 2969 return -EINVAL; 2970 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, 2971 -1, -1, -1, true); 2972 if (!ret) 2973 dev->mtu = new_mtu; 2974 return ret; 2975 } 2976 2977 static int cxgb_set_mac_addr(struct net_device *dev, void *p) 2978 { 2979 int ret; 2980 struct sockaddr *addr = p; 2981 struct port_info *pi = netdev_priv(dev); 2982 2983 if (!is_valid_ether_addr(addr->sa_data)) 2984 return -EADDRNOTAVAIL; 2985 2986 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, 2987 pi->xact_addr_filt, addr->sa_data, true, true); 2988 if (ret < 0) 2989 return ret; 2990 2991 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2992 pi->xact_addr_filt = ret; 2993 return 0; 2994 } 2995 2996 #ifdef CONFIG_NET_POLL_CONTROLLER 2997 static void cxgb_netpoll(struct net_device *dev) 2998 { 2999 struct port_info *pi = netdev_priv(dev); 3000 struct adapter *adap = pi->adapter; 3001 3002 if (adap->flags & USING_MSIX) { 3003 int i; 3004 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; 3005 3006 for (i = pi->nqsets; i; i--, rx++) 3007 t4_sge_intr_msix(0, &rx->rspq); 3008 } else 3009 t4_intr_handler(adap)(0, adap); 3010 } 3011 #endif 3012 3013 static const struct net_device_ops cxgb4_netdev_ops = { 3014 .ndo_open = cxgb_open, 3015 .ndo_stop = cxgb_close, 3016 .ndo_start_xmit = t4_eth_xmit, 3017 .ndo_select_queue = cxgb_select_queue, 3018 .ndo_get_stats64 = cxgb_get_stats, 3019 .ndo_set_rx_mode = cxgb_set_rxmode, 3020 .ndo_set_mac_address = cxgb_set_mac_addr, 3021 .ndo_set_features = cxgb_set_features, 3022 .ndo_validate_addr = eth_validate_addr, 3023 .ndo_do_ioctl = cxgb_ioctl, 3024 .ndo_change_mtu = cxgb_change_mtu, 3025 #ifdef CONFIG_NET_POLL_CONTROLLER 3026 .ndo_poll_controller = cxgb_netpoll, 3027 #endif 3028 #ifdef CONFIG_CHELSIO_T4_FCOE 3029 .ndo_fcoe_enable = cxgb_fcoe_enable, 3030 .ndo_fcoe_disable = cxgb_fcoe_disable, 3031 #endif /* CONFIG_CHELSIO_T4_FCOE */ 3032 #ifdef CONFIG_NET_RX_BUSY_POLL 3033 .ndo_busy_poll = cxgb_busy_poll, 3034 #endif 3035 3036 }; 3037 3038 void t4_fatal_err(struct adapter *adap) 3039 { 3040 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0); 3041 t4_intr_disable(adap); 3042 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); 3043 } 3044 3045 static void setup_memwin(struct adapter *adap) 3046 { 3047 u32 nic_win_base = t4_get_util_window(adap); 3048 3049 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); 3050 } 3051 3052 static void setup_memwin_rdma(struct adapter *adap) 3053 { 3054 if (adap->vres.ocq.size) { 3055 u32 start; 3056 unsigned int sz_kb; 3057 3058 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); 3059 start &= PCI_BASE_ADDRESS_MEM_MASK; 3060 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 3061 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 3062 t4_write_reg(adap, 3063 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), 3064 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); 3065 t4_write_reg(adap, 3066 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), 3067 adap->vres.ocq.start); 3068 t4_read_reg(adap, 3069 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); 3070 } 3071 } 3072 3073 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 3074 { 3075 u32 v; 3076 int ret; 3077 3078 /* get device capabilities */ 3079 memset(c, 0, sizeof(*c)); 3080 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3081 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3082 c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); 3083 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); 3084 if (ret < 0) 3085 return ret; 3086 3087 /* select capabilities we'll be using */ 3088 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) { 3089 if (!vf_acls) 3090 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM); 3091 else 3092 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM); 3093 } else if (vf_acls) { 3094 dev_err(adap->pdev_dev, "virtualization ACLs not supported"); 3095 return ret; 3096 } 3097 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3098 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3099 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); 3100 if (ret < 0) 3101 return ret; 3102 3103 ret = t4_config_glbl_rss(adap, adap->pf, 3104 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 3105 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | 3106 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); 3107 if (ret < 0) 3108 return ret; 3109 3110 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, 3111 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, 3112 FW_CMD_CAP_PF); 3113 if (ret < 0) 3114 return ret; 3115 3116 t4_sge_init(adap); 3117 3118 /* tweak some settings */ 3119 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 3120 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); 3121 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 3122 v = t4_read_reg(adap, TP_PIO_DATA_A); 3123 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 3124 3125 /* first 4 Tx modulation queues point to consecutive Tx channels */ 3126 adap->params.tp.tx_modq_map = 0xE4; 3127 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, 3128 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); 3129 3130 /* associate each Tx modulation queue with consecutive Tx channels */ 3131 v = 0x84218421; 3132 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3133 &v, 1, TP_TX_SCHED_HDR_A); 3134 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3135 &v, 1, TP_TX_SCHED_FIFO_A); 3136 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3137 &v, 1, TP_TX_SCHED_PCMD_A); 3138 3139 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 3140 if (is_offload(adap)) { 3141 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, 3142 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3143 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3144 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3145 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3146 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, 3147 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3148 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3149 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3150 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3151 } 3152 3153 /* get basic stuff going */ 3154 return t4_early_init(adap, adap->pf); 3155 } 3156 3157 /* 3158 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 3159 */ 3160 #define MAX_ATIDS 8192U 3161 3162 /* 3163 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3164 * 3165 * If the firmware we're dealing with has Configuration File support, then 3166 * we use that to perform all configuration 3167 */ 3168 3169 /* 3170 * Tweak configuration based on module parameters, etc. Most of these have 3171 * defaults assigned to them by Firmware Configuration Files (if we're using 3172 * them) but need to be explicitly set if we're using hard-coded 3173 * initialization. But even in the case of using Firmware Configuration 3174 * Files, we'd like to expose the ability to change these via module 3175 * parameters so these are essentially common tweaks/settings for 3176 * Configuration Files and hard-coded initialization ... 3177 */ 3178 static int adap_init0_tweaks(struct adapter *adapter) 3179 { 3180 /* 3181 * Fix up various Host-Dependent Parameters like Page Size, Cache 3182 * Line Size, etc. The firmware default is for a 4KB Page Size and 3183 * 64B Cache Line Size ... 3184 */ 3185 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); 3186 3187 /* 3188 * Process module parameters which affect early initialization. 3189 */ 3190 if (rx_dma_offset != 2 && rx_dma_offset != 0) { 3191 dev_err(&adapter->pdev->dev, 3192 "Ignoring illegal rx_dma_offset=%d, using 2\n", 3193 rx_dma_offset); 3194 rx_dma_offset = 2; 3195 } 3196 t4_set_reg_field(adapter, SGE_CONTROL_A, 3197 PKTSHIFT_V(PKTSHIFT_M), 3198 PKTSHIFT_V(rx_dma_offset)); 3199 3200 /* 3201 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 3202 * adds the pseudo header itself. 3203 */ 3204 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, 3205 CSUM_HAS_PSEUDO_HDR_F, 0); 3206 3207 return 0; 3208 } 3209 3210 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips 3211 * unto themselves and they contain their own firmware to perform their 3212 * tasks ... 3213 */ 3214 static int phy_aq1202_version(const u8 *phy_fw_data, 3215 size_t phy_fw_size) 3216 { 3217 int offset; 3218 3219 /* At offset 0x8 you're looking for the primary image's 3220 * starting offset which is 3 Bytes wide 3221 * 3222 * At offset 0xa of the primary image, you look for the offset 3223 * of the DRAM segment which is 3 Bytes wide. 3224 * 3225 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes 3226 * wide 3227 */ 3228 #define be16(__p) (((__p)[0] << 8) | (__p)[1]) 3229 #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) 3230 #define le24(__p) (le16(__p) | ((__p)[2] << 16)) 3231 3232 offset = le24(phy_fw_data + 0x8) << 12; 3233 offset = le24(phy_fw_data + offset + 0xa); 3234 return be16(phy_fw_data + offset + 0x27e); 3235 3236 #undef be16 3237 #undef le16 3238 #undef le24 3239 } 3240 3241 static struct info_10gbt_phy_fw { 3242 unsigned int phy_fw_id; /* PCI Device ID */ 3243 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ 3244 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); 3245 int phy_flash; /* Has FLASH for PHY Firmware */ 3246 } phy_info_array[] = { 3247 { 3248 PHY_AQ1202_DEVICEID, 3249 PHY_AQ1202_FIRMWARE, 3250 phy_aq1202_version, 3251 1, 3252 }, 3253 { 3254 PHY_BCM84834_DEVICEID, 3255 PHY_BCM84834_FIRMWARE, 3256 NULL, 3257 0, 3258 }, 3259 { 0, NULL, NULL }, 3260 }; 3261 3262 static struct info_10gbt_phy_fw *find_phy_info(int devid) 3263 { 3264 int i; 3265 3266 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { 3267 if (phy_info_array[i].phy_fw_id == devid) 3268 return &phy_info_array[i]; 3269 } 3270 return NULL; 3271 } 3272 3273 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to 3274 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error 3275 * we return a negative error number. If we transfer new firmware we return 1 3276 * (from t4_load_phy_fw()). If we don't do anything we return 0. 3277 */ 3278 static int adap_init0_phy(struct adapter *adap) 3279 { 3280 const struct firmware *phyf; 3281 int ret; 3282 struct info_10gbt_phy_fw *phy_info; 3283 3284 /* Use the device ID to determine which PHY file to flash. 3285 */ 3286 phy_info = find_phy_info(adap->pdev->device); 3287 if (!phy_info) { 3288 dev_warn(adap->pdev_dev, 3289 "No PHY Firmware file found for this PHY\n"); 3290 return -EOPNOTSUPP; 3291 } 3292 3293 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then 3294 * use that. The adapter firmware provides us with a memory buffer 3295 * where we can load a PHY firmware file from the host if we want to 3296 * override the PHY firmware File in flash. 3297 */ 3298 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, 3299 adap->pdev_dev); 3300 if (ret < 0) { 3301 /* For adapters without FLASH attached to PHY for their 3302 * firmware, it's obviously a fatal error if we can't get the 3303 * firmware to the adapter. For adapters with PHY firmware 3304 * FLASH storage, it's worth a warning if we can't find the 3305 * PHY Firmware but we'll neuter the error ... 3306 */ 3307 dev_err(adap->pdev_dev, "unable to find PHY Firmware image " 3308 "/lib/firmware/%s, error %d\n", 3309 phy_info->phy_fw_file, -ret); 3310 if (phy_info->phy_flash) { 3311 int cur_phy_fw_ver = 0; 3312 3313 t4_phy_fw_ver(adap, &cur_phy_fw_ver); 3314 dev_warn(adap->pdev_dev, "continuing with, on-adapter " 3315 "FLASH copy, version %#x\n", cur_phy_fw_ver); 3316 ret = 0; 3317 } 3318 3319 return ret; 3320 } 3321 3322 /* Load PHY Firmware onto adapter. 3323 */ 3324 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, 3325 phy_info->phy_fw_version, 3326 (u8 *)phyf->data, phyf->size); 3327 if (ret < 0) 3328 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", 3329 -ret); 3330 else if (ret > 0) { 3331 int new_phy_fw_ver = 0; 3332 3333 if (phy_info->phy_fw_version) 3334 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, 3335 phyf->size); 3336 dev_info(adap->pdev_dev, "Successfully transferred PHY " 3337 "Firmware /lib/firmware/%s, version %#x\n", 3338 phy_info->phy_fw_file, new_phy_fw_ver); 3339 } 3340 3341 release_firmware(phyf); 3342 3343 return ret; 3344 } 3345 3346 /* 3347 * Attempt to initialize the adapter via a Firmware Configuration File. 3348 */ 3349 static int adap_init0_config(struct adapter *adapter, int reset) 3350 { 3351 struct fw_caps_config_cmd caps_cmd; 3352 const struct firmware *cf; 3353 unsigned long mtype = 0, maddr = 0; 3354 u32 finiver, finicsum, cfcsum; 3355 int ret; 3356 int config_issued = 0; 3357 char *fw_config_file, fw_config_file_path[256]; 3358 char *config_name = NULL; 3359 3360 /* 3361 * Reset device if necessary. 3362 */ 3363 if (reset) { 3364 ret = t4_fw_reset(adapter, adapter->mbox, 3365 PIORSTMODE_F | PIORST_F); 3366 if (ret < 0) 3367 goto bye; 3368 } 3369 3370 /* If this is a 10Gb/s-BT adapter make sure the chip-external 3371 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs 3372 * to be performed after any global adapter RESET above since some 3373 * PHYs only have local RAM copies of the PHY firmware. 3374 */ 3375 if (is_10gbt_device(adapter->pdev->device)) { 3376 ret = adap_init0_phy(adapter); 3377 if (ret < 0) 3378 goto bye; 3379 } 3380 /* 3381 * If we have a T4 configuration file under /lib/firmware/cxgb4/, 3382 * then use that. Otherwise, use the configuration file stored 3383 * in the adapter flash ... 3384 */ 3385 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { 3386 case CHELSIO_T4: 3387 fw_config_file = FW4_CFNAME; 3388 break; 3389 case CHELSIO_T5: 3390 fw_config_file = FW5_CFNAME; 3391 break; 3392 case CHELSIO_T6: 3393 fw_config_file = FW6_CFNAME; 3394 break; 3395 default: 3396 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 3397 adapter->pdev->device); 3398 ret = -EINVAL; 3399 goto bye; 3400 } 3401 3402 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); 3403 if (ret < 0) { 3404 config_name = "On FLASH"; 3405 mtype = FW_MEMTYPE_CF_FLASH; 3406 maddr = t4_flash_cfg_addr(adapter); 3407 } else { 3408 u32 params[7], val[7]; 3409 3410 sprintf(fw_config_file_path, 3411 "/lib/firmware/%s", fw_config_file); 3412 config_name = fw_config_file_path; 3413 3414 if (cf->size >= FLASH_CFG_MAX_SIZE) 3415 ret = -ENOMEM; 3416 else { 3417 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3418 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3419 ret = t4_query_params(adapter, adapter->mbox, 3420 adapter->pf, 0, 1, params, val); 3421 if (ret == 0) { 3422 /* 3423 * For t4_memory_rw() below addresses and 3424 * sizes have to be in terms of multiples of 4 3425 * bytes. So, if the Configuration File isn't 3426 * a multiple of 4 bytes in length we'll have 3427 * to write that out separately since we can't 3428 * guarantee that the bytes following the 3429 * residual byte in the buffer returned by 3430 * request_firmware() are zeroed out ... 3431 */ 3432 size_t resid = cf->size & 0x3; 3433 size_t size = cf->size & ~0x3; 3434 __be32 *data = (__be32 *)cf->data; 3435 3436 mtype = FW_PARAMS_PARAM_Y_G(val[0]); 3437 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; 3438 3439 spin_lock(&adapter->win0_lock); 3440 ret = t4_memory_rw(adapter, 0, mtype, maddr, 3441 size, data, T4_MEMORY_WRITE); 3442 if (ret == 0 && resid != 0) { 3443 union { 3444 __be32 word; 3445 char buf[4]; 3446 } last; 3447 int i; 3448 3449 last.word = data[size >> 2]; 3450 for (i = resid; i < 4; i++) 3451 last.buf[i] = 0; 3452 ret = t4_memory_rw(adapter, 0, mtype, 3453 maddr + size, 3454 4, &last.word, 3455 T4_MEMORY_WRITE); 3456 } 3457 spin_unlock(&adapter->win0_lock); 3458 } 3459 } 3460 3461 release_firmware(cf); 3462 if (ret) 3463 goto bye; 3464 } 3465 3466 /* 3467 * Issue a Capability Configuration command to the firmware to get it 3468 * to parse the Configuration File. We don't use t4_fw_config_file() 3469 * because we want the ability to modify various features after we've 3470 * processed the configuration file ... 3471 */ 3472 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3473 caps_cmd.op_to_write = 3474 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3475 FW_CMD_REQUEST_F | 3476 FW_CMD_READ_F); 3477 caps_cmd.cfvalid_to_len16 = 3478 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | 3479 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | 3480 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | 3481 FW_LEN16(caps_cmd)); 3482 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3483 &caps_cmd); 3484 3485 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware 3486 * Configuration File in FLASH), our last gasp effort is to use the 3487 * Firmware Configuration File which is embedded in the firmware. A 3488 * very few early versions of the firmware didn't have one embedded 3489 * but we can ignore those. 3490 */ 3491 if (ret == -ENOENT) { 3492 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3493 caps_cmd.op_to_write = 3494 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3495 FW_CMD_REQUEST_F | 3496 FW_CMD_READ_F); 3497 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3498 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 3499 sizeof(caps_cmd), &caps_cmd); 3500 config_name = "Firmware Default"; 3501 } 3502 3503 config_issued = 1; 3504 if (ret < 0) 3505 goto bye; 3506 3507 finiver = ntohl(caps_cmd.finiver); 3508 finicsum = ntohl(caps_cmd.finicsum); 3509 cfcsum = ntohl(caps_cmd.cfcsum); 3510 if (finicsum != cfcsum) 3511 dev_warn(adapter->pdev_dev, "Configuration File checksum "\ 3512 "mismatch: [fini] csum=%#x, computed csum=%#x\n", 3513 finicsum, cfcsum); 3514 3515 /* 3516 * And now tell the firmware to use the configuration we just loaded. 3517 */ 3518 caps_cmd.op_to_write = 3519 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3520 FW_CMD_REQUEST_F | 3521 FW_CMD_WRITE_F); 3522 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3523 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3524 NULL); 3525 if (ret < 0) 3526 goto bye; 3527 3528 /* 3529 * Tweak configuration based on system architecture, module 3530 * parameters, etc. 3531 */ 3532 ret = adap_init0_tweaks(adapter); 3533 if (ret < 0) 3534 goto bye; 3535 3536 /* 3537 * And finally tell the firmware to initialize itself using the 3538 * parameters from the Configuration File. 3539 */ 3540 ret = t4_fw_initialize(adapter, adapter->mbox); 3541 if (ret < 0) 3542 goto bye; 3543 3544 /* Emit Firmware Configuration File information and return 3545 * successfully. 3546 */ 3547 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ 3548 "Configuration File \"%s\", version %#x, computed checksum %#x\n", 3549 config_name, finiver, cfcsum); 3550 return 0; 3551 3552 /* 3553 * Something bad happened. Return the error ... (If the "error" 3554 * is that there's no Configuration File on the adapter we don't 3555 * want to issue a warning since this is fairly common.) 3556 */ 3557 bye: 3558 if (config_issued && ret != -ENOENT) 3559 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", 3560 config_name, -ret); 3561 return ret; 3562 } 3563 3564 static struct fw_info fw_info_array[] = { 3565 { 3566 .chip = CHELSIO_T4, 3567 .fs_name = FW4_CFNAME, 3568 .fw_mod_name = FW4_FNAME, 3569 .fw_hdr = { 3570 .chip = FW_HDR_CHIP_T4, 3571 .fw_ver = __cpu_to_be32(FW_VERSION(T4)), 3572 .intfver_nic = FW_INTFVER(T4, NIC), 3573 .intfver_vnic = FW_INTFVER(T4, VNIC), 3574 .intfver_ri = FW_INTFVER(T4, RI), 3575 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3576 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3577 }, 3578 }, { 3579 .chip = CHELSIO_T5, 3580 .fs_name = FW5_CFNAME, 3581 .fw_mod_name = FW5_FNAME, 3582 .fw_hdr = { 3583 .chip = FW_HDR_CHIP_T5, 3584 .fw_ver = __cpu_to_be32(FW_VERSION(T5)), 3585 .intfver_nic = FW_INTFVER(T5, NIC), 3586 .intfver_vnic = FW_INTFVER(T5, VNIC), 3587 .intfver_ri = FW_INTFVER(T5, RI), 3588 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3589 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3590 }, 3591 }, { 3592 .chip = CHELSIO_T6, 3593 .fs_name = FW6_CFNAME, 3594 .fw_mod_name = FW6_FNAME, 3595 .fw_hdr = { 3596 .chip = FW_HDR_CHIP_T6, 3597 .fw_ver = __cpu_to_be32(FW_VERSION(T6)), 3598 .intfver_nic = FW_INTFVER(T6, NIC), 3599 .intfver_vnic = FW_INTFVER(T6, VNIC), 3600 .intfver_ofld = FW_INTFVER(T6, OFLD), 3601 .intfver_ri = FW_INTFVER(T6, RI), 3602 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3603 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3604 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3605 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3606 }, 3607 } 3608 3609 }; 3610 3611 static struct fw_info *find_fw_info(int chip) 3612 { 3613 int i; 3614 3615 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { 3616 if (fw_info_array[i].chip == chip) 3617 return &fw_info_array[i]; 3618 } 3619 return NULL; 3620 } 3621 3622 /* 3623 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3624 */ 3625 static int adap_init0(struct adapter *adap) 3626 { 3627 int ret; 3628 u32 v, port_vec; 3629 enum dev_state state; 3630 u32 params[7], val[7]; 3631 struct fw_caps_config_cmd caps_cmd; 3632 int reset = 1; 3633 3634 /* Grab Firmware Device Log parameters as early as possible so we have 3635 * access to it for debugging, etc. 3636 */ 3637 ret = t4_init_devlog_params(adap); 3638 if (ret < 0) 3639 return ret; 3640 3641 /* Contact FW, advertising Master capability */ 3642 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 3643 if (ret < 0) { 3644 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", 3645 ret); 3646 return ret; 3647 } 3648 if (ret == adap->mbox) 3649 adap->flags |= MASTER_PF; 3650 3651 /* 3652 * If we're the Master PF Driver and the device is uninitialized, 3653 * then let's consider upgrading the firmware ... (We always want 3654 * to check the firmware version number in order to A. get it for 3655 * later reporting and B. to warn if the currently loaded firmware 3656 * is excessively mismatched relative to the driver.) 3657 */ 3658 t4_get_fw_version(adap, &adap->params.fw_vers); 3659 t4_get_tp_version(adap, &adap->params.tp_vers); 3660 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { 3661 struct fw_info *fw_info; 3662 struct fw_hdr *card_fw; 3663 const struct firmware *fw; 3664 const u8 *fw_data = NULL; 3665 unsigned int fw_size = 0; 3666 3667 /* This is the firmware whose headers the driver was compiled 3668 * against 3669 */ 3670 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); 3671 if (fw_info == NULL) { 3672 dev_err(adap->pdev_dev, 3673 "unable to get firmware info for chip %d.\n", 3674 CHELSIO_CHIP_VERSION(adap->params.chip)); 3675 return -EINVAL; 3676 } 3677 3678 /* allocate memory to read the header of the firmware on the 3679 * card 3680 */ 3681 card_fw = t4_alloc_mem(sizeof(*card_fw)); 3682 3683 /* Get FW from from /lib/firmware/ */ 3684 ret = request_firmware(&fw, fw_info->fw_mod_name, 3685 adap->pdev_dev); 3686 if (ret < 0) { 3687 dev_err(adap->pdev_dev, 3688 "unable to load firmware image %s, error %d\n", 3689 fw_info->fw_mod_name, ret); 3690 } else { 3691 fw_data = fw->data; 3692 fw_size = fw->size; 3693 } 3694 3695 /* upgrade FW logic */ 3696 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, 3697 state, &reset); 3698 3699 /* Cleaning up */ 3700 release_firmware(fw); 3701 t4_free_mem(card_fw); 3702 3703 if (ret < 0) 3704 goto bye; 3705 } 3706 3707 /* 3708 * Grab VPD parameters. This should be done after we establish a 3709 * connection to the firmware since some of the VPD parameters 3710 * (notably the Core Clock frequency) are retrieved via requests to 3711 * the firmware. On the other hand, we need these fairly early on 3712 * so we do this right after getting ahold of the firmware. 3713 */ 3714 ret = t4_get_vpd_params(adap, &adap->params.vpd); 3715 if (ret < 0) 3716 goto bye; 3717 3718 /* 3719 * Find out what ports are available to us. Note that we need to do 3720 * this before calling adap_init0_no_config() since it needs nports 3721 * and portvec ... 3722 */ 3723 v = 3724 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3725 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 3726 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 3727 if (ret < 0) 3728 goto bye; 3729 3730 adap->params.nports = hweight32(port_vec); 3731 adap->params.portvec = port_vec; 3732 3733 /* If the firmware is initialized already, emit a simply note to that 3734 * effect. Otherwise, it's time to try initializing the adapter. 3735 */ 3736 if (state == DEV_STATE_INIT) { 3737 dev_info(adap->pdev_dev, "Coming up as %s: "\ 3738 "Adapter already initialized\n", 3739 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 3740 } else { 3741 dev_info(adap->pdev_dev, "Coming up as MASTER: "\ 3742 "Initializing adapter\n"); 3743 3744 /* Find out whether we're dealing with a version of the 3745 * firmware which has configuration file support. 3746 */ 3747 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3748 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3749 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 3750 params, val); 3751 3752 /* If the firmware doesn't support Configuration Files, 3753 * return an error. 3754 */ 3755 if (ret < 0) { 3756 dev_err(adap->pdev_dev, "firmware doesn't support " 3757 "Firmware Configuration Files\n"); 3758 goto bye; 3759 } 3760 3761 /* The firmware provides us with a memory buffer where we can 3762 * load a Configuration File from the host if we want to 3763 * override the Configuration File in flash. 3764 */ 3765 ret = adap_init0_config(adap, reset); 3766 if (ret == -ENOENT) { 3767 dev_err(adap->pdev_dev, "no Configuration File " 3768 "present on adapter.\n"); 3769 goto bye; 3770 } 3771 if (ret < 0) { 3772 dev_err(adap->pdev_dev, "could not initialize " 3773 "adapter, error %d\n", -ret); 3774 goto bye; 3775 } 3776 } 3777 3778 /* Give the SGE code a chance to pull in anything that it needs ... 3779 * Note that this must be called after we retrieve our VPD parameters 3780 * in order to know how to convert core ticks to seconds, etc. 3781 */ 3782 ret = t4_sge_init(adap); 3783 if (ret < 0) 3784 goto bye; 3785 3786 if (is_bypass_device(adap->pdev->device)) 3787 adap->params.bypass = 1; 3788 3789 /* 3790 * Grab some of our basic fundamental operating parameters. 3791 */ 3792 #define FW_PARAM_DEV(param) \ 3793 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 3794 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 3795 3796 #define FW_PARAM_PFVF(param) \ 3797 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 3798 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ 3799 FW_PARAMS_PARAM_Y_V(0) | \ 3800 FW_PARAMS_PARAM_Z_V(0) 3801 3802 params[0] = FW_PARAM_PFVF(EQ_START); 3803 params[1] = FW_PARAM_PFVF(L2T_START); 3804 params[2] = FW_PARAM_PFVF(L2T_END); 3805 params[3] = FW_PARAM_PFVF(FILTER_START); 3806 params[4] = FW_PARAM_PFVF(FILTER_END); 3807 params[5] = FW_PARAM_PFVF(IQFLINT_START); 3808 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); 3809 if (ret < 0) 3810 goto bye; 3811 adap->sge.egr_start = val[0]; 3812 adap->l2t_start = val[1]; 3813 adap->l2t_end = val[2]; 3814 adap->tids.ftid_base = val[3]; 3815 adap->tids.nftids = val[4] - val[3] + 1; 3816 adap->sge.ingr_start = val[5]; 3817 3818 /* qids (ingress/egress) returned from firmware can be anywhere 3819 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. 3820 * Hence driver needs to allocate memory for this range to 3821 * store the queue info. Get the highest IQFLINT/EQ index returned 3822 * in FW_EQ_*_CMD.alloc command. 3823 */ 3824 params[0] = FW_PARAM_PFVF(EQ_END); 3825 params[1] = FW_PARAM_PFVF(IQFLINT_END); 3826 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3827 if (ret < 0) 3828 goto bye; 3829 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; 3830 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; 3831 3832 adap->sge.egr_map = kcalloc(adap->sge.egr_sz, 3833 sizeof(*adap->sge.egr_map), GFP_KERNEL); 3834 if (!adap->sge.egr_map) { 3835 ret = -ENOMEM; 3836 goto bye; 3837 } 3838 3839 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, 3840 sizeof(*adap->sge.ingr_map), GFP_KERNEL); 3841 if (!adap->sge.ingr_map) { 3842 ret = -ENOMEM; 3843 goto bye; 3844 } 3845 3846 /* Allocate the memory for the vaious egress queue bitmaps 3847 * ie starving_fl, txq_maperr and blocked_fl. 3848 */ 3849 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3850 sizeof(long), GFP_KERNEL); 3851 if (!adap->sge.starving_fl) { 3852 ret = -ENOMEM; 3853 goto bye; 3854 } 3855 3856 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3857 sizeof(long), GFP_KERNEL); 3858 if (!adap->sge.txq_maperr) { 3859 ret = -ENOMEM; 3860 goto bye; 3861 } 3862 3863 #ifdef CONFIG_DEBUG_FS 3864 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3865 sizeof(long), GFP_KERNEL); 3866 if (!adap->sge.blocked_fl) { 3867 ret = -ENOMEM; 3868 goto bye; 3869 } 3870 #endif 3871 3872 params[0] = FW_PARAM_PFVF(CLIP_START); 3873 params[1] = FW_PARAM_PFVF(CLIP_END); 3874 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3875 if (ret < 0) 3876 goto bye; 3877 adap->clipt_start = val[0]; 3878 adap->clipt_end = val[1]; 3879 3880 /* query params related to active filter region */ 3881 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); 3882 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); 3883 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3884 /* If Active filter size is set we enable establishing 3885 * offload connection through firmware work request 3886 */ 3887 if ((val[0] != val[1]) && (ret >= 0)) { 3888 adap->flags |= FW_OFLD_CONN; 3889 adap->tids.aftid_base = val[0]; 3890 adap->tids.aftid_end = val[1]; 3891 } 3892 3893 /* If we're running on newer firmware, let it know that we're 3894 * prepared to deal with encapsulated CPL messages. Older 3895 * firmware won't understand this and we'll just get 3896 * unencapsulated messages ... 3897 */ 3898 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3899 val[0] = 1; 3900 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 3901 3902 /* 3903 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 3904 * capability. Earlier versions of the firmware didn't have the 3905 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 3906 * permission to use ULPTX MEMWRITE DSGL. 3907 */ 3908 if (is_t4(adap->params.chip)) { 3909 adap->params.ulptx_memwrite_dsgl = false; 3910 } else { 3911 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 3912 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 3913 1, params, val); 3914 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 3915 } 3916 3917 /* 3918 * Get device capabilities so we can determine what resources we need 3919 * to manage. 3920 */ 3921 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3922 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3923 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3924 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3925 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 3926 &caps_cmd); 3927 if (ret < 0) 3928 goto bye; 3929 3930 if (caps_cmd.ofldcaps) { 3931 /* query offload-related parameters */ 3932 params[0] = FW_PARAM_DEV(NTID); 3933 params[1] = FW_PARAM_PFVF(SERVER_START); 3934 params[2] = FW_PARAM_PFVF(SERVER_END); 3935 params[3] = FW_PARAM_PFVF(TDDP_START); 3936 params[4] = FW_PARAM_PFVF(TDDP_END); 3937 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3938 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 3939 params, val); 3940 if (ret < 0) 3941 goto bye; 3942 adap->tids.ntids = val[0]; 3943 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 3944 adap->tids.stid_base = val[1]; 3945 adap->tids.nstids = val[2] - val[1] + 1; 3946 /* 3947 * Setup server filter region. Divide the available filter 3948 * region into two parts. Regular filters get 1/3rd and server 3949 * filters get 2/3rd part. This is only enabled if workarond 3950 * path is enabled. 3951 * 1. For regular filters. 3952 * 2. Server filter: This are special filters which are used 3953 * to redirect SYN packets to offload queue. 3954 */ 3955 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { 3956 adap->tids.sftid_base = adap->tids.ftid_base + 3957 DIV_ROUND_UP(adap->tids.nftids, 3); 3958 adap->tids.nsftids = adap->tids.nftids - 3959 DIV_ROUND_UP(adap->tids.nftids, 3); 3960 adap->tids.nftids = adap->tids.sftid_base - 3961 adap->tids.ftid_base; 3962 } 3963 adap->vres.ddp.start = val[3]; 3964 adap->vres.ddp.size = val[4] - val[3] + 1; 3965 adap->params.ofldq_wr_cred = val[5]; 3966 3967 adap->params.offload = 1; 3968 } 3969 if (caps_cmd.rdmacaps) { 3970 params[0] = FW_PARAM_PFVF(STAG_START); 3971 params[1] = FW_PARAM_PFVF(STAG_END); 3972 params[2] = FW_PARAM_PFVF(RQ_START); 3973 params[3] = FW_PARAM_PFVF(RQ_END); 3974 params[4] = FW_PARAM_PFVF(PBL_START); 3975 params[5] = FW_PARAM_PFVF(PBL_END); 3976 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 3977 params, val); 3978 if (ret < 0) 3979 goto bye; 3980 adap->vres.stag.start = val[0]; 3981 adap->vres.stag.size = val[1] - val[0] + 1; 3982 adap->vres.rq.start = val[2]; 3983 adap->vres.rq.size = val[3] - val[2] + 1; 3984 adap->vres.pbl.start = val[4]; 3985 adap->vres.pbl.size = val[5] - val[4] + 1; 3986 3987 params[0] = FW_PARAM_PFVF(SQRQ_START); 3988 params[1] = FW_PARAM_PFVF(SQRQ_END); 3989 params[2] = FW_PARAM_PFVF(CQ_START); 3990 params[3] = FW_PARAM_PFVF(CQ_END); 3991 params[4] = FW_PARAM_PFVF(OCQ_START); 3992 params[5] = FW_PARAM_PFVF(OCQ_END); 3993 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, 3994 val); 3995 if (ret < 0) 3996 goto bye; 3997 adap->vres.qp.start = val[0]; 3998 adap->vres.qp.size = val[1] - val[0] + 1; 3999 adap->vres.cq.start = val[2]; 4000 adap->vres.cq.size = val[3] - val[2] + 1; 4001 adap->vres.ocq.start = val[4]; 4002 adap->vres.ocq.size = val[5] - val[4] + 1; 4003 4004 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); 4005 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4006 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, 4007 val); 4008 if (ret < 0) { 4009 adap->params.max_ordird_qp = 8; 4010 adap->params.max_ird_adapter = 32 * adap->tids.ntids; 4011 ret = 0; 4012 } else { 4013 adap->params.max_ordird_qp = val[0]; 4014 adap->params.max_ird_adapter = val[1]; 4015 } 4016 dev_info(adap->pdev_dev, 4017 "max_ordird_qp %d max_ird_adapter %d\n", 4018 adap->params.max_ordird_qp, 4019 adap->params.max_ird_adapter); 4020 } 4021 if (caps_cmd.iscsicaps) { 4022 params[0] = FW_PARAM_PFVF(ISCSI_START); 4023 params[1] = FW_PARAM_PFVF(ISCSI_END); 4024 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4025 params, val); 4026 if (ret < 0) 4027 goto bye; 4028 adap->vres.iscsi.start = val[0]; 4029 adap->vres.iscsi.size = val[1] - val[0] + 1; 4030 } 4031 #undef FW_PARAM_PFVF 4032 #undef FW_PARAM_DEV 4033 4034 /* The MTU/MSS Table is initialized by now, so load their values. If 4035 * we're initializing the adapter, then we'll make any modifications 4036 * we want to the MTU/MSS Table and also initialize the congestion 4037 * parameters. 4038 */ 4039 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 4040 if (state != DEV_STATE_INIT) { 4041 int i; 4042 4043 /* The default MTU Table contains values 1492 and 1500. 4044 * However, for TCP, it's better to have two values which are 4045 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 4046 * This allows us to have a TCP Data Payload which is a 4047 * multiple of 8 regardless of what combination of TCP Options 4048 * are in use (always a multiple of 4 bytes) which is 4049 * important for performance reasons. For instance, if no 4050 * options are in use, then we have a 20-byte IP header and a 4051 * 20-byte TCP header. In this case, a 1500-byte MSS would 4052 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 4053 * which is not a multiple of 8. So using an MSS of 1488 in 4054 * this case results in a TCP Data Payload of 1448 bytes which 4055 * is a multiple of 8. On the other hand, if 12-byte TCP Time 4056 * Stamps have been negotiated, then an MTU of 1500 bytes 4057 * results in a TCP Data Payload of 1448 bytes which, as 4058 * above, is a multiple of 8 bytes ... 4059 */ 4060 for (i = 0; i < NMTUS; i++) 4061 if (adap->params.mtus[i] == 1492) { 4062 adap->params.mtus[i] = 1488; 4063 break; 4064 } 4065 4066 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4067 adap->params.b_wnd); 4068 } 4069 t4_init_sge_params(adap); 4070 adap->flags |= FW_OK; 4071 t4_init_tp_params(adap); 4072 return 0; 4073 4074 /* 4075 * Something bad happened. If a command timed out or failed with EIO 4076 * FW does not operate within its spec or something catastrophic 4077 * happened to HW/FW, stop issuing commands. 4078 */ 4079 bye: 4080 kfree(adap->sge.egr_map); 4081 kfree(adap->sge.ingr_map); 4082 kfree(adap->sge.starving_fl); 4083 kfree(adap->sge.txq_maperr); 4084 #ifdef CONFIG_DEBUG_FS 4085 kfree(adap->sge.blocked_fl); 4086 #endif 4087 if (ret != -ETIMEDOUT && ret != -EIO) 4088 t4_fw_bye(adap, adap->mbox); 4089 return ret; 4090 } 4091 4092 /* EEH callbacks */ 4093 4094 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, 4095 pci_channel_state_t state) 4096 { 4097 int i; 4098 struct adapter *adap = pci_get_drvdata(pdev); 4099 4100 if (!adap) 4101 goto out; 4102 4103 rtnl_lock(); 4104 adap->flags &= ~FW_OK; 4105 notify_ulds(adap, CXGB4_STATE_START_RECOVERY); 4106 spin_lock(&adap->stats_lock); 4107 for_each_port(adap, i) { 4108 struct net_device *dev = adap->port[i]; 4109 4110 netif_device_detach(dev); 4111 netif_carrier_off(dev); 4112 } 4113 spin_unlock(&adap->stats_lock); 4114 disable_interrupts(adap); 4115 if (adap->flags & FULL_INIT_DONE) 4116 cxgb_down(adap); 4117 rtnl_unlock(); 4118 if ((adap->flags & DEV_ENABLED)) { 4119 pci_disable_device(pdev); 4120 adap->flags &= ~DEV_ENABLED; 4121 } 4122 out: return state == pci_channel_io_perm_failure ? 4123 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 4124 } 4125 4126 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) 4127 { 4128 int i, ret; 4129 struct fw_caps_config_cmd c; 4130 struct adapter *adap = pci_get_drvdata(pdev); 4131 4132 if (!adap) { 4133 pci_restore_state(pdev); 4134 pci_save_state(pdev); 4135 return PCI_ERS_RESULT_RECOVERED; 4136 } 4137 4138 if (!(adap->flags & DEV_ENABLED)) { 4139 if (pci_enable_device(pdev)) { 4140 dev_err(&pdev->dev, "Cannot reenable PCI " 4141 "device after reset\n"); 4142 return PCI_ERS_RESULT_DISCONNECT; 4143 } 4144 adap->flags |= DEV_ENABLED; 4145 } 4146 4147 pci_set_master(pdev); 4148 pci_restore_state(pdev); 4149 pci_save_state(pdev); 4150 pci_cleanup_aer_uncorrect_error_status(pdev); 4151 4152 if (t4_wait_dev_ready(adap->regs) < 0) 4153 return PCI_ERS_RESULT_DISCONNECT; 4154 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) 4155 return PCI_ERS_RESULT_DISCONNECT; 4156 adap->flags |= FW_OK; 4157 if (adap_init1(adap, &c)) 4158 return PCI_ERS_RESULT_DISCONNECT; 4159 4160 for_each_port(adap, i) { 4161 struct port_info *p = adap2pinfo(adap, i); 4162 4163 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, 4164 NULL, NULL); 4165 if (ret < 0) 4166 return PCI_ERS_RESULT_DISCONNECT; 4167 p->viid = ret; 4168 p->xact_addr_filt = -1; 4169 } 4170 4171 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4172 adap->params.b_wnd); 4173 setup_memwin(adap); 4174 if (cxgb_up(adap)) 4175 return PCI_ERS_RESULT_DISCONNECT; 4176 return PCI_ERS_RESULT_RECOVERED; 4177 } 4178 4179 static void eeh_resume(struct pci_dev *pdev) 4180 { 4181 int i; 4182 struct adapter *adap = pci_get_drvdata(pdev); 4183 4184 if (!adap) 4185 return; 4186 4187 rtnl_lock(); 4188 for_each_port(adap, i) { 4189 struct net_device *dev = adap->port[i]; 4190 4191 if (netif_running(dev)) { 4192 link_start(dev); 4193 cxgb_set_rxmode(dev); 4194 } 4195 netif_device_attach(dev); 4196 } 4197 rtnl_unlock(); 4198 } 4199 4200 static const struct pci_error_handlers cxgb4_eeh = { 4201 .error_detected = eeh_err_detected, 4202 .slot_reset = eeh_slot_reset, 4203 .resume = eeh_resume, 4204 }; 4205 4206 static inline bool is_x_10g_port(const struct link_config *lc) 4207 { 4208 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 || 4209 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0; 4210 } 4211 4212 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 4213 unsigned int us, unsigned int cnt, 4214 unsigned int size, unsigned int iqe_size) 4215 { 4216 q->adap = adap; 4217 cxgb4_set_rspq_intr_params(q, us, cnt); 4218 q->iqe_len = iqe_size; 4219 q->size = size; 4220 } 4221 4222 /* 4223 * Perform default configuration of DMA queues depending on the number and type 4224 * of ports we found and the number of available CPUs. Most settings can be 4225 * modified by the admin prior to actual use. 4226 */ 4227 static void cfg_queues(struct adapter *adap) 4228 { 4229 struct sge *s = &adap->sge; 4230 int i, n10g = 0, qidx = 0; 4231 #ifndef CONFIG_CHELSIO_T4_DCB 4232 int q10g = 0; 4233 #endif 4234 int ciq_size; 4235 4236 for_each_port(adap, i) 4237 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); 4238 #ifdef CONFIG_CHELSIO_T4_DCB 4239 /* For Data Center Bridging support we need to be able to support up 4240 * to 8 Traffic Priorities; each of which will be assigned to its 4241 * own TX Queue in order to prevent Head-Of-Line Blocking. 4242 */ 4243 if (adap->params.nports * 8 > MAX_ETH_QSETS) { 4244 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", 4245 MAX_ETH_QSETS, adap->params.nports * 8); 4246 BUG_ON(1); 4247 } 4248 4249 for_each_port(adap, i) { 4250 struct port_info *pi = adap2pinfo(adap, i); 4251 4252 pi->first_qset = qidx; 4253 pi->nqsets = 8; 4254 qidx += pi->nqsets; 4255 } 4256 #else /* !CONFIG_CHELSIO_T4_DCB */ 4257 /* 4258 * We default to 1 queue per non-10G port and up to # of cores queues 4259 * per 10G port. 4260 */ 4261 if (n10g) 4262 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; 4263 if (q10g > netif_get_num_default_rss_queues()) 4264 q10g = netif_get_num_default_rss_queues(); 4265 4266 for_each_port(adap, i) { 4267 struct port_info *pi = adap2pinfo(adap, i); 4268 4269 pi->first_qset = qidx; 4270 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; 4271 qidx += pi->nqsets; 4272 } 4273 #endif /* !CONFIG_CHELSIO_T4_DCB */ 4274 4275 s->ethqsets = qidx; 4276 s->max_ethqsets = qidx; /* MSI-X may lower it later */ 4277 4278 if (is_offload(adap)) { 4279 /* 4280 * For offload we use 1 queue/channel if all ports are up to 1G, 4281 * otherwise we divide all available queues amongst the channels 4282 * capped by the number of available cores. 4283 */ 4284 if (n10g) { 4285 i = min_t(int, ARRAY_SIZE(s->ofldrxq), 4286 num_online_cpus()); 4287 s->ofldqsets = roundup(i, adap->params.nports); 4288 } else 4289 s->ofldqsets = adap->params.nports; 4290 /* For RDMA one Rx queue per channel suffices */ 4291 s->rdmaqs = adap->params.nports; 4292 /* Try and allow at least 1 CIQ per cpu rounding down 4293 * to the number of ports, with a minimum of 1 per port. 4294 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port. 4295 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port. 4296 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port. 4297 */ 4298 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus()); 4299 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) * 4300 adap->params.nports; 4301 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports); 4302 } 4303 4304 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 4305 struct sge_eth_rxq *r = &s->ethrxq[i]; 4306 4307 init_rspq(adap, &r->rspq, 5, 10, 1024, 64); 4308 r->fl.size = 72; 4309 } 4310 4311 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 4312 s->ethtxq[i].q.size = 1024; 4313 4314 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) 4315 s->ctrlq[i].q.size = 512; 4316 4317 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) 4318 s->ofldtxq[i].q.size = 1024; 4319 4320 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) { 4321 struct sge_ofld_rxq *r = &s->ofldrxq[i]; 4322 4323 init_rspq(adap, &r->rspq, 5, 1, 1024, 64); 4324 r->rspq.uld = CXGB4_ULD_ISCSI; 4325 r->fl.size = 72; 4326 } 4327 4328 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) { 4329 struct sge_ofld_rxq *r = &s->rdmarxq[i]; 4330 4331 init_rspq(adap, &r->rspq, 5, 1, 511, 64); 4332 r->rspq.uld = CXGB4_ULD_RDMA; 4333 r->fl.size = 72; 4334 } 4335 4336 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids; 4337 if (ciq_size > SGE_MAX_IQ_SIZE) { 4338 CH_WARN(adap, "CIQ size too small for available IQs\n"); 4339 ciq_size = SGE_MAX_IQ_SIZE; 4340 } 4341 4342 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) { 4343 struct sge_ofld_rxq *r = &s->rdmaciq[i]; 4344 4345 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64); 4346 r->rspq.uld = CXGB4_ULD_RDMA; 4347 } 4348 4349 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); 4350 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64); 4351 } 4352 4353 /* 4354 * Reduce the number of Ethernet queues across all ports to at most n. 4355 * n provides at least one queue per port. 4356 */ 4357 static void reduce_ethqs(struct adapter *adap, int n) 4358 { 4359 int i; 4360 struct port_info *pi; 4361 4362 while (n < adap->sge.ethqsets) 4363 for_each_port(adap, i) { 4364 pi = adap2pinfo(adap, i); 4365 if (pi->nqsets > 1) { 4366 pi->nqsets--; 4367 adap->sge.ethqsets--; 4368 if (adap->sge.ethqsets <= n) 4369 break; 4370 } 4371 } 4372 4373 n = 0; 4374 for_each_port(adap, i) { 4375 pi = adap2pinfo(adap, i); 4376 pi->first_qset = n; 4377 n += pi->nqsets; 4378 } 4379 } 4380 4381 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ 4382 #define EXTRA_VECS 2 4383 4384 static int enable_msix(struct adapter *adap) 4385 { 4386 int ofld_need = 0; 4387 int i, want, need, allocated; 4388 struct sge *s = &adap->sge; 4389 unsigned int nchan = adap->params.nports; 4390 struct msix_entry *entries; 4391 4392 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1), 4393 GFP_KERNEL); 4394 if (!entries) 4395 return -ENOMEM; 4396 4397 for (i = 0; i < MAX_INGQ + 1; ++i) 4398 entries[i].entry = i; 4399 4400 want = s->max_ethqsets + EXTRA_VECS; 4401 if (is_offload(adap)) { 4402 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets; 4403 /* need nchan for each possible ULD */ 4404 ofld_need = 3 * nchan; 4405 } 4406 #ifdef CONFIG_CHELSIO_T4_DCB 4407 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for 4408 * each port. 4409 */ 4410 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need; 4411 #else 4412 need = adap->params.nports + EXTRA_VECS + ofld_need; 4413 #endif 4414 allocated = pci_enable_msix_range(adap->pdev, entries, need, want); 4415 if (allocated < 0) { 4416 dev_info(adap->pdev_dev, "not enough MSI-X vectors left," 4417 " not using MSI-X\n"); 4418 kfree(entries); 4419 return allocated; 4420 } 4421 4422 /* Distribute available vectors to the various queue groups. 4423 * Every group gets its minimum requirement and NIC gets top 4424 * priority for leftovers. 4425 */ 4426 i = allocated - EXTRA_VECS - ofld_need; 4427 if (i < s->max_ethqsets) { 4428 s->max_ethqsets = i; 4429 if (i < s->ethqsets) 4430 reduce_ethqs(adap, i); 4431 } 4432 if (is_offload(adap)) { 4433 if (allocated < want) { 4434 s->rdmaqs = nchan; 4435 s->rdmaciqs = nchan; 4436 } 4437 4438 /* leftovers go to OFLD */ 4439 i = allocated - EXTRA_VECS - s->max_ethqsets - 4440 s->rdmaqs - s->rdmaciqs; 4441 s->ofldqsets = (i / nchan) * nchan; /* round down */ 4442 } 4443 for (i = 0; i < allocated; ++i) 4444 adap->msix_info[i].vec = entries[i].vector; 4445 4446 kfree(entries); 4447 return 0; 4448 } 4449 4450 #undef EXTRA_VECS 4451 4452 static int init_rss(struct adapter *adap) 4453 { 4454 unsigned int i; 4455 int err; 4456 4457 err = t4_init_rss_mode(adap, adap->mbox); 4458 if (err) 4459 return err; 4460 4461 for_each_port(adap, i) { 4462 struct port_info *pi = adap2pinfo(adap, i); 4463 4464 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 4465 if (!pi->rss) 4466 return -ENOMEM; 4467 } 4468 return 0; 4469 } 4470 4471 static void print_port_info(const struct net_device *dev) 4472 { 4473 char buf[80]; 4474 char *bufp = buf; 4475 const char *spd = ""; 4476 const struct port_info *pi = netdev_priv(dev); 4477 const struct adapter *adap = pi->adapter; 4478 4479 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) 4480 spd = " 2.5 GT/s"; 4481 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) 4482 spd = " 5 GT/s"; 4483 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) 4484 spd = " 8 GT/s"; 4485 4486 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) 4487 bufp += sprintf(bufp, "100/"); 4488 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 4489 bufp += sprintf(bufp, "1000/"); 4490 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 4491 bufp += sprintf(bufp, "10G/"); 4492 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 4493 bufp += sprintf(bufp, "40G/"); 4494 if (bufp != buf) 4495 --bufp; 4496 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); 4497 4498 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n", 4499 adap->params.vpd.id, 4500 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 4501 is_offload(adap) ? "R" : "", adap->params.pci.width, spd, 4502 (adap->flags & USING_MSIX) ? " MSI-X" : 4503 (adap->flags & USING_MSI) ? " MSI" : ""); 4504 netdev_info(dev, "S/N: %s, P/N: %s\n", 4505 adap->params.vpd.sn, adap->params.vpd.pn); 4506 } 4507 4508 static void enable_pcie_relaxed_ordering(struct pci_dev *dev) 4509 { 4510 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); 4511 } 4512 4513 /* 4514 * Free the following resources: 4515 * - memory used for tables 4516 * - MSI/MSI-X 4517 * - net devices 4518 * - resources FW is holding for us 4519 */ 4520 static void free_some_resources(struct adapter *adapter) 4521 { 4522 unsigned int i; 4523 4524 t4_free_mem(adapter->l2t); 4525 t4_free_mem(adapter->tids.tid_tab); 4526 kfree(adapter->sge.egr_map); 4527 kfree(adapter->sge.ingr_map); 4528 kfree(adapter->sge.starving_fl); 4529 kfree(adapter->sge.txq_maperr); 4530 #ifdef CONFIG_DEBUG_FS 4531 kfree(adapter->sge.blocked_fl); 4532 #endif 4533 disable_msi(adapter); 4534 4535 for_each_port(adapter, i) 4536 if (adapter->port[i]) { 4537 struct port_info *pi = adap2pinfo(adapter, i); 4538 4539 if (pi->viid != 0) 4540 t4_free_vi(adapter, adapter->mbox, adapter->pf, 4541 0, pi->viid); 4542 kfree(adap2pinfo(adapter, i)->rss); 4543 free_netdev(adapter->port[i]); 4544 } 4545 if (adapter->flags & FW_OK) 4546 t4_fw_bye(adapter, adapter->pf); 4547 } 4548 4549 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) 4550 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ 4551 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) 4552 #define SEGMENT_SIZE 128 4553 4554 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 4555 { 4556 int func, i, err, s_qpp, qpp, num_seg; 4557 struct port_info *pi; 4558 bool highdma = false; 4559 struct adapter *adapter = NULL; 4560 void __iomem *regs; 4561 4562 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); 4563 4564 err = pci_request_regions(pdev, KBUILD_MODNAME); 4565 if (err) { 4566 /* Just info, some other driver may have claimed the device. */ 4567 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 4568 return err; 4569 } 4570 4571 err = pci_enable_device(pdev); 4572 if (err) { 4573 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4574 goto out_release_regions; 4575 } 4576 4577 regs = pci_ioremap_bar(pdev, 0); 4578 if (!regs) { 4579 dev_err(&pdev->dev, "cannot map device registers\n"); 4580 err = -ENOMEM; 4581 goto out_disable_device; 4582 } 4583 4584 err = t4_wait_dev_ready(regs); 4585 if (err < 0) 4586 goto out_unmap_bar0; 4587 4588 /* We control everything through one PF */ 4589 func = SOURCEPF_G(readl(regs + PL_WHOAMI_A)); 4590 if (func != ent->driver_data) { 4591 iounmap(regs); 4592 pci_disable_device(pdev); 4593 pci_save_state(pdev); /* to restore SR-IOV later */ 4594 goto sriov; 4595 } 4596 4597 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 4598 highdma = true; 4599 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4600 if (err) { 4601 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 4602 "coherent allocations\n"); 4603 goto out_unmap_bar0; 4604 } 4605 } else { 4606 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4607 if (err) { 4608 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4609 goto out_unmap_bar0; 4610 } 4611 } 4612 4613 pci_enable_pcie_error_reporting(pdev); 4614 enable_pcie_relaxed_ordering(pdev); 4615 pci_set_master(pdev); 4616 pci_save_state(pdev); 4617 4618 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 4619 if (!adapter) { 4620 err = -ENOMEM; 4621 goto out_unmap_bar0; 4622 } 4623 4624 adapter->workq = create_singlethread_workqueue("cxgb4"); 4625 if (!adapter->workq) { 4626 err = -ENOMEM; 4627 goto out_free_adapter; 4628 } 4629 4630 /* PCI device has been enabled */ 4631 adapter->flags |= DEV_ENABLED; 4632 4633 adapter->regs = regs; 4634 adapter->pdev = pdev; 4635 adapter->pdev_dev = &pdev->dev; 4636 adapter->mbox = func; 4637 adapter->pf = func; 4638 adapter->msg_enable = dflt_msg_enable; 4639 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); 4640 4641 spin_lock_init(&adapter->stats_lock); 4642 spin_lock_init(&adapter->tid_release_lock); 4643 spin_lock_init(&adapter->win0_lock); 4644 4645 INIT_WORK(&adapter->tid_release_task, process_tid_release_list); 4646 INIT_WORK(&adapter->db_full_task, process_db_full); 4647 INIT_WORK(&adapter->db_drop_task, process_db_drop); 4648 4649 err = t4_prep_adapter(adapter); 4650 if (err) 4651 goto out_free_adapter; 4652 4653 4654 if (!is_t4(adapter->params.chip)) { 4655 s_qpp = (QUEUESPERPAGEPF0_S + 4656 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * 4657 adapter->pf); 4658 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, 4659 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); 4660 num_seg = PAGE_SIZE / SEGMENT_SIZE; 4661 4662 /* Each segment size is 128B. Write coalescing is enabled only 4663 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the 4664 * queue is less no of segments that can be accommodated in 4665 * a page size. 4666 */ 4667 if (qpp > num_seg) { 4668 dev_err(&pdev->dev, 4669 "Incorrect number of egress queues per page\n"); 4670 err = -EINVAL; 4671 goto out_free_adapter; 4672 } 4673 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), 4674 pci_resource_len(pdev, 2)); 4675 if (!adapter->bar2) { 4676 dev_err(&pdev->dev, "cannot map device bar2 region\n"); 4677 err = -ENOMEM; 4678 goto out_free_adapter; 4679 } 4680 t4_write_reg(adapter, SGE_STAT_CFG_A, 4681 STATSOURCE_T5_V(7) | STATMODE_V(0)); 4682 } 4683 4684 setup_memwin(adapter); 4685 err = adap_init0(adapter); 4686 #ifdef CONFIG_DEBUG_FS 4687 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); 4688 #endif 4689 setup_memwin_rdma(adapter); 4690 if (err) 4691 goto out_unmap_bar; 4692 4693 for_each_port(adapter, i) { 4694 struct net_device *netdev; 4695 4696 netdev = alloc_etherdev_mq(sizeof(struct port_info), 4697 MAX_ETH_QSETS); 4698 if (!netdev) { 4699 err = -ENOMEM; 4700 goto out_free_dev; 4701 } 4702 4703 SET_NETDEV_DEV(netdev, &pdev->dev); 4704 4705 adapter->port[i] = netdev; 4706 pi = netdev_priv(netdev); 4707 pi->adapter = adapter; 4708 pi->xact_addr_filt = -1; 4709 pi->port_id = i; 4710 netdev->irq = pdev->irq; 4711 4712 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | 4713 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4714 NETIF_F_RXCSUM | NETIF_F_RXHASH | 4715 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 4716 if (highdma) 4717 netdev->hw_features |= NETIF_F_HIGHDMA; 4718 netdev->features |= netdev->hw_features; 4719 netdev->vlan_features = netdev->features & VLAN_FEAT; 4720 4721 netdev->priv_flags |= IFF_UNICAST_FLT; 4722 4723 netdev->netdev_ops = &cxgb4_netdev_ops; 4724 #ifdef CONFIG_CHELSIO_T4_DCB 4725 netdev->dcbnl_ops = &cxgb4_dcb_ops; 4726 cxgb4_dcb_state_init(netdev); 4727 #endif 4728 cxgb4_set_ethtool_ops(netdev); 4729 } 4730 4731 pci_set_drvdata(pdev, adapter); 4732 4733 if (adapter->flags & FW_OK) { 4734 err = t4_port_init(adapter, func, func, 0); 4735 if (err) 4736 goto out_free_dev; 4737 } else if (adapter->params.nports == 1) { 4738 /* If we don't have a connection to the firmware -- possibly 4739 * because of an error -- grab the raw VPD parameters so we 4740 * can set the proper MAC Address on the debug network 4741 * interface that we've created. 4742 */ 4743 u8 hw_addr[ETH_ALEN]; 4744 u8 *na = adapter->params.vpd.na; 4745 4746 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); 4747 if (!err) { 4748 for (i = 0; i < ETH_ALEN; i++) 4749 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 4750 hex2val(na[2 * i + 1])); 4751 t4_set_hw_addr(adapter, 0, hw_addr); 4752 } 4753 } 4754 4755 /* Configure queues and allocate tables now, they can be needed as 4756 * soon as the first register_netdev completes. 4757 */ 4758 cfg_queues(adapter); 4759 4760 adapter->l2t = t4_init_l2t(); 4761 if (!adapter->l2t) { 4762 /* We tolerate a lack of L2T, giving up some functionality */ 4763 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); 4764 adapter->params.offload = 0; 4765 } 4766 4767 #if IS_ENABLED(CONFIG_IPV6) 4768 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 4769 adapter->clipt_end); 4770 if (!adapter->clipt) { 4771 /* We tolerate a lack of clip_table, giving up 4772 * some functionality 4773 */ 4774 dev_warn(&pdev->dev, 4775 "could not allocate Clip table, continuing\n"); 4776 adapter->params.offload = 0; 4777 } 4778 #endif 4779 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) { 4780 dev_warn(&pdev->dev, "could not allocate TID table, " 4781 "continuing\n"); 4782 adapter->params.offload = 0; 4783 } 4784 4785 /* See what interrupts we'll be using */ 4786 if (msi > 1 && enable_msix(adapter) == 0) 4787 adapter->flags |= USING_MSIX; 4788 else if (msi > 0 && pci_enable_msi(pdev) == 0) 4789 adapter->flags |= USING_MSI; 4790 4791 err = init_rss(adapter); 4792 if (err) 4793 goto out_free_dev; 4794 4795 /* 4796 * The card is now ready to go. If any errors occur during device 4797 * registration we do not fail the whole card but rather proceed only 4798 * with the ports we manage to register successfully. However we must 4799 * register at least one net device. 4800 */ 4801 for_each_port(adapter, i) { 4802 pi = adap2pinfo(adapter, i); 4803 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); 4804 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); 4805 4806 err = register_netdev(adapter->port[i]); 4807 if (err) 4808 break; 4809 adapter->chan_map[pi->tx_chan] = i; 4810 print_port_info(adapter->port[i]); 4811 } 4812 if (i == 0) { 4813 dev_err(&pdev->dev, "could not register any net devices\n"); 4814 goto out_free_dev; 4815 } 4816 if (err) { 4817 dev_warn(&pdev->dev, "only %d net devices registered\n", i); 4818 err = 0; 4819 } 4820 4821 if (cxgb4_debugfs_root) { 4822 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), 4823 cxgb4_debugfs_root); 4824 setup_debugfs(adapter); 4825 } 4826 4827 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ 4828 pdev->needs_freset = 1; 4829 4830 if (is_offload(adapter)) 4831 attach_ulds(adapter); 4832 4833 sriov: 4834 #ifdef CONFIG_PCI_IOV 4835 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0) 4836 if (pci_enable_sriov(pdev, num_vf[func]) == 0) 4837 dev_info(&pdev->dev, 4838 "instantiated %u virtual functions\n", 4839 num_vf[func]); 4840 #endif 4841 return 0; 4842 4843 out_free_dev: 4844 free_some_resources(adapter); 4845 out_unmap_bar: 4846 if (!is_t4(adapter->params.chip)) 4847 iounmap(adapter->bar2); 4848 out_free_adapter: 4849 if (adapter->workq) 4850 destroy_workqueue(adapter->workq); 4851 4852 kfree(adapter); 4853 out_unmap_bar0: 4854 iounmap(regs); 4855 out_disable_device: 4856 pci_disable_pcie_error_reporting(pdev); 4857 pci_disable_device(pdev); 4858 out_release_regions: 4859 pci_release_regions(pdev); 4860 return err; 4861 } 4862 4863 static void remove_one(struct pci_dev *pdev) 4864 { 4865 struct adapter *adapter = pci_get_drvdata(pdev); 4866 4867 #ifdef CONFIG_PCI_IOV 4868 pci_disable_sriov(pdev); 4869 4870 #endif 4871 4872 if (adapter) { 4873 int i; 4874 4875 /* Tear down per-adapter Work Queue first since it can contain 4876 * references to our adapter data structure. 4877 */ 4878 destroy_workqueue(adapter->workq); 4879 4880 if (is_offload(adapter)) 4881 detach_ulds(adapter); 4882 4883 disable_interrupts(adapter); 4884 4885 for_each_port(adapter, i) 4886 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 4887 unregister_netdev(adapter->port[i]); 4888 4889 debugfs_remove_recursive(adapter->debugfs_root); 4890 4891 /* If we allocated filters, free up state associated with any 4892 * valid filters ... 4893 */ 4894 if (adapter->tids.ftid_tab) { 4895 struct filter_entry *f = &adapter->tids.ftid_tab[0]; 4896 for (i = 0; i < (adapter->tids.nftids + 4897 adapter->tids.nsftids); i++, f++) 4898 if (f->valid) 4899 clear_filter(adapter, f); 4900 } 4901 4902 if (adapter->flags & FULL_INIT_DONE) 4903 cxgb_down(adapter); 4904 4905 free_some_resources(adapter); 4906 #if IS_ENABLED(CONFIG_IPV6) 4907 t4_cleanup_clip_tbl(adapter); 4908 #endif 4909 iounmap(adapter->regs); 4910 if (!is_t4(adapter->params.chip)) 4911 iounmap(adapter->bar2); 4912 pci_disable_pcie_error_reporting(pdev); 4913 if ((adapter->flags & DEV_ENABLED)) { 4914 pci_disable_device(pdev); 4915 adapter->flags &= ~DEV_ENABLED; 4916 } 4917 pci_release_regions(pdev); 4918 synchronize_rcu(); 4919 kfree(adapter); 4920 } else 4921 pci_release_regions(pdev); 4922 } 4923 4924 static struct pci_driver cxgb4_driver = { 4925 .name = KBUILD_MODNAME, 4926 .id_table = cxgb4_pci_tbl, 4927 .probe = init_one, 4928 .remove = remove_one, 4929 .shutdown = remove_one, 4930 .err_handler = &cxgb4_eeh, 4931 }; 4932 4933 static int __init cxgb4_init_module(void) 4934 { 4935 int ret; 4936 4937 /* Debugfs support is optional, just warn if this fails */ 4938 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); 4939 if (!cxgb4_debugfs_root) 4940 pr_warn("could not create debugfs entry, continuing\n"); 4941 4942 ret = pci_register_driver(&cxgb4_driver); 4943 if (ret < 0) 4944 debugfs_remove(cxgb4_debugfs_root); 4945 4946 #if IS_ENABLED(CONFIG_IPV6) 4947 if (!inet6addr_registered) { 4948 register_inet6addr_notifier(&cxgb4_inet6addr_notifier); 4949 inet6addr_registered = true; 4950 } 4951 #endif 4952 4953 return ret; 4954 } 4955 4956 static void __exit cxgb4_cleanup_module(void) 4957 { 4958 #if IS_ENABLED(CONFIG_IPV6) 4959 if (inet6addr_registered) { 4960 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); 4961 inet6addr_registered = false; 4962 } 4963 #endif 4964 pci_unregister_driver(&cxgb4_driver); 4965 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ 4966 } 4967 4968 module_init(cxgb4_init_module); 4969 module_exit(cxgb4_cleanup_module); 4970