1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 36 37 #include <linux/bitmap.h> 38 #include <linux/crc32.h> 39 #include <linux/ctype.h> 40 #include <linux/debugfs.h> 41 #include <linux/err.h> 42 #include <linux/etherdevice.h> 43 #include <linux/firmware.h> 44 #include <linux/if.h> 45 #include <linux/if_vlan.h> 46 #include <linux/init.h> 47 #include <linux/log2.h> 48 #include <linux/mdio.h> 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/mutex.h> 52 #include <linux/netdevice.h> 53 #include <linux/pci.h> 54 #include <linux/aer.h> 55 #include <linux/rtnetlink.h> 56 #include <linux/sched.h> 57 #include <linux/seq_file.h> 58 #include <linux/sockios.h> 59 #include <linux/vmalloc.h> 60 #include <linux/workqueue.h> 61 #include <net/neighbour.h> 62 #include <net/netevent.h> 63 #include <net/addrconf.h> 64 #include <net/bonding.h> 65 #include <net/addrconf.h> 66 #include <linux/uaccess.h> 67 #include <linux/crash_dump.h> 68 69 #include "cxgb4.h" 70 #include "cxgb4_filter.h" 71 #include "t4_regs.h" 72 #include "t4_values.h" 73 #include "t4_msg.h" 74 #include "t4fw_api.h" 75 #include "t4fw_version.h" 76 #include "cxgb4_dcb.h" 77 #include "cxgb4_debugfs.h" 78 #include "clip_tbl.h" 79 #include "l2t.h" 80 #include "sched.h" 81 #include "cxgb4_tc_u32.h" 82 #include "cxgb4_ptp.h" 83 84 char cxgb4_driver_name[] = KBUILD_MODNAME; 85 86 #ifdef DRV_VERSION 87 #undef DRV_VERSION 88 #endif 89 #define DRV_VERSION "2.0.0-ko" 90 const char cxgb4_driver_version[] = DRV_VERSION; 91 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" 92 93 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 94 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 95 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 96 97 /* Macros needed to support the PCI Device ID Table ... 98 */ 99 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 100 static const struct pci_device_id cxgb4_pci_tbl[] = { 101 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 102 103 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is 104 * called for both. 105 */ 106 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 107 108 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 109 {PCI_VDEVICE(CHELSIO, (devid)), 4} 110 111 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 112 { 0, } \ 113 } 114 115 #include "t4_pci_id_tbl.h" 116 117 #define FW4_FNAME "cxgb4/t4fw.bin" 118 #define FW5_FNAME "cxgb4/t5fw.bin" 119 #define FW6_FNAME "cxgb4/t6fw.bin" 120 #define FW4_CFNAME "cxgb4/t4-config.txt" 121 #define FW5_CFNAME "cxgb4/t5-config.txt" 122 #define FW6_CFNAME "cxgb4/t6-config.txt" 123 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 124 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 125 #define PHY_AQ1202_DEVICEID 0x4409 126 #define PHY_BCM84834_DEVICEID 0x4486 127 128 MODULE_DESCRIPTION(DRV_DESC); 129 MODULE_AUTHOR("Chelsio Communications"); 130 MODULE_LICENSE("Dual BSD/GPL"); 131 MODULE_VERSION(DRV_VERSION); 132 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); 133 MODULE_FIRMWARE(FW4_FNAME); 134 MODULE_FIRMWARE(FW5_FNAME); 135 MODULE_FIRMWARE(FW6_FNAME); 136 137 /* 138 * The driver uses the best interrupt scheme available on a platform in the 139 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which 140 * of these schemes the driver may consider as follows: 141 * 142 * msi = 2: choose from among all three options 143 * msi = 1: only consider MSI and INTx interrupts 144 * msi = 0: force INTx interrupts 145 */ 146 static int msi = 2; 147 148 module_param(msi, int, 0644); 149 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); 150 151 /* 152 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers 153 * offset by 2 bytes in order to have the IP headers line up on 4-byte 154 * boundaries. This is a requirement for many architectures which will throw 155 * a machine check fault if an attempt is made to access one of the 4-byte IP 156 * header fields on a non-4-byte boundary. And it's a major performance issue 157 * even on some architectures which allow it like some implementations of the 158 * x86 ISA. However, some architectures don't mind this and for some very 159 * edge-case performance sensitive applications (like forwarding large volumes 160 * of small packets), setting this DMA offset to 0 will decrease the number of 161 * PCI-E Bus transfers enough to measurably affect performance. 162 */ 163 static int rx_dma_offset = 2; 164 165 /* TX Queue select used to determine what algorithm to use for selecting TX 166 * queue. Select between the kernel provided function (select_queue=0) or user 167 * cxgb_select_queue function (select_queue=1) 168 * 169 * Default: select_queue=0 170 */ 171 static int select_queue; 172 module_param(select_queue, int, 0644); 173 MODULE_PARM_DESC(select_queue, 174 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); 175 176 static struct dentry *cxgb4_debugfs_root; 177 178 LIST_HEAD(adapter_list); 179 DEFINE_MUTEX(uld_mutex); 180 181 static void link_report(struct net_device *dev) 182 { 183 if (!netif_carrier_ok(dev)) 184 netdev_info(dev, "link down\n"); 185 else { 186 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; 187 188 const char *s; 189 const struct port_info *p = netdev_priv(dev); 190 191 switch (p->link_cfg.speed) { 192 case 100: 193 s = "100Mbps"; 194 break; 195 case 1000: 196 s = "1Gbps"; 197 break; 198 case 10000: 199 s = "10Gbps"; 200 break; 201 case 25000: 202 s = "25Gbps"; 203 break; 204 case 40000: 205 s = "40Gbps"; 206 break; 207 case 100000: 208 s = "100Gbps"; 209 break; 210 default: 211 pr_info("%s: unsupported speed: %d\n", 212 dev->name, p->link_cfg.speed); 213 return; 214 } 215 216 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, 217 fc[p->link_cfg.fc]); 218 } 219 } 220 221 #ifdef CONFIG_CHELSIO_T4_DCB 222 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ 223 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) 224 { 225 struct port_info *pi = netdev_priv(dev); 226 struct adapter *adap = pi->adapter; 227 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; 228 int i; 229 230 /* We use a simple mapping of Port TX Queue Index to DCB 231 * Priority when we're enabling DCB. 232 */ 233 for (i = 0; i < pi->nqsets; i++, txq++) { 234 u32 name, value; 235 int err; 236 237 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 238 FW_PARAMS_PARAM_X_V( 239 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | 240 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); 241 value = enable ? i : 0xffffffff; 242 243 /* Since we can be called while atomic (from "interrupt 244 * level") we need to issue the Set Parameters Commannd 245 * without sleeping (timeout < 0). 246 */ 247 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 248 &name, &value, 249 -FW_CMD_MAX_TIMEOUT); 250 251 if (err) 252 dev_err(adap->pdev_dev, 253 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", 254 enable ? "set" : "unset", pi->port_id, i, -err); 255 else 256 txq->dcb_prio = value; 257 } 258 } 259 260 static int cxgb4_dcb_enabled(const struct net_device *dev) 261 { 262 struct port_info *pi = netdev_priv(dev); 263 264 if (!pi->dcb.enabled) 265 return 0; 266 267 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || 268 (pi->dcb.state == CXGB4_DCB_STATE_HOST)); 269 } 270 #endif /* CONFIG_CHELSIO_T4_DCB */ 271 272 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) 273 { 274 struct net_device *dev = adapter->port[port_id]; 275 276 /* Skip changes from disabled ports. */ 277 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { 278 if (link_stat) 279 netif_carrier_on(dev); 280 else { 281 #ifdef CONFIG_CHELSIO_T4_DCB 282 if (cxgb4_dcb_enabled(dev)) { 283 cxgb4_dcb_state_init(dev); 284 dcb_tx_queue_prio_enable(dev, false); 285 } 286 #endif /* CONFIG_CHELSIO_T4_DCB */ 287 netif_carrier_off(dev); 288 } 289 290 link_report(dev); 291 } 292 } 293 294 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 295 { 296 static const char *mod_str[] = { 297 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 298 }; 299 300 const struct net_device *dev = adap->port[port_id]; 301 const struct port_info *pi = netdev_priv(dev); 302 303 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 304 netdev_info(dev, "port module unplugged\n"); 305 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 306 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); 307 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 308 netdev_info(dev, "%s: unsupported port module inserted\n", 309 dev->name); 310 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 311 netdev_info(dev, "%s: unknown port module inserted\n", 312 dev->name); 313 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 314 netdev_info(dev, "%s: transceiver module error\n", dev->name); 315 else 316 netdev_info(dev, "%s: unknown module type %d inserted\n", 317 dev->name, pi->mod_type); 318 } 319 320 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ 321 module_param(dbfifo_int_thresh, int, 0644); 322 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); 323 324 /* 325 * usecs to sleep while draining the dbfifo 326 */ 327 static int dbfifo_drain_delay = 1000; 328 module_param(dbfifo_drain_delay, int, 0644); 329 MODULE_PARM_DESC(dbfifo_drain_delay, 330 "usecs to sleep while draining the dbfifo"); 331 332 static inline int cxgb4_set_addr_hash(struct port_info *pi) 333 { 334 struct adapter *adap = pi->adapter; 335 u64 vec = 0; 336 bool ucast = false; 337 struct hash_mac_addr *entry; 338 339 /* Calculate the hash vector for the updated list and program it */ 340 list_for_each_entry(entry, &adap->mac_hlist, list) { 341 ucast |= is_unicast_ether_addr(entry->addr); 342 vec |= (1ULL << hash_mac_addr(entry->addr)); 343 } 344 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, 345 vec, false); 346 } 347 348 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) 349 { 350 struct port_info *pi = netdev_priv(netdev); 351 struct adapter *adap = pi->adapter; 352 int ret; 353 u64 mhash = 0; 354 u64 uhash = 0; 355 bool free = false; 356 bool ucast = is_unicast_ether_addr(mac_addr); 357 const u8 *maclist[1] = {mac_addr}; 358 struct hash_mac_addr *new_entry; 359 360 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist, 361 NULL, ucast ? &uhash : &mhash, false); 362 if (ret < 0) 363 goto out; 364 /* if hash != 0, then add the addr to hash addr list 365 * so on the end we will calculate the hash for the 366 * list and program it 367 */ 368 if (uhash || mhash) { 369 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); 370 if (!new_entry) 371 return -ENOMEM; 372 ether_addr_copy(new_entry->addr, mac_addr); 373 list_add_tail(&new_entry->list, &adap->mac_hlist); 374 ret = cxgb4_set_addr_hash(pi); 375 } 376 out: 377 return ret < 0 ? ret : 0; 378 } 379 380 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) 381 { 382 struct port_info *pi = netdev_priv(netdev); 383 struct adapter *adap = pi->adapter; 384 int ret; 385 const u8 *maclist[1] = {mac_addr}; 386 struct hash_mac_addr *entry, *tmp; 387 388 /* If the MAC address to be removed is in the hash addr 389 * list, delete it from the list and update hash vector 390 */ 391 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { 392 if (ether_addr_equal(entry->addr, mac_addr)) { 393 list_del(&entry->list); 394 kfree(entry); 395 return cxgb4_set_addr_hash(pi); 396 } 397 } 398 399 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false); 400 return ret < 0 ? -EINVAL : 0; 401 } 402 403 /* 404 * Set Rx properties of a port, such as promiscruity, address filters, and MTU. 405 * If @mtu is -1 it is left unchanged. 406 */ 407 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) 408 { 409 struct port_info *pi = netdev_priv(dev); 410 struct adapter *adapter = pi->adapter; 411 412 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 413 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 414 415 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, 416 (dev->flags & IFF_PROMISC) ? 1 : 0, 417 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, 418 sleep_ok); 419 } 420 421 /** 422 * link_start - enable a port 423 * @dev: the port to enable 424 * 425 * Performs the MAC and PHY actions needed to enable a port. 426 */ 427 static int link_start(struct net_device *dev) 428 { 429 int ret; 430 struct port_info *pi = netdev_priv(dev); 431 unsigned int mb = pi->adapter->pf; 432 433 /* 434 * We do not set address filters and promiscuity here, the stack does 435 * that step explicitly. 436 */ 437 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, 438 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 439 if (ret == 0) { 440 ret = t4_change_mac(pi->adapter, mb, pi->viid, 441 pi->xact_addr_filt, dev->dev_addr, true, 442 true); 443 if (ret >= 0) { 444 pi->xact_addr_filt = ret; 445 ret = 0; 446 } 447 } 448 if (ret == 0) 449 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, 450 &pi->link_cfg); 451 if (ret == 0) { 452 local_bh_disable(); 453 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true, 454 true, CXGB4_DCB_ENABLED); 455 local_bh_enable(); 456 } 457 458 return ret; 459 } 460 461 #ifdef CONFIG_CHELSIO_T4_DCB 462 /* Handle a Data Center Bridging update message from the firmware. */ 463 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) 464 { 465 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); 466 struct net_device *dev = adap->port[adap->chan_map[port]]; 467 int old_dcb_enabled = cxgb4_dcb_enabled(dev); 468 int new_dcb_enabled; 469 470 cxgb4_dcb_handle_fw_update(adap, pcmd); 471 new_dcb_enabled = cxgb4_dcb_enabled(dev); 472 473 /* If the DCB has become enabled or disabled on the port then we're 474 * going to need to set up/tear down DCB Priority parameters for the 475 * TX Queues associated with the port. 476 */ 477 if (new_dcb_enabled != old_dcb_enabled) 478 dcb_tx_queue_prio_enable(dev, new_dcb_enabled); 479 } 480 #endif /* CONFIG_CHELSIO_T4_DCB */ 481 482 /* Response queue handler for the FW event queue. 483 */ 484 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 485 const struct pkt_gl *gl) 486 { 487 u8 opcode = ((const struct rss_header *)rsp)->opcode; 488 489 rsp++; /* skip RSS header */ 490 491 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 492 */ 493 if (unlikely(opcode == CPL_FW4_MSG && 494 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { 495 rsp++; 496 opcode = ((const struct rss_header *)rsp)->opcode; 497 rsp++; 498 if (opcode != CPL_SGE_EGR_UPDATE) { 499 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" 500 , opcode); 501 goto out; 502 } 503 } 504 505 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 506 const struct cpl_sge_egr_update *p = (void *)rsp; 507 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); 508 struct sge_txq *txq; 509 510 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; 511 txq->restarts++; 512 if (txq->q_type == CXGB4_TXQ_ETH) { 513 struct sge_eth_txq *eq; 514 515 eq = container_of(txq, struct sge_eth_txq, q); 516 netif_tx_wake_queue(eq->txq); 517 } else { 518 struct sge_uld_txq *oq; 519 520 oq = container_of(txq, struct sge_uld_txq, q); 521 tasklet_schedule(&oq->qresume_tsk); 522 } 523 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 524 const struct cpl_fw6_msg *p = (void *)rsp; 525 526 #ifdef CONFIG_CHELSIO_T4_DCB 527 const struct fw_port_cmd *pcmd = (const void *)p->data; 528 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); 529 unsigned int action = 530 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); 531 532 if (cmd == FW_PORT_CMD && 533 (action == FW_PORT_ACTION_GET_PORT_INFO || 534 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 535 int port = FW_PORT_CMD_PORTID_G( 536 be32_to_cpu(pcmd->op_to_portid)); 537 struct net_device *dev; 538 int dcbxdis, state_input; 539 540 dev = q->adap->port[q->adap->chan_map[port]]; 541 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO 542 ? !!(pcmd->u.info.dcbxdis_pkd & 543 FW_PORT_CMD_DCBXDIS_F) 544 : !!(pcmd->u.info32.lstatus32_to_cbllen32 & 545 FW_PORT_CMD_DCBXDIS32_F)); 546 state_input = (dcbxdis 547 ? CXGB4_DCB_INPUT_FW_DISABLED 548 : CXGB4_DCB_INPUT_FW_ENABLED); 549 550 cxgb4_dcb_state_fsm(dev, state_input); 551 } 552 553 if (cmd == FW_PORT_CMD && 554 action == FW_PORT_ACTION_L2_DCB_CFG) 555 dcb_rpl(q->adap, pcmd); 556 else 557 #endif 558 if (p->type == 0) 559 t4_handle_fw_rpl(q->adap, p->data); 560 } else if (opcode == CPL_L2T_WRITE_RPL) { 561 const struct cpl_l2t_write_rpl *p = (void *)rsp; 562 563 do_l2t_write_rpl(q->adap, p); 564 } else if (opcode == CPL_SET_TCB_RPL) { 565 const struct cpl_set_tcb_rpl *p = (void *)rsp; 566 567 filter_rpl(q->adap, p); 568 } else 569 dev_err(q->adap->pdev_dev, 570 "unexpected CPL %#x on FW event queue\n", opcode); 571 out: 572 return 0; 573 } 574 575 static void disable_msi(struct adapter *adapter) 576 { 577 if (adapter->flags & USING_MSIX) { 578 pci_disable_msix(adapter->pdev); 579 adapter->flags &= ~USING_MSIX; 580 } else if (adapter->flags & USING_MSI) { 581 pci_disable_msi(adapter->pdev); 582 adapter->flags &= ~USING_MSI; 583 } 584 } 585 586 /* 587 * Interrupt handler for non-data events used with MSI-X. 588 */ 589 static irqreturn_t t4_nondata_intr(int irq, void *cookie) 590 { 591 struct adapter *adap = cookie; 592 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); 593 594 if (v & PFSW_F) { 595 adap->swintr = 1; 596 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); 597 } 598 if (adap->flags & MASTER_PF) 599 t4_slow_intr_handler(adap); 600 return IRQ_HANDLED; 601 } 602 603 /* 604 * Name the MSI-X interrupts. 605 */ 606 static void name_msix_vecs(struct adapter *adap) 607 { 608 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); 609 610 /* non-data interrupts */ 611 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); 612 613 /* FW events */ 614 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", 615 adap->port[0]->name); 616 617 /* Ethernet queues */ 618 for_each_port(adap, j) { 619 struct net_device *d = adap->port[j]; 620 const struct port_info *pi = netdev_priv(d); 621 622 for (i = 0; i < pi->nqsets; i++, msi_idx++) 623 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", 624 d->name, i); 625 } 626 } 627 628 static int request_msix_queue_irqs(struct adapter *adap) 629 { 630 struct sge *s = &adap->sge; 631 int err, ethqidx; 632 int msi_index = 2; 633 634 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, 635 adap->msix_info[1].desc, &s->fw_evtq); 636 if (err) 637 return err; 638 639 for_each_ethrxq(s, ethqidx) { 640 err = request_irq(adap->msix_info[msi_index].vec, 641 t4_sge_intr_msix, 0, 642 adap->msix_info[msi_index].desc, 643 &s->ethrxq[ethqidx].rspq); 644 if (err) 645 goto unwind; 646 msi_index++; 647 } 648 return 0; 649 650 unwind: 651 while (--ethqidx >= 0) 652 free_irq(adap->msix_info[--msi_index].vec, 653 &s->ethrxq[ethqidx].rspq); 654 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 655 return err; 656 } 657 658 static void free_msix_queue_irqs(struct adapter *adap) 659 { 660 int i, msi_index = 2; 661 struct sge *s = &adap->sge; 662 663 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 664 for_each_ethrxq(s, i) 665 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); 666 } 667 668 /** 669 * cxgb4_write_rss - write the RSS table for a given port 670 * @pi: the port 671 * @queues: array of queue indices for RSS 672 * 673 * Sets up the portion of the HW RSS table for the port's VI to distribute 674 * packets to the Rx queues in @queues. 675 * Should never be called before setting up sge eth rx queues 676 */ 677 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 678 { 679 u16 *rss; 680 int i, err; 681 struct adapter *adapter = pi->adapter; 682 const struct sge_eth_rxq *rxq; 683 684 rxq = &adapter->sge.ethrxq[pi->first_qset]; 685 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL); 686 if (!rss) 687 return -ENOMEM; 688 689 /* map the queue indices to queue ids */ 690 for (i = 0; i < pi->rss_size; i++, queues++) 691 rss[i] = rxq[*queues].rspq.abs_id; 692 693 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 694 pi->rss_size, rss, pi->rss_size); 695 /* If Tunnel All Lookup isn't specified in the global RSS 696 * Configuration, then we need to specify a default Ingress 697 * Queue for any ingress packets which aren't hashed. We'll 698 * use our first ingress queue ... 699 */ 700 if (!err) 701 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 702 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | 703 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | 704 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | 705 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | 706 FW_RSS_VI_CONFIG_CMD_UDPEN_F, 707 rss[0]); 708 kfree(rss); 709 return err; 710 } 711 712 /** 713 * setup_rss - configure RSS 714 * @adap: the adapter 715 * 716 * Sets up RSS for each port. 717 */ 718 static int setup_rss(struct adapter *adap) 719 { 720 int i, j, err; 721 722 for_each_port(adap, i) { 723 const struct port_info *pi = adap2pinfo(adap, i); 724 725 /* Fill default values with equal distribution */ 726 for (j = 0; j < pi->rss_size; j++) 727 pi->rss[j] = j % pi->nqsets; 728 729 err = cxgb4_write_rss(pi, pi->rss); 730 if (err) 731 return err; 732 } 733 return 0; 734 } 735 736 /* 737 * Return the channel of the ingress queue with the given qid. 738 */ 739 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) 740 { 741 qid -= p->ingr_start; 742 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; 743 } 744 745 /* 746 * Wait until all NAPI handlers are descheduled. 747 */ 748 static void quiesce_rx(struct adapter *adap) 749 { 750 int i; 751 752 for (i = 0; i < adap->sge.ingr_sz; i++) { 753 struct sge_rspq *q = adap->sge.ingr_map[i]; 754 755 if (q && q->handler) 756 napi_disable(&q->napi); 757 } 758 } 759 760 /* Disable interrupt and napi handler */ 761 static void disable_interrupts(struct adapter *adap) 762 { 763 if (adap->flags & FULL_INIT_DONE) { 764 t4_intr_disable(adap); 765 if (adap->flags & USING_MSIX) { 766 free_msix_queue_irqs(adap); 767 free_irq(adap->msix_info[0].vec, adap); 768 } else { 769 free_irq(adap->pdev->irq, adap); 770 } 771 quiesce_rx(adap); 772 } 773 } 774 775 /* 776 * Enable NAPI scheduling and interrupt generation for all Rx queues. 777 */ 778 static void enable_rx(struct adapter *adap) 779 { 780 int i; 781 782 for (i = 0; i < adap->sge.ingr_sz; i++) { 783 struct sge_rspq *q = adap->sge.ingr_map[i]; 784 785 if (!q) 786 continue; 787 if (q->handler) 788 napi_enable(&q->napi); 789 790 /* 0-increment GTS to start the timer and enable interrupts */ 791 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 792 SEINTARM_V(q->intr_params) | 793 INGRESSQID_V(q->cntxt_id)); 794 } 795 } 796 797 798 static int setup_fw_sge_queues(struct adapter *adap) 799 { 800 struct sge *s = &adap->sge; 801 int err = 0; 802 803 bitmap_zero(s->starving_fl, s->egr_sz); 804 bitmap_zero(s->txq_maperr, s->egr_sz); 805 806 if (adap->flags & USING_MSIX) 807 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */ 808 else { 809 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, 810 NULL, NULL, NULL, -1); 811 if (err) 812 return err; 813 adap->msi_idx = -((int)s->intrq.abs_id + 1); 814 } 815 816 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], 817 adap->msi_idx, NULL, fwevtq_handler, NULL, -1); 818 if (err) 819 t4_free_sge_resources(adap); 820 return err; 821 } 822 823 /** 824 * setup_sge_queues - configure SGE Tx/Rx/response queues 825 * @adap: the adapter 826 * 827 * Determines how many sets of SGE queues to use and initializes them. 828 * We support multiple queue sets per port if we have MSI-X, otherwise 829 * just one queue set per port. 830 */ 831 static int setup_sge_queues(struct adapter *adap) 832 { 833 int err, i, j; 834 struct sge *s = &adap->sge; 835 struct sge_uld_rxq_info *rxq_info = NULL; 836 unsigned int cmplqid = 0; 837 838 if (is_uld(adap)) 839 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; 840 841 for_each_port(adap, i) { 842 struct net_device *dev = adap->port[i]; 843 struct port_info *pi = netdev_priv(dev); 844 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; 845 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; 846 847 for (j = 0; j < pi->nqsets; j++, q++) { 848 if (adap->msi_idx > 0) 849 adap->msi_idx++; 850 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, 851 adap->msi_idx, &q->fl, 852 t4_ethrx_handler, 853 NULL, 854 t4_get_tp_ch_map(adap, 855 pi->tx_chan)); 856 if (err) 857 goto freeout; 858 q->rspq.idx = j; 859 memset(&q->stats, 0, sizeof(q->stats)); 860 } 861 for (j = 0; j < pi->nqsets; j++, t++) { 862 err = t4_sge_alloc_eth_txq(adap, t, dev, 863 netdev_get_tx_queue(dev, j), 864 s->fw_evtq.cntxt_id); 865 if (err) 866 goto freeout; 867 } 868 } 869 870 for_each_port(adap, i) { 871 /* Note that cmplqid below is 0 if we don't 872 * have RDMA queues, and that's the right value. 873 */ 874 if (rxq_info) 875 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; 876 877 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], 878 s->fw_evtq.cntxt_id, cmplqid); 879 if (err) 880 goto freeout; 881 } 882 883 if (!is_t4(adap->params.chip)) { 884 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0], 885 netdev_get_tx_queue(adap->port[0], 0) 886 , s->fw_evtq.cntxt_id); 887 if (err) 888 goto freeout; 889 } 890 891 t4_write_reg(adap, is_t4(adap->params.chip) ? 892 MPS_TRC_RSS_CONTROL_A : 893 MPS_T5_TRC_RSS_CONTROL_A, 894 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | 895 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); 896 return 0; 897 freeout: 898 t4_free_sge_resources(adap); 899 return err; 900 } 901 902 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, 903 void *accel_priv, select_queue_fallback_t fallback) 904 { 905 int txq; 906 907 #ifdef CONFIG_CHELSIO_T4_DCB 908 /* If a Data Center Bridging has been successfully negotiated on this 909 * link then we'll use the skb's priority to map it to a TX Queue. 910 * The skb's priority is determined via the VLAN Tag Priority Code 911 * Point field. 912 */ 913 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) { 914 u16 vlan_tci; 915 int err; 916 917 err = vlan_get_tag(skb, &vlan_tci); 918 if (unlikely(err)) { 919 if (net_ratelimit()) 920 netdev_warn(dev, 921 "TX Packet without VLAN Tag on DCB Link\n"); 922 txq = 0; 923 } else { 924 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 925 #ifdef CONFIG_CHELSIO_T4_FCOE 926 if (skb->protocol == htons(ETH_P_FCOE)) 927 txq = skb->priority & 0x7; 928 #endif /* CONFIG_CHELSIO_T4_FCOE */ 929 } 930 return txq; 931 } 932 #endif /* CONFIG_CHELSIO_T4_DCB */ 933 934 if (select_queue) { 935 txq = (skb_rx_queue_recorded(skb) 936 ? skb_get_rx_queue(skb) 937 : smp_processor_id()); 938 939 while (unlikely(txq >= dev->real_num_tx_queues)) 940 txq -= dev->real_num_tx_queues; 941 942 return txq; 943 } 944 945 return fallback(dev, skb) % dev->real_num_tx_queues; 946 } 947 948 static int closest_timer(const struct sge *s, int time) 949 { 950 int i, delta, match = 0, min_delta = INT_MAX; 951 952 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 953 delta = time - s->timer_val[i]; 954 if (delta < 0) 955 delta = -delta; 956 if (delta < min_delta) { 957 min_delta = delta; 958 match = i; 959 } 960 } 961 return match; 962 } 963 964 static int closest_thres(const struct sge *s, int thres) 965 { 966 int i, delta, match = 0, min_delta = INT_MAX; 967 968 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 969 delta = thres - s->counter_val[i]; 970 if (delta < 0) 971 delta = -delta; 972 if (delta < min_delta) { 973 min_delta = delta; 974 match = i; 975 } 976 } 977 return match; 978 } 979 980 /** 981 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 982 * @q: the Rx queue 983 * @us: the hold-off time in us, or 0 to disable timer 984 * @cnt: the hold-off packet count, or 0 to disable counter 985 * 986 * Sets an Rx queue's interrupt hold-off time and packet count. At least 987 * one of the two needs to be enabled for the queue to generate interrupts. 988 */ 989 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, 990 unsigned int us, unsigned int cnt) 991 { 992 struct adapter *adap = q->adap; 993 994 if ((us | cnt) == 0) 995 cnt = 1; 996 997 if (cnt) { 998 int err; 999 u32 v, new_idx; 1000 1001 new_idx = closest_thres(&adap->sge, cnt); 1002 if (q->desc && q->pktcnt_idx != new_idx) { 1003 /* the queue has already been created, update it */ 1004 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 1005 FW_PARAMS_PARAM_X_V( 1006 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 1007 FW_PARAMS_PARAM_YZ_V(q->cntxt_id); 1008 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 1009 &v, &new_idx); 1010 if (err) 1011 return err; 1012 } 1013 q->pktcnt_idx = new_idx; 1014 } 1015 1016 us = us == 0 ? 6 : closest_timer(&adap->sge, us); 1017 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); 1018 return 0; 1019 } 1020 1021 static int cxgb_set_features(struct net_device *dev, netdev_features_t features) 1022 { 1023 const struct port_info *pi = netdev_priv(dev); 1024 netdev_features_t changed = dev->features ^ features; 1025 int err; 1026 1027 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) 1028 return 0; 1029 1030 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, 1031 -1, -1, -1, 1032 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); 1033 if (unlikely(err)) 1034 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; 1035 return err; 1036 } 1037 1038 static int setup_debugfs(struct adapter *adap) 1039 { 1040 if (IS_ERR_OR_NULL(adap->debugfs_root)) 1041 return -1; 1042 1043 #ifdef CONFIG_DEBUG_FS 1044 t4_setup_debugfs(adap); 1045 #endif 1046 return 0; 1047 } 1048 1049 /* 1050 * upper-layer driver support 1051 */ 1052 1053 /* 1054 * Allocate an active-open TID and set it to the supplied value. 1055 */ 1056 int cxgb4_alloc_atid(struct tid_info *t, void *data) 1057 { 1058 int atid = -1; 1059 1060 spin_lock_bh(&t->atid_lock); 1061 if (t->afree) { 1062 union aopen_entry *p = t->afree; 1063 1064 atid = (p - t->atid_tab) + t->atid_base; 1065 t->afree = p->next; 1066 p->data = data; 1067 t->atids_in_use++; 1068 } 1069 spin_unlock_bh(&t->atid_lock); 1070 return atid; 1071 } 1072 EXPORT_SYMBOL(cxgb4_alloc_atid); 1073 1074 /* 1075 * Release an active-open TID. 1076 */ 1077 void cxgb4_free_atid(struct tid_info *t, unsigned int atid) 1078 { 1079 union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; 1080 1081 spin_lock_bh(&t->atid_lock); 1082 p->next = t->afree; 1083 t->afree = p; 1084 t->atids_in_use--; 1085 spin_unlock_bh(&t->atid_lock); 1086 } 1087 EXPORT_SYMBOL(cxgb4_free_atid); 1088 1089 /* 1090 * Allocate a server TID and set it to the supplied value. 1091 */ 1092 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) 1093 { 1094 int stid; 1095 1096 spin_lock_bh(&t->stid_lock); 1097 if (family == PF_INET) { 1098 stid = find_first_zero_bit(t->stid_bmap, t->nstids); 1099 if (stid < t->nstids) 1100 __set_bit(stid, t->stid_bmap); 1101 else 1102 stid = -1; 1103 } else { 1104 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); 1105 if (stid < 0) 1106 stid = -1; 1107 } 1108 if (stid >= 0) { 1109 t->stid_tab[stid].data = data; 1110 stid += t->stid_base; 1111 /* IPv6 requires max of 520 bits or 16 cells in TCAM 1112 * This is equivalent to 4 TIDs. With CLIP enabled it 1113 * needs 2 TIDs. 1114 */ 1115 if (family == PF_INET6) { 1116 t->stids_in_use += 2; 1117 t->v6_stids_in_use += 2; 1118 } else { 1119 t->stids_in_use++; 1120 } 1121 } 1122 spin_unlock_bh(&t->stid_lock); 1123 return stid; 1124 } 1125 EXPORT_SYMBOL(cxgb4_alloc_stid); 1126 1127 /* Allocate a server filter TID and set it to the supplied value. 1128 */ 1129 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) 1130 { 1131 int stid; 1132 1133 spin_lock_bh(&t->stid_lock); 1134 if (family == PF_INET) { 1135 stid = find_next_zero_bit(t->stid_bmap, 1136 t->nstids + t->nsftids, t->nstids); 1137 if (stid < (t->nstids + t->nsftids)) 1138 __set_bit(stid, t->stid_bmap); 1139 else 1140 stid = -1; 1141 } else { 1142 stid = -1; 1143 } 1144 if (stid >= 0) { 1145 t->stid_tab[stid].data = data; 1146 stid -= t->nstids; 1147 stid += t->sftid_base; 1148 t->sftids_in_use++; 1149 } 1150 spin_unlock_bh(&t->stid_lock); 1151 return stid; 1152 } 1153 EXPORT_SYMBOL(cxgb4_alloc_sftid); 1154 1155 /* Release a server TID. 1156 */ 1157 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) 1158 { 1159 /* Is it a server filter TID? */ 1160 if (t->nsftids && (stid >= t->sftid_base)) { 1161 stid -= t->sftid_base; 1162 stid += t->nstids; 1163 } else { 1164 stid -= t->stid_base; 1165 } 1166 1167 spin_lock_bh(&t->stid_lock); 1168 if (family == PF_INET) 1169 __clear_bit(stid, t->stid_bmap); 1170 else 1171 bitmap_release_region(t->stid_bmap, stid, 1); 1172 t->stid_tab[stid].data = NULL; 1173 if (stid < t->nstids) { 1174 if (family == PF_INET6) { 1175 t->stids_in_use -= 2; 1176 t->v6_stids_in_use -= 2; 1177 } else { 1178 t->stids_in_use--; 1179 } 1180 } else { 1181 t->sftids_in_use--; 1182 } 1183 1184 spin_unlock_bh(&t->stid_lock); 1185 } 1186 EXPORT_SYMBOL(cxgb4_free_stid); 1187 1188 /* 1189 * Populate a TID_RELEASE WR. Caller must properly size the skb. 1190 */ 1191 static void mk_tid_release(struct sk_buff *skb, unsigned int chan, 1192 unsigned int tid) 1193 { 1194 struct cpl_tid_release *req; 1195 1196 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); 1197 req = __skb_put(skb, sizeof(*req)); 1198 INIT_TP_WR(req, tid); 1199 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); 1200 } 1201 1202 /* 1203 * Queue a TID release request and if necessary schedule a work queue to 1204 * process it. 1205 */ 1206 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, 1207 unsigned int tid) 1208 { 1209 void **p = &t->tid_tab[tid]; 1210 struct adapter *adap = container_of(t, struct adapter, tids); 1211 1212 spin_lock_bh(&adap->tid_release_lock); 1213 *p = adap->tid_release_head; 1214 /* Low 2 bits encode the Tx channel number */ 1215 adap->tid_release_head = (void **)((uintptr_t)p | chan); 1216 if (!adap->tid_release_task_busy) { 1217 adap->tid_release_task_busy = true; 1218 queue_work(adap->workq, &adap->tid_release_task); 1219 } 1220 spin_unlock_bh(&adap->tid_release_lock); 1221 } 1222 1223 /* 1224 * Process the list of pending TID release requests. 1225 */ 1226 static void process_tid_release_list(struct work_struct *work) 1227 { 1228 struct sk_buff *skb; 1229 struct adapter *adap; 1230 1231 adap = container_of(work, struct adapter, tid_release_task); 1232 1233 spin_lock_bh(&adap->tid_release_lock); 1234 while (adap->tid_release_head) { 1235 void **p = adap->tid_release_head; 1236 unsigned int chan = (uintptr_t)p & 3; 1237 p = (void *)p - chan; 1238 1239 adap->tid_release_head = *p; 1240 *p = NULL; 1241 spin_unlock_bh(&adap->tid_release_lock); 1242 1243 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), 1244 GFP_KERNEL))) 1245 schedule_timeout_uninterruptible(1); 1246 1247 mk_tid_release(skb, chan, p - adap->tids.tid_tab); 1248 t4_ofld_send(adap, skb); 1249 spin_lock_bh(&adap->tid_release_lock); 1250 } 1251 adap->tid_release_task_busy = false; 1252 spin_unlock_bh(&adap->tid_release_lock); 1253 } 1254 1255 /* 1256 * Release a TID and inform HW. If we are unable to allocate the release 1257 * message we defer to a work queue. 1258 */ 1259 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 1260 unsigned short family) 1261 { 1262 struct sk_buff *skb; 1263 struct adapter *adap = container_of(t, struct adapter, tids); 1264 1265 WARN_ON(tid >= t->ntids); 1266 1267 if (t->tid_tab[tid]) { 1268 t->tid_tab[tid] = NULL; 1269 atomic_dec(&t->conns_in_use); 1270 if (t->hash_base && (tid >= t->hash_base)) { 1271 if (family == AF_INET6) 1272 atomic_sub(2, &t->hash_tids_in_use); 1273 else 1274 atomic_dec(&t->hash_tids_in_use); 1275 } else { 1276 if (family == AF_INET6) 1277 atomic_sub(2, &t->tids_in_use); 1278 else 1279 atomic_dec(&t->tids_in_use); 1280 } 1281 } 1282 1283 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); 1284 if (likely(skb)) { 1285 mk_tid_release(skb, chan, tid); 1286 t4_ofld_send(adap, skb); 1287 } else 1288 cxgb4_queue_tid_release(t, chan, tid); 1289 } 1290 EXPORT_SYMBOL(cxgb4_remove_tid); 1291 1292 /* 1293 * Allocate and initialize the TID tables. Returns 0 on success. 1294 */ 1295 static int tid_init(struct tid_info *t) 1296 { 1297 struct adapter *adap = container_of(t, struct adapter, tids); 1298 unsigned int max_ftids = t->nftids + t->nsftids; 1299 unsigned int natids = t->natids; 1300 unsigned int stid_bmap_size; 1301 unsigned int ftid_bmap_size; 1302 size_t size; 1303 1304 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); 1305 ftid_bmap_size = BITS_TO_LONGS(t->nftids); 1306 size = t->ntids * sizeof(*t->tid_tab) + 1307 natids * sizeof(*t->atid_tab) + 1308 t->nstids * sizeof(*t->stid_tab) + 1309 t->nsftids * sizeof(*t->stid_tab) + 1310 stid_bmap_size * sizeof(long) + 1311 max_ftids * sizeof(*t->ftid_tab) + 1312 ftid_bmap_size * sizeof(long); 1313 1314 t->tid_tab = kvzalloc(size, GFP_KERNEL); 1315 if (!t->tid_tab) 1316 return -ENOMEM; 1317 1318 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 1319 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; 1320 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; 1321 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; 1322 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; 1323 spin_lock_init(&t->stid_lock); 1324 spin_lock_init(&t->atid_lock); 1325 spin_lock_init(&t->ftid_lock); 1326 1327 t->stids_in_use = 0; 1328 t->v6_stids_in_use = 0; 1329 t->sftids_in_use = 0; 1330 t->afree = NULL; 1331 t->atids_in_use = 0; 1332 atomic_set(&t->tids_in_use, 0); 1333 atomic_set(&t->conns_in_use, 0); 1334 atomic_set(&t->hash_tids_in_use, 0); 1335 1336 /* Setup the free list for atid_tab and clear the stid bitmap. */ 1337 if (natids) { 1338 while (--natids) 1339 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 1340 t->afree = t->atid_tab; 1341 } 1342 1343 if (is_offload(adap)) { 1344 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1345 /* Reserve stid 0 for T4/T5 adapters */ 1346 if (!t->stid_base && 1347 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1348 __set_bit(0, t->stid_bmap); 1349 } 1350 1351 bitmap_zero(t->ftid_bmap, t->nftids); 1352 return 0; 1353 } 1354 1355 /** 1356 * cxgb4_create_server - create an IP server 1357 * @dev: the device 1358 * @stid: the server TID 1359 * @sip: local IP address to bind server to 1360 * @sport: the server's TCP port 1361 * @queue: queue to direct messages from this server to 1362 * 1363 * Create an IP server for the given port and address. 1364 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1365 */ 1366 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 1367 __be32 sip, __be16 sport, __be16 vlan, 1368 unsigned int queue) 1369 { 1370 unsigned int chan; 1371 struct sk_buff *skb; 1372 struct adapter *adap; 1373 struct cpl_pass_open_req *req; 1374 int ret; 1375 1376 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1377 if (!skb) 1378 return -ENOMEM; 1379 1380 adap = netdev2adap(dev); 1381 req = __skb_put(skb, sizeof(*req)); 1382 INIT_TP_WR(req, 0); 1383 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); 1384 req->local_port = sport; 1385 req->peer_port = htons(0); 1386 req->local_ip = sip; 1387 req->peer_ip = htonl(0); 1388 chan = rxq_to_chan(&adap->sge, queue); 1389 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1390 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1391 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1392 ret = t4_mgmt_tx(adap, skb); 1393 return net_xmit_eval(ret); 1394 } 1395 EXPORT_SYMBOL(cxgb4_create_server); 1396 1397 /* cxgb4_create_server6 - create an IPv6 server 1398 * @dev: the device 1399 * @stid: the server TID 1400 * @sip: local IPv6 address to bind server to 1401 * @sport: the server's TCP port 1402 * @queue: queue to direct messages from this server to 1403 * 1404 * Create an IPv6 server for the given port and address. 1405 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1406 */ 1407 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 1408 const struct in6_addr *sip, __be16 sport, 1409 unsigned int queue) 1410 { 1411 unsigned int chan; 1412 struct sk_buff *skb; 1413 struct adapter *adap; 1414 struct cpl_pass_open_req6 *req; 1415 int ret; 1416 1417 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1418 if (!skb) 1419 return -ENOMEM; 1420 1421 adap = netdev2adap(dev); 1422 req = __skb_put(skb, sizeof(*req)); 1423 INIT_TP_WR(req, 0); 1424 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); 1425 req->local_port = sport; 1426 req->peer_port = htons(0); 1427 req->local_ip_hi = *(__be64 *)(sip->s6_addr); 1428 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); 1429 req->peer_ip_hi = cpu_to_be64(0); 1430 req->peer_ip_lo = cpu_to_be64(0); 1431 chan = rxq_to_chan(&adap->sge, queue); 1432 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1433 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1434 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1435 ret = t4_mgmt_tx(adap, skb); 1436 return net_xmit_eval(ret); 1437 } 1438 EXPORT_SYMBOL(cxgb4_create_server6); 1439 1440 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 1441 unsigned int queue, bool ipv6) 1442 { 1443 struct sk_buff *skb; 1444 struct adapter *adap; 1445 struct cpl_close_listsvr_req *req; 1446 int ret; 1447 1448 adap = netdev2adap(dev); 1449 1450 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1451 if (!skb) 1452 return -ENOMEM; 1453 1454 req = __skb_put(skb, sizeof(*req)); 1455 INIT_TP_WR(req, 0); 1456 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); 1457 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : 1458 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); 1459 ret = t4_mgmt_tx(adap, skb); 1460 return net_xmit_eval(ret); 1461 } 1462 EXPORT_SYMBOL(cxgb4_remove_server); 1463 1464 /** 1465 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU 1466 * @mtus: the HW MTU table 1467 * @mtu: the target MTU 1468 * @idx: index of selected entry in the MTU table 1469 * 1470 * Returns the index and the value in the HW MTU table that is closest to 1471 * but does not exceed @mtu, unless @mtu is smaller than any value in the 1472 * table, in which case that smallest available value is selected. 1473 */ 1474 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 1475 unsigned int *idx) 1476 { 1477 unsigned int i = 0; 1478 1479 while (i < NMTUS - 1 && mtus[i + 1] <= mtu) 1480 ++i; 1481 if (idx) 1482 *idx = i; 1483 return mtus[i]; 1484 } 1485 EXPORT_SYMBOL(cxgb4_best_mtu); 1486 1487 /** 1488 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned 1489 * @mtus: the HW MTU table 1490 * @header_size: Header Size 1491 * @data_size_max: maximum Data Segment Size 1492 * @data_size_align: desired Data Segment Size Alignment (2^N) 1493 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) 1494 * 1495 * Similar to cxgb4_best_mtu() but instead of searching the Hardware 1496 * MTU Table based solely on a Maximum MTU parameter, we break that 1497 * parameter up into a Header Size and Maximum Data Segment Size, and 1498 * provide a desired Data Segment Size Alignment. If we find an MTU in 1499 * the Hardware MTU Table which will result in a Data Segment Size with 1500 * the requested alignment _and_ that MTU isn't "too far" from the 1501 * closest MTU, then we'll return that rather than the closest MTU. 1502 */ 1503 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 1504 unsigned short header_size, 1505 unsigned short data_size_max, 1506 unsigned short data_size_align, 1507 unsigned int *mtu_idxp) 1508 { 1509 unsigned short max_mtu = header_size + data_size_max; 1510 unsigned short data_size_align_mask = data_size_align - 1; 1511 int mtu_idx, aligned_mtu_idx; 1512 1513 /* Scan the MTU Table till we find an MTU which is larger than our 1514 * Maximum MTU or we reach the end of the table. Along the way, 1515 * record the last MTU found, if any, which will result in a Data 1516 * Segment Length matching the requested alignment. 1517 */ 1518 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { 1519 unsigned short data_size = mtus[mtu_idx] - header_size; 1520 1521 /* If this MTU minus the Header Size would result in a 1522 * Data Segment Size of the desired alignment, remember it. 1523 */ 1524 if ((data_size & data_size_align_mask) == 0) 1525 aligned_mtu_idx = mtu_idx; 1526 1527 /* If we're not at the end of the Hardware MTU Table and the 1528 * next element is larger than our Maximum MTU, drop out of 1529 * the loop. 1530 */ 1531 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) 1532 break; 1533 } 1534 1535 /* If we fell out of the loop because we ran to the end of the table, 1536 * then we just have to use the last [largest] entry. 1537 */ 1538 if (mtu_idx == NMTUS) 1539 mtu_idx--; 1540 1541 /* If we found an MTU which resulted in the requested Data Segment 1542 * Length alignment and that's "not far" from the largest MTU which is 1543 * less than or equal to the maximum MTU, then use that. 1544 */ 1545 if (aligned_mtu_idx >= 0 && 1546 mtu_idx - aligned_mtu_idx <= 1) 1547 mtu_idx = aligned_mtu_idx; 1548 1549 /* If the caller has passed in an MTU Index pointer, pass the 1550 * MTU Index back. Return the MTU value. 1551 */ 1552 if (mtu_idxp) 1553 *mtu_idxp = mtu_idx; 1554 return mtus[mtu_idx]; 1555 } 1556 EXPORT_SYMBOL(cxgb4_best_aligned_mtu); 1557 1558 /** 1559 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI 1560 * @chip: chip type 1561 * @viid: VI id of the given port 1562 * 1563 * Return the SMT index for this VI. 1564 */ 1565 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid) 1566 { 1567 /* In T4/T5, SMT contains 256 SMAC entries organized in 1568 * 128 rows of 2 entries each. 1569 * In T6, SMT contains 256 SMAC entries in 256 rows. 1570 * TODO: The below code needs to be updated when we add support 1571 * for 256 VFs. 1572 */ 1573 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 1574 return ((viid & 0x7f) << 1); 1575 else 1576 return (viid & 0x7f); 1577 } 1578 EXPORT_SYMBOL(cxgb4_tp_smt_idx); 1579 1580 /** 1581 * cxgb4_port_chan - get the HW channel of a port 1582 * @dev: the net device for the port 1583 * 1584 * Return the HW Tx channel of the given port. 1585 */ 1586 unsigned int cxgb4_port_chan(const struct net_device *dev) 1587 { 1588 return netdev2pinfo(dev)->tx_chan; 1589 } 1590 EXPORT_SYMBOL(cxgb4_port_chan); 1591 1592 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 1593 { 1594 struct adapter *adap = netdev2adap(dev); 1595 u32 v1, v2, lp_count, hp_count; 1596 1597 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1598 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1599 if (is_t4(adap->params.chip)) { 1600 lp_count = LP_COUNT_G(v1); 1601 hp_count = HP_COUNT_G(v1); 1602 } else { 1603 lp_count = LP_COUNT_T5_G(v1); 1604 hp_count = HP_COUNT_T5_G(v2); 1605 } 1606 return lpfifo ? lp_count : hp_count; 1607 } 1608 EXPORT_SYMBOL(cxgb4_dbfifo_count); 1609 1610 /** 1611 * cxgb4_port_viid - get the VI id of a port 1612 * @dev: the net device for the port 1613 * 1614 * Return the VI id of the given port. 1615 */ 1616 unsigned int cxgb4_port_viid(const struct net_device *dev) 1617 { 1618 return netdev2pinfo(dev)->viid; 1619 } 1620 EXPORT_SYMBOL(cxgb4_port_viid); 1621 1622 /** 1623 * cxgb4_port_idx - get the index of a port 1624 * @dev: the net device for the port 1625 * 1626 * Return the index of the given port. 1627 */ 1628 unsigned int cxgb4_port_idx(const struct net_device *dev) 1629 { 1630 return netdev2pinfo(dev)->port_id; 1631 } 1632 EXPORT_SYMBOL(cxgb4_port_idx); 1633 1634 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 1635 struct tp_tcp_stats *v6) 1636 { 1637 struct adapter *adap = pci_get_drvdata(pdev); 1638 1639 spin_lock(&adap->stats_lock); 1640 t4_tp_get_tcp_stats(adap, v4, v6); 1641 spin_unlock(&adap->stats_lock); 1642 } 1643 EXPORT_SYMBOL(cxgb4_get_tcp_stats); 1644 1645 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 1646 const unsigned int *pgsz_order) 1647 { 1648 struct adapter *adap = netdev2adap(dev); 1649 1650 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); 1651 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | 1652 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | 1653 HPZ3_V(pgsz_order[3])); 1654 } 1655 EXPORT_SYMBOL(cxgb4_iscsi_init); 1656 1657 int cxgb4_flush_eq_cache(struct net_device *dev) 1658 { 1659 struct adapter *adap = netdev2adap(dev); 1660 1661 return t4_sge_ctxt_flush(adap, adap->mbox); 1662 } 1663 EXPORT_SYMBOL(cxgb4_flush_eq_cache); 1664 1665 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 1666 { 1667 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; 1668 __be64 indices; 1669 int ret; 1670 1671 spin_lock(&adap->win0_lock); 1672 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, 1673 sizeof(indices), (__be32 *)&indices, 1674 T4_MEMORY_READ); 1675 spin_unlock(&adap->win0_lock); 1676 if (!ret) { 1677 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; 1678 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; 1679 } 1680 return ret; 1681 } 1682 1683 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 1684 u16 size) 1685 { 1686 struct adapter *adap = netdev2adap(dev); 1687 u16 hw_pidx, hw_cidx; 1688 int ret; 1689 1690 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); 1691 if (ret) 1692 goto out; 1693 1694 if (pidx != hw_pidx) { 1695 u16 delta; 1696 u32 val; 1697 1698 if (pidx >= hw_pidx) 1699 delta = pidx - hw_pidx; 1700 else 1701 delta = size - hw_pidx + pidx; 1702 1703 if (is_t4(adap->params.chip)) 1704 val = PIDX_V(delta); 1705 else 1706 val = PIDX_T5_V(delta); 1707 wmb(); 1708 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1709 QID_V(qid) | val); 1710 } 1711 out: 1712 return ret; 1713 } 1714 EXPORT_SYMBOL(cxgb4_sync_txq_pidx); 1715 1716 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) 1717 { 1718 struct adapter *adap; 1719 u32 offset, memtype, memaddr; 1720 u32 edc0_size, edc1_size, mc0_size, mc1_size, size; 1721 u32 edc0_end, edc1_end, mc0_end, mc1_end; 1722 int ret; 1723 1724 adap = netdev2adap(dev); 1725 1726 offset = ((stag >> 8) * 32) + adap->vres.stag.start; 1727 1728 /* Figure out where the offset lands in the Memory Type/Address scheme. 1729 * This code assumes that the memory is laid out starting at offset 0 1730 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 1731 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have 1732 * MC0, and some have both MC0 and MC1. 1733 */ 1734 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 1735 edc0_size = EDRAM0_SIZE_G(size) << 20; 1736 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 1737 edc1_size = EDRAM1_SIZE_G(size) << 20; 1738 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 1739 mc0_size = EXT_MEM0_SIZE_G(size) << 20; 1740 1741 edc0_end = edc0_size; 1742 edc1_end = edc0_end + edc1_size; 1743 mc0_end = edc1_end + mc0_size; 1744 1745 if (offset < edc0_end) { 1746 memtype = MEM_EDC0; 1747 memaddr = offset; 1748 } else if (offset < edc1_end) { 1749 memtype = MEM_EDC1; 1750 memaddr = offset - edc0_end; 1751 } else { 1752 if (offset < mc0_end) { 1753 memtype = MEM_MC0; 1754 memaddr = offset - edc1_end; 1755 } else if (is_t5(adap->params.chip)) { 1756 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 1757 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 1758 mc1_end = mc0_end + mc1_size; 1759 if (offset < mc1_end) { 1760 memtype = MEM_MC1; 1761 memaddr = offset - mc0_end; 1762 } else { 1763 /* offset beyond the end of any memory */ 1764 goto err; 1765 } 1766 } else { 1767 /* T4/T6 only has a single memory channel */ 1768 goto err; 1769 } 1770 } 1771 1772 spin_lock(&adap->win0_lock); 1773 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); 1774 spin_unlock(&adap->win0_lock); 1775 return ret; 1776 1777 err: 1778 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", 1779 stag, offset); 1780 return -EINVAL; 1781 } 1782 EXPORT_SYMBOL(cxgb4_read_tpte); 1783 1784 u64 cxgb4_read_sge_timestamp(struct net_device *dev) 1785 { 1786 u32 hi, lo; 1787 struct adapter *adap; 1788 1789 adap = netdev2adap(dev); 1790 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); 1791 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); 1792 1793 return ((u64)hi << 32) | (u64)lo; 1794 } 1795 EXPORT_SYMBOL(cxgb4_read_sge_timestamp); 1796 1797 int cxgb4_bar2_sge_qregs(struct net_device *dev, 1798 unsigned int qid, 1799 enum cxgb4_bar2_qtype qtype, 1800 int user, 1801 u64 *pbar2_qoffset, 1802 unsigned int *pbar2_qid) 1803 { 1804 return t4_bar2_sge_qregs(netdev2adap(dev), 1805 qid, 1806 (qtype == CXGB4_BAR2_QTYPE_EGRESS 1807 ? T4_BAR2_QTYPE_EGRESS 1808 : T4_BAR2_QTYPE_INGRESS), 1809 user, 1810 pbar2_qoffset, 1811 pbar2_qid); 1812 } 1813 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); 1814 1815 static struct pci_driver cxgb4_driver; 1816 1817 static void check_neigh_update(struct neighbour *neigh) 1818 { 1819 const struct device *parent; 1820 const struct net_device *netdev = neigh->dev; 1821 1822 if (is_vlan_dev(netdev)) 1823 netdev = vlan_dev_real_dev(netdev); 1824 parent = netdev->dev.parent; 1825 if (parent && parent->driver == &cxgb4_driver.driver) 1826 t4_l2t_update(dev_get_drvdata(parent), neigh); 1827 } 1828 1829 static int netevent_cb(struct notifier_block *nb, unsigned long event, 1830 void *data) 1831 { 1832 switch (event) { 1833 case NETEVENT_NEIGH_UPDATE: 1834 check_neigh_update(data); 1835 break; 1836 case NETEVENT_REDIRECT: 1837 default: 1838 break; 1839 } 1840 return 0; 1841 } 1842 1843 static bool netevent_registered; 1844 static struct notifier_block cxgb4_netevent_nb = { 1845 .notifier_call = netevent_cb 1846 }; 1847 1848 static void drain_db_fifo(struct adapter *adap, int usecs) 1849 { 1850 u32 v1, v2, lp_count, hp_count; 1851 1852 do { 1853 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1854 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1855 if (is_t4(adap->params.chip)) { 1856 lp_count = LP_COUNT_G(v1); 1857 hp_count = HP_COUNT_G(v1); 1858 } else { 1859 lp_count = LP_COUNT_T5_G(v1); 1860 hp_count = HP_COUNT_T5_G(v2); 1861 } 1862 1863 if (lp_count == 0 && hp_count == 0) 1864 break; 1865 set_current_state(TASK_UNINTERRUPTIBLE); 1866 schedule_timeout(usecs_to_jiffies(usecs)); 1867 } while (1); 1868 } 1869 1870 static void disable_txq_db(struct sge_txq *q) 1871 { 1872 unsigned long flags; 1873 1874 spin_lock_irqsave(&q->db_lock, flags); 1875 q->db_disabled = 1; 1876 spin_unlock_irqrestore(&q->db_lock, flags); 1877 } 1878 1879 static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 1880 { 1881 spin_lock_irq(&q->db_lock); 1882 if (q->db_pidx_inc) { 1883 /* Make sure that all writes to the TX descriptors 1884 * are committed before we tell HW about them. 1885 */ 1886 wmb(); 1887 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1888 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); 1889 q->db_pidx_inc = 0; 1890 } 1891 q->db_disabled = 0; 1892 spin_unlock_irq(&q->db_lock); 1893 } 1894 1895 static void disable_dbs(struct adapter *adap) 1896 { 1897 int i; 1898 1899 for_each_ethrxq(&adap->sge, i) 1900 disable_txq_db(&adap->sge.ethtxq[i].q); 1901 if (is_offload(adap)) { 1902 struct sge_uld_txq_info *txq_info = 1903 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 1904 1905 if (txq_info) { 1906 for_each_ofldtxq(&adap->sge, i) { 1907 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 1908 1909 disable_txq_db(&txq->q); 1910 } 1911 } 1912 } 1913 for_each_port(adap, i) 1914 disable_txq_db(&adap->sge.ctrlq[i].q); 1915 } 1916 1917 static void enable_dbs(struct adapter *adap) 1918 { 1919 int i; 1920 1921 for_each_ethrxq(&adap->sge, i) 1922 enable_txq_db(adap, &adap->sge.ethtxq[i].q); 1923 if (is_offload(adap)) { 1924 struct sge_uld_txq_info *txq_info = 1925 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 1926 1927 if (txq_info) { 1928 for_each_ofldtxq(&adap->sge, i) { 1929 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 1930 1931 enable_txq_db(adap, &txq->q); 1932 } 1933 } 1934 } 1935 for_each_port(adap, i) 1936 enable_txq_db(adap, &adap->sge.ctrlq[i].q); 1937 } 1938 1939 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) 1940 { 1941 enum cxgb4_uld type = CXGB4_ULD_RDMA; 1942 1943 if (adap->uld && adap->uld[type].handle) 1944 adap->uld[type].control(adap->uld[type].handle, cmd); 1945 } 1946 1947 static void process_db_full(struct work_struct *work) 1948 { 1949 struct adapter *adap; 1950 1951 adap = container_of(work, struct adapter, db_full_task); 1952 1953 drain_db_fifo(adap, dbfifo_drain_delay); 1954 enable_dbs(adap); 1955 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 1956 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1957 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 1958 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 1959 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 1960 else 1961 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 1962 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); 1963 } 1964 1965 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 1966 { 1967 u16 hw_pidx, hw_cidx; 1968 int ret; 1969 1970 spin_lock_irq(&q->db_lock); 1971 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); 1972 if (ret) 1973 goto out; 1974 if (q->db_pidx != hw_pidx) { 1975 u16 delta; 1976 u32 val; 1977 1978 if (q->db_pidx >= hw_pidx) 1979 delta = q->db_pidx - hw_pidx; 1980 else 1981 delta = q->size - hw_pidx + q->db_pidx; 1982 1983 if (is_t4(adap->params.chip)) 1984 val = PIDX_V(delta); 1985 else 1986 val = PIDX_T5_V(delta); 1987 wmb(); 1988 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1989 QID_V(q->cntxt_id) | val); 1990 } 1991 out: 1992 q->db_disabled = 0; 1993 q->db_pidx_inc = 0; 1994 spin_unlock_irq(&q->db_lock); 1995 if (ret) 1996 CH_WARN(adap, "DB drop recovery failed.\n"); 1997 } 1998 1999 static void recover_all_queues(struct adapter *adap) 2000 { 2001 int i; 2002 2003 for_each_ethrxq(&adap->sge, i) 2004 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); 2005 if (is_offload(adap)) { 2006 struct sge_uld_txq_info *txq_info = 2007 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2008 if (txq_info) { 2009 for_each_ofldtxq(&adap->sge, i) { 2010 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2011 2012 sync_txq_pidx(adap, &txq->q); 2013 } 2014 } 2015 } 2016 for_each_port(adap, i) 2017 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); 2018 } 2019 2020 static void process_db_drop(struct work_struct *work) 2021 { 2022 struct adapter *adap; 2023 2024 adap = container_of(work, struct adapter, db_drop_task); 2025 2026 if (is_t4(adap->params.chip)) { 2027 drain_db_fifo(adap, dbfifo_drain_delay); 2028 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); 2029 drain_db_fifo(adap, dbfifo_drain_delay); 2030 recover_all_queues(adap); 2031 drain_db_fifo(adap, dbfifo_drain_delay); 2032 enable_dbs(adap); 2033 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2034 } else if (is_t5(adap->params.chip)) { 2035 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2036 u16 qid = (dropped_db >> 15) & 0x1ffff; 2037 u16 pidx_inc = dropped_db & 0x1fff; 2038 u64 bar2_qoffset; 2039 unsigned int bar2_qid; 2040 int ret; 2041 2042 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, 2043 0, &bar2_qoffset, &bar2_qid); 2044 if (ret) 2045 dev_err(adap->pdev_dev, "doorbell drop recovery: " 2046 "qid=%d, pidx_inc=%d\n", qid, pidx_inc); 2047 else 2048 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), 2049 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); 2050 2051 /* Re-enable BAR2 WC */ 2052 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2053 } 2054 2055 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2056 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2057 } 2058 2059 void t4_db_full(struct adapter *adap) 2060 { 2061 if (is_t4(adap->params.chip)) { 2062 disable_dbs(adap); 2063 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2064 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2065 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); 2066 queue_work(adap->workq, &adap->db_full_task); 2067 } 2068 } 2069 2070 void t4_db_dropped(struct adapter *adap) 2071 { 2072 if (is_t4(adap->params.chip)) { 2073 disable_dbs(adap); 2074 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2075 } 2076 queue_work(adap->workq, &adap->db_drop_task); 2077 } 2078 2079 void t4_register_netevent_notifier(void) 2080 { 2081 if (!netevent_registered) { 2082 register_netevent_notifier(&cxgb4_netevent_nb); 2083 netevent_registered = true; 2084 } 2085 } 2086 2087 static void detach_ulds(struct adapter *adap) 2088 { 2089 unsigned int i; 2090 2091 mutex_lock(&uld_mutex); 2092 list_del(&adap->list_node); 2093 2094 for (i = 0; i < CXGB4_ULD_MAX; i++) 2095 if (adap->uld && adap->uld[i].handle) 2096 adap->uld[i].state_change(adap->uld[i].handle, 2097 CXGB4_STATE_DETACH); 2098 2099 if (netevent_registered && list_empty(&adapter_list)) { 2100 unregister_netevent_notifier(&cxgb4_netevent_nb); 2101 netevent_registered = false; 2102 } 2103 mutex_unlock(&uld_mutex); 2104 } 2105 2106 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) 2107 { 2108 unsigned int i; 2109 2110 mutex_lock(&uld_mutex); 2111 for (i = 0; i < CXGB4_ULD_MAX; i++) 2112 if (adap->uld && adap->uld[i].handle) 2113 adap->uld[i].state_change(adap->uld[i].handle, 2114 new_state); 2115 mutex_unlock(&uld_mutex); 2116 } 2117 2118 #if IS_ENABLED(CONFIG_IPV6) 2119 static int cxgb4_inet6addr_handler(struct notifier_block *this, 2120 unsigned long event, void *data) 2121 { 2122 struct inet6_ifaddr *ifa = data; 2123 struct net_device *event_dev = ifa->idev->dev; 2124 const struct device *parent = NULL; 2125 #if IS_ENABLED(CONFIG_BONDING) 2126 struct adapter *adap; 2127 #endif 2128 if (is_vlan_dev(event_dev)) 2129 event_dev = vlan_dev_real_dev(event_dev); 2130 #if IS_ENABLED(CONFIG_BONDING) 2131 if (event_dev->flags & IFF_MASTER) { 2132 list_for_each_entry(adap, &adapter_list, list_node) { 2133 switch (event) { 2134 case NETDEV_UP: 2135 cxgb4_clip_get(adap->port[0], 2136 (const u32 *)ifa, 1); 2137 break; 2138 case NETDEV_DOWN: 2139 cxgb4_clip_release(adap->port[0], 2140 (const u32 *)ifa, 1); 2141 break; 2142 default: 2143 break; 2144 } 2145 } 2146 return NOTIFY_OK; 2147 } 2148 #endif 2149 2150 if (event_dev) 2151 parent = event_dev->dev.parent; 2152 2153 if (parent && parent->driver == &cxgb4_driver.driver) { 2154 switch (event) { 2155 case NETDEV_UP: 2156 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); 2157 break; 2158 case NETDEV_DOWN: 2159 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); 2160 break; 2161 default: 2162 break; 2163 } 2164 } 2165 return NOTIFY_OK; 2166 } 2167 2168 static bool inet6addr_registered; 2169 static struct notifier_block cxgb4_inet6addr_notifier = { 2170 .notifier_call = cxgb4_inet6addr_handler 2171 }; 2172 2173 static void update_clip(const struct adapter *adap) 2174 { 2175 int i; 2176 struct net_device *dev; 2177 int ret; 2178 2179 rcu_read_lock(); 2180 2181 for (i = 0; i < MAX_NPORTS; i++) { 2182 dev = adap->port[i]; 2183 ret = 0; 2184 2185 if (dev) 2186 ret = cxgb4_update_root_dev_clip(dev); 2187 2188 if (ret < 0) 2189 break; 2190 } 2191 rcu_read_unlock(); 2192 } 2193 #endif /* IS_ENABLED(CONFIG_IPV6) */ 2194 2195 /** 2196 * cxgb_up - enable the adapter 2197 * @adap: adapter being enabled 2198 * 2199 * Called when the first port is enabled, this function performs the 2200 * actions necessary to make an adapter operational, such as completing 2201 * the initialization of HW modules, and enabling interrupts. 2202 * 2203 * Must be called with the rtnl lock held. 2204 */ 2205 static int cxgb_up(struct adapter *adap) 2206 { 2207 int err; 2208 2209 mutex_lock(&uld_mutex); 2210 err = setup_sge_queues(adap); 2211 if (err) 2212 goto rel_lock; 2213 err = setup_rss(adap); 2214 if (err) 2215 goto freeq; 2216 2217 if (adap->flags & USING_MSIX) { 2218 name_msix_vecs(adap); 2219 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, 2220 adap->msix_info[0].desc, adap); 2221 if (err) 2222 goto irq_err; 2223 err = request_msix_queue_irqs(adap); 2224 if (err) { 2225 free_irq(adap->msix_info[0].vec, adap); 2226 goto irq_err; 2227 } 2228 } else { 2229 err = request_irq(adap->pdev->irq, t4_intr_handler(adap), 2230 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, 2231 adap->port[0]->name, adap); 2232 if (err) 2233 goto irq_err; 2234 } 2235 2236 enable_rx(adap); 2237 t4_sge_start(adap); 2238 t4_intr_enable(adap); 2239 adap->flags |= FULL_INIT_DONE; 2240 mutex_unlock(&uld_mutex); 2241 2242 notify_ulds(adap, CXGB4_STATE_UP); 2243 #if IS_ENABLED(CONFIG_IPV6) 2244 update_clip(adap); 2245 #endif 2246 /* Initialize hash mac addr list*/ 2247 INIT_LIST_HEAD(&adap->mac_hlist); 2248 return err; 2249 2250 irq_err: 2251 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); 2252 freeq: 2253 t4_free_sge_resources(adap); 2254 rel_lock: 2255 mutex_unlock(&uld_mutex); 2256 return err; 2257 } 2258 2259 static void cxgb_down(struct adapter *adapter) 2260 { 2261 cancel_work_sync(&adapter->tid_release_task); 2262 cancel_work_sync(&adapter->db_full_task); 2263 cancel_work_sync(&adapter->db_drop_task); 2264 adapter->tid_release_task_busy = false; 2265 adapter->tid_release_head = NULL; 2266 2267 t4_sge_stop(adapter); 2268 t4_free_sge_resources(adapter); 2269 adapter->flags &= ~FULL_INIT_DONE; 2270 } 2271 2272 /* 2273 * net_device operations 2274 */ 2275 static int cxgb_open(struct net_device *dev) 2276 { 2277 int err; 2278 struct port_info *pi = netdev_priv(dev); 2279 struct adapter *adapter = pi->adapter; 2280 2281 netif_carrier_off(dev); 2282 2283 if (!(adapter->flags & FULL_INIT_DONE)) { 2284 err = cxgb_up(adapter); 2285 if (err < 0) 2286 return err; 2287 } 2288 2289 /* It's possible that the basic port information could have 2290 * changed since we first read it. 2291 */ 2292 err = t4_update_port_info(pi); 2293 if (err < 0) 2294 return err; 2295 2296 err = link_start(dev); 2297 if (!err) 2298 netif_tx_start_all_queues(dev); 2299 return err; 2300 } 2301 2302 static int cxgb_close(struct net_device *dev) 2303 { 2304 struct port_info *pi = netdev_priv(dev); 2305 struct adapter *adapter = pi->adapter; 2306 2307 netif_tx_stop_all_queues(dev); 2308 netif_carrier_off(dev); 2309 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false); 2310 } 2311 2312 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 2313 __be32 sip, __be16 sport, __be16 vlan, 2314 unsigned int queue, unsigned char port, unsigned char mask) 2315 { 2316 int ret; 2317 struct filter_entry *f; 2318 struct adapter *adap; 2319 int i; 2320 u8 *val; 2321 2322 adap = netdev2adap(dev); 2323 2324 /* Adjust stid to correct filter index */ 2325 stid -= adap->tids.sftid_base; 2326 stid += adap->tids.nftids; 2327 2328 /* Check to make sure the filter requested is writable ... 2329 */ 2330 f = &adap->tids.ftid_tab[stid]; 2331 ret = writable_filter(f); 2332 if (ret) 2333 return ret; 2334 2335 /* Clear out any old resources being used by the filter before 2336 * we start constructing the new filter. 2337 */ 2338 if (f->valid) 2339 clear_filter(adap, f); 2340 2341 /* Clear out filter specifications */ 2342 memset(&f->fs, 0, sizeof(struct ch_filter_specification)); 2343 f->fs.val.lport = cpu_to_be16(sport); 2344 f->fs.mask.lport = ~0; 2345 val = (u8 *)&sip; 2346 if ((val[0] | val[1] | val[2] | val[3]) != 0) { 2347 for (i = 0; i < 4; i++) { 2348 f->fs.val.lip[i] = val[i]; 2349 f->fs.mask.lip[i] = ~0; 2350 } 2351 if (adap->params.tp.vlan_pri_map & PORT_F) { 2352 f->fs.val.iport = port; 2353 f->fs.mask.iport = mask; 2354 } 2355 } 2356 2357 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { 2358 f->fs.val.proto = IPPROTO_TCP; 2359 f->fs.mask.proto = ~0; 2360 } 2361 2362 f->fs.dirsteer = 1; 2363 f->fs.iq = queue; 2364 /* Mark filter as locked */ 2365 f->locked = 1; 2366 f->fs.rpttid = 1; 2367 2368 /* Save the actual tid. We need this to get the corresponding 2369 * filter entry structure in filter_rpl. 2370 */ 2371 f->tid = stid + adap->tids.ftid_base; 2372 ret = set_filter_wr(adap, stid); 2373 if (ret) { 2374 clear_filter(adap, f); 2375 return ret; 2376 } 2377 2378 return 0; 2379 } 2380 EXPORT_SYMBOL(cxgb4_create_server_filter); 2381 2382 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 2383 unsigned int queue, bool ipv6) 2384 { 2385 struct filter_entry *f; 2386 struct adapter *adap; 2387 2388 adap = netdev2adap(dev); 2389 2390 /* Adjust stid to correct filter index */ 2391 stid -= adap->tids.sftid_base; 2392 stid += adap->tids.nftids; 2393 2394 f = &adap->tids.ftid_tab[stid]; 2395 /* Unlock the filter */ 2396 f->locked = 0; 2397 2398 return delete_filter(adap, stid); 2399 } 2400 EXPORT_SYMBOL(cxgb4_remove_server_filter); 2401 2402 static void cxgb_get_stats(struct net_device *dev, 2403 struct rtnl_link_stats64 *ns) 2404 { 2405 struct port_stats stats; 2406 struct port_info *p = netdev_priv(dev); 2407 struct adapter *adapter = p->adapter; 2408 2409 /* Block retrieving statistics during EEH error 2410 * recovery. Otherwise, the recovery might fail 2411 * and the PCI device will be removed permanently 2412 */ 2413 spin_lock(&adapter->stats_lock); 2414 if (!netif_device_present(dev)) { 2415 spin_unlock(&adapter->stats_lock); 2416 return; 2417 } 2418 t4_get_port_stats_offset(adapter, p->tx_chan, &stats, 2419 &p->stats_base); 2420 spin_unlock(&adapter->stats_lock); 2421 2422 ns->tx_bytes = stats.tx_octets; 2423 ns->tx_packets = stats.tx_frames; 2424 ns->rx_bytes = stats.rx_octets; 2425 ns->rx_packets = stats.rx_frames; 2426 ns->multicast = stats.rx_mcast_frames; 2427 2428 /* detailed rx_errors */ 2429 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + 2430 stats.rx_runt; 2431 ns->rx_over_errors = 0; 2432 ns->rx_crc_errors = stats.rx_fcs_err; 2433 ns->rx_frame_errors = stats.rx_symbol_err; 2434 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + 2435 stats.rx_ovflow2 + stats.rx_ovflow3 + 2436 stats.rx_trunc0 + stats.rx_trunc1 + 2437 stats.rx_trunc2 + stats.rx_trunc3; 2438 ns->rx_missed_errors = 0; 2439 2440 /* detailed tx_errors */ 2441 ns->tx_aborted_errors = 0; 2442 ns->tx_carrier_errors = 0; 2443 ns->tx_fifo_errors = 0; 2444 ns->tx_heartbeat_errors = 0; 2445 ns->tx_window_errors = 0; 2446 2447 ns->tx_errors = stats.tx_error_frames; 2448 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + 2449 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; 2450 } 2451 2452 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 2453 { 2454 unsigned int mbox; 2455 int ret = 0, prtad, devad; 2456 struct port_info *pi = netdev_priv(dev); 2457 struct adapter *adapter = pi->adapter; 2458 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; 2459 2460 switch (cmd) { 2461 case SIOCGMIIPHY: 2462 if (pi->mdio_addr < 0) 2463 return -EOPNOTSUPP; 2464 data->phy_id = pi->mdio_addr; 2465 break; 2466 case SIOCGMIIREG: 2467 case SIOCSMIIREG: 2468 if (mdio_phy_id_is_c45(data->phy_id)) { 2469 prtad = mdio_phy_id_prtad(data->phy_id); 2470 devad = mdio_phy_id_devad(data->phy_id); 2471 } else if (data->phy_id < 32) { 2472 prtad = data->phy_id; 2473 devad = 0; 2474 data->reg_num &= 0x1f; 2475 } else 2476 return -EINVAL; 2477 2478 mbox = pi->adapter->pf; 2479 if (cmd == SIOCGMIIREG) 2480 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, 2481 data->reg_num, &data->val_out); 2482 else 2483 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, 2484 data->reg_num, data->val_in); 2485 break; 2486 case SIOCGHWTSTAMP: 2487 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2488 sizeof(pi->tstamp_config)) ? 2489 -EFAULT : 0; 2490 case SIOCSHWTSTAMP: 2491 if (copy_from_user(&pi->tstamp_config, req->ifr_data, 2492 sizeof(pi->tstamp_config))) 2493 return -EFAULT; 2494 2495 if (!is_t4(adapter->params.chip)) { 2496 switch (pi->tstamp_config.tx_type) { 2497 case HWTSTAMP_TX_OFF: 2498 case HWTSTAMP_TX_ON: 2499 break; 2500 default: 2501 return -ERANGE; 2502 } 2503 2504 switch (pi->tstamp_config.rx_filter) { 2505 case HWTSTAMP_FILTER_NONE: 2506 pi->rxtstamp = false; 2507 break; 2508 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2509 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2510 cxgb4_ptprx_timestamping(pi, pi->port_id, 2511 PTP_TS_L4); 2512 break; 2513 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2514 cxgb4_ptprx_timestamping(pi, pi->port_id, 2515 PTP_TS_L2_L4); 2516 break; 2517 case HWTSTAMP_FILTER_ALL: 2518 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2519 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2520 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2521 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2522 pi->rxtstamp = true; 2523 break; 2524 default: 2525 pi->tstamp_config.rx_filter = 2526 HWTSTAMP_FILTER_NONE; 2527 return -ERANGE; 2528 } 2529 2530 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) && 2531 (pi->tstamp_config.rx_filter == 2532 HWTSTAMP_FILTER_NONE)) { 2533 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0) 2534 pi->ptp_enable = false; 2535 } 2536 2537 if (pi->tstamp_config.rx_filter != 2538 HWTSTAMP_FILTER_NONE) { 2539 if (cxgb4_ptp_redirect_rx_packet(adapter, 2540 pi) >= 0) 2541 pi->ptp_enable = true; 2542 } 2543 } else { 2544 /* For T4 Adapters */ 2545 switch (pi->tstamp_config.rx_filter) { 2546 case HWTSTAMP_FILTER_NONE: 2547 pi->rxtstamp = false; 2548 break; 2549 case HWTSTAMP_FILTER_ALL: 2550 pi->rxtstamp = true; 2551 break; 2552 default: 2553 pi->tstamp_config.rx_filter = 2554 HWTSTAMP_FILTER_NONE; 2555 return -ERANGE; 2556 } 2557 } 2558 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2559 sizeof(pi->tstamp_config)) ? 2560 -EFAULT : 0; 2561 default: 2562 return -EOPNOTSUPP; 2563 } 2564 return ret; 2565 } 2566 2567 static void cxgb_set_rxmode(struct net_device *dev) 2568 { 2569 /* unfortunately we can't return errors to the stack */ 2570 set_rxmode(dev, -1, false); 2571 } 2572 2573 static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2574 { 2575 int ret; 2576 struct port_info *pi = netdev_priv(dev); 2577 2578 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, 2579 -1, -1, -1, true); 2580 if (!ret) 2581 dev->mtu = new_mtu; 2582 return ret; 2583 } 2584 2585 #ifdef CONFIG_PCI_IOV 2586 static int dummy_open(struct net_device *dev) 2587 { 2588 /* Turn carrier off since we don't have to transmit anything on this 2589 * interface. 2590 */ 2591 netif_carrier_off(dev); 2592 return 0; 2593 } 2594 2595 /* Fill MAC address that will be assigned by the FW */ 2596 static void fill_vf_station_mac_addr(struct adapter *adap) 2597 { 2598 unsigned int i; 2599 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; 2600 int err; 2601 u8 *na; 2602 u16 a, b; 2603 2604 err = t4_get_raw_vpd_params(adap, &adap->params.vpd); 2605 if (!err) { 2606 na = adap->params.vpd.na; 2607 for (i = 0; i < ETH_ALEN; i++) 2608 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 2609 hex2val(na[2 * i + 1])); 2610 a = (hw_addr[0] << 8) | hw_addr[1]; 2611 b = (hw_addr[1] << 8) | hw_addr[2]; 2612 a ^= b; 2613 a |= 0x0200; /* locally assigned Ethernet MAC address */ 2614 a &= ~0x0100; /* not a multicast Ethernet MAC address */ 2615 macaddr[0] = a >> 8; 2616 macaddr[1] = a & 0xff; 2617 2618 for (i = 2; i < 5; i++) 2619 macaddr[i] = hw_addr[i + 1]; 2620 2621 for (i = 0; i < adap->num_vfs; i++) { 2622 macaddr[5] = adap->pf * 16 + i; 2623 ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr); 2624 } 2625 } 2626 } 2627 2628 static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 2629 { 2630 struct port_info *pi = netdev_priv(dev); 2631 struct adapter *adap = pi->adapter; 2632 int ret; 2633 2634 /* verify MAC addr is valid */ 2635 if (!is_valid_ether_addr(mac)) { 2636 dev_err(pi->adapter->pdev_dev, 2637 "Invalid Ethernet address %pM for VF %d\n", 2638 mac, vf); 2639 return -EINVAL; 2640 } 2641 2642 dev_info(pi->adapter->pdev_dev, 2643 "Setting MAC %pM on VF %d\n", mac, vf); 2644 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); 2645 if (!ret) 2646 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); 2647 return ret; 2648 } 2649 2650 static int cxgb_get_vf_config(struct net_device *dev, 2651 int vf, struct ifla_vf_info *ivi) 2652 { 2653 struct port_info *pi = netdev_priv(dev); 2654 struct adapter *adap = pi->adapter; 2655 2656 if (vf >= adap->num_vfs) 2657 return -EINVAL; 2658 ivi->vf = vf; 2659 ivi->max_tx_rate = adap->vfinfo[vf].tx_rate; 2660 ivi->min_tx_rate = 0; 2661 ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr); 2662 return 0; 2663 } 2664 2665 static int cxgb_get_phys_port_id(struct net_device *dev, 2666 struct netdev_phys_item_id *ppid) 2667 { 2668 struct port_info *pi = netdev_priv(dev); 2669 unsigned int phy_port_id; 2670 2671 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; 2672 ppid->id_len = sizeof(phy_port_id); 2673 memcpy(ppid->id, &phy_port_id, ppid->id_len); 2674 return 0; 2675 } 2676 2677 static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 2678 int max_tx_rate) 2679 { 2680 struct port_info *pi = netdev_priv(dev); 2681 struct adapter *adap = pi->adapter; 2682 unsigned int link_ok, speed, mtu; 2683 u32 fw_pfvf, fw_class; 2684 int class_id = vf; 2685 int ret; 2686 u16 pktsize; 2687 2688 if (vf >= adap->num_vfs) 2689 return -EINVAL; 2690 2691 if (min_tx_rate) { 2692 dev_err(adap->pdev_dev, 2693 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n", 2694 min_tx_rate, vf); 2695 return -EINVAL; 2696 } 2697 2698 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu); 2699 if (ret != FW_SUCCESS) { 2700 dev_err(adap->pdev_dev, 2701 "Failed to get link information for VF %d\n", vf); 2702 return -EINVAL; 2703 } 2704 2705 if (!link_ok) { 2706 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf); 2707 return -EINVAL; 2708 } 2709 2710 if (max_tx_rate > speed) { 2711 dev_err(adap->pdev_dev, 2712 "Max tx rate %d for VF %d can't be > link-speed %u", 2713 max_tx_rate, vf, speed); 2714 return -EINVAL; 2715 } 2716 2717 pktsize = mtu; 2718 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */ 2719 pktsize = pktsize - sizeof(struct ethhdr) - 4; 2720 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */ 2721 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr); 2722 /* configure Traffic Class for rate-limiting */ 2723 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET, 2724 SCHED_CLASS_LEVEL_CL_RL, 2725 SCHED_CLASS_MODE_CLASS, 2726 SCHED_CLASS_RATEUNIT_BITS, 2727 SCHED_CLASS_RATEMODE_ABS, 2728 pi->tx_chan, class_id, 0, 2729 max_tx_rate * 1000, 0, pktsize); 2730 if (ret) { 2731 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n", 2732 ret); 2733 return -EINVAL; 2734 } 2735 dev_info(adap->pdev_dev, 2736 "Class %d with MSS %u configured with rate %u\n", 2737 class_id, pktsize, max_tx_rate); 2738 2739 /* bind VF to configured Traffic Class */ 2740 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 2741 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 2742 fw_class = class_id; 2743 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf, 2744 &fw_class); 2745 if (ret) { 2746 dev_err(adap->pdev_dev, 2747 "Err %d in binding VF %d to Traffic Class %d\n", 2748 ret, vf, class_id); 2749 return -EINVAL; 2750 } 2751 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n", 2752 adap->pf, vf, class_id); 2753 adap->vfinfo[vf].tx_rate = max_tx_rate; 2754 return 0; 2755 } 2756 2757 #endif 2758 2759 static int cxgb_set_mac_addr(struct net_device *dev, void *p) 2760 { 2761 int ret; 2762 struct sockaddr *addr = p; 2763 struct port_info *pi = netdev_priv(dev); 2764 2765 if (!is_valid_ether_addr(addr->sa_data)) 2766 return -EADDRNOTAVAIL; 2767 2768 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, 2769 pi->xact_addr_filt, addr->sa_data, true, true); 2770 if (ret < 0) 2771 return ret; 2772 2773 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2774 pi->xact_addr_filt = ret; 2775 return 0; 2776 } 2777 2778 #ifdef CONFIG_NET_POLL_CONTROLLER 2779 static void cxgb_netpoll(struct net_device *dev) 2780 { 2781 struct port_info *pi = netdev_priv(dev); 2782 struct adapter *adap = pi->adapter; 2783 2784 if (adap->flags & USING_MSIX) { 2785 int i; 2786 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; 2787 2788 for (i = pi->nqsets; i; i--, rx++) 2789 t4_sge_intr_msix(0, &rx->rspq); 2790 } else 2791 t4_intr_handler(adap)(0, adap); 2792 } 2793 #endif 2794 2795 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 2796 { 2797 struct port_info *pi = netdev_priv(dev); 2798 struct adapter *adap = pi->adapter; 2799 struct sched_class *e; 2800 struct ch_sched_params p; 2801 struct ch_sched_queue qe; 2802 u32 req_rate; 2803 int err = 0; 2804 2805 if (!can_sched(dev)) 2806 return -ENOTSUPP; 2807 2808 if (index < 0 || index > pi->nqsets - 1) 2809 return -EINVAL; 2810 2811 if (!(adap->flags & FULL_INIT_DONE)) { 2812 dev_err(adap->pdev_dev, 2813 "Failed to rate limit on queue %d. Link Down?\n", 2814 index); 2815 return -EINVAL; 2816 } 2817 2818 /* Convert from Mbps to Kbps */ 2819 req_rate = rate << 10; 2820 2821 /* Max rate is 10 Gbps */ 2822 if (req_rate >= SCHED_MAX_RATE_KBPS) { 2823 dev_err(adap->pdev_dev, 2824 "Invalid rate %u Mbps, Max rate is %u Gbps\n", 2825 rate, SCHED_MAX_RATE_KBPS); 2826 return -ERANGE; 2827 } 2828 2829 /* First unbind the queue from any existing class */ 2830 memset(&qe, 0, sizeof(qe)); 2831 qe.queue = index; 2832 qe.class = SCHED_CLS_NONE; 2833 2834 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); 2835 if (err) { 2836 dev_err(adap->pdev_dev, 2837 "Unbinding Queue %d on port %d fail. Err: %d\n", 2838 index, pi->port_id, err); 2839 return err; 2840 } 2841 2842 /* Queue already unbound */ 2843 if (!req_rate) 2844 return 0; 2845 2846 /* Fetch any available unused or matching scheduling class */ 2847 memset(&p, 0, sizeof(p)); 2848 p.type = SCHED_CLASS_TYPE_PACKET; 2849 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; 2850 p.u.params.mode = SCHED_CLASS_MODE_CLASS; 2851 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; 2852 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; 2853 p.u.params.channel = pi->tx_chan; 2854 p.u.params.class = SCHED_CLS_NONE; 2855 p.u.params.minrate = 0; 2856 p.u.params.maxrate = req_rate; 2857 p.u.params.weight = 0; 2858 p.u.params.pktsize = dev->mtu; 2859 2860 e = cxgb4_sched_class_alloc(dev, &p); 2861 if (!e) 2862 return -ENOMEM; 2863 2864 /* Bind the queue to a scheduling class */ 2865 memset(&qe, 0, sizeof(qe)); 2866 qe.queue = index; 2867 qe.class = e->idx; 2868 2869 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); 2870 if (err) 2871 dev_err(adap->pdev_dev, 2872 "Queue rate limiting failed. Err: %d\n", err); 2873 return err; 2874 } 2875 2876 static int cxgb_setup_tc_cls_u32(struct net_device *dev, 2877 struct tc_cls_u32_offload *cls_u32) 2878 { 2879 if (!is_classid_clsact_ingress(cls_u32->common.classid) || 2880 cls_u32->common.chain_index) 2881 return -EOPNOTSUPP; 2882 2883 switch (cls_u32->command) { 2884 case TC_CLSU32_NEW_KNODE: 2885 case TC_CLSU32_REPLACE_KNODE: 2886 return cxgb4_config_knode(dev, cls_u32); 2887 case TC_CLSU32_DELETE_KNODE: 2888 return cxgb4_delete_knode(dev, cls_u32); 2889 default: 2890 return -EOPNOTSUPP; 2891 } 2892 } 2893 2894 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2895 void *type_data) 2896 { 2897 struct port_info *pi = netdev2pinfo(dev); 2898 struct adapter *adap = netdev2adap(dev); 2899 2900 if (!(adap->flags & FULL_INIT_DONE)) { 2901 dev_err(adap->pdev_dev, 2902 "Failed to setup tc on port %d. Link Down?\n", 2903 pi->port_id); 2904 return -EINVAL; 2905 } 2906 2907 switch (type) { 2908 case TC_SETUP_CLSU32: 2909 return cxgb_setup_tc_cls_u32(dev, type_data); 2910 default: 2911 return -EOPNOTSUPP; 2912 } 2913 } 2914 2915 static netdev_features_t cxgb_fix_features(struct net_device *dev, 2916 netdev_features_t features) 2917 { 2918 /* Disable GRO, if RX_CSUM is disabled */ 2919 if (!(features & NETIF_F_RXCSUM)) 2920 features &= ~NETIF_F_GRO; 2921 2922 return features; 2923 } 2924 2925 static const struct net_device_ops cxgb4_netdev_ops = { 2926 .ndo_open = cxgb_open, 2927 .ndo_stop = cxgb_close, 2928 .ndo_start_xmit = t4_eth_xmit, 2929 .ndo_select_queue = cxgb_select_queue, 2930 .ndo_get_stats64 = cxgb_get_stats, 2931 .ndo_set_rx_mode = cxgb_set_rxmode, 2932 .ndo_set_mac_address = cxgb_set_mac_addr, 2933 .ndo_set_features = cxgb_set_features, 2934 .ndo_validate_addr = eth_validate_addr, 2935 .ndo_do_ioctl = cxgb_ioctl, 2936 .ndo_change_mtu = cxgb_change_mtu, 2937 #ifdef CONFIG_NET_POLL_CONTROLLER 2938 .ndo_poll_controller = cxgb_netpoll, 2939 #endif 2940 #ifdef CONFIG_CHELSIO_T4_FCOE 2941 .ndo_fcoe_enable = cxgb_fcoe_enable, 2942 .ndo_fcoe_disable = cxgb_fcoe_disable, 2943 #endif /* CONFIG_CHELSIO_T4_FCOE */ 2944 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, 2945 .ndo_setup_tc = cxgb_setup_tc, 2946 .ndo_fix_features = cxgb_fix_features, 2947 }; 2948 2949 #ifdef CONFIG_PCI_IOV 2950 static const struct net_device_ops cxgb4_mgmt_netdev_ops = { 2951 .ndo_open = dummy_open, 2952 .ndo_set_vf_mac = cxgb_set_vf_mac, 2953 .ndo_get_vf_config = cxgb_get_vf_config, 2954 .ndo_set_vf_rate = cxgb_set_vf_rate, 2955 .ndo_get_phys_port_id = cxgb_get_phys_port_id, 2956 }; 2957 #endif 2958 2959 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2960 { 2961 struct adapter *adapter = netdev2adap(dev); 2962 2963 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); 2964 strlcpy(info->version, cxgb4_driver_version, 2965 sizeof(info->version)); 2966 strlcpy(info->bus_info, pci_name(adapter->pdev), 2967 sizeof(info->bus_info)); 2968 } 2969 2970 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { 2971 .get_drvinfo = get_drvinfo, 2972 }; 2973 2974 void t4_fatal_err(struct adapter *adap) 2975 { 2976 int port; 2977 2978 if (pci_channel_offline(adap->pdev)) 2979 return; 2980 2981 /* Disable the SGE since ULDs are going to free resources that 2982 * could be exposed to the adapter. RDMA MWs for example... 2983 */ 2984 t4_shutdown_adapter(adap); 2985 for_each_port(adap, port) { 2986 struct net_device *dev = adap->port[port]; 2987 2988 /* If we get here in very early initialization the network 2989 * devices may not have been set up yet. 2990 */ 2991 if (!dev) 2992 continue; 2993 2994 netif_tx_stop_all_queues(dev); 2995 netif_carrier_off(dev); 2996 } 2997 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); 2998 } 2999 3000 static void setup_memwin(struct adapter *adap) 3001 { 3002 u32 nic_win_base = t4_get_util_window(adap); 3003 3004 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); 3005 } 3006 3007 static void setup_memwin_rdma(struct adapter *adap) 3008 { 3009 if (adap->vres.ocq.size) { 3010 u32 start; 3011 unsigned int sz_kb; 3012 3013 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); 3014 start &= PCI_BASE_ADDRESS_MEM_MASK; 3015 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 3016 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 3017 t4_write_reg(adap, 3018 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), 3019 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); 3020 t4_write_reg(adap, 3021 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), 3022 adap->vres.ocq.start); 3023 t4_read_reg(adap, 3024 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); 3025 } 3026 } 3027 3028 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 3029 { 3030 u32 v; 3031 int ret; 3032 3033 /* get device capabilities */ 3034 memset(c, 0, sizeof(*c)); 3035 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3036 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3037 c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); 3038 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); 3039 if (ret < 0) 3040 return ret; 3041 3042 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3043 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3044 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); 3045 if (ret < 0) 3046 return ret; 3047 3048 ret = t4_config_glbl_rss(adap, adap->pf, 3049 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 3050 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | 3051 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); 3052 if (ret < 0) 3053 return ret; 3054 3055 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, 3056 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, 3057 FW_CMD_CAP_PF); 3058 if (ret < 0) 3059 return ret; 3060 3061 t4_sge_init(adap); 3062 3063 /* tweak some settings */ 3064 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 3065 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); 3066 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 3067 v = t4_read_reg(adap, TP_PIO_DATA_A); 3068 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 3069 3070 /* first 4 Tx modulation queues point to consecutive Tx channels */ 3071 adap->params.tp.tx_modq_map = 0xE4; 3072 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, 3073 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); 3074 3075 /* associate each Tx modulation queue with consecutive Tx channels */ 3076 v = 0x84218421; 3077 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3078 &v, 1, TP_TX_SCHED_HDR_A); 3079 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3080 &v, 1, TP_TX_SCHED_FIFO_A); 3081 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3082 &v, 1, TP_TX_SCHED_PCMD_A); 3083 3084 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 3085 if (is_offload(adap)) { 3086 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, 3087 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3088 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3089 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3090 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3091 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, 3092 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3093 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3094 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3095 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3096 } 3097 3098 /* get basic stuff going */ 3099 return t4_early_init(adap, adap->pf); 3100 } 3101 3102 /* 3103 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 3104 */ 3105 #define MAX_ATIDS 8192U 3106 3107 /* 3108 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3109 * 3110 * If the firmware we're dealing with has Configuration File support, then 3111 * we use that to perform all configuration 3112 */ 3113 3114 /* 3115 * Tweak configuration based on module parameters, etc. Most of these have 3116 * defaults assigned to them by Firmware Configuration Files (if we're using 3117 * them) but need to be explicitly set if we're using hard-coded 3118 * initialization. But even in the case of using Firmware Configuration 3119 * Files, we'd like to expose the ability to change these via module 3120 * parameters so these are essentially common tweaks/settings for 3121 * Configuration Files and hard-coded initialization ... 3122 */ 3123 static int adap_init0_tweaks(struct adapter *adapter) 3124 { 3125 /* 3126 * Fix up various Host-Dependent Parameters like Page Size, Cache 3127 * Line Size, etc. The firmware default is for a 4KB Page Size and 3128 * 64B Cache Line Size ... 3129 */ 3130 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); 3131 3132 /* 3133 * Process module parameters which affect early initialization. 3134 */ 3135 if (rx_dma_offset != 2 && rx_dma_offset != 0) { 3136 dev_err(&adapter->pdev->dev, 3137 "Ignoring illegal rx_dma_offset=%d, using 2\n", 3138 rx_dma_offset); 3139 rx_dma_offset = 2; 3140 } 3141 t4_set_reg_field(adapter, SGE_CONTROL_A, 3142 PKTSHIFT_V(PKTSHIFT_M), 3143 PKTSHIFT_V(rx_dma_offset)); 3144 3145 /* 3146 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 3147 * adds the pseudo header itself. 3148 */ 3149 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, 3150 CSUM_HAS_PSEUDO_HDR_F, 0); 3151 3152 return 0; 3153 } 3154 3155 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips 3156 * unto themselves and they contain their own firmware to perform their 3157 * tasks ... 3158 */ 3159 static int phy_aq1202_version(const u8 *phy_fw_data, 3160 size_t phy_fw_size) 3161 { 3162 int offset; 3163 3164 /* At offset 0x8 you're looking for the primary image's 3165 * starting offset which is 3 Bytes wide 3166 * 3167 * At offset 0xa of the primary image, you look for the offset 3168 * of the DRAM segment which is 3 Bytes wide. 3169 * 3170 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes 3171 * wide 3172 */ 3173 #define be16(__p) (((__p)[0] << 8) | (__p)[1]) 3174 #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) 3175 #define le24(__p) (le16(__p) | ((__p)[2] << 16)) 3176 3177 offset = le24(phy_fw_data + 0x8) << 12; 3178 offset = le24(phy_fw_data + offset + 0xa); 3179 return be16(phy_fw_data + offset + 0x27e); 3180 3181 #undef be16 3182 #undef le16 3183 #undef le24 3184 } 3185 3186 static struct info_10gbt_phy_fw { 3187 unsigned int phy_fw_id; /* PCI Device ID */ 3188 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ 3189 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); 3190 int phy_flash; /* Has FLASH for PHY Firmware */ 3191 } phy_info_array[] = { 3192 { 3193 PHY_AQ1202_DEVICEID, 3194 PHY_AQ1202_FIRMWARE, 3195 phy_aq1202_version, 3196 1, 3197 }, 3198 { 3199 PHY_BCM84834_DEVICEID, 3200 PHY_BCM84834_FIRMWARE, 3201 NULL, 3202 0, 3203 }, 3204 { 0, NULL, NULL }, 3205 }; 3206 3207 static struct info_10gbt_phy_fw *find_phy_info(int devid) 3208 { 3209 int i; 3210 3211 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { 3212 if (phy_info_array[i].phy_fw_id == devid) 3213 return &phy_info_array[i]; 3214 } 3215 return NULL; 3216 } 3217 3218 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to 3219 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error 3220 * we return a negative error number. If we transfer new firmware we return 1 3221 * (from t4_load_phy_fw()). If we don't do anything we return 0. 3222 */ 3223 static int adap_init0_phy(struct adapter *adap) 3224 { 3225 const struct firmware *phyf; 3226 int ret; 3227 struct info_10gbt_phy_fw *phy_info; 3228 3229 /* Use the device ID to determine which PHY file to flash. 3230 */ 3231 phy_info = find_phy_info(adap->pdev->device); 3232 if (!phy_info) { 3233 dev_warn(adap->pdev_dev, 3234 "No PHY Firmware file found for this PHY\n"); 3235 return -EOPNOTSUPP; 3236 } 3237 3238 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then 3239 * use that. The adapter firmware provides us with a memory buffer 3240 * where we can load a PHY firmware file from the host if we want to 3241 * override the PHY firmware File in flash. 3242 */ 3243 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, 3244 adap->pdev_dev); 3245 if (ret < 0) { 3246 /* For adapters without FLASH attached to PHY for their 3247 * firmware, it's obviously a fatal error if we can't get the 3248 * firmware to the adapter. For adapters with PHY firmware 3249 * FLASH storage, it's worth a warning if we can't find the 3250 * PHY Firmware but we'll neuter the error ... 3251 */ 3252 dev_err(adap->pdev_dev, "unable to find PHY Firmware image " 3253 "/lib/firmware/%s, error %d\n", 3254 phy_info->phy_fw_file, -ret); 3255 if (phy_info->phy_flash) { 3256 int cur_phy_fw_ver = 0; 3257 3258 t4_phy_fw_ver(adap, &cur_phy_fw_ver); 3259 dev_warn(adap->pdev_dev, "continuing with, on-adapter " 3260 "FLASH copy, version %#x\n", cur_phy_fw_ver); 3261 ret = 0; 3262 } 3263 3264 return ret; 3265 } 3266 3267 /* Load PHY Firmware onto adapter. 3268 */ 3269 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, 3270 phy_info->phy_fw_version, 3271 (u8 *)phyf->data, phyf->size); 3272 if (ret < 0) 3273 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", 3274 -ret); 3275 else if (ret > 0) { 3276 int new_phy_fw_ver = 0; 3277 3278 if (phy_info->phy_fw_version) 3279 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, 3280 phyf->size); 3281 dev_info(adap->pdev_dev, "Successfully transferred PHY " 3282 "Firmware /lib/firmware/%s, version %#x\n", 3283 phy_info->phy_fw_file, new_phy_fw_ver); 3284 } 3285 3286 release_firmware(phyf); 3287 3288 return ret; 3289 } 3290 3291 /* 3292 * Attempt to initialize the adapter via a Firmware Configuration File. 3293 */ 3294 static int adap_init0_config(struct adapter *adapter, int reset) 3295 { 3296 struct fw_caps_config_cmd caps_cmd; 3297 const struct firmware *cf; 3298 unsigned long mtype = 0, maddr = 0; 3299 u32 finiver, finicsum, cfcsum; 3300 int ret; 3301 int config_issued = 0; 3302 char *fw_config_file, fw_config_file_path[256]; 3303 char *config_name = NULL; 3304 3305 /* 3306 * Reset device if necessary. 3307 */ 3308 if (reset) { 3309 ret = t4_fw_reset(adapter, adapter->mbox, 3310 PIORSTMODE_F | PIORST_F); 3311 if (ret < 0) 3312 goto bye; 3313 } 3314 3315 /* If this is a 10Gb/s-BT adapter make sure the chip-external 3316 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs 3317 * to be performed after any global adapter RESET above since some 3318 * PHYs only have local RAM copies of the PHY firmware. 3319 */ 3320 if (is_10gbt_device(adapter->pdev->device)) { 3321 ret = adap_init0_phy(adapter); 3322 if (ret < 0) 3323 goto bye; 3324 } 3325 /* 3326 * If we have a T4 configuration file under /lib/firmware/cxgb4/, 3327 * then use that. Otherwise, use the configuration file stored 3328 * in the adapter flash ... 3329 */ 3330 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { 3331 case CHELSIO_T4: 3332 fw_config_file = FW4_CFNAME; 3333 break; 3334 case CHELSIO_T5: 3335 fw_config_file = FW5_CFNAME; 3336 break; 3337 case CHELSIO_T6: 3338 fw_config_file = FW6_CFNAME; 3339 break; 3340 default: 3341 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 3342 adapter->pdev->device); 3343 ret = -EINVAL; 3344 goto bye; 3345 } 3346 3347 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); 3348 if (ret < 0) { 3349 config_name = "On FLASH"; 3350 mtype = FW_MEMTYPE_CF_FLASH; 3351 maddr = t4_flash_cfg_addr(adapter); 3352 } else { 3353 u32 params[7], val[7]; 3354 3355 sprintf(fw_config_file_path, 3356 "/lib/firmware/%s", fw_config_file); 3357 config_name = fw_config_file_path; 3358 3359 if (cf->size >= FLASH_CFG_MAX_SIZE) 3360 ret = -ENOMEM; 3361 else { 3362 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3363 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3364 ret = t4_query_params(adapter, adapter->mbox, 3365 adapter->pf, 0, 1, params, val); 3366 if (ret == 0) { 3367 /* 3368 * For t4_memory_rw() below addresses and 3369 * sizes have to be in terms of multiples of 4 3370 * bytes. So, if the Configuration File isn't 3371 * a multiple of 4 bytes in length we'll have 3372 * to write that out separately since we can't 3373 * guarantee that the bytes following the 3374 * residual byte in the buffer returned by 3375 * request_firmware() are zeroed out ... 3376 */ 3377 size_t resid = cf->size & 0x3; 3378 size_t size = cf->size & ~0x3; 3379 __be32 *data = (__be32 *)cf->data; 3380 3381 mtype = FW_PARAMS_PARAM_Y_G(val[0]); 3382 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; 3383 3384 spin_lock(&adapter->win0_lock); 3385 ret = t4_memory_rw(adapter, 0, mtype, maddr, 3386 size, data, T4_MEMORY_WRITE); 3387 if (ret == 0 && resid != 0) { 3388 union { 3389 __be32 word; 3390 char buf[4]; 3391 } last; 3392 int i; 3393 3394 last.word = data[size >> 2]; 3395 for (i = resid; i < 4; i++) 3396 last.buf[i] = 0; 3397 ret = t4_memory_rw(adapter, 0, mtype, 3398 maddr + size, 3399 4, &last.word, 3400 T4_MEMORY_WRITE); 3401 } 3402 spin_unlock(&adapter->win0_lock); 3403 } 3404 } 3405 3406 release_firmware(cf); 3407 if (ret) 3408 goto bye; 3409 } 3410 3411 /* 3412 * Issue a Capability Configuration command to the firmware to get it 3413 * to parse the Configuration File. We don't use t4_fw_config_file() 3414 * because we want the ability to modify various features after we've 3415 * processed the configuration file ... 3416 */ 3417 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3418 caps_cmd.op_to_write = 3419 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3420 FW_CMD_REQUEST_F | 3421 FW_CMD_READ_F); 3422 caps_cmd.cfvalid_to_len16 = 3423 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | 3424 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | 3425 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | 3426 FW_LEN16(caps_cmd)); 3427 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3428 &caps_cmd); 3429 3430 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware 3431 * Configuration File in FLASH), our last gasp effort is to use the 3432 * Firmware Configuration File which is embedded in the firmware. A 3433 * very few early versions of the firmware didn't have one embedded 3434 * but we can ignore those. 3435 */ 3436 if (ret == -ENOENT) { 3437 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3438 caps_cmd.op_to_write = 3439 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3440 FW_CMD_REQUEST_F | 3441 FW_CMD_READ_F); 3442 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3443 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 3444 sizeof(caps_cmd), &caps_cmd); 3445 config_name = "Firmware Default"; 3446 } 3447 3448 config_issued = 1; 3449 if (ret < 0) 3450 goto bye; 3451 3452 finiver = ntohl(caps_cmd.finiver); 3453 finicsum = ntohl(caps_cmd.finicsum); 3454 cfcsum = ntohl(caps_cmd.cfcsum); 3455 if (finicsum != cfcsum) 3456 dev_warn(adapter->pdev_dev, "Configuration File checksum "\ 3457 "mismatch: [fini] csum=%#x, computed csum=%#x\n", 3458 finicsum, cfcsum); 3459 3460 /* 3461 * And now tell the firmware to use the configuration we just loaded. 3462 */ 3463 caps_cmd.op_to_write = 3464 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3465 FW_CMD_REQUEST_F | 3466 FW_CMD_WRITE_F); 3467 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3468 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3469 NULL); 3470 if (ret < 0) 3471 goto bye; 3472 3473 /* 3474 * Tweak configuration based on system architecture, module 3475 * parameters, etc. 3476 */ 3477 ret = adap_init0_tweaks(adapter); 3478 if (ret < 0) 3479 goto bye; 3480 3481 /* 3482 * And finally tell the firmware to initialize itself using the 3483 * parameters from the Configuration File. 3484 */ 3485 ret = t4_fw_initialize(adapter, adapter->mbox); 3486 if (ret < 0) 3487 goto bye; 3488 3489 /* Emit Firmware Configuration File information and return 3490 * successfully. 3491 */ 3492 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ 3493 "Configuration File \"%s\", version %#x, computed checksum %#x\n", 3494 config_name, finiver, cfcsum); 3495 return 0; 3496 3497 /* 3498 * Something bad happened. Return the error ... (If the "error" 3499 * is that there's no Configuration File on the adapter we don't 3500 * want to issue a warning since this is fairly common.) 3501 */ 3502 bye: 3503 if (config_issued && ret != -ENOENT) 3504 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", 3505 config_name, -ret); 3506 return ret; 3507 } 3508 3509 static struct fw_info fw_info_array[] = { 3510 { 3511 .chip = CHELSIO_T4, 3512 .fs_name = FW4_CFNAME, 3513 .fw_mod_name = FW4_FNAME, 3514 .fw_hdr = { 3515 .chip = FW_HDR_CHIP_T4, 3516 .fw_ver = __cpu_to_be32(FW_VERSION(T4)), 3517 .intfver_nic = FW_INTFVER(T4, NIC), 3518 .intfver_vnic = FW_INTFVER(T4, VNIC), 3519 .intfver_ri = FW_INTFVER(T4, RI), 3520 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3521 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3522 }, 3523 }, { 3524 .chip = CHELSIO_T5, 3525 .fs_name = FW5_CFNAME, 3526 .fw_mod_name = FW5_FNAME, 3527 .fw_hdr = { 3528 .chip = FW_HDR_CHIP_T5, 3529 .fw_ver = __cpu_to_be32(FW_VERSION(T5)), 3530 .intfver_nic = FW_INTFVER(T5, NIC), 3531 .intfver_vnic = FW_INTFVER(T5, VNIC), 3532 .intfver_ri = FW_INTFVER(T5, RI), 3533 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3534 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3535 }, 3536 }, { 3537 .chip = CHELSIO_T6, 3538 .fs_name = FW6_CFNAME, 3539 .fw_mod_name = FW6_FNAME, 3540 .fw_hdr = { 3541 .chip = FW_HDR_CHIP_T6, 3542 .fw_ver = __cpu_to_be32(FW_VERSION(T6)), 3543 .intfver_nic = FW_INTFVER(T6, NIC), 3544 .intfver_vnic = FW_INTFVER(T6, VNIC), 3545 .intfver_ofld = FW_INTFVER(T6, OFLD), 3546 .intfver_ri = FW_INTFVER(T6, RI), 3547 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3548 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3549 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3550 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3551 }, 3552 } 3553 3554 }; 3555 3556 static struct fw_info *find_fw_info(int chip) 3557 { 3558 int i; 3559 3560 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { 3561 if (fw_info_array[i].chip == chip) 3562 return &fw_info_array[i]; 3563 } 3564 return NULL; 3565 } 3566 3567 /* 3568 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3569 */ 3570 static int adap_init0(struct adapter *adap) 3571 { 3572 int ret; 3573 u32 v, port_vec; 3574 enum dev_state state; 3575 u32 params[7], val[7]; 3576 struct fw_caps_config_cmd caps_cmd; 3577 int reset = 1; 3578 3579 /* Grab Firmware Device Log parameters as early as possible so we have 3580 * access to it for debugging, etc. 3581 */ 3582 ret = t4_init_devlog_params(adap); 3583 if (ret < 0) 3584 return ret; 3585 3586 /* Contact FW, advertising Master capability */ 3587 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, 3588 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); 3589 if (ret < 0) { 3590 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", 3591 ret); 3592 return ret; 3593 } 3594 if (ret == adap->mbox) 3595 adap->flags |= MASTER_PF; 3596 3597 /* 3598 * If we're the Master PF Driver and the device is uninitialized, 3599 * then let's consider upgrading the firmware ... (We always want 3600 * to check the firmware version number in order to A. get it for 3601 * later reporting and B. to warn if the currently loaded firmware 3602 * is excessively mismatched relative to the driver.) 3603 */ 3604 3605 t4_get_version_info(adap); 3606 ret = t4_check_fw_version(adap); 3607 /* If firmware is too old (not supported by driver) force an update. */ 3608 if (ret) 3609 state = DEV_STATE_UNINIT; 3610 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { 3611 struct fw_info *fw_info; 3612 struct fw_hdr *card_fw; 3613 const struct firmware *fw; 3614 const u8 *fw_data = NULL; 3615 unsigned int fw_size = 0; 3616 3617 /* This is the firmware whose headers the driver was compiled 3618 * against 3619 */ 3620 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); 3621 if (fw_info == NULL) { 3622 dev_err(adap->pdev_dev, 3623 "unable to get firmware info for chip %d.\n", 3624 CHELSIO_CHIP_VERSION(adap->params.chip)); 3625 return -EINVAL; 3626 } 3627 3628 /* allocate memory to read the header of the firmware on the 3629 * card 3630 */ 3631 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL); 3632 3633 /* Get FW from from /lib/firmware/ */ 3634 ret = request_firmware(&fw, fw_info->fw_mod_name, 3635 adap->pdev_dev); 3636 if (ret < 0) { 3637 dev_err(adap->pdev_dev, 3638 "unable to load firmware image %s, error %d\n", 3639 fw_info->fw_mod_name, ret); 3640 } else { 3641 fw_data = fw->data; 3642 fw_size = fw->size; 3643 } 3644 3645 /* upgrade FW logic */ 3646 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, 3647 state, &reset); 3648 3649 /* Cleaning up */ 3650 release_firmware(fw); 3651 kvfree(card_fw); 3652 3653 if (ret < 0) 3654 goto bye; 3655 } 3656 3657 /* 3658 * Grab VPD parameters. This should be done after we establish a 3659 * connection to the firmware since some of the VPD parameters 3660 * (notably the Core Clock frequency) are retrieved via requests to 3661 * the firmware. On the other hand, we need these fairly early on 3662 * so we do this right after getting ahold of the firmware. 3663 */ 3664 ret = t4_get_vpd_params(adap, &adap->params.vpd); 3665 if (ret < 0) 3666 goto bye; 3667 3668 /* 3669 * Find out what ports are available to us. Note that we need to do 3670 * this before calling adap_init0_no_config() since it needs nports 3671 * and portvec ... 3672 */ 3673 v = 3674 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3675 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 3676 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 3677 if (ret < 0) 3678 goto bye; 3679 3680 adap->params.nports = hweight32(port_vec); 3681 adap->params.portvec = port_vec; 3682 3683 /* If the firmware is initialized already, emit a simply note to that 3684 * effect. Otherwise, it's time to try initializing the adapter. 3685 */ 3686 if (state == DEV_STATE_INIT) { 3687 dev_info(adap->pdev_dev, "Coming up as %s: "\ 3688 "Adapter already initialized\n", 3689 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 3690 } else { 3691 dev_info(adap->pdev_dev, "Coming up as MASTER: "\ 3692 "Initializing adapter\n"); 3693 3694 /* Find out whether we're dealing with a version of the 3695 * firmware which has configuration file support. 3696 */ 3697 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3698 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3699 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 3700 params, val); 3701 3702 /* If the firmware doesn't support Configuration Files, 3703 * return an error. 3704 */ 3705 if (ret < 0) { 3706 dev_err(adap->pdev_dev, "firmware doesn't support " 3707 "Firmware Configuration Files\n"); 3708 goto bye; 3709 } 3710 3711 /* The firmware provides us with a memory buffer where we can 3712 * load a Configuration File from the host if we want to 3713 * override the Configuration File in flash. 3714 */ 3715 ret = adap_init0_config(adap, reset); 3716 if (ret == -ENOENT) { 3717 dev_err(adap->pdev_dev, "no Configuration File " 3718 "present on adapter.\n"); 3719 goto bye; 3720 } 3721 if (ret < 0) { 3722 dev_err(adap->pdev_dev, "could not initialize " 3723 "adapter, error %d\n", -ret); 3724 goto bye; 3725 } 3726 } 3727 3728 /* Give the SGE code a chance to pull in anything that it needs ... 3729 * Note that this must be called after we retrieve our VPD parameters 3730 * in order to know how to convert core ticks to seconds, etc. 3731 */ 3732 ret = t4_sge_init(adap); 3733 if (ret < 0) 3734 goto bye; 3735 3736 if (is_bypass_device(adap->pdev->device)) 3737 adap->params.bypass = 1; 3738 3739 /* 3740 * Grab some of our basic fundamental operating parameters. 3741 */ 3742 #define FW_PARAM_DEV(param) \ 3743 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 3744 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 3745 3746 #define FW_PARAM_PFVF(param) \ 3747 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 3748 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ 3749 FW_PARAMS_PARAM_Y_V(0) | \ 3750 FW_PARAMS_PARAM_Z_V(0) 3751 3752 params[0] = FW_PARAM_PFVF(EQ_START); 3753 params[1] = FW_PARAM_PFVF(L2T_START); 3754 params[2] = FW_PARAM_PFVF(L2T_END); 3755 params[3] = FW_PARAM_PFVF(FILTER_START); 3756 params[4] = FW_PARAM_PFVF(FILTER_END); 3757 params[5] = FW_PARAM_PFVF(IQFLINT_START); 3758 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); 3759 if (ret < 0) 3760 goto bye; 3761 adap->sge.egr_start = val[0]; 3762 adap->l2t_start = val[1]; 3763 adap->l2t_end = val[2]; 3764 adap->tids.ftid_base = val[3]; 3765 adap->tids.nftids = val[4] - val[3] + 1; 3766 adap->sge.ingr_start = val[5]; 3767 3768 /* qids (ingress/egress) returned from firmware can be anywhere 3769 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. 3770 * Hence driver needs to allocate memory for this range to 3771 * store the queue info. Get the highest IQFLINT/EQ index returned 3772 * in FW_EQ_*_CMD.alloc command. 3773 */ 3774 params[0] = FW_PARAM_PFVF(EQ_END); 3775 params[1] = FW_PARAM_PFVF(IQFLINT_END); 3776 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3777 if (ret < 0) 3778 goto bye; 3779 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; 3780 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; 3781 3782 adap->sge.egr_map = kcalloc(adap->sge.egr_sz, 3783 sizeof(*adap->sge.egr_map), GFP_KERNEL); 3784 if (!adap->sge.egr_map) { 3785 ret = -ENOMEM; 3786 goto bye; 3787 } 3788 3789 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, 3790 sizeof(*adap->sge.ingr_map), GFP_KERNEL); 3791 if (!adap->sge.ingr_map) { 3792 ret = -ENOMEM; 3793 goto bye; 3794 } 3795 3796 /* Allocate the memory for the vaious egress queue bitmaps 3797 * ie starving_fl, txq_maperr and blocked_fl. 3798 */ 3799 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3800 sizeof(long), GFP_KERNEL); 3801 if (!adap->sge.starving_fl) { 3802 ret = -ENOMEM; 3803 goto bye; 3804 } 3805 3806 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3807 sizeof(long), GFP_KERNEL); 3808 if (!adap->sge.txq_maperr) { 3809 ret = -ENOMEM; 3810 goto bye; 3811 } 3812 3813 #ifdef CONFIG_DEBUG_FS 3814 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3815 sizeof(long), GFP_KERNEL); 3816 if (!adap->sge.blocked_fl) { 3817 ret = -ENOMEM; 3818 goto bye; 3819 } 3820 #endif 3821 3822 params[0] = FW_PARAM_PFVF(CLIP_START); 3823 params[1] = FW_PARAM_PFVF(CLIP_END); 3824 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3825 if (ret < 0) 3826 goto bye; 3827 adap->clipt_start = val[0]; 3828 adap->clipt_end = val[1]; 3829 3830 /* We don't yet have a PARAMs calls to retrieve the number of Traffic 3831 * Classes supported by the hardware/firmware so we hard code it here 3832 * for now. 3833 */ 3834 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; 3835 3836 /* query params related to active filter region */ 3837 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); 3838 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); 3839 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3840 /* If Active filter size is set we enable establishing 3841 * offload connection through firmware work request 3842 */ 3843 if ((val[0] != val[1]) && (ret >= 0)) { 3844 adap->flags |= FW_OFLD_CONN; 3845 adap->tids.aftid_base = val[0]; 3846 adap->tids.aftid_end = val[1]; 3847 } 3848 3849 /* If we're running on newer firmware, let it know that we're 3850 * prepared to deal with encapsulated CPL messages. Older 3851 * firmware won't understand this and we'll just get 3852 * unencapsulated messages ... 3853 */ 3854 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3855 val[0] = 1; 3856 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 3857 3858 /* 3859 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 3860 * capability. Earlier versions of the firmware didn't have the 3861 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 3862 * permission to use ULPTX MEMWRITE DSGL. 3863 */ 3864 if (is_t4(adap->params.chip)) { 3865 adap->params.ulptx_memwrite_dsgl = false; 3866 } else { 3867 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 3868 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 3869 1, params, val); 3870 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 3871 } 3872 3873 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ 3874 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 3875 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 3876 1, params, val); 3877 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); 3878 3879 /* 3880 * Get device capabilities so we can determine what resources we need 3881 * to manage. 3882 */ 3883 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3884 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3885 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3886 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3887 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 3888 &caps_cmd); 3889 if (ret < 0) 3890 goto bye; 3891 3892 if (caps_cmd.ofldcaps) { 3893 /* query offload-related parameters */ 3894 params[0] = FW_PARAM_DEV(NTID); 3895 params[1] = FW_PARAM_PFVF(SERVER_START); 3896 params[2] = FW_PARAM_PFVF(SERVER_END); 3897 params[3] = FW_PARAM_PFVF(TDDP_START); 3898 params[4] = FW_PARAM_PFVF(TDDP_END); 3899 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3900 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 3901 params, val); 3902 if (ret < 0) 3903 goto bye; 3904 adap->tids.ntids = val[0]; 3905 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 3906 adap->tids.stid_base = val[1]; 3907 adap->tids.nstids = val[2] - val[1] + 1; 3908 /* 3909 * Setup server filter region. Divide the available filter 3910 * region into two parts. Regular filters get 1/3rd and server 3911 * filters get 2/3rd part. This is only enabled if workarond 3912 * path is enabled. 3913 * 1. For regular filters. 3914 * 2. Server filter: This are special filters which are used 3915 * to redirect SYN packets to offload queue. 3916 */ 3917 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { 3918 adap->tids.sftid_base = adap->tids.ftid_base + 3919 DIV_ROUND_UP(adap->tids.nftids, 3); 3920 adap->tids.nsftids = adap->tids.nftids - 3921 DIV_ROUND_UP(adap->tids.nftids, 3); 3922 adap->tids.nftids = adap->tids.sftid_base - 3923 adap->tids.ftid_base; 3924 } 3925 adap->vres.ddp.start = val[3]; 3926 adap->vres.ddp.size = val[4] - val[3] + 1; 3927 adap->params.ofldq_wr_cred = val[5]; 3928 3929 adap->params.offload = 1; 3930 adap->num_ofld_uld += 1; 3931 } 3932 if (caps_cmd.rdmacaps) { 3933 params[0] = FW_PARAM_PFVF(STAG_START); 3934 params[1] = FW_PARAM_PFVF(STAG_END); 3935 params[2] = FW_PARAM_PFVF(RQ_START); 3936 params[3] = FW_PARAM_PFVF(RQ_END); 3937 params[4] = FW_PARAM_PFVF(PBL_START); 3938 params[5] = FW_PARAM_PFVF(PBL_END); 3939 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 3940 params, val); 3941 if (ret < 0) 3942 goto bye; 3943 adap->vres.stag.start = val[0]; 3944 adap->vres.stag.size = val[1] - val[0] + 1; 3945 adap->vres.rq.start = val[2]; 3946 adap->vres.rq.size = val[3] - val[2] + 1; 3947 adap->vres.pbl.start = val[4]; 3948 adap->vres.pbl.size = val[5] - val[4] + 1; 3949 3950 params[0] = FW_PARAM_PFVF(SQRQ_START); 3951 params[1] = FW_PARAM_PFVF(SQRQ_END); 3952 params[2] = FW_PARAM_PFVF(CQ_START); 3953 params[3] = FW_PARAM_PFVF(CQ_END); 3954 params[4] = FW_PARAM_PFVF(OCQ_START); 3955 params[5] = FW_PARAM_PFVF(OCQ_END); 3956 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, 3957 val); 3958 if (ret < 0) 3959 goto bye; 3960 adap->vres.qp.start = val[0]; 3961 adap->vres.qp.size = val[1] - val[0] + 1; 3962 adap->vres.cq.start = val[2]; 3963 adap->vres.cq.size = val[3] - val[2] + 1; 3964 adap->vres.ocq.start = val[4]; 3965 adap->vres.ocq.size = val[5] - val[4] + 1; 3966 3967 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); 3968 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); 3969 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, 3970 val); 3971 if (ret < 0) { 3972 adap->params.max_ordird_qp = 8; 3973 adap->params.max_ird_adapter = 32 * adap->tids.ntids; 3974 ret = 0; 3975 } else { 3976 adap->params.max_ordird_qp = val[0]; 3977 adap->params.max_ird_adapter = val[1]; 3978 } 3979 dev_info(adap->pdev_dev, 3980 "max_ordird_qp %d max_ird_adapter %d\n", 3981 adap->params.max_ordird_qp, 3982 adap->params.max_ird_adapter); 3983 adap->num_ofld_uld += 2; 3984 } 3985 if (caps_cmd.iscsicaps) { 3986 params[0] = FW_PARAM_PFVF(ISCSI_START); 3987 params[1] = FW_PARAM_PFVF(ISCSI_END); 3988 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 3989 params, val); 3990 if (ret < 0) 3991 goto bye; 3992 adap->vres.iscsi.start = val[0]; 3993 adap->vres.iscsi.size = val[1] - val[0] + 1; 3994 /* LIO target and cxgb4i initiaitor */ 3995 adap->num_ofld_uld += 2; 3996 } 3997 if (caps_cmd.cryptocaps) { 3998 /* Should query params here...TODO */ 3999 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE); 4000 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4001 params, val); 4002 if (ret < 0) { 4003 if (ret != -EINVAL) 4004 goto bye; 4005 } else { 4006 adap->vres.ncrypto_fc = val[0]; 4007 } 4008 adap->params.crypto |= ULP_CRYPTO_LOOKASIDE; 4009 adap->num_uld += 1; 4010 } 4011 #undef FW_PARAM_PFVF 4012 #undef FW_PARAM_DEV 4013 4014 /* The MTU/MSS Table is initialized by now, so load their values. If 4015 * we're initializing the adapter, then we'll make any modifications 4016 * we want to the MTU/MSS Table and also initialize the congestion 4017 * parameters. 4018 */ 4019 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 4020 if (state != DEV_STATE_INIT) { 4021 int i; 4022 4023 /* The default MTU Table contains values 1492 and 1500. 4024 * However, for TCP, it's better to have two values which are 4025 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 4026 * This allows us to have a TCP Data Payload which is a 4027 * multiple of 8 regardless of what combination of TCP Options 4028 * are in use (always a multiple of 4 bytes) which is 4029 * important for performance reasons. For instance, if no 4030 * options are in use, then we have a 20-byte IP header and a 4031 * 20-byte TCP header. In this case, a 1500-byte MSS would 4032 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 4033 * which is not a multiple of 8. So using an MSS of 1488 in 4034 * this case results in a TCP Data Payload of 1448 bytes which 4035 * is a multiple of 8. On the other hand, if 12-byte TCP Time 4036 * Stamps have been negotiated, then an MTU of 1500 bytes 4037 * results in a TCP Data Payload of 1448 bytes which, as 4038 * above, is a multiple of 8 bytes ... 4039 */ 4040 for (i = 0; i < NMTUS; i++) 4041 if (adap->params.mtus[i] == 1492) { 4042 adap->params.mtus[i] = 1488; 4043 break; 4044 } 4045 4046 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4047 adap->params.b_wnd); 4048 } 4049 t4_init_sge_params(adap); 4050 adap->flags |= FW_OK; 4051 t4_init_tp_params(adap); 4052 return 0; 4053 4054 /* 4055 * Something bad happened. If a command timed out or failed with EIO 4056 * FW does not operate within its spec or something catastrophic 4057 * happened to HW/FW, stop issuing commands. 4058 */ 4059 bye: 4060 kfree(adap->sge.egr_map); 4061 kfree(adap->sge.ingr_map); 4062 kfree(adap->sge.starving_fl); 4063 kfree(adap->sge.txq_maperr); 4064 #ifdef CONFIG_DEBUG_FS 4065 kfree(adap->sge.blocked_fl); 4066 #endif 4067 if (ret != -ETIMEDOUT && ret != -EIO) 4068 t4_fw_bye(adap, adap->mbox); 4069 return ret; 4070 } 4071 4072 /* EEH callbacks */ 4073 4074 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, 4075 pci_channel_state_t state) 4076 { 4077 int i; 4078 struct adapter *adap = pci_get_drvdata(pdev); 4079 4080 if (!adap) 4081 goto out; 4082 4083 rtnl_lock(); 4084 adap->flags &= ~FW_OK; 4085 notify_ulds(adap, CXGB4_STATE_START_RECOVERY); 4086 spin_lock(&adap->stats_lock); 4087 for_each_port(adap, i) { 4088 struct net_device *dev = adap->port[i]; 4089 if (dev) { 4090 netif_device_detach(dev); 4091 netif_carrier_off(dev); 4092 } 4093 } 4094 spin_unlock(&adap->stats_lock); 4095 disable_interrupts(adap); 4096 if (adap->flags & FULL_INIT_DONE) 4097 cxgb_down(adap); 4098 rtnl_unlock(); 4099 if ((adap->flags & DEV_ENABLED)) { 4100 pci_disable_device(pdev); 4101 adap->flags &= ~DEV_ENABLED; 4102 } 4103 out: return state == pci_channel_io_perm_failure ? 4104 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 4105 } 4106 4107 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) 4108 { 4109 int i, ret; 4110 struct fw_caps_config_cmd c; 4111 struct adapter *adap = pci_get_drvdata(pdev); 4112 4113 if (!adap) { 4114 pci_restore_state(pdev); 4115 pci_save_state(pdev); 4116 return PCI_ERS_RESULT_RECOVERED; 4117 } 4118 4119 if (!(adap->flags & DEV_ENABLED)) { 4120 if (pci_enable_device(pdev)) { 4121 dev_err(&pdev->dev, "Cannot reenable PCI " 4122 "device after reset\n"); 4123 return PCI_ERS_RESULT_DISCONNECT; 4124 } 4125 adap->flags |= DEV_ENABLED; 4126 } 4127 4128 pci_set_master(pdev); 4129 pci_restore_state(pdev); 4130 pci_save_state(pdev); 4131 pci_cleanup_aer_uncorrect_error_status(pdev); 4132 4133 if (t4_wait_dev_ready(adap->regs) < 0) 4134 return PCI_ERS_RESULT_DISCONNECT; 4135 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) 4136 return PCI_ERS_RESULT_DISCONNECT; 4137 adap->flags |= FW_OK; 4138 if (adap_init1(adap, &c)) 4139 return PCI_ERS_RESULT_DISCONNECT; 4140 4141 for_each_port(adap, i) { 4142 struct port_info *p = adap2pinfo(adap, i); 4143 4144 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, 4145 NULL, NULL); 4146 if (ret < 0) 4147 return PCI_ERS_RESULT_DISCONNECT; 4148 p->viid = ret; 4149 p->xact_addr_filt = -1; 4150 } 4151 4152 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4153 adap->params.b_wnd); 4154 setup_memwin(adap); 4155 if (cxgb_up(adap)) 4156 return PCI_ERS_RESULT_DISCONNECT; 4157 return PCI_ERS_RESULT_RECOVERED; 4158 } 4159 4160 static void eeh_resume(struct pci_dev *pdev) 4161 { 4162 int i; 4163 struct adapter *adap = pci_get_drvdata(pdev); 4164 4165 if (!adap) 4166 return; 4167 4168 rtnl_lock(); 4169 for_each_port(adap, i) { 4170 struct net_device *dev = adap->port[i]; 4171 if (dev) { 4172 if (netif_running(dev)) { 4173 link_start(dev); 4174 cxgb_set_rxmode(dev); 4175 } 4176 netif_device_attach(dev); 4177 } 4178 } 4179 rtnl_unlock(); 4180 } 4181 4182 static const struct pci_error_handlers cxgb4_eeh = { 4183 .error_detected = eeh_err_detected, 4184 .slot_reset = eeh_slot_reset, 4185 .resume = eeh_resume, 4186 }; 4187 4188 /* Return true if the Link Configuration supports "High Speeds" (those greater 4189 * than 1Gb/s). 4190 */ 4191 static inline bool is_x_10g_port(const struct link_config *lc) 4192 { 4193 unsigned int speeds, high_speeds; 4194 4195 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps)); 4196 high_speeds = speeds & 4197 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 4198 4199 return high_speeds != 0; 4200 } 4201 4202 /* 4203 * Perform default configuration of DMA queues depending on the number and type 4204 * of ports we found and the number of available CPUs. Most settings can be 4205 * modified by the admin prior to actual use. 4206 */ 4207 static void cfg_queues(struct adapter *adap) 4208 { 4209 struct sge *s = &adap->sge; 4210 int i = 0, n10g = 0, qidx = 0; 4211 #ifndef CONFIG_CHELSIO_T4_DCB 4212 int q10g = 0; 4213 #endif 4214 4215 /* Reduce memory usage in kdump environment, disable all offload. 4216 */ 4217 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) { 4218 adap->params.offload = 0; 4219 adap->params.crypto = 0; 4220 } 4221 4222 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); 4223 #ifdef CONFIG_CHELSIO_T4_DCB 4224 /* For Data Center Bridging support we need to be able to support up 4225 * to 8 Traffic Priorities; each of which will be assigned to its 4226 * own TX Queue in order to prevent Head-Of-Line Blocking. 4227 */ 4228 if (adap->params.nports * 8 > MAX_ETH_QSETS) { 4229 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", 4230 MAX_ETH_QSETS, adap->params.nports * 8); 4231 BUG_ON(1); 4232 } 4233 4234 for_each_port(adap, i) { 4235 struct port_info *pi = adap2pinfo(adap, i); 4236 4237 pi->first_qset = qidx; 4238 pi->nqsets = is_kdump_kernel() ? 1 : 8; 4239 qidx += pi->nqsets; 4240 } 4241 #else /* !CONFIG_CHELSIO_T4_DCB */ 4242 /* 4243 * We default to 1 queue per non-10G port and up to # of cores queues 4244 * per 10G port. 4245 */ 4246 if (n10g) 4247 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; 4248 if (q10g > netif_get_num_default_rss_queues()) 4249 q10g = netif_get_num_default_rss_queues(); 4250 4251 if (is_kdump_kernel()) 4252 q10g = 1; 4253 4254 for_each_port(adap, i) { 4255 struct port_info *pi = adap2pinfo(adap, i); 4256 4257 pi->first_qset = qidx; 4258 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; 4259 qidx += pi->nqsets; 4260 } 4261 #endif /* !CONFIG_CHELSIO_T4_DCB */ 4262 4263 s->ethqsets = qidx; 4264 s->max_ethqsets = qidx; /* MSI-X may lower it later */ 4265 4266 if (is_uld(adap)) { 4267 /* 4268 * For offload we use 1 queue/channel if all ports are up to 1G, 4269 * otherwise we divide all available queues amongst the channels 4270 * capped by the number of available cores. 4271 */ 4272 if (n10g) { 4273 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus()); 4274 s->ofldqsets = roundup(i, adap->params.nports); 4275 } else { 4276 s->ofldqsets = adap->params.nports; 4277 } 4278 } 4279 4280 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 4281 struct sge_eth_rxq *r = &s->ethrxq[i]; 4282 4283 init_rspq(adap, &r->rspq, 5, 10, 1024, 64); 4284 r->fl.size = 72; 4285 } 4286 4287 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 4288 s->ethtxq[i].q.size = 1024; 4289 4290 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) 4291 s->ctrlq[i].q.size = 512; 4292 4293 if (!is_t4(adap->params.chip)) 4294 s->ptptxq.q.size = 8; 4295 4296 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); 4297 init_rspq(adap, &s->intrq, 0, 1, 512, 64); 4298 } 4299 4300 /* 4301 * Reduce the number of Ethernet queues across all ports to at most n. 4302 * n provides at least one queue per port. 4303 */ 4304 static void reduce_ethqs(struct adapter *adap, int n) 4305 { 4306 int i; 4307 struct port_info *pi; 4308 4309 while (n < adap->sge.ethqsets) 4310 for_each_port(adap, i) { 4311 pi = adap2pinfo(adap, i); 4312 if (pi->nqsets > 1) { 4313 pi->nqsets--; 4314 adap->sge.ethqsets--; 4315 if (adap->sge.ethqsets <= n) 4316 break; 4317 } 4318 } 4319 4320 n = 0; 4321 for_each_port(adap, i) { 4322 pi = adap2pinfo(adap, i); 4323 pi->first_qset = n; 4324 n += pi->nqsets; 4325 } 4326 } 4327 4328 static int get_msix_info(struct adapter *adap) 4329 { 4330 struct uld_msix_info *msix_info; 4331 unsigned int max_ingq = 0; 4332 4333 if (is_offload(adap)) 4334 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld; 4335 if (is_pci_uld(adap)) 4336 max_ingq += MAX_OFLD_QSETS * adap->num_uld; 4337 4338 if (!max_ingq) 4339 goto out; 4340 4341 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL); 4342 if (!msix_info) 4343 return -ENOMEM; 4344 4345 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq), 4346 sizeof(long), GFP_KERNEL); 4347 if (!adap->msix_bmap_ulds.msix_bmap) { 4348 kfree(msix_info); 4349 return -ENOMEM; 4350 } 4351 spin_lock_init(&adap->msix_bmap_ulds.lock); 4352 adap->msix_info_ulds = msix_info; 4353 out: 4354 return 0; 4355 } 4356 4357 static void free_msix_info(struct adapter *adap) 4358 { 4359 if (!(adap->num_uld && adap->num_ofld_uld)) 4360 return; 4361 4362 kfree(adap->msix_info_ulds); 4363 kfree(adap->msix_bmap_ulds.msix_bmap); 4364 } 4365 4366 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ 4367 #define EXTRA_VECS 2 4368 4369 static int enable_msix(struct adapter *adap) 4370 { 4371 int ofld_need = 0, uld_need = 0; 4372 int i, j, want, need, allocated; 4373 struct sge *s = &adap->sge; 4374 unsigned int nchan = adap->params.nports; 4375 struct msix_entry *entries; 4376 int max_ingq = MAX_INGQ; 4377 4378 if (is_pci_uld(adap)) 4379 max_ingq += (MAX_OFLD_QSETS * adap->num_uld); 4380 if (is_offload(adap)) 4381 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld); 4382 entries = kmalloc(sizeof(*entries) * (max_ingq + 1), 4383 GFP_KERNEL); 4384 if (!entries) 4385 return -ENOMEM; 4386 4387 /* map for msix */ 4388 if (get_msix_info(adap)) { 4389 adap->params.offload = 0; 4390 adap->params.crypto = 0; 4391 } 4392 4393 for (i = 0; i < max_ingq + 1; ++i) 4394 entries[i].entry = i; 4395 4396 want = s->max_ethqsets + EXTRA_VECS; 4397 if (is_offload(adap)) { 4398 want += adap->num_ofld_uld * s->ofldqsets; 4399 ofld_need = adap->num_ofld_uld * nchan; 4400 } 4401 if (is_pci_uld(adap)) { 4402 want += adap->num_uld * s->ofldqsets; 4403 uld_need = adap->num_uld * nchan; 4404 } 4405 #ifdef CONFIG_CHELSIO_T4_DCB 4406 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for 4407 * each port. 4408 */ 4409 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need; 4410 #else 4411 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need; 4412 #endif 4413 allocated = pci_enable_msix_range(adap->pdev, entries, need, want); 4414 if (allocated < 0) { 4415 dev_info(adap->pdev_dev, "not enough MSI-X vectors left," 4416 " not using MSI-X\n"); 4417 kfree(entries); 4418 return allocated; 4419 } 4420 4421 /* Distribute available vectors to the various queue groups. 4422 * Every group gets its minimum requirement and NIC gets top 4423 * priority for leftovers. 4424 */ 4425 i = allocated - EXTRA_VECS - ofld_need - uld_need; 4426 if (i < s->max_ethqsets) { 4427 s->max_ethqsets = i; 4428 if (i < s->ethqsets) 4429 reduce_ethqs(adap, i); 4430 } 4431 if (is_uld(adap)) { 4432 if (allocated < want) 4433 s->nqs_per_uld = nchan; 4434 else 4435 s->nqs_per_uld = s->ofldqsets; 4436 } 4437 4438 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i) 4439 adap->msix_info[i].vec = entries[i].vector; 4440 if (is_uld(adap)) { 4441 for (j = 0 ; i < allocated; ++i, j++) { 4442 adap->msix_info_ulds[j].vec = entries[i].vector; 4443 adap->msix_info_ulds[j].idx = i; 4444 } 4445 adap->msix_bmap_ulds.mapsize = j; 4446 } 4447 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " 4448 "nic %d per uld %d\n", 4449 allocated, s->max_ethqsets, s->nqs_per_uld); 4450 4451 kfree(entries); 4452 return 0; 4453 } 4454 4455 #undef EXTRA_VECS 4456 4457 static int init_rss(struct adapter *adap) 4458 { 4459 unsigned int i; 4460 int err; 4461 4462 err = t4_init_rss_mode(adap, adap->mbox); 4463 if (err) 4464 return err; 4465 4466 for_each_port(adap, i) { 4467 struct port_info *pi = adap2pinfo(adap, i); 4468 4469 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 4470 if (!pi->rss) 4471 return -ENOMEM; 4472 } 4473 return 0; 4474 } 4475 4476 static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap, 4477 enum pci_bus_speed *speed, 4478 enum pcie_link_width *width) 4479 { 4480 u32 lnkcap1, lnkcap2; 4481 int err1, err2; 4482 4483 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ 4484 4485 *speed = PCI_SPEED_UNKNOWN; 4486 *width = PCIE_LNK_WIDTH_UNKNOWN; 4487 4488 err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP, 4489 &lnkcap1); 4490 err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2, 4491 &lnkcap2); 4492 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ 4493 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 4494 *speed = PCIE_SPEED_8_0GT; 4495 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 4496 *speed = PCIE_SPEED_5_0GT; 4497 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 4498 *speed = PCIE_SPEED_2_5GT; 4499 } 4500 if (!err1) { 4501 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; 4502 if (!lnkcap2) { /* pre-r3.0 */ 4503 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) 4504 *speed = PCIE_SPEED_5_0GT; 4505 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) 4506 *speed = PCIE_SPEED_2_5GT; 4507 } 4508 } 4509 4510 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) 4511 return err1 ? err1 : err2 ? err2 : -EINVAL; 4512 return 0; 4513 } 4514 4515 static void cxgb4_check_pcie_caps(struct adapter *adap) 4516 { 4517 enum pcie_link_width width, width_cap; 4518 enum pci_bus_speed speed, speed_cap; 4519 4520 #define PCIE_SPEED_STR(speed) \ 4521 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ 4522 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ 4523 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ 4524 "Unknown") 4525 4526 if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) { 4527 dev_warn(adap->pdev_dev, 4528 "Unable to determine PCIe device BW capabilities\n"); 4529 return; 4530 } 4531 4532 if (pcie_get_minimum_link(adap->pdev, &speed, &width) || 4533 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 4534 dev_warn(adap->pdev_dev, 4535 "Unable to determine PCI Express bandwidth.\n"); 4536 return; 4537 } 4538 4539 dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n", 4540 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); 4541 dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n", 4542 width, width_cap); 4543 if (speed < speed_cap || width < width_cap) 4544 dev_info(adap->pdev_dev, 4545 "A slot with more lanes and/or higher speed is " 4546 "suggested for optimal performance.\n"); 4547 } 4548 4549 /* Dump basic information about the adapter */ 4550 static void print_adapter_info(struct adapter *adapter) 4551 { 4552 /* Hardware/Firmware/etc. Version/Revision IDs */ 4553 t4_dump_version_info(adapter); 4554 4555 /* Software/Hardware configuration */ 4556 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", 4557 is_offload(adapter) ? "R" : "", 4558 ((adapter->flags & USING_MSIX) ? "MSI-X" : 4559 (adapter->flags & USING_MSI) ? "MSI" : ""), 4560 is_offload(adapter) ? "Offload" : "non-Offload"); 4561 } 4562 4563 static void print_port_info(const struct net_device *dev) 4564 { 4565 char buf[80]; 4566 char *bufp = buf; 4567 const char *spd = ""; 4568 const struct port_info *pi = netdev_priv(dev); 4569 const struct adapter *adap = pi->adapter; 4570 4571 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) 4572 spd = " 2.5 GT/s"; 4573 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) 4574 spd = " 5 GT/s"; 4575 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) 4576 spd = " 8 GT/s"; 4577 4578 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 4579 bufp += sprintf(bufp, "100M/"); 4580 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 4581 bufp += sprintf(bufp, "1G/"); 4582 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 4583 bufp += sprintf(bufp, "10G/"); 4584 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 4585 bufp += sprintf(bufp, "25G/"); 4586 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 4587 bufp += sprintf(bufp, "40G/"); 4588 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 4589 bufp += sprintf(bufp, "50G/"); 4590 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 4591 bufp += sprintf(bufp, "100G/"); 4592 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G) 4593 bufp += sprintf(bufp, "200G/"); 4594 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G) 4595 bufp += sprintf(bufp, "400G/"); 4596 if (bufp != buf) 4597 --bufp; 4598 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); 4599 4600 netdev_info(dev, "%s: Chelsio %s (%s) %s\n", 4601 dev->name, adap->params.vpd.id, adap->name, buf); 4602 } 4603 4604 /* 4605 * Free the following resources: 4606 * - memory used for tables 4607 * - MSI/MSI-X 4608 * - net devices 4609 * - resources FW is holding for us 4610 */ 4611 static void free_some_resources(struct adapter *adapter) 4612 { 4613 unsigned int i; 4614 4615 kvfree(adapter->l2t); 4616 t4_cleanup_sched(adapter); 4617 kvfree(adapter->tids.tid_tab); 4618 cxgb4_cleanup_tc_u32(adapter); 4619 kfree(adapter->sge.egr_map); 4620 kfree(adapter->sge.ingr_map); 4621 kfree(adapter->sge.starving_fl); 4622 kfree(adapter->sge.txq_maperr); 4623 #ifdef CONFIG_DEBUG_FS 4624 kfree(adapter->sge.blocked_fl); 4625 #endif 4626 disable_msi(adapter); 4627 4628 for_each_port(adapter, i) 4629 if (adapter->port[i]) { 4630 struct port_info *pi = adap2pinfo(adapter, i); 4631 4632 if (pi->viid != 0) 4633 t4_free_vi(adapter, adapter->mbox, adapter->pf, 4634 0, pi->viid); 4635 kfree(adap2pinfo(adapter, i)->rss); 4636 free_netdev(adapter->port[i]); 4637 } 4638 if (adapter->flags & FW_OK) 4639 t4_fw_bye(adapter, adapter->pf); 4640 } 4641 4642 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) 4643 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ 4644 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) 4645 #define SEGMENT_SIZE 128 4646 4647 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev) 4648 { 4649 u16 device_id; 4650 4651 /* Retrieve adapter's device ID */ 4652 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 4653 4654 switch (device_id >> 12) { 4655 case CHELSIO_T4: 4656 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 4657 case CHELSIO_T5: 4658 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 4659 case CHELSIO_T6: 4660 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 4661 default: 4662 dev_err(&pdev->dev, "Device %d is not supported\n", 4663 device_id); 4664 } 4665 return -EINVAL; 4666 } 4667 4668 #ifdef CONFIG_PCI_IOV 4669 static void dummy_setup(struct net_device *dev) 4670 { 4671 dev->type = ARPHRD_NONE; 4672 dev->mtu = 0; 4673 dev->hard_header_len = 0; 4674 dev->addr_len = 0; 4675 dev->tx_queue_len = 0; 4676 dev->flags |= IFF_NOARP; 4677 dev->priv_flags |= IFF_NO_QUEUE; 4678 4679 /* Initialize the device structure. */ 4680 dev->netdev_ops = &cxgb4_mgmt_netdev_ops; 4681 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; 4682 dev->needs_free_netdev = true; 4683 } 4684 4685 static int config_mgmt_dev(struct pci_dev *pdev) 4686 { 4687 struct adapter *adap = pci_get_drvdata(pdev); 4688 struct net_device *netdev; 4689 struct port_info *pi; 4690 char name[IFNAMSIZ]; 4691 int err; 4692 4693 snprintf(name, IFNAMSIZ, "mgmtpf%d%d", adap->adap_idx, adap->pf); 4694 netdev = alloc_netdev(sizeof(struct port_info), name, NET_NAME_UNKNOWN, 4695 dummy_setup); 4696 if (!netdev) 4697 return -ENOMEM; 4698 4699 pi = netdev_priv(netdev); 4700 pi->adapter = adap; 4701 pi->tx_chan = adap->pf % adap->params.nports; 4702 SET_NETDEV_DEV(netdev, &pdev->dev); 4703 4704 adap->port[0] = netdev; 4705 pi->port_id = 0; 4706 4707 err = register_netdev(adap->port[0]); 4708 if (err) { 4709 pr_info("Unable to register VF mgmt netdev %s\n", name); 4710 free_netdev(adap->port[0]); 4711 adap->port[0] = NULL; 4712 return err; 4713 } 4714 return 0; 4715 } 4716 4717 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) 4718 { 4719 struct adapter *adap = pci_get_drvdata(pdev); 4720 int err = 0; 4721 int current_vfs = pci_num_vf(pdev); 4722 u32 pcie_fw; 4723 4724 pcie_fw = readl(adap->regs + PCIE_FW_A); 4725 /* Check if cxgb4 is the MASTER and fw is initialized */ 4726 if (!(pcie_fw & PCIE_FW_INIT_F) || 4727 !(pcie_fw & PCIE_FW_MASTER_VLD_F) || 4728 PCIE_FW_MASTER_G(pcie_fw) != 4) { 4729 dev_warn(&pdev->dev, 4730 "cxgb4 driver needs to be MASTER to support SRIOV\n"); 4731 return -EOPNOTSUPP; 4732 } 4733 4734 /* If any of the VF's is already assigned to Guest OS, then 4735 * SRIOV for the same cannot be modified 4736 */ 4737 if (current_vfs && pci_vfs_assigned(pdev)) { 4738 dev_err(&pdev->dev, 4739 "Cannot modify SR-IOV while VFs are assigned\n"); 4740 num_vfs = current_vfs; 4741 return num_vfs; 4742 } 4743 4744 /* Disable SRIOV when zero is passed. 4745 * One needs to disable SRIOV before modifying it, else 4746 * stack throws the below warning: 4747 * " 'n' VFs already enabled. Disable before enabling 'm' VFs." 4748 */ 4749 if (!num_vfs) { 4750 pci_disable_sriov(pdev); 4751 if (adap->port[0]) { 4752 unregister_netdev(adap->port[0]); 4753 adap->port[0] = NULL; 4754 } 4755 /* free VF resources */ 4756 kfree(adap->vfinfo); 4757 adap->vfinfo = NULL; 4758 adap->num_vfs = 0; 4759 return num_vfs; 4760 } 4761 4762 if (num_vfs != current_vfs) { 4763 err = pci_enable_sriov(pdev, num_vfs); 4764 if (err) 4765 return err; 4766 4767 adap->num_vfs = num_vfs; 4768 err = config_mgmt_dev(pdev); 4769 if (err) 4770 return err; 4771 } 4772 4773 adap->vfinfo = kcalloc(adap->num_vfs, 4774 sizeof(struct vf_info), GFP_KERNEL); 4775 if (adap->vfinfo) 4776 fill_vf_station_mac_addr(adap); 4777 return num_vfs; 4778 } 4779 #endif 4780 4781 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 4782 { 4783 int func, i, err, s_qpp, qpp, num_seg; 4784 struct port_info *pi; 4785 bool highdma = false; 4786 struct adapter *adapter = NULL; 4787 struct net_device *netdev; 4788 void __iomem *regs; 4789 u32 whoami, pl_rev; 4790 enum chip_type chip; 4791 static int adap_idx = 1; 4792 #ifdef CONFIG_PCI_IOV 4793 u32 v, port_vec; 4794 #endif 4795 4796 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); 4797 4798 err = pci_request_regions(pdev, KBUILD_MODNAME); 4799 if (err) { 4800 /* Just info, some other driver may have claimed the device. */ 4801 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 4802 return err; 4803 } 4804 4805 err = pci_enable_device(pdev); 4806 if (err) { 4807 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4808 goto out_release_regions; 4809 } 4810 4811 regs = pci_ioremap_bar(pdev, 0); 4812 if (!regs) { 4813 dev_err(&pdev->dev, "cannot map device registers\n"); 4814 err = -ENOMEM; 4815 goto out_disable_device; 4816 } 4817 4818 err = t4_wait_dev_ready(regs); 4819 if (err < 0) 4820 goto out_unmap_bar0; 4821 4822 /* We control everything through one PF */ 4823 whoami = readl(regs + PL_WHOAMI_A); 4824 pl_rev = REV_G(readl(regs + PL_REV_A)); 4825 chip = get_chip_type(pdev, pl_rev); 4826 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? 4827 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 4828 if (func != ent->driver_data) { 4829 #ifndef CONFIG_PCI_IOV 4830 iounmap(regs); 4831 #endif 4832 pci_disable_device(pdev); 4833 pci_save_state(pdev); /* to restore SR-IOV later */ 4834 goto sriov; 4835 } 4836 4837 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 4838 highdma = true; 4839 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4840 if (err) { 4841 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 4842 "coherent allocations\n"); 4843 goto out_unmap_bar0; 4844 } 4845 } else { 4846 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4847 if (err) { 4848 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4849 goto out_unmap_bar0; 4850 } 4851 } 4852 4853 pci_enable_pcie_error_reporting(pdev); 4854 pci_set_master(pdev); 4855 pci_save_state(pdev); 4856 4857 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 4858 if (!adapter) { 4859 err = -ENOMEM; 4860 goto out_unmap_bar0; 4861 } 4862 adap_idx++; 4863 4864 adapter->workq = create_singlethread_workqueue("cxgb4"); 4865 if (!adapter->workq) { 4866 err = -ENOMEM; 4867 goto out_free_adapter; 4868 } 4869 4870 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + 4871 (sizeof(struct mbox_cmd) * 4872 T4_OS_LOG_MBOX_CMDS), 4873 GFP_KERNEL); 4874 if (!adapter->mbox_log) { 4875 err = -ENOMEM; 4876 goto out_free_adapter; 4877 } 4878 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; 4879 4880 /* PCI device has been enabled */ 4881 adapter->flags |= DEV_ENABLED; 4882 4883 adapter->regs = regs; 4884 adapter->pdev = pdev; 4885 adapter->pdev_dev = &pdev->dev; 4886 adapter->name = pci_name(pdev); 4887 adapter->mbox = func; 4888 adapter->pf = func; 4889 adapter->msg_enable = DFLT_MSG_ENABLE; 4890 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); 4891 4892 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver 4893 * Ingress Packet Data to Free List Buffers in order to allow for 4894 * chipset performance optimizations between the Root Complex and 4895 * Memory Controllers. (Messages to the associated Ingress Queue 4896 * notifying new Packet Placement in the Free Lists Buffers will be 4897 * send without the Relaxed Ordering Attribute thus guaranteeing that 4898 * all preceding PCIe Transaction Layer Packets will be processed 4899 * first.) But some Root Complexes have various issues with Upstream 4900 * Transaction Layer Packets with the Relaxed Ordering Attribute set. 4901 * The PCIe devices which under the Root Complexes will be cleared the 4902 * Relaxed Ordering bit in the configuration space, So we check our 4903 * PCIe configuration space to see if it's flagged with advice against 4904 * using Relaxed Ordering. 4905 */ 4906 if (!pcie_relaxed_ordering_enabled(pdev)) 4907 adapter->flags |= ROOT_NO_RELAXED_ORDERING; 4908 4909 spin_lock_init(&adapter->stats_lock); 4910 spin_lock_init(&adapter->tid_release_lock); 4911 spin_lock_init(&adapter->win0_lock); 4912 spin_lock_init(&adapter->mbox_lock); 4913 4914 INIT_LIST_HEAD(&adapter->mlist.list); 4915 4916 INIT_WORK(&adapter->tid_release_task, process_tid_release_list); 4917 INIT_WORK(&adapter->db_full_task, process_db_full); 4918 INIT_WORK(&adapter->db_drop_task, process_db_drop); 4919 4920 err = t4_prep_adapter(adapter); 4921 if (err) 4922 goto out_free_adapter; 4923 4924 4925 if (!is_t4(adapter->params.chip)) { 4926 s_qpp = (QUEUESPERPAGEPF0_S + 4927 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * 4928 adapter->pf); 4929 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, 4930 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); 4931 num_seg = PAGE_SIZE / SEGMENT_SIZE; 4932 4933 /* Each segment size is 128B. Write coalescing is enabled only 4934 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the 4935 * queue is less no of segments that can be accommodated in 4936 * a page size. 4937 */ 4938 if (qpp > num_seg) { 4939 dev_err(&pdev->dev, 4940 "Incorrect number of egress queues per page\n"); 4941 err = -EINVAL; 4942 goto out_free_adapter; 4943 } 4944 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), 4945 pci_resource_len(pdev, 2)); 4946 if (!adapter->bar2) { 4947 dev_err(&pdev->dev, "cannot map device bar2 region\n"); 4948 err = -ENOMEM; 4949 goto out_free_adapter; 4950 } 4951 } 4952 4953 setup_memwin(adapter); 4954 err = adap_init0(adapter); 4955 #ifdef CONFIG_DEBUG_FS 4956 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); 4957 #endif 4958 setup_memwin_rdma(adapter); 4959 if (err) 4960 goto out_unmap_bar; 4961 4962 /* configure SGE_STAT_CFG_A to read WC stats */ 4963 if (!is_t4(adapter->params.chip)) 4964 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | 4965 (is_t5(adapter->params.chip) ? STATMODE_V(0) : 4966 T6_STATMODE_V(0))); 4967 4968 for_each_port(adapter, i) { 4969 netdev = alloc_etherdev_mq(sizeof(struct port_info), 4970 MAX_ETH_QSETS); 4971 if (!netdev) { 4972 err = -ENOMEM; 4973 goto out_free_dev; 4974 } 4975 4976 SET_NETDEV_DEV(netdev, &pdev->dev); 4977 4978 adapter->port[i] = netdev; 4979 pi = netdev_priv(netdev); 4980 pi->adapter = adapter; 4981 pi->xact_addr_filt = -1; 4982 pi->port_id = i; 4983 netdev->irq = pdev->irq; 4984 4985 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | 4986 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4987 NETIF_F_RXCSUM | NETIF_F_RXHASH | 4988 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 4989 NETIF_F_HW_TC; 4990 if (highdma) 4991 netdev->hw_features |= NETIF_F_HIGHDMA; 4992 netdev->features |= netdev->hw_features; 4993 netdev->vlan_features = netdev->features & VLAN_FEAT; 4994 4995 netdev->priv_flags |= IFF_UNICAST_FLT; 4996 4997 /* MTU range: 81 - 9600 */ 4998 netdev->min_mtu = 81; 4999 netdev->max_mtu = MAX_MTU; 5000 5001 netdev->netdev_ops = &cxgb4_netdev_ops; 5002 #ifdef CONFIG_CHELSIO_T4_DCB 5003 netdev->dcbnl_ops = &cxgb4_dcb_ops; 5004 cxgb4_dcb_state_init(netdev); 5005 #endif 5006 cxgb4_set_ethtool_ops(netdev); 5007 } 5008 5009 pci_set_drvdata(pdev, adapter); 5010 5011 if (adapter->flags & FW_OK) { 5012 err = t4_port_init(adapter, func, func, 0); 5013 if (err) 5014 goto out_free_dev; 5015 } else if (adapter->params.nports == 1) { 5016 /* If we don't have a connection to the firmware -- possibly 5017 * because of an error -- grab the raw VPD parameters so we 5018 * can set the proper MAC Address on the debug network 5019 * interface that we've created. 5020 */ 5021 u8 hw_addr[ETH_ALEN]; 5022 u8 *na = adapter->params.vpd.na; 5023 5024 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); 5025 if (!err) { 5026 for (i = 0; i < ETH_ALEN; i++) 5027 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 5028 hex2val(na[2 * i + 1])); 5029 t4_set_hw_addr(adapter, 0, hw_addr); 5030 } 5031 } 5032 5033 /* Configure queues and allocate tables now, they can be needed as 5034 * soon as the first register_netdev completes. 5035 */ 5036 cfg_queues(adapter); 5037 5038 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 5039 if (!adapter->l2t) { 5040 /* We tolerate a lack of L2T, giving up some functionality */ 5041 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); 5042 adapter->params.offload = 0; 5043 } 5044 5045 #if IS_ENABLED(CONFIG_IPV6) 5046 if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) && 5047 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { 5048 /* CLIP functionality is not present in hardware, 5049 * hence disable all offload features 5050 */ 5051 dev_warn(&pdev->dev, 5052 "CLIP not enabled in hardware, continuing\n"); 5053 adapter->params.offload = 0; 5054 } else { 5055 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 5056 adapter->clipt_end); 5057 if (!adapter->clipt) { 5058 /* We tolerate a lack of clip_table, giving up 5059 * some functionality 5060 */ 5061 dev_warn(&pdev->dev, 5062 "could not allocate Clip table, continuing\n"); 5063 adapter->params.offload = 0; 5064 } 5065 } 5066 #endif 5067 5068 for_each_port(adapter, i) { 5069 pi = adap2pinfo(adapter, i); 5070 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); 5071 if (!pi->sched_tbl) 5072 dev_warn(&pdev->dev, 5073 "could not activate scheduling on port %d\n", 5074 i); 5075 } 5076 5077 if (tid_init(&adapter->tids) < 0) { 5078 dev_warn(&pdev->dev, "could not allocate TID table, " 5079 "continuing\n"); 5080 adapter->params.offload = 0; 5081 } else { 5082 adapter->tc_u32 = cxgb4_init_tc_u32(adapter); 5083 if (!adapter->tc_u32) 5084 dev_warn(&pdev->dev, 5085 "could not offload tc u32, continuing\n"); 5086 } 5087 5088 if (is_offload(adapter)) { 5089 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { 5090 u32 hash_base, hash_reg; 5091 5092 if (chip <= CHELSIO_T5) { 5093 hash_reg = LE_DB_TID_HASHBASE_A; 5094 hash_base = t4_read_reg(adapter, hash_reg); 5095 adapter->tids.hash_base = hash_base / 4; 5096 } else { 5097 hash_reg = T6_LE_DB_HASH_TID_BASE_A; 5098 hash_base = t4_read_reg(adapter, hash_reg); 5099 adapter->tids.hash_base = hash_base; 5100 } 5101 } 5102 } 5103 5104 /* See what interrupts we'll be using */ 5105 if (msi > 1 && enable_msix(adapter) == 0) 5106 adapter->flags |= USING_MSIX; 5107 else if (msi > 0 && pci_enable_msi(pdev) == 0) { 5108 adapter->flags |= USING_MSI; 5109 if (msi > 1) 5110 free_msix_info(adapter); 5111 } 5112 5113 /* check for PCI Express bandwidth capabiltites */ 5114 cxgb4_check_pcie_caps(adapter); 5115 5116 err = init_rss(adapter); 5117 if (err) 5118 goto out_free_dev; 5119 5120 /* 5121 * The card is now ready to go. If any errors occur during device 5122 * registration we do not fail the whole card but rather proceed only 5123 * with the ports we manage to register successfully. However we must 5124 * register at least one net device. 5125 */ 5126 for_each_port(adapter, i) { 5127 pi = adap2pinfo(adapter, i); 5128 adapter->port[i]->dev_port = pi->lport; 5129 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); 5130 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); 5131 5132 netif_carrier_off(adapter->port[i]); 5133 5134 err = register_netdev(adapter->port[i]); 5135 if (err) 5136 break; 5137 adapter->chan_map[pi->tx_chan] = i; 5138 print_port_info(adapter->port[i]); 5139 } 5140 if (i == 0) { 5141 dev_err(&pdev->dev, "could not register any net devices\n"); 5142 goto out_free_dev; 5143 } 5144 if (err) { 5145 dev_warn(&pdev->dev, "only %d net devices registered\n", i); 5146 err = 0; 5147 } 5148 5149 if (cxgb4_debugfs_root) { 5150 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), 5151 cxgb4_debugfs_root); 5152 setup_debugfs(adapter); 5153 } 5154 5155 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ 5156 pdev->needs_freset = 1; 5157 5158 if (is_uld(adapter)) { 5159 mutex_lock(&uld_mutex); 5160 list_add_tail(&adapter->list_node, &adapter_list); 5161 mutex_unlock(&uld_mutex); 5162 } 5163 5164 if (!is_t4(adapter->params.chip)) 5165 cxgb4_ptp_init(adapter); 5166 5167 print_adapter_info(adapter); 5168 setup_fw_sge_queues(adapter); 5169 return 0; 5170 5171 sriov: 5172 #ifdef CONFIG_PCI_IOV 5173 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 5174 if (!adapter) { 5175 err = -ENOMEM; 5176 goto free_pci_region; 5177 } 5178 5179 adapter->pdev = pdev; 5180 adapter->pdev_dev = &pdev->dev; 5181 adapter->name = pci_name(pdev); 5182 adapter->mbox = func; 5183 adapter->pf = func; 5184 adapter->regs = regs; 5185 adapter->adap_idx = adap_idx; 5186 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + 5187 (sizeof(struct mbox_cmd) * 5188 T4_OS_LOG_MBOX_CMDS), 5189 GFP_KERNEL); 5190 if (!adapter->mbox_log) { 5191 err = -ENOMEM; 5192 goto free_adapter; 5193 } 5194 spin_lock_init(&adapter->mbox_lock); 5195 INIT_LIST_HEAD(&adapter->mlist.list); 5196 5197 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 5198 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 5199 err = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1, 5200 &v, &port_vec); 5201 if (err < 0) { 5202 dev_err(adapter->pdev_dev, "Could not fetch port params\n"); 5203 goto free_mbox_log; 5204 } 5205 5206 adapter->params.nports = hweight32(port_vec); 5207 pci_set_drvdata(pdev, adapter); 5208 return 0; 5209 5210 free_mbox_log: 5211 kfree(adapter->mbox_log); 5212 free_adapter: 5213 kfree(adapter); 5214 free_pci_region: 5215 iounmap(regs); 5216 pci_disable_sriov(pdev); 5217 pci_release_regions(pdev); 5218 return err; 5219 #else 5220 return 0; 5221 #endif 5222 5223 out_free_dev: 5224 free_some_resources(adapter); 5225 if (adapter->flags & USING_MSIX) 5226 free_msix_info(adapter); 5227 if (adapter->num_uld || adapter->num_ofld_uld) 5228 t4_uld_mem_free(adapter); 5229 out_unmap_bar: 5230 if (!is_t4(adapter->params.chip)) 5231 iounmap(adapter->bar2); 5232 out_free_adapter: 5233 if (adapter->workq) 5234 destroy_workqueue(adapter->workq); 5235 5236 kfree(adapter->mbox_log); 5237 kfree(adapter); 5238 out_unmap_bar0: 5239 iounmap(regs); 5240 out_disable_device: 5241 pci_disable_pcie_error_reporting(pdev); 5242 pci_disable_device(pdev); 5243 out_release_regions: 5244 pci_release_regions(pdev); 5245 return err; 5246 } 5247 5248 static void remove_one(struct pci_dev *pdev) 5249 { 5250 struct adapter *adapter = pci_get_drvdata(pdev); 5251 5252 if (!adapter) { 5253 pci_release_regions(pdev); 5254 return; 5255 } 5256 5257 if (adapter->pf == 4) { 5258 int i; 5259 5260 /* Tear down per-adapter Work Queue first since it can contain 5261 * references to our adapter data structure. 5262 */ 5263 destroy_workqueue(adapter->workq); 5264 5265 if (is_uld(adapter)) { 5266 detach_ulds(adapter); 5267 t4_uld_clean_up(adapter); 5268 } 5269 5270 disable_interrupts(adapter); 5271 5272 for_each_port(adapter, i) 5273 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5274 unregister_netdev(adapter->port[i]); 5275 5276 debugfs_remove_recursive(adapter->debugfs_root); 5277 5278 if (!is_t4(adapter->params.chip)) 5279 cxgb4_ptp_stop(adapter); 5280 5281 /* If we allocated filters, free up state associated with any 5282 * valid filters ... 5283 */ 5284 clear_all_filters(adapter); 5285 5286 if (adapter->flags & FULL_INIT_DONE) 5287 cxgb_down(adapter); 5288 5289 if (adapter->flags & USING_MSIX) 5290 free_msix_info(adapter); 5291 if (adapter->num_uld || adapter->num_ofld_uld) 5292 t4_uld_mem_free(adapter); 5293 free_some_resources(adapter); 5294 #if IS_ENABLED(CONFIG_IPV6) 5295 t4_cleanup_clip_tbl(adapter); 5296 #endif 5297 iounmap(adapter->regs); 5298 if (!is_t4(adapter->params.chip)) 5299 iounmap(adapter->bar2); 5300 pci_disable_pcie_error_reporting(pdev); 5301 if ((adapter->flags & DEV_ENABLED)) { 5302 pci_disable_device(pdev); 5303 adapter->flags &= ~DEV_ENABLED; 5304 } 5305 pci_release_regions(pdev); 5306 kfree(adapter->mbox_log); 5307 synchronize_rcu(); 5308 kfree(adapter); 5309 } 5310 #ifdef CONFIG_PCI_IOV 5311 else { 5312 if (adapter->port[0]) 5313 unregister_netdev(adapter->port[0]); 5314 iounmap(adapter->regs); 5315 kfree(adapter->vfinfo); 5316 kfree(adapter->mbox_log); 5317 kfree(adapter); 5318 pci_disable_sriov(pdev); 5319 pci_release_regions(pdev); 5320 } 5321 #endif 5322 } 5323 5324 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt 5325 * delivery. This is essentially a stripped down version of the PCI remove() 5326 * function where we do the minimal amount of work necessary to shutdown any 5327 * further activity. 5328 */ 5329 static void shutdown_one(struct pci_dev *pdev) 5330 { 5331 struct adapter *adapter = pci_get_drvdata(pdev); 5332 5333 /* As with remove_one() above (see extended comment), we only want do 5334 * do cleanup on PCI Devices which went all the way through init_one() 5335 * ... 5336 */ 5337 if (!adapter) { 5338 pci_release_regions(pdev); 5339 return; 5340 } 5341 5342 if (adapter->pf == 4) { 5343 int i; 5344 5345 for_each_port(adapter, i) 5346 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5347 cxgb_close(adapter->port[i]); 5348 5349 if (is_uld(adapter)) { 5350 detach_ulds(adapter); 5351 t4_uld_clean_up(adapter); 5352 } 5353 5354 disable_interrupts(adapter); 5355 disable_msi(adapter); 5356 5357 t4_sge_stop(adapter); 5358 if (adapter->flags & FW_OK) 5359 t4_fw_bye(adapter, adapter->mbox); 5360 } 5361 #ifdef CONFIG_PCI_IOV 5362 else { 5363 if (adapter->port[0]) 5364 unregister_netdev(adapter->port[0]); 5365 iounmap(adapter->regs); 5366 kfree(adapter->vfinfo); 5367 kfree(adapter->mbox_log); 5368 kfree(adapter); 5369 pci_disable_sriov(pdev); 5370 pci_release_regions(pdev); 5371 } 5372 #endif 5373 } 5374 5375 static struct pci_driver cxgb4_driver = { 5376 .name = KBUILD_MODNAME, 5377 .id_table = cxgb4_pci_tbl, 5378 .probe = init_one, 5379 .remove = remove_one, 5380 .shutdown = shutdown_one, 5381 #ifdef CONFIG_PCI_IOV 5382 .sriov_configure = cxgb4_iov_configure, 5383 #endif 5384 .err_handler = &cxgb4_eeh, 5385 }; 5386 5387 static int __init cxgb4_init_module(void) 5388 { 5389 int ret; 5390 5391 /* Debugfs support is optional, just warn if this fails */ 5392 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); 5393 if (!cxgb4_debugfs_root) 5394 pr_warn("could not create debugfs entry, continuing\n"); 5395 5396 ret = pci_register_driver(&cxgb4_driver); 5397 if (ret < 0) 5398 debugfs_remove(cxgb4_debugfs_root); 5399 5400 #if IS_ENABLED(CONFIG_IPV6) 5401 if (!inet6addr_registered) { 5402 register_inet6addr_notifier(&cxgb4_inet6addr_notifier); 5403 inet6addr_registered = true; 5404 } 5405 #endif 5406 5407 return ret; 5408 } 5409 5410 static void __exit cxgb4_cleanup_module(void) 5411 { 5412 #if IS_ENABLED(CONFIG_IPV6) 5413 if (inet6addr_registered) { 5414 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); 5415 inet6addr_registered = false; 5416 } 5417 #endif 5418 pci_unregister_driver(&cxgb4_driver); 5419 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ 5420 } 5421 5422 module_init(cxgb4_init_module); 5423 module_exit(cxgb4_cleanup_module); 5424