1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 36 37 #include <linux/bitmap.h> 38 #include <linux/crc32.h> 39 #include <linux/ctype.h> 40 #include <linux/debugfs.h> 41 #include <linux/err.h> 42 #include <linux/etherdevice.h> 43 #include <linux/firmware.h> 44 #include <linux/if.h> 45 #include <linux/if_vlan.h> 46 #include <linux/init.h> 47 #include <linux/log2.h> 48 #include <linux/mdio.h> 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/mutex.h> 52 #include <linux/netdevice.h> 53 #include <linux/pci.h> 54 #include <linux/aer.h> 55 #include <linux/rtnetlink.h> 56 #include <linux/sched.h> 57 #include <linux/seq_file.h> 58 #include <linux/sockios.h> 59 #include <linux/vmalloc.h> 60 #include <linux/workqueue.h> 61 #include <net/neighbour.h> 62 #include <net/netevent.h> 63 #include <net/addrconf.h> 64 #include <net/bonding.h> 65 #include <linux/uaccess.h> 66 #include <linux/crash_dump.h> 67 #include <net/udp_tunnel.h> 68 #include <net/xfrm.h> 69 70 #include "cxgb4.h" 71 #include "cxgb4_filter.h" 72 #include "t4_regs.h" 73 #include "t4_values.h" 74 #include "t4_msg.h" 75 #include "t4fw_api.h" 76 #include "t4fw_version.h" 77 #include "cxgb4_dcb.h" 78 #include "srq.h" 79 #include "cxgb4_debugfs.h" 80 #include "clip_tbl.h" 81 #include "l2t.h" 82 #include "smt.h" 83 #include "sched.h" 84 #include "cxgb4_tc_u32.h" 85 #include "cxgb4_tc_flower.h" 86 #include "cxgb4_tc_mqprio.h" 87 #include "cxgb4_tc_matchall.h" 88 #include "cxgb4_ptp.h" 89 #include "cxgb4_cudbg.h" 90 91 char cxgb4_driver_name[] = KBUILD_MODNAME; 92 93 #ifdef DRV_VERSION 94 #undef DRV_VERSION 95 #endif 96 #define DRV_VERSION "2.0.0-ko" 97 const char cxgb4_driver_version[] = DRV_VERSION; 98 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" 99 100 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 101 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 102 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 103 104 /* Macros needed to support the PCI Device ID Table ... 105 */ 106 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 107 static const struct pci_device_id cxgb4_pci_tbl[] = { 108 #define CXGB4_UNIFIED_PF 0x4 109 110 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF 111 112 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is 113 * called for both. 114 */ 115 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 116 117 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 118 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF} 119 120 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 121 { 0, } \ 122 } 123 124 #include "t4_pci_id_tbl.h" 125 126 #define FW4_FNAME "cxgb4/t4fw.bin" 127 #define FW5_FNAME "cxgb4/t5fw.bin" 128 #define FW6_FNAME "cxgb4/t6fw.bin" 129 #define FW4_CFNAME "cxgb4/t4-config.txt" 130 #define FW5_CFNAME "cxgb4/t5-config.txt" 131 #define FW6_CFNAME "cxgb4/t6-config.txt" 132 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 133 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 134 #define PHY_AQ1202_DEVICEID 0x4409 135 #define PHY_BCM84834_DEVICEID 0x4486 136 137 MODULE_DESCRIPTION(DRV_DESC); 138 MODULE_AUTHOR("Chelsio Communications"); 139 MODULE_LICENSE("Dual BSD/GPL"); 140 MODULE_VERSION(DRV_VERSION); 141 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); 142 MODULE_FIRMWARE(FW4_FNAME); 143 MODULE_FIRMWARE(FW5_FNAME); 144 MODULE_FIRMWARE(FW6_FNAME); 145 146 /* 147 * The driver uses the best interrupt scheme available on a platform in the 148 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which 149 * of these schemes the driver may consider as follows: 150 * 151 * msi = 2: choose from among all three options 152 * msi = 1: only consider MSI and INTx interrupts 153 * msi = 0: force INTx interrupts 154 */ 155 static int msi = 2; 156 157 module_param(msi, int, 0644); 158 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); 159 160 /* 161 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers 162 * offset by 2 bytes in order to have the IP headers line up on 4-byte 163 * boundaries. This is a requirement for many architectures which will throw 164 * a machine check fault if an attempt is made to access one of the 4-byte IP 165 * header fields on a non-4-byte boundary. And it's a major performance issue 166 * even on some architectures which allow it like some implementations of the 167 * x86 ISA. However, some architectures don't mind this and for some very 168 * edge-case performance sensitive applications (like forwarding large volumes 169 * of small packets), setting this DMA offset to 0 will decrease the number of 170 * PCI-E Bus transfers enough to measurably affect performance. 171 */ 172 static int rx_dma_offset = 2; 173 174 /* TX Queue select used to determine what algorithm to use for selecting TX 175 * queue. Select between the kernel provided function (select_queue=0) or user 176 * cxgb_select_queue function (select_queue=1) 177 * 178 * Default: select_queue=0 179 */ 180 static int select_queue; 181 module_param(select_queue, int, 0644); 182 MODULE_PARM_DESC(select_queue, 183 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); 184 185 static struct dentry *cxgb4_debugfs_root; 186 187 LIST_HEAD(adapter_list); 188 DEFINE_MUTEX(uld_mutex); 189 190 static int cfg_queues(struct adapter *adap); 191 192 static void link_report(struct net_device *dev) 193 { 194 if (!netif_carrier_ok(dev)) 195 netdev_info(dev, "link down\n"); 196 else { 197 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; 198 199 const char *s; 200 const struct port_info *p = netdev_priv(dev); 201 202 switch (p->link_cfg.speed) { 203 case 100: 204 s = "100Mbps"; 205 break; 206 case 1000: 207 s = "1Gbps"; 208 break; 209 case 10000: 210 s = "10Gbps"; 211 break; 212 case 25000: 213 s = "25Gbps"; 214 break; 215 case 40000: 216 s = "40Gbps"; 217 break; 218 case 50000: 219 s = "50Gbps"; 220 break; 221 case 100000: 222 s = "100Gbps"; 223 break; 224 default: 225 pr_info("%s: unsupported speed: %d\n", 226 dev->name, p->link_cfg.speed); 227 return; 228 } 229 230 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, 231 fc[p->link_cfg.fc]); 232 } 233 } 234 235 #ifdef CONFIG_CHELSIO_T4_DCB 236 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ 237 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) 238 { 239 struct port_info *pi = netdev_priv(dev); 240 struct adapter *adap = pi->adapter; 241 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; 242 int i; 243 244 /* We use a simple mapping of Port TX Queue Index to DCB 245 * Priority when we're enabling DCB. 246 */ 247 for (i = 0; i < pi->nqsets; i++, txq++) { 248 u32 name, value; 249 int err; 250 251 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 252 FW_PARAMS_PARAM_X_V( 253 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | 254 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); 255 value = enable ? i : 0xffffffff; 256 257 /* Since we can be called while atomic (from "interrupt 258 * level") we need to issue the Set Parameters Commannd 259 * without sleeping (timeout < 0). 260 */ 261 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 262 &name, &value, 263 -FW_CMD_MAX_TIMEOUT); 264 265 if (err) 266 dev_err(adap->pdev_dev, 267 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", 268 enable ? "set" : "unset", pi->port_id, i, -err); 269 else 270 txq->dcb_prio = enable ? value : 0; 271 } 272 } 273 274 int cxgb4_dcb_enabled(const struct net_device *dev) 275 { 276 struct port_info *pi = netdev_priv(dev); 277 278 if (!pi->dcb.enabled) 279 return 0; 280 281 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || 282 (pi->dcb.state == CXGB4_DCB_STATE_HOST)); 283 } 284 #endif /* CONFIG_CHELSIO_T4_DCB */ 285 286 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) 287 { 288 struct net_device *dev = adapter->port[port_id]; 289 290 /* Skip changes from disabled ports. */ 291 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { 292 if (link_stat) 293 netif_carrier_on(dev); 294 else { 295 #ifdef CONFIG_CHELSIO_T4_DCB 296 if (cxgb4_dcb_enabled(dev)) { 297 cxgb4_dcb_reset(dev); 298 dcb_tx_queue_prio_enable(dev, false); 299 } 300 #endif /* CONFIG_CHELSIO_T4_DCB */ 301 netif_carrier_off(dev); 302 } 303 304 link_report(dev); 305 } 306 } 307 308 void t4_os_portmod_changed(struct adapter *adap, int port_id) 309 { 310 static const char *mod_str[] = { 311 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 312 }; 313 314 struct net_device *dev = adap->port[port_id]; 315 struct port_info *pi = netdev_priv(dev); 316 317 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 318 netdev_info(dev, "port module unplugged\n"); 319 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 320 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); 321 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 322 netdev_info(dev, "%s: unsupported port module inserted\n", 323 dev->name); 324 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 325 netdev_info(dev, "%s: unknown port module inserted\n", 326 dev->name); 327 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 328 netdev_info(dev, "%s: transceiver module error\n", dev->name); 329 else 330 netdev_info(dev, "%s: unknown module type %d inserted\n", 331 dev->name, pi->mod_type); 332 333 /* If the interface is running, then we'll need any "sticky" Link 334 * Parameters redone with a new Transceiver Module. 335 */ 336 pi->link_cfg.redo_l1cfg = netif_running(dev); 337 } 338 339 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ 340 module_param(dbfifo_int_thresh, int, 0644); 341 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); 342 343 /* 344 * usecs to sleep while draining the dbfifo 345 */ 346 static int dbfifo_drain_delay = 1000; 347 module_param(dbfifo_drain_delay, int, 0644); 348 MODULE_PARM_DESC(dbfifo_drain_delay, 349 "usecs to sleep while draining the dbfifo"); 350 351 static inline int cxgb4_set_addr_hash(struct port_info *pi) 352 { 353 struct adapter *adap = pi->adapter; 354 u64 vec = 0; 355 bool ucast = false; 356 struct hash_mac_addr *entry; 357 358 /* Calculate the hash vector for the updated list and program it */ 359 list_for_each_entry(entry, &adap->mac_hlist, list) { 360 ucast |= is_unicast_ether_addr(entry->addr); 361 vec |= (1ULL << hash_mac_addr(entry->addr)); 362 } 363 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, 364 vec, false); 365 } 366 367 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) 368 { 369 struct port_info *pi = netdev_priv(netdev); 370 struct adapter *adap = pi->adapter; 371 int ret; 372 u64 mhash = 0; 373 u64 uhash = 0; 374 /* idx stores the index of allocated filters, 375 * its size should be modified based on the number of 376 * MAC addresses that we allocate filters for 377 */ 378 379 u16 idx[1] = {}; 380 bool free = false; 381 bool ucast = is_unicast_ether_addr(mac_addr); 382 const u8 *maclist[1] = {mac_addr}; 383 struct hash_mac_addr *new_entry; 384 385 ret = cxgb4_alloc_mac_filt(adap, pi->viid, free, 1, maclist, 386 idx, ucast ? &uhash : &mhash, false); 387 if (ret < 0) 388 goto out; 389 /* if hash != 0, then add the addr to hash addr list 390 * so on the end we will calculate the hash for the 391 * list and program it 392 */ 393 if (uhash || mhash) { 394 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); 395 if (!new_entry) 396 return -ENOMEM; 397 ether_addr_copy(new_entry->addr, mac_addr); 398 list_add_tail(&new_entry->list, &adap->mac_hlist); 399 ret = cxgb4_set_addr_hash(pi); 400 } 401 out: 402 return ret < 0 ? ret : 0; 403 } 404 405 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) 406 { 407 struct port_info *pi = netdev_priv(netdev); 408 struct adapter *adap = pi->adapter; 409 int ret; 410 const u8 *maclist[1] = {mac_addr}; 411 struct hash_mac_addr *entry, *tmp; 412 413 /* If the MAC address to be removed is in the hash addr 414 * list, delete it from the list and update hash vector 415 */ 416 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { 417 if (ether_addr_equal(entry->addr, mac_addr)) { 418 list_del(&entry->list); 419 kfree(entry); 420 return cxgb4_set_addr_hash(pi); 421 } 422 } 423 424 ret = cxgb4_free_mac_filt(adap, pi->viid, 1, maclist, false); 425 return ret < 0 ? -EINVAL : 0; 426 } 427 428 /* 429 * Set Rx properties of a port, such as promiscruity, address filters, and MTU. 430 * If @mtu is -1 it is left unchanged. 431 */ 432 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) 433 { 434 struct port_info *pi = netdev_priv(dev); 435 struct adapter *adapter = pi->adapter; 436 437 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 438 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 439 440 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, 441 (dev->flags & IFF_PROMISC) ? 1 : 0, 442 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, 443 sleep_ok); 444 } 445 446 /** 447 * cxgb4_change_mac - Update match filter for a MAC address. 448 * @pi: the port_info 449 * @viid: the VI id 450 * @tcam_idx: TCAM index of existing filter for old value of MAC address, 451 * or -1 452 * @addr: the new MAC address value 453 * @persist: whether a new MAC allocation should be persistent 454 * @add_smt: if true also add the address to the HW SMT 455 * 456 * Modifies an MPS filter and sets it to the new MAC address if 457 * @tcam_idx >= 0, or adds the MAC address to a new filter if 458 * @tcam_idx < 0. In the latter case the address is added persistently 459 * if @persist is %true. 460 * Addresses are programmed to hash region, if tcam runs out of entries. 461 * 462 */ 463 int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 464 int *tcam_idx, const u8 *addr, bool persist, 465 u8 *smt_idx) 466 { 467 struct adapter *adapter = pi->adapter; 468 struct hash_mac_addr *entry, *new_entry; 469 int ret; 470 471 ret = t4_change_mac(adapter, adapter->mbox, viid, 472 *tcam_idx, addr, persist, smt_idx); 473 /* We ran out of TCAM entries. try programming hash region. */ 474 if (ret == -ENOMEM) { 475 /* If the MAC address to be updated is in the hash addr 476 * list, update it from the list 477 */ 478 list_for_each_entry(entry, &adapter->mac_hlist, list) { 479 if (entry->iface_mac) { 480 ether_addr_copy(entry->addr, addr); 481 goto set_hash; 482 } 483 } 484 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL); 485 if (!new_entry) 486 return -ENOMEM; 487 ether_addr_copy(new_entry->addr, addr); 488 new_entry->iface_mac = true; 489 list_add_tail(&new_entry->list, &adapter->mac_hlist); 490 set_hash: 491 ret = cxgb4_set_addr_hash(pi); 492 } else if (ret >= 0) { 493 *tcam_idx = ret; 494 ret = 0; 495 } 496 497 return ret; 498 } 499 500 /* 501 * link_start - enable a port 502 * @dev: the port to enable 503 * 504 * Performs the MAC and PHY actions needed to enable a port. 505 */ 506 static int link_start(struct net_device *dev) 507 { 508 int ret; 509 struct port_info *pi = netdev_priv(dev); 510 unsigned int mb = pi->adapter->pf; 511 512 /* 513 * We do not set address filters and promiscuity here, the stack does 514 * that step explicitly. 515 */ 516 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, 517 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 518 if (ret == 0) 519 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt, 520 dev->dev_addr, true, &pi->smt_idx); 521 if (ret == 0) 522 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, 523 &pi->link_cfg); 524 if (ret == 0) { 525 local_bh_disable(); 526 ret = t4_enable_pi_params(pi->adapter, mb, pi, true, 527 true, CXGB4_DCB_ENABLED); 528 local_bh_enable(); 529 } 530 531 return ret; 532 } 533 534 #ifdef CONFIG_CHELSIO_T4_DCB 535 /* Handle a Data Center Bridging update message from the firmware. */ 536 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) 537 { 538 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); 539 struct net_device *dev = adap->port[adap->chan_map[port]]; 540 int old_dcb_enabled = cxgb4_dcb_enabled(dev); 541 int new_dcb_enabled; 542 543 cxgb4_dcb_handle_fw_update(adap, pcmd); 544 new_dcb_enabled = cxgb4_dcb_enabled(dev); 545 546 /* If the DCB has become enabled or disabled on the port then we're 547 * going to need to set up/tear down DCB Priority parameters for the 548 * TX Queues associated with the port. 549 */ 550 if (new_dcb_enabled != old_dcb_enabled) 551 dcb_tx_queue_prio_enable(dev, new_dcb_enabled); 552 } 553 #endif /* CONFIG_CHELSIO_T4_DCB */ 554 555 /* Response queue handler for the FW event queue. 556 */ 557 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 558 const struct pkt_gl *gl) 559 { 560 u8 opcode = ((const struct rss_header *)rsp)->opcode; 561 562 rsp++; /* skip RSS header */ 563 564 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 565 */ 566 if (unlikely(opcode == CPL_FW4_MSG && 567 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { 568 rsp++; 569 opcode = ((const struct rss_header *)rsp)->opcode; 570 rsp++; 571 if (opcode != CPL_SGE_EGR_UPDATE) { 572 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" 573 , opcode); 574 goto out; 575 } 576 } 577 578 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 579 const struct cpl_sge_egr_update *p = (void *)rsp; 580 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); 581 struct sge_txq *txq; 582 583 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; 584 txq->restarts++; 585 if (txq->q_type == CXGB4_TXQ_ETH) { 586 struct sge_eth_txq *eq; 587 588 eq = container_of(txq, struct sge_eth_txq, q); 589 t4_sge_eth_txq_egress_update(q->adap, eq, -1); 590 } else { 591 struct sge_uld_txq *oq; 592 593 oq = container_of(txq, struct sge_uld_txq, q); 594 tasklet_schedule(&oq->qresume_tsk); 595 } 596 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 597 const struct cpl_fw6_msg *p = (void *)rsp; 598 599 #ifdef CONFIG_CHELSIO_T4_DCB 600 const struct fw_port_cmd *pcmd = (const void *)p->data; 601 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); 602 unsigned int action = 603 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); 604 605 if (cmd == FW_PORT_CMD && 606 (action == FW_PORT_ACTION_GET_PORT_INFO || 607 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 608 int port = FW_PORT_CMD_PORTID_G( 609 be32_to_cpu(pcmd->op_to_portid)); 610 struct net_device *dev; 611 int dcbxdis, state_input; 612 613 dev = q->adap->port[q->adap->chan_map[port]]; 614 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO 615 ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F) 616 : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32) 617 & FW_PORT_CMD_DCBXDIS32_F)); 618 state_input = (dcbxdis 619 ? CXGB4_DCB_INPUT_FW_DISABLED 620 : CXGB4_DCB_INPUT_FW_ENABLED); 621 622 cxgb4_dcb_state_fsm(dev, state_input); 623 } 624 625 if (cmd == FW_PORT_CMD && 626 action == FW_PORT_ACTION_L2_DCB_CFG) 627 dcb_rpl(q->adap, pcmd); 628 else 629 #endif 630 if (p->type == 0) 631 t4_handle_fw_rpl(q->adap, p->data); 632 } else if (opcode == CPL_L2T_WRITE_RPL) { 633 const struct cpl_l2t_write_rpl *p = (void *)rsp; 634 635 do_l2t_write_rpl(q->adap, p); 636 } else if (opcode == CPL_SMT_WRITE_RPL) { 637 const struct cpl_smt_write_rpl *p = (void *)rsp; 638 639 do_smt_write_rpl(q->adap, p); 640 } else if (opcode == CPL_SET_TCB_RPL) { 641 const struct cpl_set_tcb_rpl *p = (void *)rsp; 642 643 filter_rpl(q->adap, p); 644 } else if (opcode == CPL_ACT_OPEN_RPL) { 645 const struct cpl_act_open_rpl *p = (void *)rsp; 646 647 hash_filter_rpl(q->adap, p); 648 } else if (opcode == CPL_ABORT_RPL_RSS) { 649 const struct cpl_abort_rpl_rss *p = (void *)rsp; 650 651 hash_del_filter_rpl(q->adap, p); 652 } else if (opcode == CPL_SRQ_TABLE_RPL) { 653 const struct cpl_srq_table_rpl *p = (void *)rsp; 654 655 do_srq_table_rpl(q->adap, p); 656 } else 657 dev_err(q->adap->pdev_dev, 658 "unexpected CPL %#x on FW event queue\n", opcode); 659 out: 660 return 0; 661 } 662 663 static void disable_msi(struct adapter *adapter) 664 { 665 if (adapter->flags & CXGB4_USING_MSIX) { 666 pci_disable_msix(adapter->pdev); 667 adapter->flags &= ~CXGB4_USING_MSIX; 668 } else if (adapter->flags & CXGB4_USING_MSI) { 669 pci_disable_msi(adapter->pdev); 670 adapter->flags &= ~CXGB4_USING_MSI; 671 } 672 } 673 674 /* 675 * Interrupt handler for non-data events used with MSI-X. 676 */ 677 static irqreturn_t t4_nondata_intr(int irq, void *cookie) 678 { 679 struct adapter *adap = cookie; 680 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); 681 682 if (v & PFSW_F) { 683 adap->swintr = 1; 684 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); 685 } 686 if (adap->flags & CXGB4_MASTER_PF) 687 t4_slow_intr_handler(adap); 688 return IRQ_HANDLED; 689 } 690 691 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 692 cpumask_var_t *aff_mask, int idx) 693 { 694 int rv; 695 696 if (!zalloc_cpumask_var(aff_mask, GFP_KERNEL)) { 697 dev_err(adap->pdev_dev, "alloc_cpumask_var failed\n"); 698 return -ENOMEM; 699 } 700 701 cpumask_set_cpu(cpumask_local_spread(idx, dev_to_node(adap->pdev_dev)), 702 *aff_mask); 703 704 rv = irq_set_affinity_hint(vec, *aff_mask); 705 if (rv) 706 dev_warn(adap->pdev_dev, 707 "irq_set_affinity_hint %u failed %d\n", 708 vec, rv); 709 710 return 0; 711 } 712 713 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask) 714 { 715 irq_set_affinity_hint(vec, NULL); 716 free_cpumask_var(aff_mask); 717 } 718 719 static int request_msix_queue_irqs(struct adapter *adap) 720 { 721 struct sge *s = &adap->sge; 722 struct msix_info *minfo; 723 int err, ethqidx; 724 725 if (s->fwevtq_msix_idx < 0) 726 return -ENOMEM; 727 728 err = request_irq(adap->msix_info[s->fwevtq_msix_idx].vec, 729 t4_sge_intr_msix, 0, 730 adap->msix_info[s->fwevtq_msix_idx].desc, 731 &s->fw_evtq); 732 if (err) 733 return err; 734 735 for_each_ethrxq(s, ethqidx) { 736 minfo = s->ethrxq[ethqidx].msix; 737 err = request_irq(minfo->vec, 738 t4_sge_intr_msix, 0, 739 minfo->desc, 740 &s->ethrxq[ethqidx].rspq); 741 if (err) 742 goto unwind; 743 744 cxgb4_set_msix_aff(adap, minfo->vec, 745 &minfo->aff_mask, ethqidx); 746 } 747 return 0; 748 749 unwind: 750 while (--ethqidx >= 0) { 751 minfo = s->ethrxq[ethqidx].msix; 752 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask); 753 free_irq(minfo->vec, &s->ethrxq[ethqidx].rspq); 754 } 755 free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq); 756 return err; 757 } 758 759 static void free_msix_queue_irqs(struct adapter *adap) 760 { 761 struct sge *s = &adap->sge; 762 struct msix_info *minfo; 763 int i; 764 765 free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq); 766 for_each_ethrxq(s, i) { 767 minfo = s->ethrxq[i].msix; 768 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask); 769 free_irq(minfo->vec, &s->ethrxq[i].rspq); 770 } 771 } 772 773 static int setup_ppod_edram(struct adapter *adap) 774 { 775 unsigned int param, val; 776 int ret; 777 778 /* Driver sends FW_PARAMS_PARAM_DEV_PPOD_EDRAM read command to check 779 * if firmware supports ppod edram feature or not. If firmware 780 * returns 1, then driver can enable this feature by sending 781 * FW_PARAMS_PARAM_DEV_PPOD_EDRAM write command with value 1 to 782 * enable ppod edram feature. 783 */ 784 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 785 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PPOD_EDRAM)); 786 787 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 788 if (ret < 0) { 789 dev_warn(adap->pdev_dev, 790 "querying PPOD_EDRAM support failed: %d\n", 791 ret); 792 return -1; 793 } 794 795 if (val != 1) 796 return -1; 797 798 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 799 if (ret < 0) { 800 dev_err(adap->pdev_dev, 801 "setting PPOD_EDRAM failed: %d\n", ret); 802 return -1; 803 } 804 return 0; 805 } 806 807 /** 808 * cxgb4_write_rss - write the RSS table for a given port 809 * @pi: the port 810 * @queues: array of queue indices for RSS 811 * 812 * Sets up the portion of the HW RSS table for the port's VI to distribute 813 * packets to the Rx queues in @queues. 814 * Should never be called before setting up sge eth rx queues 815 */ 816 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 817 { 818 u16 *rss; 819 int i, err; 820 struct adapter *adapter = pi->adapter; 821 const struct sge_eth_rxq *rxq; 822 823 rxq = &adapter->sge.ethrxq[pi->first_qset]; 824 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL); 825 if (!rss) 826 return -ENOMEM; 827 828 /* map the queue indices to queue ids */ 829 for (i = 0; i < pi->rss_size; i++, queues++) 830 rss[i] = rxq[*queues].rspq.abs_id; 831 832 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 833 pi->rss_size, rss, pi->rss_size); 834 /* If Tunnel All Lookup isn't specified in the global RSS 835 * Configuration, then we need to specify a default Ingress 836 * Queue for any ingress packets which aren't hashed. We'll 837 * use our first ingress queue ... 838 */ 839 if (!err) 840 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 841 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | 842 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | 843 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | 844 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | 845 FW_RSS_VI_CONFIG_CMD_UDPEN_F, 846 rss[0]); 847 kfree(rss); 848 return err; 849 } 850 851 /** 852 * setup_rss - configure RSS 853 * @adap: the adapter 854 * 855 * Sets up RSS for each port. 856 */ 857 static int setup_rss(struct adapter *adap) 858 { 859 int i, j, err; 860 861 for_each_port(adap, i) { 862 const struct port_info *pi = adap2pinfo(adap, i); 863 864 /* Fill default values with equal distribution */ 865 for (j = 0; j < pi->rss_size; j++) 866 pi->rss[j] = j % pi->nqsets; 867 868 err = cxgb4_write_rss(pi, pi->rss); 869 if (err) 870 return err; 871 } 872 return 0; 873 } 874 875 /* 876 * Return the channel of the ingress queue with the given qid. 877 */ 878 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) 879 { 880 qid -= p->ingr_start; 881 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; 882 } 883 884 void cxgb4_quiesce_rx(struct sge_rspq *q) 885 { 886 if (q->handler) 887 napi_disable(&q->napi); 888 } 889 890 /* 891 * Wait until all NAPI handlers are descheduled. 892 */ 893 static void quiesce_rx(struct adapter *adap) 894 { 895 int i; 896 897 for (i = 0; i < adap->sge.ingr_sz; i++) { 898 struct sge_rspq *q = adap->sge.ingr_map[i]; 899 900 if (!q) 901 continue; 902 903 cxgb4_quiesce_rx(q); 904 } 905 } 906 907 /* Disable interrupt and napi handler */ 908 static void disable_interrupts(struct adapter *adap) 909 { 910 struct sge *s = &adap->sge; 911 912 if (adap->flags & CXGB4_FULL_INIT_DONE) { 913 t4_intr_disable(adap); 914 if (adap->flags & CXGB4_USING_MSIX) { 915 free_msix_queue_irqs(adap); 916 free_irq(adap->msix_info[s->nd_msix_idx].vec, 917 adap); 918 } else { 919 free_irq(adap->pdev->irq, adap); 920 } 921 quiesce_rx(adap); 922 } 923 } 924 925 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q) 926 { 927 if (q->handler) 928 napi_enable(&q->napi); 929 930 /* 0-increment GTS to start the timer and enable interrupts */ 931 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 932 SEINTARM_V(q->intr_params) | 933 INGRESSQID_V(q->cntxt_id)); 934 } 935 936 /* 937 * Enable NAPI scheduling and interrupt generation for all Rx queues. 938 */ 939 static void enable_rx(struct adapter *adap) 940 { 941 int i; 942 943 for (i = 0; i < adap->sge.ingr_sz; i++) { 944 struct sge_rspq *q = adap->sge.ingr_map[i]; 945 946 if (!q) 947 continue; 948 949 cxgb4_enable_rx(adap, q); 950 } 951 } 952 953 static int setup_non_data_intr(struct adapter *adap) 954 { 955 int msix; 956 957 adap->sge.nd_msix_idx = -1; 958 if (!(adap->flags & CXGB4_USING_MSIX)) 959 return 0; 960 961 /* Request MSI-X vector for non-data interrupt */ 962 msix = cxgb4_get_msix_idx_from_bmap(adap); 963 if (msix < 0) 964 return -ENOMEM; 965 966 snprintf(adap->msix_info[msix].desc, 967 sizeof(adap->msix_info[msix].desc), 968 "%s", adap->port[0]->name); 969 970 adap->sge.nd_msix_idx = msix; 971 return 0; 972 } 973 974 static int setup_fw_sge_queues(struct adapter *adap) 975 { 976 struct sge *s = &adap->sge; 977 int msix, err = 0; 978 979 bitmap_zero(s->starving_fl, s->egr_sz); 980 bitmap_zero(s->txq_maperr, s->egr_sz); 981 982 if (adap->flags & CXGB4_USING_MSIX) { 983 s->fwevtq_msix_idx = -1; 984 msix = cxgb4_get_msix_idx_from_bmap(adap); 985 if (msix < 0) 986 return -ENOMEM; 987 988 snprintf(adap->msix_info[msix].desc, 989 sizeof(adap->msix_info[msix].desc), 990 "%s-FWeventq", adap->port[0]->name); 991 } else { 992 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, 993 NULL, NULL, NULL, -1); 994 if (err) 995 return err; 996 msix = -((int)s->intrq.abs_id + 1); 997 } 998 999 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], 1000 msix, NULL, fwevtq_handler, NULL, -1); 1001 if (err && msix >= 0) 1002 cxgb4_free_msix_idx_in_bmap(adap, msix); 1003 1004 s->fwevtq_msix_idx = msix; 1005 return err; 1006 } 1007 1008 /** 1009 * setup_sge_queues - configure SGE Tx/Rx/response queues 1010 * @adap: the adapter 1011 * 1012 * Determines how many sets of SGE queues to use and initializes them. 1013 * We support multiple queue sets per port if we have MSI-X, otherwise 1014 * just one queue set per port. 1015 */ 1016 static int setup_sge_queues(struct adapter *adap) 1017 { 1018 struct sge_uld_rxq_info *rxq_info = NULL; 1019 struct sge *s = &adap->sge; 1020 unsigned int cmplqid = 0; 1021 int err, i, j, msix = 0; 1022 1023 if (is_uld(adap)) 1024 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; 1025 1026 if (!(adap->flags & CXGB4_USING_MSIX)) 1027 msix = -((int)s->intrq.abs_id + 1); 1028 1029 for_each_port(adap, i) { 1030 struct net_device *dev = adap->port[i]; 1031 struct port_info *pi = netdev_priv(dev); 1032 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; 1033 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; 1034 1035 for (j = 0; j < pi->nqsets; j++, q++) { 1036 if (msix >= 0) { 1037 msix = cxgb4_get_msix_idx_from_bmap(adap); 1038 if (msix < 0) { 1039 err = msix; 1040 goto freeout; 1041 } 1042 1043 snprintf(adap->msix_info[msix].desc, 1044 sizeof(adap->msix_info[msix].desc), 1045 "%s-Rx%d", dev->name, j); 1046 q->msix = &adap->msix_info[msix]; 1047 } 1048 1049 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, 1050 msix, &q->fl, 1051 t4_ethrx_handler, 1052 NULL, 1053 t4_get_tp_ch_map(adap, 1054 pi->tx_chan)); 1055 if (err) 1056 goto freeout; 1057 q->rspq.idx = j; 1058 memset(&q->stats, 0, sizeof(q->stats)); 1059 } 1060 1061 q = &s->ethrxq[pi->first_qset]; 1062 for (j = 0; j < pi->nqsets; j++, t++, q++) { 1063 err = t4_sge_alloc_eth_txq(adap, t, dev, 1064 netdev_get_tx_queue(dev, j), 1065 q->rspq.cntxt_id, 1066 !!(adap->flags & CXGB4_SGE_DBQ_TIMER)); 1067 if (err) 1068 goto freeout; 1069 } 1070 } 1071 1072 for_each_port(adap, i) { 1073 /* Note that cmplqid below is 0 if we don't 1074 * have RDMA queues, and that's the right value. 1075 */ 1076 if (rxq_info) 1077 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; 1078 1079 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], 1080 s->fw_evtq.cntxt_id, cmplqid); 1081 if (err) 1082 goto freeout; 1083 } 1084 1085 if (!is_t4(adap->params.chip)) { 1086 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0], 1087 netdev_get_tx_queue(adap->port[0], 0) 1088 , s->fw_evtq.cntxt_id, false); 1089 if (err) 1090 goto freeout; 1091 } 1092 1093 t4_write_reg(adap, is_t4(adap->params.chip) ? 1094 MPS_TRC_RSS_CONTROL_A : 1095 MPS_T5_TRC_RSS_CONTROL_A, 1096 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | 1097 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); 1098 return 0; 1099 freeout: 1100 dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err); 1101 t4_free_sge_resources(adap); 1102 return err; 1103 } 1104 1105 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, 1106 struct net_device *sb_dev) 1107 { 1108 int txq; 1109 1110 #ifdef CONFIG_CHELSIO_T4_DCB 1111 /* If a Data Center Bridging has been successfully negotiated on this 1112 * link then we'll use the skb's priority to map it to a TX Queue. 1113 * The skb's priority is determined via the VLAN Tag Priority Code 1114 * Point field. 1115 */ 1116 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) { 1117 u16 vlan_tci; 1118 int err; 1119 1120 err = vlan_get_tag(skb, &vlan_tci); 1121 if (unlikely(err)) { 1122 if (net_ratelimit()) 1123 netdev_warn(dev, 1124 "TX Packet without VLAN Tag on DCB Link\n"); 1125 txq = 0; 1126 } else { 1127 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 1128 #ifdef CONFIG_CHELSIO_T4_FCOE 1129 if (skb->protocol == htons(ETH_P_FCOE)) 1130 txq = skb->priority & 0x7; 1131 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1132 } 1133 return txq; 1134 } 1135 #endif /* CONFIG_CHELSIO_T4_DCB */ 1136 1137 if (dev->num_tc) { 1138 struct port_info *pi = netdev2pinfo(dev); 1139 u8 ver, proto; 1140 1141 ver = ip_hdr(skb)->version; 1142 proto = (ver == 6) ? ipv6_hdr(skb)->nexthdr : 1143 ip_hdr(skb)->protocol; 1144 1145 /* Send unsupported traffic pattern to normal NIC queues. */ 1146 txq = netdev_pick_tx(dev, skb, sb_dev); 1147 if (xfrm_offload(skb) || is_ptp_enabled(skb, dev) || 1148 skb->encapsulation || 1149 (proto != IPPROTO_TCP && proto != IPPROTO_UDP)) 1150 txq = txq % pi->nqsets; 1151 1152 return txq; 1153 } 1154 1155 if (select_queue) { 1156 txq = (skb_rx_queue_recorded(skb) 1157 ? skb_get_rx_queue(skb) 1158 : smp_processor_id()); 1159 1160 while (unlikely(txq >= dev->real_num_tx_queues)) 1161 txq -= dev->real_num_tx_queues; 1162 1163 return txq; 1164 } 1165 1166 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 1167 } 1168 1169 static int closest_timer(const struct sge *s, int time) 1170 { 1171 int i, delta, match = 0, min_delta = INT_MAX; 1172 1173 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 1174 delta = time - s->timer_val[i]; 1175 if (delta < 0) 1176 delta = -delta; 1177 if (delta < min_delta) { 1178 min_delta = delta; 1179 match = i; 1180 } 1181 } 1182 return match; 1183 } 1184 1185 static int closest_thres(const struct sge *s, int thres) 1186 { 1187 int i, delta, match = 0, min_delta = INT_MAX; 1188 1189 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 1190 delta = thres - s->counter_val[i]; 1191 if (delta < 0) 1192 delta = -delta; 1193 if (delta < min_delta) { 1194 min_delta = delta; 1195 match = i; 1196 } 1197 } 1198 return match; 1199 } 1200 1201 /** 1202 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 1203 * @q: the Rx queue 1204 * @us: the hold-off time in us, or 0 to disable timer 1205 * @cnt: the hold-off packet count, or 0 to disable counter 1206 * 1207 * Sets an Rx queue's interrupt hold-off time and packet count. At least 1208 * one of the two needs to be enabled for the queue to generate interrupts. 1209 */ 1210 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, 1211 unsigned int us, unsigned int cnt) 1212 { 1213 struct adapter *adap = q->adap; 1214 1215 if ((us | cnt) == 0) 1216 cnt = 1; 1217 1218 if (cnt) { 1219 int err; 1220 u32 v, new_idx; 1221 1222 new_idx = closest_thres(&adap->sge, cnt); 1223 if (q->desc && q->pktcnt_idx != new_idx) { 1224 /* the queue has already been created, update it */ 1225 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 1226 FW_PARAMS_PARAM_X_V( 1227 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 1228 FW_PARAMS_PARAM_YZ_V(q->cntxt_id); 1229 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 1230 &v, &new_idx); 1231 if (err) 1232 return err; 1233 } 1234 q->pktcnt_idx = new_idx; 1235 } 1236 1237 us = us == 0 ? 6 : closest_timer(&adap->sge, us); 1238 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); 1239 return 0; 1240 } 1241 1242 static int cxgb_set_features(struct net_device *dev, netdev_features_t features) 1243 { 1244 const struct port_info *pi = netdev_priv(dev); 1245 netdev_features_t changed = dev->features ^ features; 1246 int err; 1247 1248 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) 1249 return 0; 1250 1251 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, 1252 -1, -1, -1, 1253 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); 1254 if (unlikely(err)) 1255 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; 1256 return err; 1257 } 1258 1259 static int setup_debugfs(struct adapter *adap) 1260 { 1261 if (IS_ERR_OR_NULL(adap->debugfs_root)) 1262 return -1; 1263 1264 #ifdef CONFIG_DEBUG_FS 1265 t4_setup_debugfs(adap); 1266 #endif 1267 return 0; 1268 } 1269 1270 /* 1271 * upper-layer driver support 1272 */ 1273 1274 /* 1275 * Allocate an active-open TID and set it to the supplied value. 1276 */ 1277 int cxgb4_alloc_atid(struct tid_info *t, void *data) 1278 { 1279 int atid = -1; 1280 1281 spin_lock_bh(&t->atid_lock); 1282 if (t->afree) { 1283 union aopen_entry *p = t->afree; 1284 1285 atid = (p - t->atid_tab) + t->atid_base; 1286 t->afree = p->next; 1287 p->data = data; 1288 t->atids_in_use++; 1289 } 1290 spin_unlock_bh(&t->atid_lock); 1291 return atid; 1292 } 1293 EXPORT_SYMBOL(cxgb4_alloc_atid); 1294 1295 /* 1296 * Release an active-open TID. 1297 */ 1298 void cxgb4_free_atid(struct tid_info *t, unsigned int atid) 1299 { 1300 union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; 1301 1302 spin_lock_bh(&t->atid_lock); 1303 p->next = t->afree; 1304 t->afree = p; 1305 t->atids_in_use--; 1306 spin_unlock_bh(&t->atid_lock); 1307 } 1308 EXPORT_SYMBOL(cxgb4_free_atid); 1309 1310 /* 1311 * Allocate a server TID and set it to the supplied value. 1312 */ 1313 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) 1314 { 1315 int stid; 1316 1317 spin_lock_bh(&t->stid_lock); 1318 if (family == PF_INET) { 1319 stid = find_first_zero_bit(t->stid_bmap, t->nstids); 1320 if (stid < t->nstids) 1321 __set_bit(stid, t->stid_bmap); 1322 else 1323 stid = -1; 1324 } else { 1325 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); 1326 if (stid < 0) 1327 stid = -1; 1328 } 1329 if (stid >= 0) { 1330 t->stid_tab[stid].data = data; 1331 stid += t->stid_base; 1332 /* IPv6 requires max of 520 bits or 16 cells in TCAM 1333 * This is equivalent to 4 TIDs. With CLIP enabled it 1334 * needs 2 TIDs. 1335 */ 1336 if (family == PF_INET6) { 1337 t->stids_in_use += 2; 1338 t->v6_stids_in_use += 2; 1339 } else { 1340 t->stids_in_use++; 1341 } 1342 } 1343 spin_unlock_bh(&t->stid_lock); 1344 return stid; 1345 } 1346 EXPORT_SYMBOL(cxgb4_alloc_stid); 1347 1348 /* Allocate a server filter TID and set it to the supplied value. 1349 */ 1350 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) 1351 { 1352 int stid; 1353 1354 spin_lock_bh(&t->stid_lock); 1355 if (family == PF_INET) { 1356 stid = find_next_zero_bit(t->stid_bmap, 1357 t->nstids + t->nsftids, t->nstids); 1358 if (stid < (t->nstids + t->nsftids)) 1359 __set_bit(stid, t->stid_bmap); 1360 else 1361 stid = -1; 1362 } else { 1363 stid = -1; 1364 } 1365 if (stid >= 0) { 1366 t->stid_tab[stid].data = data; 1367 stid -= t->nstids; 1368 stid += t->sftid_base; 1369 t->sftids_in_use++; 1370 } 1371 spin_unlock_bh(&t->stid_lock); 1372 return stid; 1373 } 1374 EXPORT_SYMBOL(cxgb4_alloc_sftid); 1375 1376 /* Release a server TID. 1377 */ 1378 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) 1379 { 1380 /* Is it a server filter TID? */ 1381 if (t->nsftids && (stid >= t->sftid_base)) { 1382 stid -= t->sftid_base; 1383 stid += t->nstids; 1384 } else { 1385 stid -= t->stid_base; 1386 } 1387 1388 spin_lock_bh(&t->stid_lock); 1389 if (family == PF_INET) 1390 __clear_bit(stid, t->stid_bmap); 1391 else 1392 bitmap_release_region(t->stid_bmap, stid, 1); 1393 t->stid_tab[stid].data = NULL; 1394 if (stid < t->nstids) { 1395 if (family == PF_INET6) { 1396 t->stids_in_use -= 2; 1397 t->v6_stids_in_use -= 2; 1398 } else { 1399 t->stids_in_use--; 1400 } 1401 } else { 1402 t->sftids_in_use--; 1403 } 1404 1405 spin_unlock_bh(&t->stid_lock); 1406 } 1407 EXPORT_SYMBOL(cxgb4_free_stid); 1408 1409 /* 1410 * Populate a TID_RELEASE WR. Caller must properly size the skb. 1411 */ 1412 static void mk_tid_release(struct sk_buff *skb, unsigned int chan, 1413 unsigned int tid) 1414 { 1415 struct cpl_tid_release *req; 1416 1417 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); 1418 req = __skb_put(skb, sizeof(*req)); 1419 INIT_TP_WR(req, tid); 1420 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); 1421 } 1422 1423 /* 1424 * Queue a TID release request and if necessary schedule a work queue to 1425 * process it. 1426 */ 1427 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, 1428 unsigned int tid) 1429 { 1430 void **p = &t->tid_tab[tid]; 1431 struct adapter *adap = container_of(t, struct adapter, tids); 1432 1433 spin_lock_bh(&adap->tid_release_lock); 1434 *p = adap->tid_release_head; 1435 /* Low 2 bits encode the Tx channel number */ 1436 adap->tid_release_head = (void **)((uintptr_t)p | chan); 1437 if (!adap->tid_release_task_busy) { 1438 adap->tid_release_task_busy = true; 1439 queue_work(adap->workq, &adap->tid_release_task); 1440 } 1441 spin_unlock_bh(&adap->tid_release_lock); 1442 } 1443 1444 /* 1445 * Process the list of pending TID release requests. 1446 */ 1447 static void process_tid_release_list(struct work_struct *work) 1448 { 1449 struct sk_buff *skb; 1450 struct adapter *adap; 1451 1452 adap = container_of(work, struct adapter, tid_release_task); 1453 1454 spin_lock_bh(&adap->tid_release_lock); 1455 while (adap->tid_release_head) { 1456 void **p = adap->tid_release_head; 1457 unsigned int chan = (uintptr_t)p & 3; 1458 p = (void *)p - chan; 1459 1460 adap->tid_release_head = *p; 1461 *p = NULL; 1462 spin_unlock_bh(&adap->tid_release_lock); 1463 1464 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), 1465 GFP_KERNEL))) 1466 schedule_timeout_uninterruptible(1); 1467 1468 mk_tid_release(skb, chan, p - adap->tids.tid_tab); 1469 t4_ofld_send(adap, skb); 1470 spin_lock_bh(&adap->tid_release_lock); 1471 } 1472 adap->tid_release_task_busy = false; 1473 spin_unlock_bh(&adap->tid_release_lock); 1474 } 1475 1476 /* 1477 * Release a TID and inform HW. If we are unable to allocate the release 1478 * message we defer to a work queue. 1479 */ 1480 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 1481 unsigned short family) 1482 { 1483 struct sk_buff *skb; 1484 struct adapter *adap = container_of(t, struct adapter, tids); 1485 1486 WARN_ON(tid >= t->ntids); 1487 1488 if (t->tid_tab[tid]) { 1489 t->tid_tab[tid] = NULL; 1490 atomic_dec(&t->conns_in_use); 1491 if (t->hash_base && (tid >= t->hash_base)) { 1492 if (family == AF_INET6) 1493 atomic_sub(2, &t->hash_tids_in_use); 1494 else 1495 atomic_dec(&t->hash_tids_in_use); 1496 } else { 1497 if (family == AF_INET6) 1498 atomic_sub(2, &t->tids_in_use); 1499 else 1500 atomic_dec(&t->tids_in_use); 1501 } 1502 } 1503 1504 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); 1505 if (likely(skb)) { 1506 mk_tid_release(skb, chan, tid); 1507 t4_ofld_send(adap, skb); 1508 } else 1509 cxgb4_queue_tid_release(t, chan, tid); 1510 } 1511 EXPORT_SYMBOL(cxgb4_remove_tid); 1512 1513 /* 1514 * Allocate and initialize the TID tables. Returns 0 on success. 1515 */ 1516 static int tid_init(struct tid_info *t) 1517 { 1518 struct adapter *adap = container_of(t, struct adapter, tids); 1519 unsigned int max_ftids = t->nftids + t->nsftids; 1520 unsigned int natids = t->natids; 1521 unsigned int eotid_bmap_size; 1522 unsigned int stid_bmap_size; 1523 unsigned int ftid_bmap_size; 1524 size_t size; 1525 1526 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); 1527 ftid_bmap_size = BITS_TO_LONGS(t->nftids); 1528 eotid_bmap_size = BITS_TO_LONGS(t->neotids); 1529 size = t->ntids * sizeof(*t->tid_tab) + 1530 natids * sizeof(*t->atid_tab) + 1531 t->nstids * sizeof(*t->stid_tab) + 1532 t->nsftids * sizeof(*t->stid_tab) + 1533 stid_bmap_size * sizeof(long) + 1534 max_ftids * sizeof(*t->ftid_tab) + 1535 ftid_bmap_size * sizeof(long) + 1536 t->neotids * sizeof(*t->eotid_tab) + 1537 eotid_bmap_size * sizeof(long); 1538 1539 t->tid_tab = kvzalloc(size, GFP_KERNEL); 1540 if (!t->tid_tab) 1541 return -ENOMEM; 1542 1543 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 1544 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; 1545 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; 1546 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; 1547 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; 1548 t->eotid_tab = (struct eotid_entry *)&t->ftid_bmap[ftid_bmap_size]; 1549 t->eotid_bmap = (unsigned long *)&t->eotid_tab[t->neotids]; 1550 spin_lock_init(&t->stid_lock); 1551 spin_lock_init(&t->atid_lock); 1552 spin_lock_init(&t->ftid_lock); 1553 1554 t->stids_in_use = 0; 1555 t->v6_stids_in_use = 0; 1556 t->sftids_in_use = 0; 1557 t->afree = NULL; 1558 t->atids_in_use = 0; 1559 atomic_set(&t->tids_in_use, 0); 1560 atomic_set(&t->conns_in_use, 0); 1561 atomic_set(&t->hash_tids_in_use, 0); 1562 1563 /* Setup the free list for atid_tab and clear the stid bitmap. */ 1564 if (natids) { 1565 while (--natids) 1566 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 1567 t->afree = t->atid_tab; 1568 } 1569 1570 if (is_offload(adap)) { 1571 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1572 /* Reserve stid 0 for T4/T5 adapters */ 1573 if (!t->stid_base && 1574 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1575 __set_bit(0, t->stid_bmap); 1576 1577 if (t->neotids) 1578 bitmap_zero(t->eotid_bmap, t->neotids); 1579 } 1580 1581 bitmap_zero(t->ftid_bmap, t->nftids); 1582 return 0; 1583 } 1584 1585 /** 1586 * cxgb4_create_server - create an IP server 1587 * @dev: the device 1588 * @stid: the server TID 1589 * @sip: local IP address to bind server to 1590 * @sport: the server's TCP port 1591 * @queue: queue to direct messages from this server to 1592 * 1593 * Create an IP server for the given port and address. 1594 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1595 */ 1596 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 1597 __be32 sip, __be16 sport, __be16 vlan, 1598 unsigned int queue) 1599 { 1600 unsigned int chan; 1601 struct sk_buff *skb; 1602 struct adapter *adap; 1603 struct cpl_pass_open_req *req; 1604 int ret; 1605 1606 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1607 if (!skb) 1608 return -ENOMEM; 1609 1610 adap = netdev2adap(dev); 1611 req = __skb_put(skb, sizeof(*req)); 1612 INIT_TP_WR(req, 0); 1613 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); 1614 req->local_port = sport; 1615 req->peer_port = htons(0); 1616 req->local_ip = sip; 1617 req->peer_ip = htonl(0); 1618 chan = rxq_to_chan(&adap->sge, queue); 1619 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1620 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1621 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1622 ret = t4_mgmt_tx(adap, skb); 1623 return net_xmit_eval(ret); 1624 } 1625 EXPORT_SYMBOL(cxgb4_create_server); 1626 1627 /* cxgb4_create_server6 - create an IPv6 server 1628 * @dev: the device 1629 * @stid: the server TID 1630 * @sip: local IPv6 address to bind server to 1631 * @sport: the server's TCP port 1632 * @queue: queue to direct messages from this server to 1633 * 1634 * Create an IPv6 server for the given port and address. 1635 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1636 */ 1637 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 1638 const struct in6_addr *sip, __be16 sport, 1639 unsigned int queue) 1640 { 1641 unsigned int chan; 1642 struct sk_buff *skb; 1643 struct adapter *adap; 1644 struct cpl_pass_open_req6 *req; 1645 int ret; 1646 1647 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1648 if (!skb) 1649 return -ENOMEM; 1650 1651 adap = netdev2adap(dev); 1652 req = __skb_put(skb, sizeof(*req)); 1653 INIT_TP_WR(req, 0); 1654 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); 1655 req->local_port = sport; 1656 req->peer_port = htons(0); 1657 req->local_ip_hi = *(__be64 *)(sip->s6_addr); 1658 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); 1659 req->peer_ip_hi = cpu_to_be64(0); 1660 req->peer_ip_lo = cpu_to_be64(0); 1661 chan = rxq_to_chan(&adap->sge, queue); 1662 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1663 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1664 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1665 ret = t4_mgmt_tx(adap, skb); 1666 return net_xmit_eval(ret); 1667 } 1668 EXPORT_SYMBOL(cxgb4_create_server6); 1669 1670 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 1671 unsigned int queue, bool ipv6) 1672 { 1673 struct sk_buff *skb; 1674 struct adapter *adap; 1675 struct cpl_close_listsvr_req *req; 1676 int ret; 1677 1678 adap = netdev2adap(dev); 1679 1680 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1681 if (!skb) 1682 return -ENOMEM; 1683 1684 req = __skb_put(skb, sizeof(*req)); 1685 INIT_TP_WR(req, 0); 1686 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); 1687 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : 1688 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); 1689 ret = t4_mgmt_tx(adap, skb); 1690 return net_xmit_eval(ret); 1691 } 1692 EXPORT_SYMBOL(cxgb4_remove_server); 1693 1694 /** 1695 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU 1696 * @mtus: the HW MTU table 1697 * @mtu: the target MTU 1698 * @idx: index of selected entry in the MTU table 1699 * 1700 * Returns the index and the value in the HW MTU table that is closest to 1701 * but does not exceed @mtu, unless @mtu is smaller than any value in the 1702 * table, in which case that smallest available value is selected. 1703 */ 1704 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 1705 unsigned int *idx) 1706 { 1707 unsigned int i = 0; 1708 1709 while (i < NMTUS - 1 && mtus[i + 1] <= mtu) 1710 ++i; 1711 if (idx) 1712 *idx = i; 1713 return mtus[i]; 1714 } 1715 EXPORT_SYMBOL(cxgb4_best_mtu); 1716 1717 /** 1718 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned 1719 * @mtus: the HW MTU table 1720 * @header_size: Header Size 1721 * @data_size_max: maximum Data Segment Size 1722 * @data_size_align: desired Data Segment Size Alignment (2^N) 1723 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) 1724 * 1725 * Similar to cxgb4_best_mtu() but instead of searching the Hardware 1726 * MTU Table based solely on a Maximum MTU parameter, we break that 1727 * parameter up into a Header Size and Maximum Data Segment Size, and 1728 * provide a desired Data Segment Size Alignment. If we find an MTU in 1729 * the Hardware MTU Table which will result in a Data Segment Size with 1730 * the requested alignment _and_ that MTU isn't "too far" from the 1731 * closest MTU, then we'll return that rather than the closest MTU. 1732 */ 1733 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 1734 unsigned short header_size, 1735 unsigned short data_size_max, 1736 unsigned short data_size_align, 1737 unsigned int *mtu_idxp) 1738 { 1739 unsigned short max_mtu = header_size + data_size_max; 1740 unsigned short data_size_align_mask = data_size_align - 1; 1741 int mtu_idx, aligned_mtu_idx; 1742 1743 /* Scan the MTU Table till we find an MTU which is larger than our 1744 * Maximum MTU or we reach the end of the table. Along the way, 1745 * record the last MTU found, if any, which will result in a Data 1746 * Segment Length matching the requested alignment. 1747 */ 1748 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { 1749 unsigned short data_size = mtus[mtu_idx] - header_size; 1750 1751 /* If this MTU minus the Header Size would result in a 1752 * Data Segment Size of the desired alignment, remember it. 1753 */ 1754 if ((data_size & data_size_align_mask) == 0) 1755 aligned_mtu_idx = mtu_idx; 1756 1757 /* If we're not at the end of the Hardware MTU Table and the 1758 * next element is larger than our Maximum MTU, drop out of 1759 * the loop. 1760 */ 1761 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) 1762 break; 1763 } 1764 1765 /* If we fell out of the loop because we ran to the end of the table, 1766 * then we just have to use the last [largest] entry. 1767 */ 1768 if (mtu_idx == NMTUS) 1769 mtu_idx--; 1770 1771 /* If we found an MTU which resulted in the requested Data Segment 1772 * Length alignment and that's "not far" from the largest MTU which is 1773 * less than or equal to the maximum MTU, then use that. 1774 */ 1775 if (aligned_mtu_idx >= 0 && 1776 mtu_idx - aligned_mtu_idx <= 1) 1777 mtu_idx = aligned_mtu_idx; 1778 1779 /* If the caller has passed in an MTU Index pointer, pass the 1780 * MTU Index back. Return the MTU value. 1781 */ 1782 if (mtu_idxp) 1783 *mtu_idxp = mtu_idx; 1784 return mtus[mtu_idx]; 1785 } 1786 EXPORT_SYMBOL(cxgb4_best_aligned_mtu); 1787 1788 /** 1789 * cxgb4_port_chan - get the HW channel of a port 1790 * @dev: the net device for the port 1791 * 1792 * Return the HW Tx channel of the given port. 1793 */ 1794 unsigned int cxgb4_port_chan(const struct net_device *dev) 1795 { 1796 return netdev2pinfo(dev)->tx_chan; 1797 } 1798 EXPORT_SYMBOL(cxgb4_port_chan); 1799 1800 /** 1801 * cxgb4_port_e2cchan - get the HW c-channel of a port 1802 * @dev: the net device for the port 1803 * 1804 * Return the HW RX c-channel of the given port. 1805 */ 1806 unsigned int cxgb4_port_e2cchan(const struct net_device *dev) 1807 { 1808 return netdev2pinfo(dev)->rx_cchan; 1809 } 1810 EXPORT_SYMBOL(cxgb4_port_e2cchan); 1811 1812 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 1813 { 1814 struct adapter *adap = netdev2adap(dev); 1815 u32 v1, v2, lp_count, hp_count; 1816 1817 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1818 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1819 if (is_t4(adap->params.chip)) { 1820 lp_count = LP_COUNT_G(v1); 1821 hp_count = HP_COUNT_G(v1); 1822 } else { 1823 lp_count = LP_COUNT_T5_G(v1); 1824 hp_count = HP_COUNT_T5_G(v2); 1825 } 1826 return lpfifo ? lp_count : hp_count; 1827 } 1828 EXPORT_SYMBOL(cxgb4_dbfifo_count); 1829 1830 /** 1831 * cxgb4_port_viid - get the VI id of a port 1832 * @dev: the net device for the port 1833 * 1834 * Return the VI id of the given port. 1835 */ 1836 unsigned int cxgb4_port_viid(const struct net_device *dev) 1837 { 1838 return netdev2pinfo(dev)->viid; 1839 } 1840 EXPORT_SYMBOL(cxgb4_port_viid); 1841 1842 /** 1843 * cxgb4_port_idx - get the index of a port 1844 * @dev: the net device for the port 1845 * 1846 * Return the index of the given port. 1847 */ 1848 unsigned int cxgb4_port_idx(const struct net_device *dev) 1849 { 1850 return netdev2pinfo(dev)->port_id; 1851 } 1852 EXPORT_SYMBOL(cxgb4_port_idx); 1853 1854 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 1855 struct tp_tcp_stats *v6) 1856 { 1857 struct adapter *adap = pci_get_drvdata(pdev); 1858 1859 spin_lock(&adap->stats_lock); 1860 t4_tp_get_tcp_stats(adap, v4, v6, false); 1861 spin_unlock(&adap->stats_lock); 1862 } 1863 EXPORT_SYMBOL(cxgb4_get_tcp_stats); 1864 1865 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 1866 const unsigned int *pgsz_order) 1867 { 1868 struct adapter *adap = netdev2adap(dev); 1869 1870 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); 1871 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | 1872 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | 1873 HPZ3_V(pgsz_order[3])); 1874 } 1875 EXPORT_SYMBOL(cxgb4_iscsi_init); 1876 1877 int cxgb4_flush_eq_cache(struct net_device *dev) 1878 { 1879 struct adapter *adap = netdev2adap(dev); 1880 1881 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS); 1882 } 1883 EXPORT_SYMBOL(cxgb4_flush_eq_cache); 1884 1885 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 1886 { 1887 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; 1888 __be64 indices; 1889 int ret; 1890 1891 spin_lock(&adap->win0_lock); 1892 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, 1893 sizeof(indices), (__be32 *)&indices, 1894 T4_MEMORY_READ); 1895 spin_unlock(&adap->win0_lock); 1896 if (!ret) { 1897 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; 1898 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; 1899 } 1900 return ret; 1901 } 1902 1903 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 1904 u16 size) 1905 { 1906 struct adapter *adap = netdev2adap(dev); 1907 u16 hw_pidx, hw_cidx; 1908 int ret; 1909 1910 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); 1911 if (ret) 1912 goto out; 1913 1914 if (pidx != hw_pidx) { 1915 u16 delta; 1916 u32 val; 1917 1918 if (pidx >= hw_pidx) 1919 delta = pidx - hw_pidx; 1920 else 1921 delta = size - hw_pidx + pidx; 1922 1923 if (is_t4(adap->params.chip)) 1924 val = PIDX_V(delta); 1925 else 1926 val = PIDX_T5_V(delta); 1927 wmb(); 1928 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1929 QID_V(qid) | val); 1930 } 1931 out: 1932 return ret; 1933 } 1934 EXPORT_SYMBOL(cxgb4_sync_txq_pidx); 1935 1936 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) 1937 { 1938 u32 edc0_size, edc1_size, mc0_size, mc1_size, size; 1939 u32 edc0_end, edc1_end, mc0_end, mc1_end; 1940 u32 offset, memtype, memaddr; 1941 struct adapter *adap; 1942 u32 hma_size = 0; 1943 int ret; 1944 1945 adap = netdev2adap(dev); 1946 1947 offset = ((stag >> 8) * 32) + adap->vres.stag.start; 1948 1949 /* Figure out where the offset lands in the Memory Type/Address scheme. 1950 * This code assumes that the memory is laid out starting at offset 0 1951 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 1952 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have 1953 * MC0, and some have both MC0 and MC1. 1954 */ 1955 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 1956 edc0_size = EDRAM0_SIZE_G(size) << 20; 1957 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 1958 edc1_size = EDRAM1_SIZE_G(size) << 20; 1959 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 1960 mc0_size = EXT_MEM0_SIZE_G(size) << 20; 1961 1962 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) { 1963 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 1964 hma_size = EXT_MEM1_SIZE_G(size) << 20; 1965 } 1966 edc0_end = edc0_size; 1967 edc1_end = edc0_end + edc1_size; 1968 mc0_end = edc1_end + mc0_size; 1969 1970 if (offset < edc0_end) { 1971 memtype = MEM_EDC0; 1972 memaddr = offset; 1973 } else if (offset < edc1_end) { 1974 memtype = MEM_EDC1; 1975 memaddr = offset - edc0_end; 1976 } else { 1977 if (hma_size && (offset < (edc1_end + hma_size))) { 1978 memtype = MEM_HMA; 1979 memaddr = offset - edc1_end; 1980 } else if (offset < mc0_end) { 1981 memtype = MEM_MC0; 1982 memaddr = offset - edc1_end; 1983 } else if (is_t5(adap->params.chip)) { 1984 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 1985 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 1986 mc1_end = mc0_end + mc1_size; 1987 if (offset < mc1_end) { 1988 memtype = MEM_MC1; 1989 memaddr = offset - mc0_end; 1990 } else { 1991 /* offset beyond the end of any memory */ 1992 goto err; 1993 } 1994 } else { 1995 /* T4/T6 only has a single memory channel */ 1996 goto err; 1997 } 1998 } 1999 2000 spin_lock(&adap->win0_lock); 2001 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); 2002 spin_unlock(&adap->win0_lock); 2003 return ret; 2004 2005 err: 2006 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", 2007 stag, offset); 2008 return -EINVAL; 2009 } 2010 EXPORT_SYMBOL(cxgb4_read_tpte); 2011 2012 u64 cxgb4_read_sge_timestamp(struct net_device *dev) 2013 { 2014 u32 hi, lo; 2015 struct adapter *adap; 2016 2017 adap = netdev2adap(dev); 2018 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); 2019 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); 2020 2021 return ((u64)hi << 32) | (u64)lo; 2022 } 2023 EXPORT_SYMBOL(cxgb4_read_sge_timestamp); 2024 2025 int cxgb4_bar2_sge_qregs(struct net_device *dev, 2026 unsigned int qid, 2027 enum cxgb4_bar2_qtype qtype, 2028 int user, 2029 u64 *pbar2_qoffset, 2030 unsigned int *pbar2_qid) 2031 { 2032 return t4_bar2_sge_qregs(netdev2adap(dev), 2033 qid, 2034 (qtype == CXGB4_BAR2_QTYPE_EGRESS 2035 ? T4_BAR2_QTYPE_EGRESS 2036 : T4_BAR2_QTYPE_INGRESS), 2037 user, 2038 pbar2_qoffset, 2039 pbar2_qid); 2040 } 2041 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); 2042 2043 static struct pci_driver cxgb4_driver; 2044 2045 static void check_neigh_update(struct neighbour *neigh) 2046 { 2047 const struct device *parent; 2048 const struct net_device *netdev = neigh->dev; 2049 2050 if (is_vlan_dev(netdev)) 2051 netdev = vlan_dev_real_dev(netdev); 2052 parent = netdev->dev.parent; 2053 if (parent && parent->driver == &cxgb4_driver.driver) 2054 t4_l2t_update(dev_get_drvdata(parent), neigh); 2055 } 2056 2057 static int netevent_cb(struct notifier_block *nb, unsigned long event, 2058 void *data) 2059 { 2060 switch (event) { 2061 case NETEVENT_NEIGH_UPDATE: 2062 check_neigh_update(data); 2063 break; 2064 case NETEVENT_REDIRECT: 2065 default: 2066 break; 2067 } 2068 return 0; 2069 } 2070 2071 static bool netevent_registered; 2072 static struct notifier_block cxgb4_netevent_nb = { 2073 .notifier_call = netevent_cb 2074 }; 2075 2076 static void drain_db_fifo(struct adapter *adap, int usecs) 2077 { 2078 u32 v1, v2, lp_count, hp_count; 2079 2080 do { 2081 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 2082 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 2083 if (is_t4(adap->params.chip)) { 2084 lp_count = LP_COUNT_G(v1); 2085 hp_count = HP_COUNT_G(v1); 2086 } else { 2087 lp_count = LP_COUNT_T5_G(v1); 2088 hp_count = HP_COUNT_T5_G(v2); 2089 } 2090 2091 if (lp_count == 0 && hp_count == 0) 2092 break; 2093 set_current_state(TASK_UNINTERRUPTIBLE); 2094 schedule_timeout(usecs_to_jiffies(usecs)); 2095 } while (1); 2096 } 2097 2098 static void disable_txq_db(struct sge_txq *q) 2099 { 2100 unsigned long flags; 2101 2102 spin_lock_irqsave(&q->db_lock, flags); 2103 q->db_disabled = 1; 2104 spin_unlock_irqrestore(&q->db_lock, flags); 2105 } 2106 2107 static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 2108 { 2109 spin_lock_irq(&q->db_lock); 2110 if (q->db_pidx_inc) { 2111 /* Make sure that all writes to the TX descriptors 2112 * are committed before we tell HW about them. 2113 */ 2114 wmb(); 2115 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2116 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); 2117 q->db_pidx_inc = 0; 2118 } 2119 q->db_disabled = 0; 2120 spin_unlock_irq(&q->db_lock); 2121 } 2122 2123 static void disable_dbs(struct adapter *adap) 2124 { 2125 int i; 2126 2127 for_each_ethrxq(&adap->sge, i) 2128 disable_txq_db(&adap->sge.ethtxq[i].q); 2129 if (is_offload(adap)) { 2130 struct sge_uld_txq_info *txq_info = 2131 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2132 2133 if (txq_info) { 2134 for_each_ofldtxq(&adap->sge, i) { 2135 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2136 2137 disable_txq_db(&txq->q); 2138 } 2139 } 2140 } 2141 for_each_port(adap, i) 2142 disable_txq_db(&adap->sge.ctrlq[i].q); 2143 } 2144 2145 static void enable_dbs(struct adapter *adap) 2146 { 2147 int i; 2148 2149 for_each_ethrxq(&adap->sge, i) 2150 enable_txq_db(adap, &adap->sge.ethtxq[i].q); 2151 if (is_offload(adap)) { 2152 struct sge_uld_txq_info *txq_info = 2153 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2154 2155 if (txq_info) { 2156 for_each_ofldtxq(&adap->sge, i) { 2157 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2158 2159 enable_txq_db(adap, &txq->q); 2160 } 2161 } 2162 } 2163 for_each_port(adap, i) 2164 enable_txq_db(adap, &adap->sge.ctrlq[i].q); 2165 } 2166 2167 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) 2168 { 2169 enum cxgb4_uld type = CXGB4_ULD_RDMA; 2170 2171 if (adap->uld && adap->uld[type].handle) 2172 adap->uld[type].control(adap->uld[type].handle, cmd); 2173 } 2174 2175 static void process_db_full(struct work_struct *work) 2176 { 2177 struct adapter *adap; 2178 2179 adap = container_of(work, struct adapter, db_full_task); 2180 2181 drain_db_fifo(adap, dbfifo_drain_delay); 2182 enable_dbs(adap); 2183 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2184 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2185 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2186 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 2187 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 2188 else 2189 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2190 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); 2191 } 2192 2193 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 2194 { 2195 u16 hw_pidx, hw_cidx; 2196 int ret; 2197 2198 spin_lock_irq(&q->db_lock); 2199 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); 2200 if (ret) 2201 goto out; 2202 if (q->db_pidx != hw_pidx) { 2203 u16 delta; 2204 u32 val; 2205 2206 if (q->db_pidx >= hw_pidx) 2207 delta = q->db_pidx - hw_pidx; 2208 else 2209 delta = q->size - hw_pidx + q->db_pidx; 2210 2211 if (is_t4(adap->params.chip)) 2212 val = PIDX_V(delta); 2213 else 2214 val = PIDX_T5_V(delta); 2215 wmb(); 2216 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2217 QID_V(q->cntxt_id) | val); 2218 } 2219 out: 2220 q->db_disabled = 0; 2221 q->db_pidx_inc = 0; 2222 spin_unlock_irq(&q->db_lock); 2223 if (ret) 2224 CH_WARN(adap, "DB drop recovery failed.\n"); 2225 } 2226 2227 static void recover_all_queues(struct adapter *adap) 2228 { 2229 int i; 2230 2231 for_each_ethrxq(&adap->sge, i) 2232 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); 2233 if (is_offload(adap)) { 2234 struct sge_uld_txq_info *txq_info = 2235 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2236 if (txq_info) { 2237 for_each_ofldtxq(&adap->sge, i) { 2238 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2239 2240 sync_txq_pidx(adap, &txq->q); 2241 } 2242 } 2243 } 2244 for_each_port(adap, i) 2245 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); 2246 } 2247 2248 static void process_db_drop(struct work_struct *work) 2249 { 2250 struct adapter *adap; 2251 2252 adap = container_of(work, struct adapter, db_drop_task); 2253 2254 if (is_t4(adap->params.chip)) { 2255 drain_db_fifo(adap, dbfifo_drain_delay); 2256 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); 2257 drain_db_fifo(adap, dbfifo_drain_delay); 2258 recover_all_queues(adap); 2259 drain_db_fifo(adap, dbfifo_drain_delay); 2260 enable_dbs(adap); 2261 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2262 } else if (is_t5(adap->params.chip)) { 2263 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2264 u16 qid = (dropped_db >> 15) & 0x1ffff; 2265 u16 pidx_inc = dropped_db & 0x1fff; 2266 u64 bar2_qoffset; 2267 unsigned int bar2_qid; 2268 int ret; 2269 2270 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, 2271 0, &bar2_qoffset, &bar2_qid); 2272 if (ret) 2273 dev_err(adap->pdev_dev, "doorbell drop recovery: " 2274 "qid=%d, pidx_inc=%d\n", qid, pidx_inc); 2275 else 2276 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), 2277 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); 2278 2279 /* Re-enable BAR2 WC */ 2280 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2281 } 2282 2283 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2284 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2285 } 2286 2287 void t4_db_full(struct adapter *adap) 2288 { 2289 if (is_t4(adap->params.chip)) { 2290 disable_dbs(adap); 2291 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2292 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2293 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); 2294 queue_work(adap->workq, &adap->db_full_task); 2295 } 2296 } 2297 2298 void t4_db_dropped(struct adapter *adap) 2299 { 2300 if (is_t4(adap->params.chip)) { 2301 disable_dbs(adap); 2302 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2303 } 2304 queue_work(adap->workq, &adap->db_drop_task); 2305 } 2306 2307 void t4_register_netevent_notifier(void) 2308 { 2309 if (!netevent_registered) { 2310 register_netevent_notifier(&cxgb4_netevent_nb); 2311 netevent_registered = true; 2312 } 2313 } 2314 2315 static void detach_ulds(struct adapter *adap) 2316 { 2317 unsigned int i; 2318 2319 mutex_lock(&uld_mutex); 2320 list_del(&adap->list_node); 2321 2322 for (i = 0; i < CXGB4_ULD_MAX; i++) 2323 if (adap->uld && adap->uld[i].handle) 2324 adap->uld[i].state_change(adap->uld[i].handle, 2325 CXGB4_STATE_DETACH); 2326 2327 if (netevent_registered && list_empty(&adapter_list)) { 2328 unregister_netevent_notifier(&cxgb4_netevent_nb); 2329 netevent_registered = false; 2330 } 2331 mutex_unlock(&uld_mutex); 2332 } 2333 2334 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) 2335 { 2336 unsigned int i; 2337 2338 mutex_lock(&uld_mutex); 2339 for (i = 0; i < CXGB4_ULD_MAX; i++) 2340 if (adap->uld && adap->uld[i].handle) 2341 adap->uld[i].state_change(adap->uld[i].handle, 2342 new_state); 2343 mutex_unlock(&uld_mutex); 2344 } 2345 2346 #if IS_ENABLED(CONFIG_IPV6) 2347 static int cxgb4_inet6addr_handler(struct notifier_block *this, 2348 unsigned long event, void *data) 2349 { 2350 struct inet6_ifaddr *ifa = data; 2351 struct net_device *event_dev = ifa->idev->dev; 2352 const struct device *parent = NULL; 2353 #if IS_ENABLED(CONFIG_BONDING) 2354 struct adapter *adap; 2355 #endif 2356 if (is_vlan_dev(event_dev)) 2357 event_dev = vlan_dev_real_dev(event_dev); 2358 #if IS_ENABLED(CONFIG_BONDING) 2359 if (event_dev->flags & IFF_MASTER) { 2360 list_for_each_entry(adap, &adapter_list, list_node) { 2361 switch (event) { 2362 case NETDEV_UP: 2363 cxgb4_clip_get(adap->port[0], 2364 (const u32 *)ifa, 1); 2365 break; 2366 case NETDEV_DOWN: 2367 cxgb4_clip_release(adap->port[0], 2368 (const u32 *)ifa, 1); 2369 break; 2370 default: 2371 break; 2372 } 2373 } 2374 return NOTIFY_OK; 2375 } 2376 #endif 2377 2378 if (event_dev) 2379 parent = event_dev->dev.parent; 2380 2381 if (parent && parent->driver == &cxgb4_driver.driver) { 2382 switch (event) { 2383 case NETDEV_UP: 2384 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); 2385 break; 2386 case NETDEV_DOWN: 2387 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); 2388 break; 2389 default: 2390 break; 2391 } 2392 } 2393 return NOTIFY_OK; 2394 } 2395 2396 static bool inet6addr_registered; 2397 static struct notifier_block cxgb4_inet6addr_notifier = { 2398 .notifier_call = cxgb4_inet6addr_handler 2399 }; 2400 2401 static void update_clip(const struct adapter *adap) 2402 { 2403 int i; 2404 struct net_device *dev; 2405 int ret; 2406 2407 rcu_read_lock(); 2408 2409 for (i = 0; i < MAX_NPORTS; i++) { 2410 dev = adap->port[i]; 2411 ret = 0; 2412 2413 if (dev) 2414 ret = cxgb4_update_root_dev_clip(dev); 2415 2416 if (ret < 0) 2417 break; 2418 } 2419 rcu_read_unlock(); 2420 } 2421 #endif /* IS_ENABLED(CONFIG_IPV6) */ 2422 2423 /** 2424 * cxgb_up - enable the adapter 2425 * @adap: adapter being enabled 2426 * 2427 * Called when the first port is enabled, this function performs the 2428 * actions necessary to make an adapter operational, such as completing 2429 * the initialization of HW modules, and enabling interrupts. 2430 * 2431 * Must be called with the rtnl lock held. 2432 */ 2433 static int cxgb_up(struct adapter *adap) 2434 { 2435 struct sge *s = &adap->sge; 2436 int err; 2437 2438 mutex_lock(&uld_mutex); 2439 err = setup_sge_queues(adap); 2440 if (err) 2441 goto rel_lock; 2442 err = setup_rss(adap); 2443 if (err) 2444 goto freeq; 2445 2446 if (adap->flags & CXGB4_USING_MSIX) { 2447 if (s->nd_msix_idx < 0) { 2448 err = -ENOMEM; 2449 goto irq_err; 2450 } 2451 2452 err = request_irq(adap->msix_info[s->nd_msix_idx].vec, 2453 t4_nondata_intr, 0, 2454 adap->msix_info[s->nd_msix_idx].desc, adap); 2455 if (err) 2456 goto irq_err; 2457 2458 err = request_msix_queue_irqs(adap); 2459 if (err) 2460 goto irq_err_free_nd_msix; 2461 } else { 2462 err = request_irq(adap->pdev->irq, t4_intr_handler(adap), 2463 (adap->flags & CXGB4_USING_MSI) ? 0 2464 : IRQF_SHARED, 2465 adap->port[0]->name, adap); 2466 if (err) 2467 goto irq_err; 2468 } 2469 2470 enable_rx(adap); 2471 t4_sge_start(adap); 2472 t4_intr_enable(adap); 2473 adap->flags |= CXGB4_FULL_INIT_DONE; 2474 mutex_unlock(&uld_mutex); 2475 2476 notify_ulds(adap, CXGB4_STATE_UP); 2477 #if IS_ENABLED(CONFIG_IPV6) 2478 update_clip(adap); 2479 #endif 2480 return err; 2481 2482 irq_err_free_nd_msix: 2483 free_irq(adap->msix_info[s->nd_msix_idx].vec, adap); 2484 irq_err: 2485 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); 2486 freeq: 2487 t4_free_sge_resources(adap); 2488 rel_lock: 2489 mutex_unlock(&uld_mutex); 2490 return err; 2491 } 2492 2493 static void cxgb_down(struct adapter *adapter) 2494 { 2495 cancel_work_sync(&adapter->tid_release_task); 2496 cancel_work_sync(&adapter->db_full_task); 2497 cancel_work_sync(&adapter->db_drop_task); 2498 adapter->tid_release_task_busy = false; 2499 adapter->tid_release_head = NULL; 2500 2501 t4_sge_stop(adapter); 2502 t4_free_sge_resources(adapter); 2503 2504 adapter->flags &= ~CXGB4_FULL_INIT_DONE; 2505 } 2506 2507 /* 2508 * net_device operations 2509 */ 2510 int cxgb_open(struct net_device *dev) 2511 { 2512 struct port_info *pi = netdev_priv(dev); 2513 struct adapter *adapter = pi->adapter; 2514 int err; 2515 2516 netif_carrier_off(dev); 2517 2518 if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) { 2519 err = cxgb_up(adapter); 2520 if (err < 0) 2521 return err; 2522 } 2523 2524 /* It's possible that the basic port information could have 2525 * changed since we first read it. 2526 */ 2527 err = t4_update_port_info(pi); 2528 if (err < 0) 2529 return err; 2530 2531 err = link_start(dev); 2532 if (!err) 2533 netif_tx_start_all_queues(dev); 2534 return err; 2535 } 2536 2537 int cxgb_close(struct net_device *dev) 2538 { 2539 struct port_info *pi = netdev_priv(dev); 2540 struct adapter *adapter = pi->adapter; 2541 int ret; 2542 2543 netif_tx_stop_all_queues(dev); 2544 netif_carrier_off(dev); 2545 ret = t4_enable_pi_params(adapter, adapter->pf, pi, 2546 false, false, false); 2547 #ifdef CONFIG_CHELSIO_T4_DCB 2548 cxgb4_dcb_reset(dev); 2549 dcb_tx_queue_prio_enable(dev, false); 2550 #endif 2551 return ret; 2552 } 2553 2554 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 2555 __be32 sip, __be16 sport, __be16 vlan, 2556 unsigned int queue, unsigned char port, unsigned char mask) 2557 { 2558 int ret; 2559 struct filter_entry *f; 2560 struct adapter *adap; 2561 int i; 2562 u8 *val; 2563 2564 adap = netdev2adap(dev); 2565 2566 /* Adjust stid to correct filter index */ 2567 stid -= adap->tids.sftid_base; 2568 stid += adap->tids.nftids; 2569 2570 /* Check to make sure the filter requested is writable ... 2571 */ 2572 f = &adap->tids.ftid_tab[stid]; 2573 ret = writable_filter(f); 2574 if (ret) 2575 return ret; 2576 2577 /* Clear out any old resources being used by the filter before 2578 * we start constructing the new filter. 2579 */ 2580 if (f->valid) 2581 clear_filter(adap, f); 2582 2583 /* Clear out filter specifications */ 2584 memset(&f->fs, 0, sizeof(struct ch_filter_specification)); 2585 f->fs.val.lport = cpu_to_be16(sport); 2586 f->fs.mask.lport = ~0; 2587 val = (u8 *)&sip; 2588 if ((val[0] | val[1] | val[2] | val[3]) != 0) { 2589 for (i = 0; i < 4; i++) { 2590 f->fs.val.lip[i] = val[i]; 2591 f->fs.mask.lip[i] = ~0; 2592 } 2593 if (adap->params.tp.vlan_pri_map & PORT_F) { 2594 f->fs.val.iport = port; 2595 f->fs.mask.iport = mask; 2596 } 2597 } 2598 2599 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { 2600 f->fs.val.proto = IPPROTO_TCP; 2601 f->fs.mask.proto = ~0; 2602 } 2603 2604 f->fs.dirsteer = 1; 2605 f->fs.iq = queue; 2606 /* Mark filter as locked */ 2607 f->locked = 1; 2608 f->fs.rpttid = 1; 2609 2610 /* Save the actual tid. We need this to get the corresponding 2611 * filter entry structure in filter_rpl. 2612 */ 2613 f->tid = stid + adap->tids.ftid_base; 2614 ret = set_filter_wr(adap, stid); 2615 if (ret) { 2616 clear_filter(adap, f); 2617 return ret; 2618 } 2619 2620 return 0; 2621 } 2622 EXPORT_SYMBOL(cxgb4_create_server_filter); 2623 2624 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 2625 unsigned int queue, bool ipv6) 2626 { 2627 struct filter_entry *f; 2628 struct adapter *adap; 2629 2630 adap = netdev2adap(dev); 2631 2632 /* Adjust stid to correct filter index */ 2633 stid -= adap->tids.sftid_base; 2634 stid += adap->tids.nftids; 2635 2636 f = &adap->tids.ftid_tab[stid]; 2637 /* Unlock the filter */ 2638 f->locked = 0; 2639 2640 return delete_filter(adap, stid); 2641 } 2642 EXPORT_SYMBOL(cxgb4_remove_server_filter); 2643 2644 static void cxgb_get_stats(struct net_device *dev, 2645 struct rtnl_link_stats64 *ns) 2646 { 2647 struct port_stats stats; 2648 struct port_info *p = netdev_priv(dev); 2649 struct adapter *adapter = p->adapter; 2650 2651 /* Block retrieving statistics during EEH error 2652 * recovery. Otherwise, the recovery might fail 2653 * and the PCI device will be removed permanently 2654 */ 2655 spin_lock(&adapter->stats_lock); 2656 if (!netif_device_present(dev)) { 2657 spin_unlock(&adapter->stats_lock); 2658 return; 2659 } 2660 t4_get_port_stats_offset(adapter, p->tx_chan, &stats, 2661 &p->stats_base); 2662 spin_unlock(&adapter->stats_lock); 2663 2664 ns->tx_bytes = stats.tx_octets; 2665 ns->tx_packets = stats.tx_frames; 2666 ns->rx_bytes = stats.rx_octets; 2667 ns->rx_packets = stats.rx_frames; 2668 ns->multicast = stats.rx_mcast_frames; 2669 2670 /* detailed rx_errors */ 2671 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + 2672 stats.rx_runt; 2673 ns->rx_over_errors = 0; 2674 ns->rx_crc_errors = stats.rx_fcs_err; 2675 ns->rx_frame_errors = stats.rx_symbol_err; 2676 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + 2677 stats.rx_ovflow2 + stats.rx_ovflow3 + 2678 stats.rx_trunc0 + stats.rx_trunc1 + 2679 stats.rx_trunc2 + stats.rx_trunc3; 2680 ns->rx_missed_errors = 0; 2681 2682 /* detailed tx_errors */ 2683 ns->tx_aborted_errors = 0; 2684 ns->tx_carrier_errors = 0; 2685 ns->tx_fifo_errors = 0; 2686 ns->tx_heartbeat_errors = 0; 2687 ns->tx_window_errors = 0; 2688 2689 ns->tx_errors = stats.tx_error_frames; 2690 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + 2691 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; 2692 } 2693 2694 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 2695 { 2696 unsigned int mbox; 2697 int ret = 0, prtad, devad; 2698 struct port_info *pi = netdev_priv(dev); 2699 struct adapter *adapter = pi->adapter; 2700 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; 2701 2702 switch (cmd) { 2703 case SIOCGMIIPHY: 2704 if (pi->mdio_addr < 0) 2705 return -EOPNOTSUPP; 2706 data->phy_id = pi->mdio_addr; 2707 break; 2708 case SIOCGMIIREG: 2709 case SIOCSMIIREG: 2710 if (mdio_phy_id_is_c45(data->phy_id)) { 2711 prtad = mdio_phy_id_prtad(data->phy_id); 2712 devad = mdio_phy_id_devad(data->phy_id); 2713 } else if (data->phy_id < 32) { 2714 prtad = data->phy_id; 2715 devad = 0; 2716 data->reg_num &= 0x1f; 2717 } else 2718 return -EINVAL; 2719 2720 mbox = pi->adapter->pf; 2721 if (cmd == SIOCGMIIREG) 2722 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, 2723 data->reg_num, &data->val_out); 2724 else 2725 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, 2726 data->reg_num, data->val_in); 2727 break; 2728 case SIOCGHWTSTAMP: 2729 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2730 sizeof(pi->tstamp_config)) ? 2731 -EFAULT : 0; 2732 case SIOCSHWTSTAMP: 2733 if (copy_from_user(&pi->tstamp_config, req->ifr_data, 2734 sizeof(pi->tstamp_config))) 2735 return -EFAULT; 2736 2737 if (!is_t4(adapter->params.chip)) { 2738 switch (pi->tstamp_config.tx_type) { 2739 case HWTSTAMP_TX_OFF: 2740 case HWTSTAMP_TX_ON: 2741 break; 2742 default: 2743 return -ERANGE; 2744 } 2745 2746 switch (pi->tstamp_config.rx_filter) { 2747 case HWTSTAMP_FILTER_NONE: 2748 pi->rxtstamp = false; 2749 break; 2750 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2751 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2752 cxgb4_ptprx_timestamping(pi, pi->port_id, 2753 PTP_TS_L4); 2754 break; 2755 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2756 cxgb4_ptprx_timestamping(pi, pi->port_id, 2757 PTP_TS_L2_L4); 2758 break; 2759 case HWTSTAMP_FILTER_ALL: 2760 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2761 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2762 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2763 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2764 pi->rxtstamp = true; 2765 break; 2766 default: 2767 pi->tstamp_config.rx_filter = 2768 HWTSTAMP_FILTER_NONE; 2769 return -ERANGE; 2770 } 2771 2772 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) && 2773 (pi->tstamp_config.rx_filter == 2774 HWTSTAMP_FILTER_NONE)) { 2775 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0) 2776 pi->ptp_enable = false; 2777 } 2778 2779 if (pi->tstamp_config.rx_filter != 2780 HWTSTAMP_FILTER_NONE) { 2781 if (cxgb4_ptp_redirect_rx_packet(adapter, 2782 pi) >= 0) 2783 pi->ptp_enable = true; 2784 } 2785 } else { 2786 /* For T4 Adapters */ 2787 switch (pi->tstamp_config.rx_filter) { 2788 case HWTSTAMP_FILTER_NONE: 2789 pi->rxtstamp = false; 2790 break; 2791 case HWTSTAMP_FILTER_ALL: 2792 pi->rxtstamp = true; 2793 break; 2794 default: 2795 pi->tstamp_config.rx_filter = 2796 HWTSTAMP_FILTER_NONE; 2797 return -ERANGE; 2798 } 2799 } 2800 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2801 sizeof(pi->tstamp_config)) ? 2802 -EFAULT : 0; 2803 default: 2804 return -EOPNOTSUPP; 2805 } 2806 return ret; 2807 } 2808 2809 static void cxgb_set_rxmode(struct net_device *dev) 2810 { 2811 /* unfortunately we can't return errors to the stack */ 2812 set_rxmode(dev, -1, false); 2813 } 2814 2815 static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2816 { 2817 int ret; 2818 struct port_info *pi = netdev_priv(dev); 2819 2820 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, 2821 -1, -1, -1, true); 2822 if (!ret) 2823 dev->mtu = new_mtu; 2824 return ret; 2825 } 2826 2827 #ifdef CONFIG_PCI_IOV 2828 static int cxgb4_mgmt_open(struct net_device *dev) 2829 { 2830 /* Turn carrier off since we don't have to transmit anything on this 2831 * interface. 2832 */ 2833 netif_carrier_off(dev); 2834 return 0; 2835 } 2836 2837 /* Fill MAC address that will be assigned by the FW */ 2838 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap) 2839 { 2840 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; 2841 unsigned int i, vf, nvfs; 2842 u16 a, b; 2843 int err; 2844 u8 *na; 2845 2846 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev, 2847 PCI_CAP_ID_VPD); 2848 err = t4_get_raw_vpd_params(adap, &adap->params.vpd); 2849 if (err) 2850 return; 2851 2852 na = adap->params.vpd.na; 2853 for (i = 0; i < ETH_ALEN; i++) 2854 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 2855 hex2val(na[2 * i + 1])); 2856 2857 a = (hw_addr[0] << 8) | hw_addr[1]; 2858 b = (hw_addr[1] << 8) | hw_addr[2]; 2859 a ^= b; 2860 a |= 0x0200; /* locally assigned Ethernet MAC address */ 2861 a &= ~0x0100; /* not a multicast Ethernet MAC address */ 2862 macaddr[0] = a >> 8; 2863 macaddr[1] = a & 0xff; 2864 2865 for (i = 2; i < 5; i++) 2866 macaddr[i] = hw_addr[i + 1]; 2867 2868 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev); 2869 vf < nvfs; vf++) { 2870 macaddr[5] = adap->pf * nvfs + vf; 2871 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr); 2872 } 2873 } 2874 2875 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 2876 { 2877 struct port_info *pi = netdev_priv(dev); 2878 struct adapter *adap = pi->adapter; 2879 int ret; 2880 2881 /* verify MAC addr is valid */ 2882 if (!is_valid_ether_addr(mac)) { 2883 dev_err(pi->adapter->pdev_dev, 2884 "Invalid Ethernet address %pM for VF %d\n", 2885 mac, vf); 2886 return -EINVAL; 2887 } 2888 2889 dev_info(pi->adapter->pdev_dev, 2890 "Setting MAC %pM on VF %d\n", mac, vf); 2891 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); 2892 if (!ret) 2893 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); 2894 return ret; 2895 } 2896 2897 static int cxgb4_mgmt_get_vf_config(struct net_device *dev, 2898 int vf, struct ifla_vf_info *ivi) 2899 { 2900 struct port_info *pi = netdev_priv(dev); 2901 struct adapter *adap = pi->adapter; 2902 struct vf_info *vfinfo; 2903 2904 if (vf >= adap->num_vfs) 2905 return -EINVAL; 2906 vfinfo = &adap->vfinfo[vf]; 2907 2908 ivi->vf = vf; 2909 ivi->max_tx_rate = vfinfo->tx_rate; 2910 ivi->min_tx_rate = 0; 2911 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr); 2912 ivi->vlan = vfinfo->vlan; 2913 ivi->linkstate = vfinfo->link_state; 2914 return 0; 2915 } 2916 2917 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev, 2918 struct netdev_phys_item_id *ppid) 2919 { 2920 struct port_info *pi = netdev_priv(dev); 2921 unsigned int phy_port_id; 2922 2923 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; 2924 ppid->id_len = sizeof(phy_port_id); 2925 memcpy(ppid->id, &phy_port_id, ppid->id_len); 2926 return 0; 2927 } 2928 2929 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf, 2930 int min_tx_rate, int max_tx_rate) 2931 { 2932 struct port_info *pi = netdev_priv(dev); 2933 struct adapter *adap = pi->adapter; 2934 unsigned int link_ok, speed, mtu; 2935 u32 fw_pfvf, fw_class; 2936 int class_id = vf; 2937 int ret; 2938 u16 pktsize; 2939 2940 if (vf >= adap->num_vfs) 2941 return -EINVAL; 2942 2943 if (min_tx_rate) { 2944 dev_err(adap->pdev_dev, 2945 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n", 2946 min_tx_rate, vf); 2947 return -EINVAL; 2948 } 2949 2950 if (max_tx_rate == 0) { 2951 /* unbind VF to to any Traffic Class */ 2952 fw_pfvf = 2953 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 2954 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 2955 fw_class = 0xffffffff; 2956 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, 2957 &fw_pfvf, &fw_class); 2958 if (ret) { 2959 dev_err(adap->pdev_dev, 2960 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n", 2961 ret, adap->pf, vf); 2962 return -EINVAL; 2963 } 2964 dev_info(adap->pdev_dev, 2965 "PF %d VF %d is unbound from TX Rate Limiting\n", 2966 adap->pf, vf); 2967 adap->vfinfo[vf].tx_rate = 0; 2968 return 0; 2969 } 2970 2971 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu); 2972 if (ret != FW_SUCCESS) { 2973 dev_err(adap->pdev_dev, 2974 "Failed to get link information for VF %d\n", vf); 2975 return -EINVAL; 2976 } 2977 2978 if (!link_ok) { 2979 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf); 2980 return -EINVAL; 2981 } 2982 2983 if (max_tx_rate > speed) { 2984 dev_err(adap->pdev_dev, 2985 "Max tx rate %d for VF %d can't be > link-speed %u", 2986 max_tx_rate, vf, speed); 2987 return -EINVAL; 2988 } 2989 2990 pktsize = mtu; 2991 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */ 2992 pktsize = pktsize - sizeof(struct ethhdr) - 4; 2993 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */ 2994 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr); 2995 /* configure Traffic Class for rate-limiting */ 2996 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET, 2997 SCHED_CLASS_LEVEL_CL_RL, 2998 SCHED_CLASS_MODE_CLASS, 2999 SCHED_CLASS_RATEUNIT_BITS, 3000 SCHED_CLASS_RATEMODE_ABS, 3001 pi->tx_chan, class_id, 0, 3002 max_tx_rate * 1000, 0, pktsize); 3003 if (ret) { 3004 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n", 3005 ret); 3006 return -EINVAL; 3007 } 3008 dev_info(adap->pdev_dev, 3009 "Class %d with MSS %u configured with rate %u\n", 3010 class_id, pktsize, max_tx_rate); 3011 3012 /* bind VF to configured Traffic Class */ 3013 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 3014 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 3015 fw_class = class_id; 3016 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf, 3017 &fw_class); 3018 if (ret) { 3019 dev_err(adap->pdev_dev, 3020 "Err %d in binding PF %d VF %d to Traffic Class %d\n", 3021 ret, adap->pf, vf, class_id); 3022 return -EINVAL; 3023 } 3024 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n", 3025 adap->pf, vf, class_id); 3026 adap->vfinfo[vf].tx_rate = max_tx_rate; 3027 return 0; 3028 } 3029 3030 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf, 3031 u16 vlan, u8 qos, __be16 vlan_proto) 3032 { 3033 struct port_info *pi = netdev_priv(dev); 3034 struct adapter *adap = pi->adapter; 3035 int ret; 3036 3037 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7) 3038 return -EINVAL; 3039 3040 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0) 3041 return -EPROTONOSUPPORT; 3042 3043 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan); 3044 if (!ret) { 3045 adap->vfinfo[vf].vlan = vlan; 3046 return 0; 3047 } 3048 3049 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n", 3050 ret, (vlan ? "setting" : "clearing"), adap->pf, vf); 3051 return ret; 3052 } 3053 3054 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf, 3055 int link) 3056 { 3057 struct port_info *pi = netdev_priv(dev); 3058 struct adapter *adap = pi->adapter; 3059 u32 param, val; 3060 int ret = 0; 3061 3062 if (vf >= adap->num_vfs) 3063 return -EINVAL; 3064 3065 switch (link) { 3066 case IFLA_VF_LINK_STATE_AUTO: 3067 val = FW_VF_LINK_STATE_AUTO; 3068 break; 3069 3070 case IFLA_VF_LINK_STATE_ENABLE: 3071 val = FW_VF_LINK_STATE_ENABLE; 3072 break; 3073 3074 case IFLA_VF_LINK_STATE_DISABLE: 3075 val = FW_VF_LINK_STATE_DISABLE; 3076 break; 3077 3078 default: 3079 return -EINVAL; 3080 } 3081 3082 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 3083 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE)); 3084 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, 3085 ¶m, &val); 3086 if (ret) { 3087 dev_err(adap->pdev_dev, 3088 "Error %d in setting PF %d VF %d link state\n", 3089 ret, adap->pf, vf); 3090 return -EINVAL; 3091 } 3092 3093 adap->vfinfo[vf].link_state = link; 3094 return ret; 3095 } 3096 #endif /* CONFIG_PCI_IOV */ 3097 3098 static int cxgb_set_mac_addr(struct net_device *dev, void *p) 3099 { 3100 int ret; 3101 struct sockaddr *addr = p; 3102 struct port_info *pi = netdev_priv(dev); 3103 3104 if (!is_valid_ether_addr(addr->sa_data)) 3105 return -EADDRNOTAVAIL; 3106 3107 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt, 3108 addr->sa_data, true, &pi->smt_idx); 3109 if (ret < 0) 3110 return ret; 3111 3112 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3113 pi->xact_addr_filt = ret; 3114 return 0; 3115 } 3116 3117 #ifdef CONFIG_NET_POLL_CONTROLLER 3118 static void cxgb_netpoll(struct net_device *dev) 3119 { 3120 struct port_info *pi = netdev_priv(dev); 3121 struct adapter *adap = pi->adapter; 3122 3123 if (adap->flags & CXGB4_USING_MSIX) { 3124 int i; 3125 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; 3126 3127 for (i = pi->nqsets; i; i--, rx++) 3128 t4_sge_intr_msix(0, &rx->rspq); 3129 } else 3130 t4_intr_handler(adap)(0, adap); 3131 } 3132 #endif 3133 3134 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 3135 { 3136 struct port_info *pi = netdev_priv(dev); 3137 struct adapter *adap = pi->adapter; 3138 struct sched_class *e; 3139 struct ch_sched_params p; 3140 struct ch_sched_queue qe; 3141 u32 req_rate; 3142 int err = 0; 3143 3144 if (!can_sched(dev)) 3145 return -ENOTSUPP; 3146 3147 if (index < 0 || index > pi->nqsets - 1) 3148 return -EINVAL; 3149 3150 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) { 3151 dev_err(adap->pdev_dev, 3152 "Failed to rate limit on queue %d. Link Down?\n", 3153 index); 3154 return -EINVAL; 3155 } 3156 3157 /* Convert from Mbps to Kbps */ 3158 req_rate = rate * 1000; 3159 3160 /* Max rate is 100 Gbps */ 3161 if (req_rate > SCHED_MAX_RATE_KBPS) { 3162 dev_err(adap->pdev_dev, 3163 "Invalid rate %u Mbps, Max rate is %u Mbps\n", 3164 rate, SCHED_MAX_RATE_KBPS / 1000); 3165 return -ERANGE; 3166 } 3167 3168 /* First unbind the queue from any existing class */ 3169 memset(&qe, 0, sizeof(qe)); 3170 qe.queue = index; 3171 qe.class = SCHED_CLS_NONE; 3172 3173 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); 3174 if (err) { 3175 dev_err(adap->pdev_dev, 3176 "Unbinding Queue %d on port %d fail. Err: %d\n", 3177 index, pi->port_id, err); 3178 return err; 3179 } 3180 3181 /* Queue already unbound */ 3182 if (!req_rate) 3183 return 0; 3184 3185 /* Fetch any available unused or matching scheduling class */ 3186 memset(&p, 0, sizeof(p)); 3187 p.type = SCHED_CLASS_TYPE_PACKET; 3188 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; 3189 p.u.params.mode = SCHED_CLASS_MODE_CLASS; 3190 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; 3191 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; 3192 p.u.params.channel = pi->tx_chan; 3193 p.u.params.class = SCHED_CLS_NONE; 3194 p.u.params.minrate = 0; 3195 p.u.params.maxrate = req_rate; 3196 p.u.params.weight = 0; 3197 p.u.params.pktsize = dev->mtu; 3198 3199 e = cxgb4_sched_class_alloc(dev, &p); 3200 if (!e) 3201 return -ENOMEM; 3202 3203 /* Bind the queue to a scheduling class */ 3204 memset(&qe, 0, sizeof(qe)); 3205 qe.queue = index; 3206 qe.class = e->idx; 3207 3208 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); 3209 if (err) 3210 dev_err(adap->pdev_dev, 3211 "Queue rate limiting failed. Err: %d\n", err); 3212 return err; 3213 } 3214 3215 static int cxgb_setup_tc_flower(struct net_device *dev, 3216 struct flow_cls_offload *cls_flower) 3217 { 3218 switch (cls_flower->command) { 3219 case FLOW_CLS_REPLACE: 3220 return cxgb4_tc_flower_replace(dev, cls_flower); 3221 case FLOW_CLS_DESTROY: 3222 return cxgb4_tc_flower_destroy(dev, cls_flower); 3223 case FLOW_CLS_STATS: 3224 return cxgb4_tc_flower_stats(dev, cls_flower); 3225 default: 3226 return -EOPNOTSUPP; 3227 } 3228 } 3229 3230 static int cxgb_setup_tc_cls_u32(struct net_device *dev, 3231 struct tc_cls_u32_offload *cls_u32) 3232 { 3233 switch (cls_u32->command) { 3234 case TC_CLSU32_NEW_KNODE: 3235 case TC_CLSU32_REPLACE_KNODE: 3236 return cxgb4_config_knode(dev, cls_u32); 3237 case TC_CLSU32_DELETE_KNODE: 3238 return cxgb4_delete_knode(dev, cls_u32); 3239 default: 3240 return -EOPNOTSUPP; 3241 } 3242 } 3243 3244 static int cxgb_setup_tc_matchall(struct net_device *dev, 3245 struct tc_cls_matchall_offload *cls_matchall, 3246 bool ingress) 3247 { 3248 struct adapter *adap = netdev2adap(dev); 3249 3250 if (!adap->tc_matchall) 3251 return -ENOMEM; 3252 3253 switch (cls_matchall->command) { 3254 case TC_CLSMATCHALL_REPLACE: 3255 return cxgb4_tc_matchall_replace(dev, cls_matchall, ingress); 3256 case TC_CLSMATCHALL_DESTROY: 3257 return cxgb4_tc_matchall_destroy(dev, cls_matchall, ingress); 3258 case TC_CLSMATCHALL_STATS: 3259 if (ingress) 3260 return cxgb4_tc_matchall_stats(dev, cls_matchall); 3261 break; 3262 default: 3263 break; 3264 } 3265 3266 return -EOPNOTSUPP; 3267 } 3268 3269 static int cxgb_setup_tc_block_ingress_cb(enum tc_setup_type type, 3270 void *type_data, void *cb_priv) 3271 { 3272 struct net_device *dev = cb_priv; 3273 struct port_info *pi = netdev2pinfo(dev); 3274 struct adapter *adap = netdev2adap(dev); 3275 3276 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) { 3277 dev_err(adap->pdev_dev, 3278 "Failed to setup tc on port %d. Link Down?\n", 3279 pi->port_id); 3280 return -EINVAL; 3281 } 3282 3283 if (!tc_cls_can_offload_and_chain0(dev, type_data)) 3284 return -EOPNOTSUPP; 3285 3286 switch (type) { 3287 case TC_SETUP_CLSU32: 3288 return cxgb_setup_tc_cls_u32(dev, type_data); 3289 case TC_SETUP_CLSFLOWER: 3290 return cxgb_setup_tc_flower(dev, type_data); 3291 case TC_SETUP_CLSMATCHALL: 3292 return cxgb_setup_tc_matchall(dev, type_data, true); 3293 default: 3294 return -EOPNOTSUPP; 3295 } 3296 } 3297 3298 static int cxgb_setup_tc_block_egress_cb(enum tc_setup_type type, 3299 void *type_data, void *cb_priv) 3300 { 3301 struct net_device *dev = cb_priv; 3302 struct port_info *pi = netdev2pinfo(dev); 3303 struct adapter *adap = netdev2adap(dev); 3304 3305 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) { 3306 dev_err(adap->pdev_dev, 3307 "Failed to setup tc on port %d. Link Down?\n", 3308 pi->port_id); 3309 return -EINVAL; 3310 } 3311 3312 if (!tc_cls_can_offload_and_chain0(dev, type_data)) 3313 return -EOPNOTSUPP; 3314 3315 switch (type) { 3316 case TC_SETUP_CLSMATCHALL: 3317 return cxgb_setup_tc_matchall(dev, type_data, false); 3318 default: 3319 break; 3320 } 3321 3322 return -EOPNOTSUPP; 3323 } 3324 3325 static int cxgb_setup_tc_mqprio(struct net_device *dev, 3326 struct tc_mqprio_qopt_offload *mqprio) 3327 { 3328 struct adapter *adap = netdev2adap(dev); 3329 3330 if (!is_ethofld(adap) || !adap->tc_mqprio) 3331 return -ENOMEM; 3332 3333 return cxgb4_setup_tc_mqprio(dev, mqprio); 3334 } 3335 3336 static LIST_HEAD(cxgb_block_cb_list); 3337 3338 static int cxgb_setup_tc_block(struct net_device *dev, 3339 struct flow_block_offload *f) 3340 { 3341 struct port_info *pi = netdev_priv(dev); 3342 flow_setup_cb_t *cb; 3343 bool ingress_only; 3344 3345 pi->tc_block_shared = f->block_shared; 3346 if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 3347 cb = cxgb_setup_tc_block_egress_cb; 3348 ingress_only = false; 3349 } else { 3350 cb = cxgb_setup_tc_block_ingress_cb; 3351 ingress_only = true; 3352 } 3353 3354 return flow_block_cb_setup_simple(f, &cxgb_block_cb_list, 3355 cb, pi, dev, ingress_only); 3356 } 3357 3358 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type, 3359 void *type_data) 3360 { 3361 switch (type) { 3362 case TC_SETUP_QDISC_MQPRIO: 3363 return cxgb_setup_tc_mqprio(dev, type_data); 3364 case TC_SETUP_BLOCK: 3365 return cxgb_setup_tc_block(dev, type_data); 3366 default: 3367 return -EOPNOTSUPP; 3368 } 3369 } 3370 3371 static void cxgb_del_udp_tunnel(struct net_device *netdev, 3372 struct udp_tunnel_info *ti) 3373 { 3374 struct port_info *pi = netdev_priv(netdev); 3375 struct adapter *adapter = pi->adapter; 3376 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); 3377 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; 3378 int ret = 0, i; 3379 3380 if (chip_ver < CHELSIO_T6) 3381 return; 3382 3383 switch (ti->type) { 3384 case UDP_TUNNEL_TYPE_VXLAN: 3385 if (!adapter->vxlan_port_cnt || 3386 adapter->vxlan_port != ti->port) 3387 return; /* Invalid VxLAN destination port */ 3388 3389 adapter->vxlan_port_cnt--; 3390 if (adapter->vxlan_port_cnt) 3391 return; 3392 3393 adapter->vxlan_port = 0; 3394 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0); 3395 break; 3396 case UDP_TUNNEL_TYPE_GENEVE: 3397 if (!adapter->geneve_port_cnt || 3398 adapter->geneve_port != ti->port) 3399 return; /* Invalid GENEVE destination port */ 3400 3401 adapter->geneve_port_cnt--; 3402 if (adapter->geneve_port_cnt) 3403 return; 3404 3405 adapter->geneve_port = 0; 3406 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0); 3407 break; 3408 default: 3409 return; 3410 } 3411 3412 /* Matchall mac entries can be deleted only after all tunnel ports 3413 * are brought down or removed. 3414 */ 3415 if (!adapter->rawf_cnt) 3416 return; 3417 for_each_port(adapter, i) { 3418 pi = adap2pinfo(adapter, i); 3419 ret = t4_free_raw_mac_filt(adapter, pi->viid, 3420 match_all_mac, match_all_mac, 3421 adapter->rawf_start + 3422 pi->port_id, 3423 1, pi->port_id, false); 3424 if (ret < 0) { 3425 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n", 3426 i); 3427 return; 3428 } 3429 } 3430 } 3431 3432 static void cxgb_add_udp_tunnel(struct net_device *netdev, 3433 struct udp_tunnel_info *ti) 3434 { 3435 struct port_info *pi = netdev_priv(netdev); 3436 struct adapter *adapter = pi->adapter; 3437 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); 3438 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; 3439 int i, ret; 3440 3441 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt) 3442 return; 3443 3444 switch (ti->type) { 3445 case UDP_TUNNEL_TYPE_VXLAN: 3446 /* Callback for adding vxlan port can be called with the same 3447 * port for both IPv4 and IPv6. We should not disable the 3448 * offloading when the same port for both protocols is added 3449 * and later one of them is removed. 3450 */ 3451 if (adapter->vxlan_port_cnt && 3452 adapter->vxlan_port == ti->port) { 3453 adapter->vxlan_port_cnt++; 3454 return; 3455 } 3456 3457 /* We will support only one VxLAN port */ 3458 if (adapter->vxlan_port_cnt) { 3459 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n", 3460 be16_to_cpu(adapter->vxlan_port), 3461 be16_to_cpu(ti->port)); 3462 return; 3463 } 3464 3465 adapter->vxlan_port = ti->port; 3466 adapter->vxlan_port_cnt = 1; 3467 3468 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 3469 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F); 3470 break; 3471 case UDP_TUNNEL_TYPE_GENEVE: 3472 if (adapter->geneve_port_cnt && 3473 adapter->geneve_port == ti->port) { 3474 adapter->geneve_port_cnt++; 3475 return; 3476 } 3477 3478 /* We will support only one GENEVE port */ 3479 if (adapter->geneve_port_cnt) { 3480 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n", 3481 be16_to_cpu(adapter->geneve_port), 3482 be16_to_cpu(ti->port)); 3483 return; 3484 } 3485 3486 adapter->geneve_port = ti->port; 3487 adapter->geneve_port_cnt = 1; 3488 3489 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 3490 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F); 3491 break; 3492 default: 3493 return; 3494 } 3495 3496 /* Create a 'match all' mac filter entry for inner mac, 3497 * if raw mac interface is supported. Once the linux kernel provides 3498 * driver entry points for adding/deleting the inner mac addresses, 3499 * we will remove this 'match all' entry and fallback to adding 3500 * exact match filters. 3501 */ 3502 for_each_port(adapter, i) { 3503 pi = adap2pinfo(adapter, i); 3504 3505 ret = t4_alloc_raw_mac_filt(adapter, pi->viid, 3506 match_all_mac, 3507 match_all_mac, 3508 adapter->rawf_start + 3509 pi->port_id, 3510 1, pi->port_id, false); 3511 if (ret < 0) { 3512 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n", 3513 be16_to_cpu(ti->port)); 3514 cxgb_del_udp_tunnel(netdev, ti); 3515 return; 3516 } 3517 } 3518 } 3519 3520 static netdev_features_t cxgb_features_check(struct sk_buff *skb, 3521 struct net_device *dev, 3522 netdev_features_t features) 3523 { 3524 struct port_info *pi = netdev_priv(dev); 3525 struct adapter *adapter = pi->adapter; 3526 3527 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) 3528 return features; 3529 3530 /* Check if hw supports offload for this packet */ 3531 if (!skb->encapsulation || cxgb_encap_offload_supported(skb)) 3532 return features; 3533 3534 /* Offload is not supported for this encapsulated packet */ 3535 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 3536 } 3537 3538 static netdev_features_t cxgb_fix_features(struct net_device *dev, 3539 netdev_features_t features) 3540 { 3541 /* Disable GRO, if RX_CSUM is disabled */ 3542 if (!(features & NETIF_F_RXCSUM)) 3543 features &= ~NETIF_F_GRO; 3544 3545 return features; 3546 } 3547 3548 static const struct net_device_ops cxgb4_netdev_ops = { 3549 .ndo_open = cxgb_open, 3550 .ndo_stop = cxgb_close, 3551 .ndo_start_xmit = t4_start_xmit, 3552 .ndo_select_queue = cxgb_select_queue, 3553 .ndo_get_stats64 = cxgb_get_stats, 3554 .ndo_set_rx_mode = cxgb_set_rxmode, 3555 .ndo_set_mac_address = cxgb_set_mac_addr, 3556 .ndo_set_features = cxgb_set_features, 3557 .ndo_validate_addr = eth_validate_addr, 3558 .ndo_do_ioctl = cxgb_ioctl, 3559 .ndo_change_mtu = cxgb_change_mtu, 3560 #ifdef CONFIG_NET_POLL_CONTROLLER 3561 .ndo_poll_controller = cxgb_netpoll, 3562 #endif 3563 #ifdef CONFIG_CHELSIO_T4_FCOE 3564 .ndo_fcoe_enable = cxgb_fcoe_enable, 3565 .ndo_fcoe_disable = cxgb_fcoe_disable, 3566 #endif /* CONFIG_CHELSIO_T4_FCOE */ 3567 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, 3568 .ndo_setup_tc = cxgb_setup_tc, 3569 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel, 3570 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel, 3571 .ndo_features_check = cxgb_features_check, 3572 .ndo_fix_features = cxgb_fix_features, 3573 }; 3574 3575 #ifdef CONFIG_PCI_IOV 3576 static const struct net_device_ops cxgb4_mgmt_netdev_ops = { 3577 .ndo_open = cxgb4_mgmt_open, 3578 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac, 3579 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config, 3580 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate, 3581 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id, 3582 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan, 3583 .ndo_set_vf_link_state = cxgb4_mgmt_set_vf_link_state, 3584 }; 3585 #endif 3586 3587 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev, 3588 struct ethtool_drvinfo *info) 3589 { 3590 struct adapter *adapter = netdev2adap(dev); 3591 3592 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); 3593 strlcpy(info->version, cxgb4_driver_version, 3594 sizeof(info->version)); 3595 strlcpy(info->bus_info, pci_name(adapter->pdev), 3596 sizeof(info->bus_info)); 3597 } 3598 3599 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { 3600 .get_drvinfo = cxgb4_mgmt_get_drvinfo, 3601 }; 3602 3603 static void notify_fatal_err(struct work_struct *work) 3604 { 3605 struct adapter *adap; 3606 3607 adap = container_of(work, struct adapter, fatal_err_notify_task); 3608 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR); 3609 } 3610 3611 void t4_fatal_err(struct adapter *adap) 3612 { 3613 int port; 3614 3615 if (pci_channel_offline(adap->pdev)) 3616 return; 3617 3618 /* Disable the SGE since ULDs are going to free resources that 3619 * could be exposed to the adapter. RDMA MWs for example... 3620 */ 3621 t4_shutdown_adapter(adap); 3622 for_each_port(adap, port) { 3623 struct net_device *dev = adap->port[port]; 3624 3625 /* If we get here in very early initialization the network 3626 * devices may not have been set up yet. 3627 */ 3628 if (!dev) 3629 continue; 3630 3631 netif_tx_stop_all_queues(dev); 3632 netif_carrier_off(dev); 3633 } 3634 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); 3635 queue_work(adap->workq, &adap->fatal_err_notify_task); 3636 } 3637 3638 static void setup_memwin(struct adapter *adap) 3639 { 3640 u32 nic_win_base = t4_get_util_window(adap); 3641 3642 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); 3643 } 3644 3645 static void setup_memwin_rdma(struct adapter *adap) 3646 { 3647 if (adap->vres.ocq.size) { 3648 u32 start; 3649 unsigned int sz_kb; 3650 3651 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); 3652 start &= PCI_BASE_ADDRESS_MEM_MASK; 3653 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 3654 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 3655 t4_write_reg(adap, 3656 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), 3657 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); 3658 t4_write_reg(adap, 3659 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), 3660 adap->vres.ocq.start); 3661 t4_read_reg(adap, 3662 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); 3663 } 3664 } 3665 3666 /* HMA Definitions */ 3667 3668 /* The maximum number of address that can be send in a single FW cmd */ 3669 #define HMA_MAX_ADDR_IN_CMD 5 3670 3671 #define HMA_PAGE_SIZE PAGE_SIZE 3672 3673 #define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */ 3674 3675 #define HMA_PAGE_ORDER \ 3676 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \ 3677 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0) 3678 3679 /* The minimum and maximum possible HMA sizes that can be specified in the FW 3680 * configuration(in units of MB). 3681 */ 3682 #define HMA_MIN_TOTAL_SIZE 1 3683 #define HMA_MAX_TOTAL_SIZE \ 3684 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \ 3685 HMA_MAX_NO_FW_ADDRESS) >> 20) 3686 3687 static void adap_free_hma_mem(struct adapter *adapter) 3688 { 3689 struct scatterlist *iter; 3690 struct page *page; 3691 int i; 3692 3693 if (!adapter->hma.sgt) 3694 return; 3695 3696 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) { 3697 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl, 3698 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL); 3699 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG; 3700 } 3701 3702 for_each_sg(adapter->hma.sgt->sgl, iter, 3703 adapter->hma.sgt->orig_nents, i) { 3704 page = sg_page(iter); 3705 if (page) 3706 __free_pages(page, HMA_PAGE_ORDER); 3707 } 3708 3709 kfree(adapter->hma.phy_addr); 3710 sg_free_table(adapter->hma.sgt); 3711 kfree(adapter->hma.sgt); 3712 adapter->hma.sgt = NULL; 3713 } 3714 3715 static int adap_config_hma(struct adapter *adapter) 3716 { 3717 struct scatterlist *sgl, *iter; 3718 struct sg_table *sgt; 3719 struct page *newpage; 3720 unsigned int i, j, k; 3721 u32 param, hma_size; 3722 unsigned int ncmds; 3723 size_t page_size; 3724 u32 page_order; 3725 int node, ret; 3726 3727 /* HMA is supported only for T6+ cards. 3728 * Avoid initializing HMA in kdump kernels. 3729 */ 3730 if (is_kdump_kernel() || 3731 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) 3732 return 0; 3733 3734 /* Get the HMA region size required by fw */ 3735 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3736 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE)); 3737 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3738 1, ¶m, &hma_size); 3739 /* An error means card has its own memory or HMA is not supported by 3740 * the firmware. Return without any errors. 3741 */ 3742 if (ret || !hma_size) 3743 return 0; 3744 3745 if (hma_size < HMA_MIN_TOTAL_SIZE || 3746 hma_size > HMA_MAX_TOTAL_SIZE) { 3747 dev_err(adapter->pdev_dev, 3748 "HMA size %uMB beyond bounds(%u-%lu)MB\n", 3749 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE); 3750 return -EINVAL; 3751 } 3752 3753 page_size = HMA_PAGE_SIZE; 3754 page_order = HMA_PAGE_ORDER; 3755 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL); 3756 if (unlikely(!adapter->hma.sgt)) { 3757 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n"); 3758 return -ENOMEM; 3759 } 3760 sgt = adapter->hma.sgt; 3761 /* FW returned value will be in MB's 3762 */ 3763 sgt->orig_nents = (hma_size << 20) / (page_size << page_order); 3764 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) { 3765 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n"); 3766 kfree(adapter->hma.sgt); 3767 adapter->hma.sgt = NULL; 3768 return -ENOMEM; 3769 } 3770 3771 sgl = adapter->hma.sgt->sgl; 3772 node = dev_to_node(adapter->pdev_dev); 3773 for_each_sg(sgl, iter, sgt->orig_nents, i) { 3774 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL | 3775 __GFP_ZERO, page_order); 3776 if (!newpage) { 3777 dev_err(adapter->pdev_dev, 3778 "Not enough memory for HMA page allocation\n"); 3779 ret = -ENOMEM; 3780 goto free_hma; 3781 } 3782 sg_set_page(iter, newpage, page_size << page_order, 0); 3783 } 3784 3785 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents, 3786 DMA_BIDIRECTIONAL); 3787 if (!sgt->nents) { 3788 dev_err(adapter->pdev_dev, 3789 "Not enough memory for HMA DMA mapping"); 3790 ret = -ENOMEM; 3791 goto free_hma; 3792 } 3793 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG; 3794 3795 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t), 3796 GFP_KERNEL); 3797 if (unlikely(!adapter->hma.phy_addr)) 3798 goto free_hma; 3799 3800 for_each_sg(sgl, iter, sgt->nents, i) { 3801 newpage = sg_page(iter); 3802 adapter->hma.phy_addr[i] = sg_dma_address(iter); 3803 } 3804 3805 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD); 3806 /* Pass on the addresses to firmware */ 3807 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) { 3808 struct fw_hma_cmd hma_cmd; 3809 u8 naddr = HMA_MAX_ADDR_IN_CMD; 3810 u8 soc = 0, eoc = 0; 3811 u8 hma_mode = 1; /* Presently we support only Page table mode */ 3812 3813 soc = (i == 0) ? 1 : 0; 3814 eoc = (i == ncmds - 1) ? 1 : 0; 3815 3816 /* For last cmd, set naddr corresponding to remaining 3817 * addresses 3818 */ 3819 if (i == ncmds - 1) { 3820 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD; 3821 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD; 3822 } 3823 memset(&hma_cmd, 0, sizeof(hma_cmd)); 3824 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) | 3825 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3826 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd)); 3827 3828 hma_cmd.mode_to_pcie_params = 3829 htonl(FW_HMA_CMD_MODE_V(hma_mode) | 3830 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc)); 3831 3832 /* HMA cmd size specified in MB's */ 3833 hma_cmd.naddr_size = 3834 htonl(FW_HMA_CMD_SIZE_V(hma_size) | 3835 FW_HMA_CMD_NADDR_V(naddr)); 3836 3837 /* Total Page size specified in units of 4K */ 3838 hma_cmd.addr_size_pkd = 3839 htonl(FW_HMA_CMD_ADDR_SIZE_V 3840 ((page_size << page_order) >> 12)); 3841 3842 /* Fill the 5 addresses */ 3843 for (j = 0; j < naddr; j++) { 3844 hma_cmd.phy_address[j] = 3845 cpu_to_be64(adapter->hma.phy_addr[j + k]); 3846 } 3847 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd, 3848 sizeof(hma_cmd), &hma_cmd); 3849 if (ret) { 3850 dev_err(adapter->pdev_dev, 3851 "HMA FW command failed with err %d\n", ret); 3852 goto free_hma; 3853 } 3854 } 3855 3856 if (!ret) 3857 dev_info(adapter->pdev_dev, 3858 "Reserved %uMB host memory for HMA\n", hma_size); 3859 return ret; 3860 3861 free_hma: 3862 adap_free_hma_mem(adapter); 3863 return ret; 3864 } 3865 3866 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 3867 { 3868 u32 v; 3869 int ret; 3870 3871 /* Now that we've successfully configured and initialized the adapter 3872 * can ask the Firmware what resources it has provisioned for us. 3873 */ 3874 ret = t4_get_pfres(adap); 3875 if (ret) { 3876 dev_err(adap->pdev_dev, 3877 "Unable to retrieve resource provisioning information\n"); 3878 return ret; 3879 } 3880 3881 /* get device capabilities */ 3882 memset(c, 0, sizeof(*c)); 3883 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3884 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3885 c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); 3886 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); 3887 if (ret < 0) 3888 return ret; 3889 3890 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3891 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3892 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); 3893 if (ret < 0) 3894 return ret; 3895 3896 ret = t4_config_glbl_rss(adap, adap->pf, 3897 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 3898 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | 3899 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); 3900 if (ret < 0) 3901 return ret; 3902 3903 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, 3904 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, 3905 FW_CMD_CAP_PF); 3906 if (ret < 0) 3907 return ret; 3908 3909 t4_sge_init(adap); 3910 3911 /* tweak some settings */ 3912 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 3913 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); 3914 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 3915 v = t4_read_reg(adap, TP_PIO_DATA_A); 3916 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 3917 3918 /* first 4 Tx modulation queues point to consecutive Tx channels */ 3919 adap->params.tp.tx_modq_map = 0xE4; 3920 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, 3921 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); 3922 3923 /* associate each Tx modulation queue with consecutive Tx channels */ 3924 v = 0x84218421; 3925 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3926 &v, 1, TP_TX_SCHED_HDR_A); 3927 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3928 &v, 1, TP_TX_SCHED_FIFO_A); 3929 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3930 &v, 1, TP_TX_SCHED_PCMD_A); 3931 3932 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 3933 if (is_offload(adap)) { 3934 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, 3935 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3936 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3937 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3938 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3939 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, 3940 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3941 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3942 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3943 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3944 } 3945 3946 /* get basic stuff going */ 3947 return t4_early_init(adap, adap->pf); 3948 } 3949 3950 /* 3951 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 3952 */ 3953 #define MAX_ATIDS 8192U 3954 3955 /* 3956 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3957 * 3958 * If the firmware we're dealing with has Configuration File support, then 3959 * we use that to perform all configuration 3960 */ 3961 3962 /* 3963 * Tweak configuration based on module parameters, etc. Most of these have 3964 * defaults assigned to them by Firmware Configuration Files (if we're using 3965 * them) but need to be explicitly set if we're using hard-coded 3966 * initialization. But even in the case of using Firmware Configuration 3967 * Files, we'd like to expose the ability to change these via module 3968 * parameters so these are essentially common tweaks/settings for 3969 * Configuration Files and hard-coded initialization ... 3970 */ 3971 static int adap_init0_tweaks(struct adapter *adapter) 3972 { 3973 /* 3974 * Fix up various Host-Dependent Parameters like Page Size, Cache 3975 * Line Size, etc. The firmware default is for a 4KB Page Size and 3976 * 64B Cache Line Size ... 3977 */ 3978 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); 3979 3980 /* 3981 * Process module parameters which affect early initialization. 3982 */ 3983 if (rx_dma_offset != 2 && rx_dma_offset != 0) { 3984 dev_err(&adapter->pdev->dev, 3985 "Ignoring illegal rx_dma_offset=%d, using 2\n", 3986 rx_dma_offset); 3987 rx_dma_offset = 2; 3988 } 3989 t4_set_reg_field(adapter, SGE_CONTROL_A, 3990 PKTSHIFT_V(PKTSHIFT_M), 3991 PKTSHIFT_V(rx_dma_offset)); 3992 3993 /* 3994 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 3995 * adds the pseudo header itself. 3996 */ 3997 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, 3998 CSUM_HAS_PSEUDO_HDR_F, 0); 3999 4000 return 0; 4001 } 4002 4003 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips 4004 * unto themselves and they contain their own firmware to perform their 4005 * tasks ... 4006 */ 4007 static int phy_aq1202_version(const u8 *phy_fw_data, 4008 size_t phy_fw_size) 4009 { 4010 int offset; 4011 4012 /* At offset 0x8 you're looking for the primary image's 4013 * starting offset which is 3 Bytes wide 4014 * 4015 * At offset 0xa of the primary image, you look for the offset 4016 * of the DRAM segment which is 3 Bytes wide. 4017 * 4018 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes 4019 * wide 4020 */ 4021 #define be16(__p) (((__p)[0] << 8) | (__p)[1]) 4022 #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) 4023 #define le24(__p) (le16(__p) | ((__p)[2] << 16)) 4024 4025 offset = le24(phy_fw_data + 0x8) << 12; 4026 offset = le24(phy_fw_data + offset + 0xa); 4027 return be16(phy_fw_data + offset + 0x27e); 4028 4029 #undef be16 4030 #undef le16 4031 #undef le24 4032 } 4033 4034 static struct info_10gbt_phy_fw { 4035 unsigned int phy_fw_id; /* PCI Device ID */ 4036 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ 4037 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); 4038 int phy_flash; /* Has FLASH for PHY Firmware */ 4039 } phy_info_array[] = { 4040 { 4041 PHY_AQ1202_DEVICEID, 4042 PHY_AQ1202_FIRMWARE, 4043 phy_aq1202_version, 4044 1, 4045 }, 4046 { 4047 PHY_BCM84834_DEVICEID, 4048 PHY_BCM84834_FIRMWARE, 4049 NULL, 4050 0, 4051 }, 4052 { 0, NULL, NULL }, 4053 }; 4054 4055 static struct info_10gbt_phy_fw *find_phy_info(int devid) 4056 { 4057 int i; 4058 4059 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { 4060 if (phy_info_array[i].phy_fw_id == devid) 4061 return &phy_info_array[i]; 4062 } 4063 return NULL; 4064 } 4065 4066 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to 4067 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error 4068 * we return a negative error number. If we transfer new firmware we return 1 4069 * (from t4_load_phy_fw()). If we don't do anything we return 0. 4070 */ 4071 static int adap_init0_phy(struct adapter *adap) 4072 { 4073 const struct firmware *phyf; 4074 int ret; 4075 struct info_10gbt_phy_fw *phy_info; 4076 4077 /* Use the device ID to determine which PHY file to flash. 4078 */ 4079 phy_info = find_phy_info(adap->pdev->device); 4080 if (!phy_info) { 4081 dev_warn(adap->pdev_dev, 4082 "No PHY Firmware file found for this PHY\n"); 4083 return -EOPNOTSUPP; 4084 } 4085 4086 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then 4087 * use that. The adapter firmware provides us with a memory buffer 4088 * where we can load a PHY firmware file from the host if we want to 4089 * override the PHY firmware File in flash. 4090 */ 4091 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, 4092 adap->pdev_dev); 4093 if (ret < 0) { 4094 /* For adapters without FLASH attached to PHY for their 4095 * firmware, it's obviously a fatal error if we can't get the 4096 * firmware to the adapter. For adapters with PHY firmware 4097 * FLASH storage, it's worth a warning if we can't find the 4098 * PHY Firmware but we'll neuter the error ... 4099 */ 4100 dev_err(adap->pdev_dev, "unable to find PHY Firmware image " 4101 "/lib/firmware/%s, error %d\n", 4102 phy_info->phy_fw_file, -ret); 4103 if (phy_info->phy_flash) { 4104 int cur_phy_fw_ver = 0; 4105 4106 t4_phy_fw_ver(adap, &cur_phy_fw_ver); 4107 dev_warn(adap->pdev_dev, "continuing with, on-adapter " 4108 "FLASH copy, version %#x\n", cur_phy_fw_ver); 4109 ret = 0; 4110 } 4111 4112 return ret; 4113 } 4114 4115 /* Load PHY Firmware onto adapter. 4116 */ 4117 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, 4118 phy_info->phy_fw_version, 4119 (u8 *)phyf->data, phyf->size); 4120 if (ret < 0) 4121 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", 4122 -ret); 4123 else if (ret > 0) { 4124 int new_phy_fw_ver = 0; 4125 4126 if (phy_info->phy_fw_version) 4127 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, 4128 phyf->size); 4129 dev_info(adap->pdev_dev, "Successfully transferred PHY " 4130 "Firmware /lib/firmware/%s, version %#x\n", 4131 phy_info->phy_fw_file, new_phy_fw_ver); 4132 } 4133 4134 release_firmware(phyf); 4135 4136 return ret; 4137 } 4138 4139 /* 4140 * Attempt to initialize the adapter via a Firmware Configuration File. 4141 */ 4142 static int adap_init0_config(struct adapter *adapter, int reset) 4143 { 4144 char *fw_config_file, fw_config_file_path[256]; 4145 u32 finiver, finicsum, cfcsum, param, val; 4146 struct fw_caps_config_cmd caps_cmd; 4147 unsigned long mtype = 0, maddr = 0; 4148 const struct firmware *cf; 4149 char *config_name = NULL; 4150 int config_issued = 0; 4151 int ret; 4152 4153 /* 4154 * Reset device if necessary. 4155 */ 4156 if (reset) { 4157 ret = t4_fw_reset(adapter, adapter->mbox, 4158 PIORSTMODE_F | PIORST_F); 4159 if (ret < 0) 4160 goto bye; 4161 } 4162 4163 /* If this is a 10Gb/s-BT adapter make sure the chip-external 4164 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs 4165 * to be performed after any global adapter RESET above since some 4166 * PHYs only have local RAM copies of the PHY firmware. 4167 */ 4168 if (is_10gbt_device(adapter->pdev->device)) { 4169 ret = adap_init0_phy(adapter); 4170 if (ret < 0) 4171 goto bye; 4172 } 4173 /* 4174 * If we have a T4 configuration file under /lib/firmware/cxgb4/, 4175 * then use that. Otherwise, use the configuration file stored 4176 * in the adapter flash ... 4177 */ 4178 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { 4179 case CHELSIO_T4: 4180 fw_config_file = FW4_CFNAME; 4181 break; 4182 case CHELSIO_T5: 4183 fw_config_file = FW5_CFNAME; 4184 break; 4185 case CHELSIO_T6: 4186 fw_config_file = FW6_CFNAME; 4187 break; 4188 default: 4189 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 4190 adapter->pdev->device); 4191 ret = -EINVAL; 4192 goto bye; 4193 } 4194 4195 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); 4196 if (ret < 0) { 4197 config_name = "On FLASH"; 4198 mtype = FW_MEMTYPE_CF_FLASH; 4199 maddr = t4_flash_cfg_addr(adapter); 4200 } else { 4201 u32 params[7], val[7]; 4202 4203 sprintf(fw_config_file_path, 4204 "/lib/firmware/%s", fw_config_file); 4205 config_name = fw_config_file_path; 4206 4207 if (cf->size >= FLASH_CFG_MAX_SIZE) 4208 ret = -ENOMEM; 4209 else { 4210 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4211 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 4212 ret = t4_query_params(adapter, adapter->mbox, 4213 adapter->pf, 0, 1, params, val); 4214 if (ret == 0) { 4215 /* 4216 * For t4_memory_rw() below addresses and 4217 * sizes have to be in terms of multiples of 4 4218 * bytes. So, if the Configuration File isn't 4219 * a multiple of 4 bytes in length we'll have 4220 * to write that out separately since we can't 4221 * guarantee that the bytes following the 4222 * residual byte in the buffer returned by 4223 * request_firmware() are zeroed out ... 4224 */ 4225 size_t resid = cf->size & 0x3; 4226 size_t size = cf->size & ~0x3; 4227 __be32 *data = (__be32 *)cf->data; 4228 4229 mtype = FW_PARAMS_PARAM_Y_G(val[0]); 4230 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; 4231 4232 spin_lock(&adapter->win0_lock); 4233 ret = t4_memory_rw(adapter, 0, mtype, maddr, 4234 size, data, T4_MEMORY_WRITE); 4235 if (ret == 0 && resid != 0) { 4236 union { 4237 __be32 word; 4238 char buf[4]; 4239 } last; 4240 int i; 4241 4242 last.word = data[size >> 2]; 4243 for (i = resid; i < 4; i++) 4244 last.buf[i] = 0; 4245 ret = t4_memory_rw(adapter, 0, mtype, 4246 maddr + size, 4247 4, &last.word, 4248 T4_MEMORY_WRITE); 4249 } 4250 spin_unlock(&adapter->win0_lock); 4251 } 4252 } 4253 4254 release_firmware(cf); 4255 if (ret) 4256 goto bye; 4257 } 4258 4259 val = 0; 4260 4261 /* Ofld + Hash filter is supported. Older fw will fail this request and 4262 * it is fine. 4263 */ 4264 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4265 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD)); 4266 ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0, 4267 1, ¶m, &val); 4268 4269 /* FW doesn't know about Hash filter + ofld support, 4270 * it's not a problem, don't return an error. 4271 */ 4272 if (ret < 0) { 4273 dev_warn(adapter->pdev_dev, 4274 "Hash filter with ofld is not supported by FW\n"); 4275 } 4276 4277 /* 4278 * Issue a Capability Configuration command to the firmware to get it 4279 * to parse the Configuration File. We don't use t4_fw_config_file() 4280 * because we want the ability to modify various features after we've 4281 * processed the configuration file ... 4282 */ 4283 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4284 caps_cmd.op_to_write = 4285 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4286 FW_CMD_REQUEST_F | 4287 FW_CMD_READ_F); 4288 caps_cmd.cfvalid_to_len16 = 4289 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | 4290 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | 4291 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | 4292 FW_LEN16(caps_cmd)); 4293 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 4294 &caps_cmd); 4295 4296 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware 4297 * Configuration File in FLASH), our last gasp effort is to use the 4298 * Firmware Configuration File which is embedded in the firmware. A 4299 * very few early versions of the firmware didn't have one embedded 4300 * but we can ignore those. 4301 */ 4302 if (ret == -ENOENT) { 4303 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4304 caps_cmd.op_to_write = 4305 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4306 FW_CMD_REQUEST_F | 4307 FW_CMD_READ_F); 4308 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4309 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 4310 sizeof(caps_cmd), &caps_cmd); 4311 config_name = "Firmware Default"; 4312 } 4313 4314 config_issued = 1; 4315 if (ret < 0) 4316 goto bye; 4317 4318 finiver = ntohl(caps_cmd.finiver); 4319 finicsum = ntohl(caps_cmd.finicsum); 4320 cfcsum = ntohl(caps_cmd.cfcsum); 4321 if (finicsum != cfcsum) 4322 dev_warn(adapter->pdev_dev, "Configuration File checksum "\ 4323 "mismatch: [fini] csum=%#x, computed csum=%#x\n", 4324 finicsum, cfcsum); 4325 4326 /* 4327 * And now tell the firmware to use the configuration we just loaded. 4328 */ 4329 caps_cmd.op_to_write = 4330 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4331 FW_CMD_REQUEST_F | 4332 FW_CMD_WRITE_F); 4333 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4334 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 4335 NULL); 4336 if (ret < 0) 4337 goto bye; 4338 4339 /* 4340 * Tweak configuration based on system architecture, module 4341 * parameters, etc. 4342 */ 4343 ret = adap_init0_tweaks(adapter); 4344 if (ret < 0) 4345 goto bye; 4346 4347 /* We will proceed even if HMA init fails. */ 4348 ret = adap_config_hma(adapter); 4349 if (ret) 4350 dev_err(adapter->pdev_dev, 4351 "HMA configuration failed with error %d\n", ret); 4352 4353 if (is_t6(adapter->params.chip)) { 4354 ret = setup_ppod_edram(adapter); 4355 if (!ret) 4356 dev_info(adapter->pdev_dev, "Successfully enabled " 4357 "ppod edram feature\n"); 4358 } 4359 4360 /* 4361 * And finally tell the firmware to initialize itself using the 4362 * parameters from the Configuration File. 4363 */ 4364 ret = t4_fw_initialize(adapter, adapter->mbox); 4365 if (ret < 0) 4366 goto bye; 4367 4368 /* Emit Firmware Configuration File information and return 4369 * successfully. 4370 */ 4371 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ 4372 "Configuration File \"%s\", version %#x, computed checksum %#x\n", 4373 config_name, finiver, cfcsum); 4374 return 0; 4375 4376 /* 4377 * Something bad happened. Return the error ... (If the "error" 4378 * is that there's no Configuration File on the adapter we don't 4379 * want to issue a warning since this is fairly common.) 4380 */ 4381 bye: 4382 if (config_issued && ret != -ENOENT) 4383 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", 4384 config_name, -ret); 4385 return ret; 4386 } 4387 4388 static struct fw_info fw_info_array[] = { 4389 { 4390 .chip = CHELSIO_T4, 4391 .fs_name = FW4_CFNAME, 4392 .fw_mod_name = FW4_FNAME, 4393 .fw_hdr = { 4394 .chip = FW_HDR_CHIP_T4, 4395 .fw_ver = __cpu_to_be32(FW_VERSION(T4)), 4396 .intfver_nic = FW_INTFVER(T4, NIC), 4397 .intfver_vnic = FW_INTFVER(T4, VNIC), 4398 .intfver_ri = FW_INTFVER(T4, RI), 4399 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4400 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4401 }, 4402 }, { 4403 .chip = CHELSIO_T5, 4404 .fs_name = FW5_CFNAME, 4405 .fw_mod_name = FW5_FNAME, 4406 .fw_hdr = { 4407 .chip = FW_HDR_CHIP_T5, 4408 .fw_ver = __cpu_to_be32(FW_VERSION(T5)), 4409 .intfver_nic = FW_INTFVER(T5, NIC), 4410 .intfver_vnic = FW_INTFVER(T5, VNIC), 4411 .intfver_ri = FW_INTFVER(T5, RI), 4412 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4413 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4414 }, 4415 }, { 4416 .chip = CHELSIO_T6, 4417 .fs_name = FW6_CFNAME, 4418 .fw_mod_name = FW6_FNAME, 4419 .fw_hdr = { 4420 .chip = FW_HDR_CHIP_T6, 4421 .fw_ver = __cpu_to_be32(FW_VERSION(T6)), 4422 .intfver_nic = FW_INTFVER(T6, NIC), 4423 .intfver_vnic = FW_INTFVER(T6, VNIC), 4424 .intfver_ofld = FW_INTFVER(T6, OFLD), 4425 .intfver_ri = FW_INTFVER(T6, RI), 4426 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4427 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4428 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4429 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4430 }, 4431 } 4432 4433 }; 4434 4435 static struct fw_info *find_fw_info(int chip) 4436 { 4437 int i; 4438 4439 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { 4440 if (fw_info_array[i].chip == chip) 4441 return &fw_info_array[i]; 4442 } 4443 return NULL; 4444 } 4445 4446 /* 4447 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 4448 */ 4449 static int adap_init0(struct adapter *adap, int vpd_skip) 4450 { 4451 struct fw_caps_config_cmd caps_cmd; 4452 u32 params[7], val[7]; 4453 enum dev_state state; 4454 u32 v, port_vec; 4455 int reset = 1; 4456 int ret; 4457 4458 /* Grab Firmware Device Log parameters as early as possible so we have 4459 * access to it for debugging, etc. 4460 */ 4461 ret = t4_init_devlog_params(adap); 4462 if (ret < 0) 4463 return ret; 4464 4465 /* Contact FW, advertising Master capability */ 4466 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, 4467 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); 4468 if (ret < 0) { 4469 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", 4470 ret); 4471 return ret; 4472 } 4473 if (ret == adap->mbox) 4474 adap->flags |= CXGB4_MASTER_PF; 4475 4476 /* 4477 * If we're the Master PF Driver and the device is uninitialized, 4478 * then let's consider upgrading the firmware ... (We always want 4479 * to check the firmware version number in order to A. get it for 4480 * later reporting and B. to warn if the currently loaded firmware 4481 * is excessively mismatched relative to the driver.) 4482 */ 4483 4484 t4_get_version_info(adap); 4485 ret = t4_check_fw_version(adap); 4486 /* If firmware is too old (not supported by driver) force an update. */ 4487 if (ret) 4488 state = DEV_STATE_UNINIT; 4489 if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) { 4490 struct fw_info *fw_info; 4491 struct fw_hdr *card_fw; 4492 const struct firmware *fw; 4493 const u8 *fw_data = NULL; 4494 unsigned int fw_size = 0; 4495 4496 /* This is the firmware whose headers the driver was compiled 4497 * against 4498 */ 4499 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); 4500 if (fw_info == NULL) { 4501 dev_err(adap->pdev_dev, 4502 "unable to get firmware info for chip %d.\n", 4503 CHELSIO_CHIP_VERSION(adap->params.chip)); 4504 return -EINVAL; 4505 } 4506 4507 /* allocate memory to read the header of the firmware on the 4508 * card 4509 */ 4510 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL); 4511 if (!card_fw) { 4512 ret = -ENOMEM; 4513 goto bye; 4514 } 4515 4516 /* Get FW from from /lib/firmware/ */ 4517 ret = request_firmware(&fw, fw_info->fw_mod_name, 4518 adap->pdev_dev); 4519 if (ret < 0) { 4520 dev_err(adap->pdev_dev, 4521 "unable to load firmware image %s, error %d\n", 4522 fw_info->fw_mod_name, ret); 4523 } else { 4524 fw_data = fw->data; 4525 fw_size = fw->size; 4526 } 4527 4528 /* upgrade FW logic */ 4529 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, 4530 state, &reset); 4531 4532 /* Cleaning up */ 4533 release_firmware(fw); 4534 kvfree(card_fw); 4535 4536 if (ret < 0) 4537 goto bye; 4538 } 4539 4540 /* If the firmware is initialized already, emit a simply note to that 4541 * effect. Otherwise, it's time to try initializing the adapter. 4542 */ 4543 if (state == DEV_STATE_INIT) { 4544 ret = adap_config_hma(adap); 4545 if (ret) 4546 dev_err(adap->pdev_dev, 4547 "HMA configuration failed with error %d\n", 4548 ret); 4549 dev_info(adap->pdev_dev, "Coming up as %s: "\ 4550 "Adapter already initialized\n", 4551 adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE"); 4552 } else { 4553 dev_info(adap->pdev_dev, "Coming up as MASTER: "\ 4554 "Initializing adapter\n"); 4555 4556 /* Find out whether we're dealing with a version of the 4557 * firmware which has configuration file support. 4558 */ 4559 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4560 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 4561 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 4562 params, val); 4563 4564 /* If the firmware doesn't support Configuration Files, 4565 * return an error. 4566 */ 4567 if (ret < 0) { 4568 dev_err(adap->pdev_dev, "firmware doesn't support " 4569 "Firmware Configuration Files\n"); 4570 goto bye; 4571 } 4572 4573 /* The firmware provides us with a memory buffer where we can 4574 * load a Configuration File from the host if we want to 4575 * override the Configuration File in flash. 4576 */ 4577 ret = adap_init0_config(adap, reset); 4578 if (ret == -ENOENT) { 4579 dev_err(adap->pdev_dev, "no Configuration File " 4580 "present on adapter.\n"); 4581 goto bye; 4582 } 4583 if (ret < 0) { 4584 dev_err(adap->pdev_dev, "could not initialize " 4585 "adapter, error %d\n", -ret); 4586 goto bye; 4587 } 4588 } 4589 4590 /* Now that we've successfully configured and initialized the adapter 4591 * (or found it already initialized), we can ask the Firmware what 4592 * resources it has provisioned for us. 4593 */ 4594 ret = t4_get_pfres(adap); 4595 if (ret) { 4596 dev_err(adap->pdev_dev, 4597 "Unable to retrieve resource provisioning information\n"); 4598 goto bye; 4599 } 4600 4601 /* Grab VPD parameters. This should be done after we establish a 4602 * connection to the firmware since some of the VPD parameters 4603 * (notably the Core Clock frequency) are retrieved via requests to 4604 * the firmware. On the other hand, we need these fairly early on 4605 * so we do this right after getting ahold of the firmware. 4606 * 4607 * We need to do this after initializing the adapter because someone 4608 * could have FLASHed a new VPD which won't be read by the firmware 4609 * until we do the RESET ... 4610 */ 4611 if (!vpd_skip) { 4612 ret = t4_get_vpd_params(adap, &adap->params.vpd); 4613 if (ret < 0) 4614 goto bye; 4615 } 4616 4617 /* Find out what ports are available to us. Note that we need to do 4618 * this before calling adap_init0_no_config() since it needs nports 4619 * and portvec ... 4620 */ 4621 v = 4622 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4623 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 4624 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 4625 if (ret < 0) 4626 goto bye; 4627 4628 adap->params.nports = hweight32(port_vec); 4629 adap->params.portvec = port_vec; 4630 4631 /* Give the SGE code a chance to pull in anything that it needs ... 4632 * Note that this must be called after we retrieve our VPD parameters 4633 * in order to know how to convert core ticks to seconds, etc. 4634 */ 4635 ret = t4_sge_init(adap); 4636 if (ret < 0) 4637 goto bye; 4638 4639 /* Grab the SGE Doorbell Queue Timer values. If successful, that 4640 * indicates that the Firmware and Hardware support this. 4641 */ 4642 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4643 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK)); 4644 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4645 1, params, val); 4646 4647 if (!ret) { 4648 adap->sge.dbqtimer_tick = val[0]; 4649 ret = t4_read_sge_dbqtimers(adap, 4650 ARRAY_SIZE(adap->sge.dbqtimer_val), 4651 adap->sge.dbqtimer_val); 4652 } 4653 4654 if (!ret) 4655 adap->flags |= CXGB4_SGE_DBQ_TIMER; 4656 4657 if (is_bypass_device(adap->pdev->device)) 4658 adap->params.bypass = 1; 4659 4660 /* 4661 * Grab some of our basic fundamental operating parameters. 4662 */ 4663 #define FW_PARAM_DEV(param) \ 4664 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 4665 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 4666 4667 #define FW_PARAM_PFVF(param) \ 4668 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 4669 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ 4670 FW_PARAMS_PARAM_Y_V(0) | \ 4671 FW_PARAMS_PARAM_Z_V(0) 4672 4673 params[0] = FW_PARAM_PFVF(EQ_START); 4674 params[1] = FW_PARAM_PFVF(L2T_START); 4675 params[2] = FW_PARAM_PFVF(L2T_END); 4676 params[3] = FW_PARAM_PFVF(FILTER_START); 4677 params[4] = FW_PARAM_PFVF(FILTER_END); 4678 params[5] = FW_PARAM_PFVF(IQFLINT_START); 4679 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); 4680 if (ret < 0) 4681 goto bye; 4682 adap->sge.egr_start = val[0]; 4683 adap->l2t_start = val[1]; 4684 adap->l2t_end = val[2]; 4685 adap->tids.ftid_base = val[3]; 4686 adap->tids.nftids = val[4] - val[3] + 1; 4687 adap->sge.ingr_start = val[5]; 4688 4689 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 4690 /* Read the raw mps entries. In T6, the last 2 tcam entries 4691 * are reserved for raw mac addresses (rawf = 2, one per port). 4692 */ 4693 params[0] = FW_PARAM_PFVF(RAWF_START); 4694 params[1] = FW_PARAM_PFVF(RAWF_END); 4695 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4696 params, val); 4697 if (ret == 0) { 4698 adap->rawf_start = val[0]; 4699 adap->rawf_cnt = val[1] - val[0] + 1; 4700 } 4701 } 4702 4703 /* qids (ingress/egress) returned from firmware can be anywhere 4704 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. 4705 * Hence driver needs to allocate memory for this range to 4706 * store the queue info. Get the highest IQFLINT/EQ index returned 4707 * in FW_EQ_*_CMD.alloc command. 4708 */ 4709 params[0] = FW_PARAM_PFVF(EQ_END); 4710 params[1] = FW_PARAM_PFVF(IQFLINT_END); 4711 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4712 if (ret < 0) 4713 goto bye; 4714 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; 4715 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; 4716 4717 adap->sge.egr_map = kcalloc(adap->sge.egr_sz, 4718 sizeof(*adap->sge.egr_map), GFP_KERNEL); 4719 if (!adap->sge.egr_map) { 4720 ret = -ENOMEM; 4721 goto bye; 4722 } 4723 4724 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, 4725 sizeof(*adap->sge.ingr_map), GFP_KERNEL); 4726 if (!adap->sge.ingr_map) { 4727 ret = -ENOMEM; 4728 goto bye; 4729 } 4730 4731 /* Allocate the memory for the vaious egress queue bitmaps 4732 * ie starving_fl, txq_maperr and blocked_fl. 4733 */ 4734 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4735 sizeof(long), GFP_KERNEL); 4736 if (!adap->sge.starving_fl) { 4737 ret = -ENOMEM; 4738 goto bye; 4739 } 4740 4741 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4742 sizeof(long), GFP_KERNEL); 4743 if (!adap->sge.txq_maperr) { 4744 ret = -ENOMEM; 4745 goto bye; 4746 } 4747 4748 #ifdef CONFIG_DEBUG_FS 4749 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4750 sizeof(long), GFP_KERNEL); 4751 if (!adap->sge.blocked_fl) { 4752 ret = -ENOMEM; 4753 goto bye; 4754 } 4755 #endif 4756 4757 params[0] = FW_PARAM_PFVF(CLIP_START); 4758 params[1] = FW_PARAM_PFVF(CLIP_END); 4759 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4760 if (ret < 0) 4761 goto bye; 4762 adap->clipt_start = val[0]; 4763 adap->clipt_end = val[1]; 4764 4765 /* Get the supported number of traffic classes */ 4766 params[0] = FW_PARAM_DEV(NUM_TM_CLASS); 4767 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 4768 if (ret < 0) { 4769 /* We couldn't retrieve the number of Traffic Classes 4770 * supported by the hardware/firmware. So we hard 4771 * code it here. 4772 */ 4773 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; 4774 } else { 4775 adap->params.nsched_cls = val[0]; 4776 } 4777 4778 /* query params related to active filter region */ 4779 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); 4780 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); 4781 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4782 /* If Active filter size is set we enable establishing 4783 * offload connection through firmware work request 4784 */ 4785 if ((val[0] != val[1]) && (ret >= 0)) { 4786 adap->flags |= CXGB4_FW_OFLD_CONN; 4787 adap->tids.aftid_base = val[0]; 4788 adap->tids.aftid_end = val[1]; 4789 } 4790 4791 /* If we're running on newer firmware, let it know that we're 4792 * prepared to deal with encapsulated CPL messages. Older 4793 * firmware won't understand this and we'll just get 4794 * unencapsulated messages ... 4795 */ 4796 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4797 val[0] = 1; 4798 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 4799 4800 /* 4801 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 4802 * capability. Earlier versions of the firmware didn't have the 4803 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 4804 * permission to use ULPTX MEMWRITE DSGL. 4805 */ 4806 if (is_t4(adap->params.chip)) { 4807 adap->params.ulptx_memwrite_dsgl = false; 4808 } else { 4809 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4810 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4811 1, params, val); 4812 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 4813 } 4814 4815 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ 4816 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 4817 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4818 1, params, val); 4819 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); 4820 4821 /* See if FW supports FW_FILTER2 work request */ 4822 if (is_t4(adap->params.chip)) { 4823 adap->params.filter2_wr_support = 0; 4824 } else { 4825 params[0] = FW_PARAM_DEV(FILTER2_WR); 4826 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4827 1, params, val); 4828 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 4829 } 4830 4831 /* Check if FW supports returning vin and smt index. 4832 * If this is not supported, driver will interpret 4833 * these values from viid. 4834 */ 4835 params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4836 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4837 1, params, val); 4838 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0); 4839 4840 /* 4841 * Get device capabilities so we can determine what resources we need 4842 * to manage. 4843 */ 4844 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4845 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4846 FW_CMD_REQUEST_F | FW_CMD_READ_F); 4847 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4848 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 4849 &caps_cmd); 4850 if (ret < 0) 4851 goto bye; 4852 4853 /* hash filter has some mandatory register settings to be tested and for 4854 * that it needs to test whether offload is enabled or not, hence 4855 * checking and setting it here. 4856 */ 4857 if (caps_cmd.ofldcaps) 4858 adap->params.offload = 1; 4859 4860 if (caps_cmd.ofldcaps || 4861 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) || 4862 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD))) { 4863 /* query offload-related parameters */ 4864 params[0] = FW_PARAM_DEV(NTID); 4865 params[1] = FW_PARAM_PFVF(SERVER_START); 4866 params[2] = FW_PARAM_PFVF(SERVER_END); 4867 params[3] = FW_PARAM_PFVF(TDDP_START); 4868 params[4] = FW_PARAM_PFVF(TDDP_END); 4869 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4870 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 4871 params, val); 4872 if (ret < 0) 4873 goto bye; 4874 adap->tids.ntids = val[0]; 4875 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 4876 adap->tids.stid_base = val[1]; 4877 adap->tids.nstids = val[2] - val[1] + 1; 4878 /* 4879 * Setup server filter region. Divide the available filter 4880 * region into two parts. Regular filters get 1/3rd and server 4881 * filters get 2/3rd part. This is only enabled if workarond 4882 * path is enabled. 4883 * 1. For regular filters. 4884 * 2. Server filter: This are special filters which are used 4885 * to redirect SYN packets to offload queue. 4886 */ 4887 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) { 4888 adap->tids.sftid_base = adap->tids.ftid_base + 4889 DIV_ROUND_UP(adap->tids.nftids, 3); 4890 adap->tids.nsftids = adap->tids.nftids - 4891 DIV_ROUND_UP(adap->tids.nftids, 3); 4892 adap->tids.nftids = adap->tids.sftid_base - 4893 adap->tids.ftid_base; 4894 } 4895 adap->vres.ddp.start = val[3]; 4896 adap->vres.ddp.size = val[4] - val[3] + 1; 4897 adap->params.ofldq_wr_cred = val[5]; 4898 4899 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 4900 init_hash_filter(adap); 4901 } else { 4902 adap->num_ofld_uld += 1; 4903 } 4904 4905 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD)) { 4906 params[0] = FW_PARAM_PFVF(ETHOFLD_START); 4907 params[1] = FW_PARAM_PFVF(ETHOFLD_END); 4908 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4909 params, val); 4910 if (!ret) { 4911 adap->tids.eotid_base = val[0]; 4912 adap->tids.neotids = min_t(u32, MAX_ATIDS, 4913 val[1] - val[0] + 1); 4914 adap->params.ethofld = 1; 4915 } 4916 } 4917 } 4918 if (caps_cmd.rdmacaps) { 4919 params[0] = FW_PARAM_PFVF(STAG_START); 4920 params[1] = FW_PARAM_PFVF(STAG_END); 4921 params[2] = FW_PARAM_PFVF(RQ_START); 4922 params[3] = FW_PARAM_PFVF(RQ_END); 4923 params[4] = FW_PARAM_PFVF(PBL_START); 4924 params[5] = FW_PARAM_PFVF(PBL_END); 4925 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 4926 params, val); 4927 if (ret < 0) 4928 goto bye; 4929 adap->vres.stag.start = val[0]; 4930 adap->vres.stag.size = val[1] - val[0] + 1; 4931 adap->vres.rq.start = val[2]; 4932 adap->vres.rq.size = val[3] - val[2] + 1; 4933 adap->vres.pbl.start = val[4]; 4934 adap->vres.pbl.size = val[5] - val[4] + 1; 4935 4936 params[0] = FW_PARAM_PFVF(SRQ_START); 4937 params[1] = FW_PARAM_PFVF(SRQ_END); 4938 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4939 params, val); 4940 if (!ret) { 4941 adap->vres.srq.start = val[0]; 4942 adap->vres.srq.size = val[1] - val[0] + 1; 4943 } 4944 if (adap->vres.srq.size) { 4945 adap->srq = t4_init_srq(adap->vres.srq.size); 4946 if (!adap->srq) 4947 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n"); 4948 } 4949 4950 params[0] = FW_PARAM_PFVF(SQRQ_START); 4951 params[1] = FW_PARAM_PFVF(SQRQ_END); 4952 params[2] = FW_PARAM_PFVF(CQ_START); 4953 params[3] = FW_PARAM_PFVF(CQ_END); 4954 params[4] = FW_PARAM_PFVF(OCQ_START); 4955 params[5] = FW_PARAM_PFVF(OCQ_END); 4956 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, 4957 val); 4958 if (ret < 0) 4959 goto bye; 4960 adap->vres.qp.start = val[0]; 4961 adap->vres.qp.size = val[1] - val[0] + 1; 4962 adap->vres.cq.start = val[2]; 4963 adap->vres.cq.size = val[3] - val[2] + 1; 4964 adap->vres.ocq.start = val[4]; 4965 adap->vres.ocq.size = val[5] - val[4] + 1; 4966 4967 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); 4968 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4969 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, 4970 val); 4971 if (ret < 0) { 4972 adap->params.max_ordird_qp = 8; 4973 adap->params.max_ird_adapter = 32 * adap->tids.ntids; 4974 ret = 0; 4975 } else { 4976 adap->params.max_ordird_qp = val[0]; 4977 adap->params.max_ird_adapter = val[1]; 4978 } 4979 dev_info(adap->pdev_dev, 4980 "max_ordird_qp %d max_ird_adapter %d\n", 4981 adap->params.max_ordird_qp, 4982 adap->params.max_ird_adapter); 4983 4984 /* Enable write_with_immediate if FW supports it */ 4985 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM); 4986 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, 4987 val); 4988 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0); 4989 4990 /* Enable write_cmpl if FW supports it */ 4991 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR); 4992 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, 4993 val); 4994 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0); 4995 adap->num_ofld_uld += 2; 4996 } 4997 if (caps_cmd.iscsicaps) { 4998 params[0] = FW_PARAM_PFVF(ISCSI_START); 4999 params[1] = FW_PARAM_PFVF(ISCSI_END); 5000 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 5001 params, val); 5002 if (ret < 0) 5003 goto bye; 5004 adap->vres.iscsi.start = val[0]; 5005 adap->vres.iscsi.size = val[1] - val[0] + 1; 5006 if (is_t6(adap->params.chip)) { 5007 params[0] = FW_PARAM_PFVF(PPOD_EDRAM_START); 5008 params[1] = FW_PARAM_PFVF(PPOD_EDRAM_END); 5009 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 5010 params, val); 5011 if (!ret) { 5012 adap->vres.ppod_edram.start = val[0]; 5013 adap->vres.ppod_edram.size = 5014 val[1] - val[0] + 1; 5015 5016 dev_info(adap->pdev_dev, 5017 "ppod edram start 0x%x end 0x%x size 0x%x\n", 5018 val[0], val[1], 5019 adap->vres.ppod_edram.size); 5020 } 5021 } 5022 /* LIO target and cxgb4i initiaitor */ 5023 adap->num_ofld_uld += 2; 5024 } 5025 if (caps_cmd.cryptocaps) { 5026 if (ntohs(caps_cmd.cryptocaps) & 5027 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) { 5028 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE); 5029 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 5030 2, params, val); 5031 if (ret < 0) { 5032 if (ret != -EINVAL) 5033 goto bye; 5034 } else { 5035 adap->vres.ncrypto_fc = val[0]; 5036 } 5037 adap->num_ofld_uld += 1; 5038 } 5039 if (ntohs(caps_cmd.cryptocaps) & 5040 FW_CAPS_CONFIG_TLS_INLINE) { 5041 params[0] = FW_PARAM_PFVF(TLS_START); 5042 params[1] = FW_PARAM_PFVF(TLS_END); 5043 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 5044 2, params, val); 5045 if (ret < 0) 5046 goto bye; 5047 adap->vres.key.start = val[0]; 5048 adap->vres.key.size = val[1] - val[0] + 1; 5049 adap->num_uld += 1; 5050 } 5051 adap->params.crypto = ntohs(caps_cmd.cryptocaps); 5052 } 5053 #undef FW_PARAM_PFVF 5054 #undef FW_PARAM_DEV 5055 5056 /* The MTU/MSS Table is initialized by now, so load their values. If 5057 * we're initializing the adapter, then we'll make any modifications 5058 * we want to the MTU/MSS Table and also initialize the congestion 5059 * parameters. 5060 */ 5061 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 5062 if (state != DEV_STATE_INIT) { 5063 int i; 5064 5065 /* The default MTU Table contains values 1492 and 1500. 5066 * However, for TCP, it's better to have two values which are 5067 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 5068 * This allows us to have a TCP Data Payload which is a 5069 * multiple of 8 regardless of what combination of TCP Options 5070 * are in use (always a multiple of 4 bytes) which is 5071 * important for performance reasons. For instance, if no 5072 * options are in use, then we have a 20-byte IP header and a 5073 * 20-byte TCP header. In this case, a 1500-byte MSS would 5074 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 5075 * which is not a multiple of 8. So using an MSS of 1488 in 5076 * this case results in a TCP Data Payload of 1448 bytes which 5077 * is a multiple of 8. On the other hand, if 12-byte TCP Time 5078 * Stamps have been negotiated, then an MTU of 1500 bytes 5079 * results in a TCP Data Payload of 1448 bytes which, as 5080 * above, is a multiple of 8 bytes ... 5081 */ 5082 for (i = 0; i < NMTUS; i++) 5083 if (adap->params.mtus[i] == 1492) { 5084 adap->params.mtus[i] = 1488; 5085 break; 5086 } 5087 5088 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 5089 adap->params.b_wnd); 5090 } 5091 t4_init_sge_params(adap); 5092 adap->flags |= CXGB4_FW_OK; 5093 t4_init_tp_params(adap, true); 5094 return 0; 5095 5096 /* 5097 * Something bad happened. If a command timed out or failed with EIO 5098 * FW does not operate within its spec or something catastrophic 5099 * happened to HW/FW, stop issuing commands. 5100 */ 5101 bye: 5102 adap_free_hma_mem(adap); 5103 kfree(adap->sge.egr_map); 5104 kfree(adap->sge.ingr_map); 5105 kfree(adap->sge.starving_fl); 5106 kfree(adap->sge.txq_maperr); 5107 #ifdef CONFIG_DEBUG_FS 5108 kfree(adap->sge.blocked_fl); 5109 #endif 5110 if (ret != -ETIMEDOUT && ret != -EIO) 5111 t4_fw_bye(adap, adap->mbox); 5112 return ret; 5113 } 5114 5115 /* EEH callbacks */ 5116 5117 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, 5118 pci_channel_state_t state) 5119 { 5120 int i; 5121 struct adapter *adap = pci_get_drvdata(pdev); 5122 5123 if (!adap) 5124 goto out; 5125 5126 rtnl_lock(); 5127 adap->flags &= ~CXGB4_FW_OK; 5128 notify_ulds(adap, CXGB4_STATE_START_RECOVERY); 5129 spin_lock(&adap->stats_lock); 5130 for_each_port(adap, i) { 5131 struct net_device *dev = adap->port[i]; 5132 if (dev) { 5133 netif_device_detach(dev); 5134 netif_carrier_off(dev); 5135 } 5136 } 5137 spin_unlock(&adap->stats_lock); 5138 disable_interrupts(adap); 5139 if (adap->flags & CXGB4_FULL_INIT_DONE) 5140 cxgb_down(adap); 5141 rtnl_unlock(); 5142 if ((adap->flags & CXGB4_DEV_ENABLED)) { 5143 pci_disable_device(pdev); 5144 adap->flags &= ~CXGB4_DEV_ENABLED; 5145 } 5146 out: return state == pci_channel_io_perm_failure ? 5147 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 5148 } 5149 5150 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) 5151 { 5152 int i, ret; 5153 struct fw_caps_config_cmd c; 5154 struct adapter *adap = pci_get_drvdata(pdev); 5155 5156 if (!adap) { 5157 pci_restore_state(pdev); 5158 pci_save_state(pdev); 5159 return PCI_ERS_RESULT_RECOVERED; 5160 } 5161 5162 if (!(adap->flags & CXGB4_DEV_ENABLED)) { 5163 if (pci_enable_device(pdev)) { 5164 dev_err(&pdev->dev, "Cannot reenable PCI " 5165 "device after reset\n"); 5166 return PCI_ERS_RESULT_DISCONNECT; 5167 } 5168 adap->flags |= CXGB4_DEV_ENABLED; 5169 } 5170 5171 pci_set_master(pdev); 5172 pci_restore_state(pdev); 5173 pci_save_state(pdev); 5174 5175 if (t4_wait_dev_ready(adap->regs) < 0) 5176 return PCI_ERS_RESULT_DISCONNECT; 5177 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) 5178 return PCI_ERS_RESULT_DISCONNECT; 5179 adap->flags |= CXGB4_FW_OK; 5180 if (adap_init1(adap, &c)) 5181 return PCI_ERS_RESULT_DISCONNECT; 5182 5183 for_each_port(adap, i) { 5184 struct port_info *pi = adap2pinfo(adap, i); 5185 u8 vivld = 0, vin = 0; 5186 5187 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1, 5188 NULL, NULL, &vivld, &vin); 5189 if (ret < 0) 5190 return PCI_ERS_RESULT_DISCONNECT; 5191 pi->viid = ret; 5192 pi->xact_addr_filt = -1; 5193 /* If fw supports returning the VIN as part of FW_VI_CMD, 5194 * save the returned values. 5195 */ 5196 if (adap->params.viid_smt_extn_support) { 5197 pi->vivld = vivld; 5198 pi->vin = vin; 5199 } else { 5200 /* Retrieve the values from VIID */ 5201 pi->vivld = FW_VIID_VIVLD_G(pi->viid); 5202 pi->vin = FW_VIID_VIN_G(pi->viid); 5203 } 5204 } 5205 5206 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 5207 adap->params.b_wnd); 5208 setup_memwin(adap); 5209 if (cxgb_up(adap)) 5210 return PCI_ERS_RESULT_DISCONNECT; 5211 return PCI_ERS_RESULT_RECOVERED; 5212 } 5213 5214 static void eeh_resume(struct pci_dev *pdev) 5215 { 5216 int i; 5217 struct adapter *adap = pci_get_drvdata(pdev); 5218 5219 if (!adap) 5220 return; 5221 5222 rtnl_lock(); 5223 for_each_port(adap, i) { 5224 struct net_device *dev = adap->port[i]; 5225 if (dev) { 5226 if (netif_running(dev)) { 5227 link_start(dev); 5228 cxgb_set_rxmode(dev); 5229 } 5230 netif_device_attach(dev); 5231 } 5232 } 5233 rtnl_unlock(); 5234 } 5235 5236 static void eeh_reset_prepare(struct pci_dev *pdev) 5237 { 5238 struct adapter *adapter = pci_get_drvdata(pdev); 5239 int i; 5240 5241 if (adapter->pf != 4) 5242 return; 5243 5244 adapter->flags &= ~CXGB4_FW_OK; 5245 5246 notify_ulds(adapter, CXGB4_STATE_DOWN); 5247 5248 for_each_port(adapter, i) 5249 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5250 cxgb_close(adapter->port[i]); 5251 5252 disable_interrupts(adapter); 5253 cxgb4_free_mps_ref_entries(adapter); 5254 5255 adap_free_hma_mem(adapter); 5256 5257 if (adapter->flags & CXGB4_FULL_INIT_DONE) 5258 cxgb_down(adapter); 5259 } 5260 5261 static void eeh_reset_done(struct pci_dev *pdev) 5262 { 5263 struct adapter *adapter = pci_get_drvdata(pdev); 5264 int err, i; 5265 5266 if (adapter->pf != 4) 5267 return; 5268 5269 err = t4_wait_dev_ready(adapter->regs); 5270 if (err < 0) { 5271 dev_err(adapter->pdev_dev, 5272 "Device not ready, err %d", err); 5273 return; 5274 } 5275 5276 setup_memwin(adapter); 5277 5278 err = adap_init0(adapter, 1); 5279 if (err) { 5280 dev_err(adapter->pdev_dev, 5281 "Adapter init failed, err %d", err); 5282 return; 5283 } 5284 5285 setup_memwin_rdma(adapter); 5286 5287 if (adapter->flags & CXGB4_FW_OK) { 5288 err = t4_port_init(adapter, adapter->pf, adapter->pf, 0); 5289 if (err) { 5290 dev_err(adapter->pdev_dev, 5291 "Port init failed, err %d", err); 5292 return; 5293 } 5294 } 5295 5296 err = cfg_queues(adapter); 5297 if (err) { 5298 dev_err(adapter->pdev_dev, 5299 "Config queues failed, err %d", err); 5300 return; 5301 } 5302 5303 cxgb4_init_mps_ref_entries(adapter); 5304 5305 err = setup_fw_sge_queues(adapter); 5306 if (err) { 5307 dev_err(adapter->pdev_dev, 5308 "FW sge queue allocation failed, err %d", err); 5309 return; 5310 } 5311 5312 for_each_port(adapter, i) 5313 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5314 cxgb_open(adapter->port[i]); 5315 } 5316 5317 static const struct pci_error_handlers cxgb4_eeh = { 5318 .error_detected = eeh_err_detected, 5319 .slot_reset = eeh_slot_reset, 5320 .resume = eeh_resume, 5321 .reset_prepare = eeh_reset_prepare, 5322 .reset_done = eeh_reset_done, 5323 }; 5324 5325 /* Return true if the Link Configuration supports "High Speeds" (those greater 5326 * than 1Gb/s). 5327 */ 5328 static inline bool is_x_10g_port(const struct link_config *lc) 5329 { 5330 unsigned int speeds, high_speeds; 5331 5332 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps)); 5333 high_speeds = speeds & 5334 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 5335 5336 return high_speeds != 0; 5337 } 5338 5339 /* Perform default configuration of DMA queues depending on the number and type 5340 * of ports we found and the number of available CPUs. Most settings can be 5341 * modified by the admin prior to actual use. 5342 */ 5343 static int cfg_queues(struct adapter *adap) 5344 { 5345 u32 avail_qsets, avail_eth_qsets, avail_uld_qsets; 5346 u32 niqflint, neq, num_ulds; 5347 struct sge *s = &adap->sge; 5348 u32 i, n10g = 0, qidx = 0; 5349 #ifndef CONFIG_CHELSIO_T4_DCB 5350 int q10g = 0; 5351 #endif 5352 5353 /* Reduce memory usage in kdump environment, disable all offload. */ 5354 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) { 5355 adap->params.offload = 0; 5356 adap->params.crypto = 0; 5357 adap->params.ethofld = 0; 5358 } 5359 5360 /* Calculate the number of Ethernet Queue Sets available based on 5361 * resources provisioned for us. We always have an Asynchronous 5362 * Firmware Event Ingress Queue. If we're operating in MSI or Legacy 5363 * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt 5364 * Ingress Queue. Meanwhile, we need two Egress Queues for each 5365 * Queue Set: one for the Free List and one for the Ethernet TX Queue. 5366 * 5367 * Note that we should also take into account all of the various 5368 * Offload Queues. But, in any situation where we're operating in 5369 * a Resource Constrained Provisioning environment, doing any Offload 5370 * at all is problematic ... 5371 */ 5372 niqflint = adap->params.pfres.niqflint - 1; 5373 if (!(adap->flags & CXGB4_USING_MSIX)) 5374 niqflint--; 5375 neq = adap->params.pfres.neq / 2; 5376 avail_qsets = min(niqflint, neq); 5377 5378 if (avail_qsets < adap->params.nports) { 5379 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n", 5380 avail_qsets, adap->params.nports); 5381 return -ENOMEM; 5382 } 5383 5384 /* Count the number of 10Gb/s or better ports */ 5385 for_each_port(adap, i) 5386 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); 5387 5388 avail_eth_qsets = min_t(u32, avail_qsets, MAX_ETH_QSETS); 5389 #ifdef CONFIG_CHELSIO_T4_DCB 5390 /* For Data Center Bridging support we need to be able to support up 5391 * to 8 Traffic Priorities; each of which will be assigned to its 5392 * own TX Queue in order to prevent Head-Of-Line Blocking. 5393 */ 5394 if (adap->params.nports * 8 > avail_eth_qsets) { 5395 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n", 5396 avail_eth_qsets, adap->params.nports * 8); 5397 return -ENOMEM; 5398 } 5399 5400 for_each_port(adap, i) { 5401 struct port_info *pi = adap2pinfo(adap, i); 5402 5403 pi->first_qset = qidx; 5404 pi->nqsets = is_kdump_kernel() ? 1 : 8; 5405 qidx += pi->nqsets; 5406 } 5407 #else /* !CONFIG_CHELSIO_T4_DCB */ 5408 /* We default to 1 queue per non-10G port and up to # of cores queues 5409 * per 10G port. 5410 */ 5411 if (n10g) 5412 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g; 5413 if (q10g > netif_get_num_default_rss_queues()) 5414 q10g = netif_get_num_default_rss_queues(); 5415 5416 if (is_kdump_kernel()) 5417 q10g = 1; 5418 5419 for_each_port(adap, i) { 5420 struct port_info *pi = adap2pinfo(adap, i); 5421 5422 pi->first_qset = qidx; 5423 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; 5424 qidx += pi->nqsets; 5425 } 5426 #endif /* !CONFIG_CHELSIO_T4_DCB */ 5427 5428 s->ethqsets = qidx; 5429 s->max_ethqsets = qidx; /* MSI-X may lower it later */ 5430 avail_qsets -= qidx; 5431 5432 if (is_uld(adap)) { 5433 /* For offload we use 1 queue/channel if all ports are up to 1G, 5434 * otherwise we divide all available queues amongst the channels 5435 * capped by the number of available cores. 5436 */ 5437 num_ulds = adap->num_uld + adap->num_ofld_uld; 5438 i = min_t(u32, MAX_OFLD_QSETS, num_online_cpus()); 5439 avail_uld_qsets = roundup(i, adap->params.nports); 5440 if (avail_qsets < num_ulds * adap->params.nports) { 5441 adap->params.offload = 0; 5442 adap->params.crypto = 0; 5443 s->ofldqsets = 0; 5444 } else if (avail_qsets < num_ulds * avail_uld_qsets || !n10g) { 5445 s->ofldqsets = adap->params.nports; 5446 } else { 5447 s->ofldqsets = avail_uld_qsets; 5448 } 5449 5450 avail_qsets -= num_ulds * s->ofldqsets; 5451 } 5452 5453 /* ETHOFLD Queues used for QoS offload should follow same 5454 * allocation scheme as normal Ethernet Queues. 5455 */ 5456 if (is_ethofld(adap)) { 5457 if (avail_qsets < s->max_ethqsets) { 5458 adap->params.ethofld = 0; 5459 s->eoqsets = 0; 5460 } else { 5461 s->eoqsets = s->max_ethqsets; 5462 } 5463 avail_qsets -= s->eoqsets; 5464 } 5465 5466 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 5467 struct sge_eth_rxq *r = &s->ethrxq[i]; 5468 5469 init_rspq(adap, &r->rspq, 5, 10, 1024, 64); 5470 r->fl.size = 72; 5471 } 5472 5473 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 5474 s->ethtxq[i].q.size = 1024; 5475 5476 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) 5477 s->ctrlq[i].q.size = 512; 5478 5479 if (!is_t4(adap->params.chip)) 5480 s->ptptxq.q.size = 8; 5481 5482 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); 5483 init_rspq(adap, &s->intrq, 0, 1, 512, 64); 5484 5485 return 0; 5486 } 5487 5488 /* 5489 * Reduce the number of Ethernet queues across all ports to at most n. 5490 * n provides at least one queue per port. 5491 */ 5492 static void reduce_ethqs(struct adapter *adap, int n) 5493 { 5494 int i; 5495 struct port_info *pi; 5496 5497 while (n < adap->sge.ethqsets) 5498 for_each_port(adap, i) { 5499 pi = adap2pinfo(adap, i); 5500 if (pi->nqsets > 1) { 5501 pi->nqsets--; 5502 adap->sge.ethqsets--; 5503 if (adap->sge.ethqsets <= n) 5504 break; 5505 } 5506 } 5507 5508 n = 0; 5509 for_each_port(adap, i) { 5510 pi = adap2pinfo(adap, i); 5511 pi->first_qset = n; 5512 n += pi->nqsets; 5513 } 5514 } 5515 5516 static int alloc_msix_info(struct adapter *adap, u32 num_vec) 5517 { 5518 struct msix_info *msix_info; 5519 5520 msix_info = kcalloc(num_vec, sizeof(*msix_info), GFP_KERNEL); 5521 if (!msix_info) 5522 return -ENOMEM; 5523 5524 adap->msix_bmap.msix_bmap = kcalloc(BITS_TO_LONGS(num_vec), 5525 sizeof(long), GFP_KERNEL); 5526 if (!adap->msix_bmap.msix_bmap) { 5527 kfree(msix_info); 5528 return -ENOMEM; 5529 } 5530 5531 spin_lock_init(&adap->msix_bmap.lock); 5532 adap->msix_bmap.mapsize = num_vec; 5533 5534 adap->msix_info = msix_info; 5535 return 0; 5536 } 5537 5538 static void free_msix_info(struct adapter *adap) 5539 { 5540 kfree(adap->msix_bmap.msix_bmap); 5541 kfree(adap->msix_info); 5542 } 5543 5544 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap) 5545 { 5546 struct msix_bmap *bmap = &adap->msix_bmap; 5547 unsigned int msix_idx; 5548 unsigned long flags; 5549 5550 spin_lock_irqsave(&bmap->lock, flags); 5551 msix_idx = find_first_zero_bit(bmap->msix_bmap, bmap->mapsize); 5552 if (msix_idx < bmap->mapsize) { 5553 __set_bit(msix_idx, bmap->msix_bmap); 5554 } else { 5555 spin_unlock_irqrestore(&bmap->lock, flags); 5556 return -ENOSPC; 5557 } 5558 5559 spin_unlock_irqrestore(&bmap->lock, flags); 5560 return msix_idx; 5561 } 5562 5563 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, 5564 unsigned int msix_idx) 5565 { 5566 struct msix_bmap *bmap = &adap->msix_bmap; 5567 unsigned long flags; 5568 5569 spin_lock_irqsave(&bmap->lock, flags); 5570 __clear_bit(msix_idx, bmap->msix_bmap); 5571 spin_unlock_irqrestore(&bmap->lock, flags); 5572 } 5573 5574 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ 5575 #define EXTRA_VECS 2 5576 5577 static int enable_msix(struct adapter *adap) 5578 { 5579 u32 eth_need, uld_need = 0, ethofld_need = 0; 5580 u32 ethqsets = 0, ofldqsets = 0, eoqsets = 0; 5581 u8 num_uld = 0, nchan = adap->params.nports; 5582 u32 i, want, need, num_vec; 5583 struct sge *s = &adap->sge; 5584 struct msix_entry *entries; 5585 struct port_info *pi; 5586 int allocated, ret; 5587 5588 want = s->max_ethqsets; 5589 #ifdef CONFIG_CHELSIO_T4_DCB 5590 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for 5591 * each port. 5592 */ 5593 need = 8 * nchan; 5594 #else 5595 need = nchan; 5596 #endif 5597 eth_need = need; 5598 if (is_uld(adap)) { 5599 num_uld = adap->num_ofld_uld + adap->num_uld; 5600 want += num_uld * s->ofldqsets; 5601 uld_need = num_uld * nchan; 5602 need += uld_need; 5603 } 5604 5605 if (is_ethofld(adap)) { 5606 want += s->eoqsets; 5607 ethofld_need = eth_need; 5608 need += ethofld_need; 5609 } 5610 5611 want += EXTRA_VECS; 5612 need += EXTRA_VECS; 5613 5614 entries = kmalloc_array(want, sizeof(*entries), GFP_KERNEL); 5615 if (!entries) 5616 return -ENOMEM; 5617 5618 for (i = 0; i < want; i++) 5619 entries[i].entry = i; 5620 5621 allocated = pci_enable_msix_range(adap->pdev, entries, need, want); 5622 if (allocated < 0) { 5623 /* Disable offload and attempt to get vectors for NIC 5624 * only mode. 5625 */ 5626 want = s->max_ethqsets + EXTRA_VECS; 5627 need = eth_need + EXTRA_VECS; 5628 allocated = pci_enable_msix_range(adap->pdev, entries, 5629 need, want); 5630 if (allocated < 0) { 5631 dev_info(adap->pdev_dev, 5632 "Disabling MSI-X due to insufficient MSI-X vectors\n"); 5633 ret = allocated; 5634 goto out_free; 5635 } 5636 5637 dev_info(adap->pdev_dev, 5638 "Disabling offload due to insufficient MSI-X vectors\n"); 5639 adap->params.offload = 0; 5640 adap->params.crypto = 0; 5641 adap->params.ethofld = 0; 5642 s->ofldqsets = 0; 5643 s->eoqsets = 0; 5644 uld_need = 0; 5645 ethofld_need = 0; 5646 } 5647 5648 num_vec = allocated; 5649 if (num_vec < want) { 5650 /* Distribute available vectors to the various queue groups. 5651 * Every group gets its minimum requirement and NIC gets top 5652 * priority for leftovers. 5653 */ 5654 ethqsets = eth_need; 5655 if (is_uld(adap)) 5656 ofldqsets = nchan; 5657 if (is_ethofld(adap)) 5658 eoqsets = ethofld_need; 5659 5660 num_vec -= need; 5661 while (num_vec) { 5662 if (num_vec < eth_need + ethofld_need || 5663 ethqsets > s->max_ethqsets) 5664 break; 5665 5666 for_each_port(adap, i) { 5667 pi = adap2pinfo(adap, i); 5668 if (pi->nqsets < 2) 5669 continue; 5670 5671 ethqsets++; 5672 num_vec--; 5673 if (ethofld_need) { 5674 eoqsets++; 5675 num_vec--; 5676 } 5677 } 5678 } 5679 5680 if (is_uld(adap)) { 5681 while (num_vec) { 5682 if (num_vec < uld_need || 5683 ofldqsets > s->ofldqsets) 5684 break; 5685 5686 ofldqsets++; 5687 num_vec -= uld_need; 5688 } 5689 } 5690 } else { 5691 ethqsets = s->max_ethqsets; 5692 if (is_uld(adap)) 5693 ofldqsets = s->ofldqsets; 5694 if (is_ethofld(adap)) 5695 eoqsets = s->eoqsets; 5696 } 5697 5698 if (ethqsets < s->max_ethqsets) { 5699 s->max_ethqsets = ethqsets; 5700 reduce_ethqs(adap, ethqsets); 5701 } 5702 5703 if (is_uld(adap)) { 5704 s->ofldqsets = ofldqsets; 5705 s->nqs_per_uld = s->ofldqsets; 5706 } 5707 5708 if (is_ethofld(adap)) 5709 s->eoqsets = eoqsets; 5710 5711 /* map for msix */ 5712 ret = alloc_msix_info(adap, allocated); 5713 if (ret) 5714 goto out_disable_msix; 5715 5716 for (i = 0; i < allocated; i++) { 5717 adap->msix_info[i].vec = entries[i].vector; 5718 adap->msix_info[i].idx = i; 5719 } 5720 5721 dev_info(adap->pdev_dev, 5722 "%d MSI-X vectors allocated, nic %d eoqsets %d per uld %d\n", 5723 allocated, s->max_ethqsets, s->eoqsets, s->nqs_per_uld); 5724 5725 kfree(entries); 5726 return 0; 5727 5728 out_disable_msix: 5729 pci_disable_msix(adap->pdev); 5730 5731 out_free: 5732 kfree(entries); 5733 return ret; 5734 } 5735 5736 #undef EXTRA_VECS 5737 5738 static int init_rss(struct adapter *adap) 5739 { 5740 unsigned int i; 5741 int err; 5742 5743 err = t4_init_rss_mode(adap, adap->mbox); 5744 if (err) 5745 return err; 5746 5747 for_each_port(adap, i) { 5748 struct port_info *pi = adap2pinfo(adap, i); 5749 5750 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 5751 if (!pi->rss) 5752 return -ENOMEM; 5753 } 5754 return 0; 5755 } 5756 5757 /* Dump basic information about the adapter */ 5758 static void print_adapter_info(struct adapter *adapter) 5759 { 5760 /* Hardware/Firmware/etc. Version/Revision IDs */ 5761 t4_dump_version_info(adapter); 5762 5763 /* Software/Hardware configuration */ 5764 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", 5765 is_offload(adapter) ? "R" : "", 5766 ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" : 5767 (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""), 5768 is_offload(adapter) ? "Offload" : "non-Offload"); 5769 } 5770 5771 static void print_port_info(const struct net_device *dev) 5772 { 5773 char buf[80]; 5774 char *bufp = buf; 5775 const struct port_info *pi = netdev_priv(dev); 5776 const struct adapter *adap = pi->adapter; 5777 5778 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 5779 bufp += sprintf(bufp, "100M/"); 5780 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 5781 bufp += sprintf(bufp, "1G/"); 5782 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 5783 bufp += sprintf(bufp, "10G/"); 5784 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 5785 bufp += sprintf(bufp, "25G/"); 5786 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 5787 bufp += sprintf(bufp, "40G/"); 5788 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 5789 bufp += sprintf(bufp, "50G/"); 5790 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 5791 bufp += sprintf(bufp, "100G/"); 5792 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G) 5793 bufp += sprintf(bufp, "200G/"); 5794 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G) 5795 bufp += sprintf(bufp, "400G/"); 5796 if (bufp != buf) 5797 --bufp; 5798 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); 5799 5800 netdev_info(dev, "%s: Chelsio %s (%s) %s\n", 5801 dev->name, adap->params.vpd.id, adap->name, buf); 5802 } 5803 5804 /* 5805 * Free the following resources: 5806 * - memory used for tables 5807 * - MSI/MSI-X 5808 * - net devices 5809 * - resources FW is holding for us 5810 */ 5811 static void free_some_resources(struct adapter *adapter) 5812 { 5813 unsigned int i; 5814 5815 kvfree(adapter->smt); 5816 kvfree(adapter->l2t); 5817 kvfree(adapter->srq); 5818 t4_cleanup_sched(adapter); 5819 kvfree(adapter->tids.tid_tab); 5820 cxgb4_cleanup_tc_matchall(adapter); 5821 cxgb4_cleanup_tc_mqprio(adapter); 5822 cxgb4_cleanup_tc_flower(adapter); 5823 cxgb4_cleanup_tc_u32(adapter); 5824 kfree(adapter->sge.egr_map); 5825 kfree(adapter->sge.ingr_map); 5826 kfree(adapter->sge.starving_fl); 5827 kfree(adapter->sge.txq_maperr); 5828 #ifdef CONFIG_DEBUG_FS 5829 kfree(adapter->sge.blocked_fl); 5830 #endif 5831 disable_msi(adapter); 5832 5833 for_each_port(adapter, i) 5834 if (adapter->port[i]) { 5835 struct port_info *pi = adap2pinfo(adapter, i); 5836 5837 if (pi->viid != 0) 5838 t4_free_vi(adapter, adapter->mbox, adapter->pf, 5839 0, pi->viid); 5840 kfree(adap2pinfo(adapter, i)->rss); 5841 free_netdev(adapter->port[i]); 5842 } 5843 if (adapter->flags & CXGB4_FW_OK) 5844 t4_fw_bye(adapter, adapter->pf); 5845 } 5846 5847 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN | \ 5848 NETIF_F_GSO_UDP_L4) 5849 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ 5850 NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) 5851 #define SEGMENT_SIZE 128 5852 5853 static int t4_get_chip_type(struct adapter *adap, int ver) 5854 { 5855 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A)); 5856 5857 switch (ver) { 5858 case CHELSIO_T4: 5859 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 5860 case CHELSIO_T5: 5861 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 5862 case CHELSIO_T6: 5863 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 5864 default: 5865 break; 5866 } 5867 return -EINVAL; 5868 } 5869 5870 #ifdef CONFIG_PCI_IOV 5871 static void cxgb4_mgmt_setup(struct net_device *dev) 5872 { 5873 dev->type = ARPHRD_NONE; 5874 dev->mtu = 0; 5875 dev->hard_header_len = 0; 5876 dev->addr_len = 0; 5877 dev->tx_queue_len = 0; 5878 dev->flags |= IFF_NOARP; 5879 dev->priv_flags |= IFF_NO_QUEUE; 5880 5881 /* Initialize the device structure. */ 5882 dev->netdev_ops = &cxgb4_mgmt_netdev_ops; 5883 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; 5884 } 5885 5886 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) 5887 { 5888 struct adapter *adap = pci_get_drvdata(pdev); 5889 int err = 0; 5890 int current_vfs = pci_num_vf(pdev); 5891 u32 pcie_fw; 5892 5893 pcie_fw = readl(adap->regs + PCIE_FW_A); 5894 /* Check if fw is initialized */ 5895 if (!(pcie_fw & PCIE_FW_INIT_F)) { 5896 dev_warn(&pdev->dev, "Device not initialized\n"); 5897 return -EOPNOTSUPP; 5898 } 5899 5900 /* If any of the VF's is already assigned to Guest OS, then 5901 * SRIOV for the same cannot be modified 5902 */ 5903 if (current_vfs && pci_vfs_assigned(pdev)) { 5904 dev_err(&pdev->dev, 5905 "Cannot modify SR-IOV while VFs are assigned\n"); 5906 return current_vfs; 5907 } 5908 /* Note that the upper-level code ensures that we're never called with 5909 * a non-zero "num_vfs" when we already have VFs instantiated. But 5910 * it never hurts to code defensively. 5911 */ 5912 if (num_vfs != 0 && current_vfs != 0) 5913 return -EBUSY; 5914 5915 /* Nothing to do for no change. */ 5916 if (num_vfs == current_vfs) 5917 return num_vfs; 5918 5919 /* Disable SRIOV when zero is passed. */ 5920 if (!num_vfs) { 5921 pci_disable_sriov(pdev); 5922 /* free VF Management Interface */ 5923 unregister_netdev(adap->port[0]); 5924 free_netdev(adap->port[0]); 5925 adap->port[0] = NULL; 5926 5927 /* free VF resources */ 5928 adap->num_vfs = 0; 5929 kfree(adap->vfinfo); 5930 adap->vfinfo = NULL; 5931 return 0; 5932 } 5933 5934 if (!current_vfs) { 5935 struct fw_pfvf_cmd port_cmd, port_rpl; 5936 struct net_device *netdev; 5937 unsigned int pmask, port; 5938 struct pci_dev *pbridge; 5939 struct port_info *pi; 5940 char name[IFNAMSIZ]; 5941 u32 devcap2; 5942 u16 flags; 5943 5944 /* If we want to instantiate Virtual Functions, then our 5945 * parent bridge's PCI-E needs to support Alternative Routing 5946 * ID (ARI) because our VFs will show up at function offset 8 5947 * and above. 5948 */ 5949 pbridge = pdev->bus->self; 5950 pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags); 5951 pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2); 5952 5953 if ((flags & PCI_EXP_FLAGS_VERS) < 2 || 5954 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) { 5955 /* Our parent bridge does not support ARI so issue a 5956 * warning and skip instantiating the VFs. They 5957 * won't be reachable. 5958 */ 5959 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n", 5960 pbridge->bus->number, PCI_SLOT(pbridge->devfn), 5961 PCI_FUNC(pbridge->devfn)); 5962 return -ENOTSUPP; 5963 } 5964 memset(&port_cmd, 0, sizeof(port_cmd)); 5965 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | 5966 FW_CMD_REQUEST_F | 5967 FW_CMD_READ_F | 5968 FW_PFVF_CMD_PFN_V(adap->pf) | 5969 FW_PFVF_CMD_VFN_V(0)); 5970 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd)); 5971 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd), 5972 &port_rpl); 5973 if (err) 5974 return err; 5975 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq)); 5976 port = ffs(pmask) - 1; 5977 /* Allocate VF Management Interface. */ 5978 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx, 5979 adap->pf); 5980 netdev = alloc_netdev(sizeof(struct port_info), 5981 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup); 5982 if (!netdev) 5983 return -ENOMEM; 5984 5985 pi = netdev_priv(netdev); 5986 pi->adapter = adap; 5987 pi->lport = port; 5988 pi->tx_chan = port; 5989 SET_NETDEV_DEV(netdev, &pdev->dev); 5990 5991 adap->port[0] = netdev; 5992 pi->port_id = 0; 5993 5994 err = register_netdev(adap->port[0]); 5995 if (err) { 5996 pr_info("Unable to register VF mgmt netdev %s\n", name); 5997 free_netdev(adap->port[0]); 5998 adap->port[0] = NULL; 5999 return err; 6000 } 6001 /* Allocate and set up VF Information. */ 6002 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev), 6003 sizeof(struct vf_info), GFP_KERNEL); 6004 if (!adap->vfinfo) { 6005 unregister_netdev(adap->port[0]); 6006 free_netdev(adap->port[0]); 6007 adap->port[0] = NULL; 6008 return -ENOMEM; 6009 } 6010 cxgb4_mgmt_fill_vf_station_mac_addr(adap); 6011 } 6012 /* Instantiate the requested number of VFs. */ 6013 err = pci_enable_sriov(pdev, num_vfs); 6014 if (err) { 6015 pr_info("Unable to instantiate %d VFs\n", num_vfs); 6016 if (!current_vfs) { 6017 unregister_netdev(adap->port[0]); 6018 free_netdev(adap->port[0]); 6019 adap->port[0] = NULL; 6020 kfree(adap->vfinfo); 6021 adap->vfinfo = NULL; 6022 } 6023 return err; 6024 } 6025 6026 adap->num_vfs = num_vfs; 6027 return num_vfs; 6028 } 6029 #endif /* CONFIG_PCI_IOV */ 6030 6031 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 6032 { 6033 struct net_device *netdev; 6034 struct adapter *adapter; 6035 static int adap_idx = 1; 6036 int s_qpp, qpp, num_seg; 6037 struct port_info *pi; 6038 bool highdma = false; 6039 enum chip_type chip; 6040 void __iomem *regs; 6041 int func, chip_ver; 6042 u16 device_id; 6043 int i, err; 6044 u32 whoami; 6045 6046 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); 6047 6048 err = pci_request_regions(pdev, KBUILD_MODNAME); 6049 if (err) { 6050 /* Just info, some other driver may have claimed the device. */ 6051 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 6052 return err; 6053 } 6054 6055 err = pci_enable_device(pdev); 6056 if (err) { 6057 dev_err(&pdev->dev, "cannot enable PCI device\n"); 6058 goto out_release_regions; 6059 } 6060 6061 regs = pci_ioremap_bar(pdev, 0); 6062 if (!regs) { 6063 dev_err(&pdev->dev, "cannot map device registers\n"); 6064 err = -ENOMEM; 6065 goto out_disable_device; 6066 } 6067 6068 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 6069 if (!adapter) { 6070 err = -ENOMEM; 6071 goto out_unmap_bar0; 6072 } 6073 6074 adapter->regs = regs; 6075 err = t4_wait_dev_ready(regs); 6076 if (err < 0) 6077 goto out_free_adapter; 6078 6079 /* We control everything through one PF */ 6080 whoami = t4_read_reg(adapter, PL_WHOAMI_A); 6081 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 6082 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id)); 6083 if ((int)chip < 0) { 6084 dev_err(&pdev->dev, "Device %d is not supported\n", device_id); 6085 err = chip; 6086 goto out_free_adapter; 6087 } 6088 chip_ver = CHELSIO_CHIP_VERSION(chip); 6089 func = chip_ver <= CHELSIO_T5 ? 6090 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 6091 6092 adapter->pdev = pdev; 6093 adapter->pdev_dev = &pdev->dev; 6094 adapter->name = pci_name(pdev); 6095 adapter->mbox = func; 6096 adapter->pf = func; 6097 adapter->params.chip = chip; 6098 adapter->adap_idx = adap_idx; 6099 adapter->msg_enable = DFLT_MSG_ENABLE; 6100 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + 6101 (sizeof(struct mbox_cmd) * 6102 T4_OS_LOG_MBOX_CMDS), 6103 GFP_KERNEL); 6104 if (!adapter->mbox_log) { 6105 err = -ENOMEM; 6106 goto out_free_adapter; 6107 } 6108 spin_lock_init(&adapter->mbox_lock); 6109 INIT_LIST_HEAD(&adapter->mlist.list); 6110 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; 6111 pci_set_drvdata(pdev, adapter); 6112 6113 if (func != ent->driver_data) { 6114 pci_disable_device(pdev); 6115 pci_save_state(pdev); /* to restore SR-IOV later */ 6116 return 0; 6117 } 6118 6119 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 6120 highdma = true; 6121 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 6122 if (err) { 6123 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 6124 "coherent allocations\n"); 6125 goto out_free_adapter; 6126 } 6127 } else { 6128 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 6129 if (err) { 6130 dev_err(&pdev->dev, "no usable DMA configuration\n"); 6131 goto out_free_adapter; 6132 } 6133 } 6134 6135 pci_enable_pcie_error_reporting(pdev); 6136 pci_set_master(pdev); 6137 pci_save_state(pdev); 6138 adap_idx++; 6139 adapter->workq = create_singlethread_workqueue("cxgb4"); 6140 if (!adapter->workq) { 6141 err = -ENOMEM; 6142 goto out_free_adapter; 6143 } 6144 6145 /* PCI device has been enabled */ 6146 adapter->flags |= CXGB4_DEV_ENABLED; 6147 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); 6148 6149 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver 6150 * Ingress Packet Data to Free List Buffers in order to allow for 6151 * chipset performance optimizations between the Root Complex and 6152 * Memory Controllers. (Messages to the associated Ingress Queue 6153 * notifying new Packet Placement in the Free Lists Buffers will be 6154 * send without the Relaxed Ordering Attribute thus guaranteeing that 6155 * all preceding PCIe Transaction Layer Packets will be processed 6156 * first.) But some Root Complexes have various issues with Upstream 6157 * Transaction Layer Packets with the Relaxed Ordering Attribute set. 6158 * The PCIe devices which under the Root Complexes will be cleared the 6159 * Relaxed Ordering bit in the configuration space, So we check our 6160 * PCIe configuration space to see if it's flagged with advice against 6161 * using Relaxed Ordering. 6162 */ 6163 if (!pcie_relaxed_ordering_enabled(pdev)) 6164 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING; 6165 6166 spin_lock_init(&adapter->stats_lock); 6167 spin_lock_init(&adapter->tid_release_lock); 6168 spin_lock_init(&adapter->win0_lock); 6169 6170 INIT_WORK(&adapter->tid_release_task, process_tid_release_list); 6171 INIT_WORK(&adapter->db_full_task, process_db_full); 6172 INIT_WORK(&adapter->db_drop_task, process_db_drop); 6173 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err); 6174 6175 err = t4_prep_adapter(adapter); 6176 if (err) 6177 goto out_free_adapter; 6178 6179 if (is_kdump_kernel()) { 6180 /* Collect hardware state and append to /proc/vmcore */ 6181 err = cxgb4_cudbg_vmcore_add_dump(adapter); 6182 if (err) { 6183 dev_warn(adapter->pdev_dev, 6184 "Fail collecting vmcore device dump, err: %d. Continuing\n", 6185 err); 6186 err = 0; 6187 } 6188 } 6189 6190 if (!is_t4(adapter->params.chip)) { 6191 s_qpp = (QUEUESPERPAGEPF0_S + 6192 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * 6193 adapter->pf); 6194 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, 6195 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); 6196 num_seg = PAGE_SIZE / SEGMENT_SIZE; 6197 6198 /* Each segment size is 128B. Write coalescing is enabled only 6199 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the 6200 * queue is less no of segments that can be accommodated in 6201 * a page size. 6202 */ 6203 if (qpp > num_seg) { 6204 dev_err(&pdev->dev, 6205 "Incorrect number of egress queues per page\n"); 6206 err = -EINVAL; 6207 goto out_free_adapter; 6208 } 6209 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), 6210 pci_resource_len(pdev, 2)); 6211 if (!adapter->bar2) { 6212 dev_err(&pdev->dev, "cannot map device bar2 region\n"); 6213 err = -ENOMEM; 6214 goto out_free_adapter; 6215 } 6216 } 6217 6218 setup_memwin(adapter); 6219 err = adap_init0(adapter, 0); 6220 #ifdef CONFIG_DEBUG_FS 6221 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); 6222 #endif 6223 setup_memwin_rdma(adapter); 6224 if (err) 6225 goto out_unmap_bar; 6226 6227 /* configure SGE_STAT_CFG_A to read WC stats */ 6228 if (!is_t4(adapter->params.chip)) 6229 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | 6230 (is_t5(adapter->params.chip) ? STATMODE_V(0) : 6231 T6_STATMODE_V(0))); 6232 6233 /* Initialize hash mac addr list */ 6234 INIT_LIST_HEAD(&adapter->mac_hlist); 6235 6236 for_each_port(adapter, i) { 6237 /* For supporting MQPRIO Offload, need some extra 6238 * queues for each ETHOFLD TIDs. Keep it equal to 6239 * MAX_ATIDs for now. Once we connect to firmware 6240 * later and query the EOTID params, we'll come to 6241 * know the actual # of EOTIDs supported. 6242 */ 6243 netdev = alloc_etherdev_mq(sizeof(struct port_info), 6244 MAX_ETH_QSETS + MAX_ATIDS); 6245 if (!netdev) { 6246 err = -ENOMEM; 6247 goto out_free_dev; 6248 } 6249 6250 SET_NETDEV_DEV(netdev, &pdev->dev); 6251 6252 adapter->port[i] = netdev; 6253 pi = netdev_priv(netdev); 6254 pi->adapter = adapter; 6255 pi->xact_addr_filt = -1; 6256 pi->port_id = i; 6257 netdev->irq = pdev->irq; 6258 6259 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | 6260 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6261 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO | 6262 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 6263 NETIF_F_HW_TC; 6264 6265 if (chip_ver > CHELSIO_T5) { 6266 netdev->hw_enc_features |= NETIF_F_IP_CSUM | 6267 NETIF_F_IPV6_CSUM | 6268 NETIF_F_RXCSUM | 6269 NETIF_F_GSO_UDP_TUNNEL | 6270 NETIF_F_GSO_UDP_TUNNEL_CSUM | 6271 NETIF_F_TSO | NETIF_F_TSO6; 6272 6273 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 6274 NETIF_F_GSO_UDP_TUNNEL_CSUM | 6275 NETIF_F_HW_TLS_RECORD; 6276 } 6277 6278 if (highdma) 6279 netdev->hw_features |= NETIF_F_HIGHDMA; 6280 netdev->features |= netdev->hw_features; 6281 netdev->vlan_features = netdev->features & VLAN_FEAT; 6282 6283 netdev->priv_flags |= IFF_UNICAST_FLT; 6284 6285 /* MTU range: 81 - 9600 */ 6286 netdev->min_mtu = 81; /* accommodate SACK */ 6287 netdev->max_mtu = MAX_MTU; 6288 6289 netdev->netdev_ops = &cxgb4_netdev_ops; 6290 #ifdef CONFIG_CHELSIO_T4_DCB 6291 netdev->dcbnl_ops = &cxgb4_dcb_ops; 6292 cxgb4_dcb_state_init(netdev); 6293 cxgb4_dcb_version_init(netdev); 6294 #endif 6295 cxgb4_set_ethtool_ops(netdev); 6296 } 6297 6298 cxgb4_init_ethtool_dump(adapter); 6299 6300 pci_set_drvdata(pdev, adapter); 6301 6302 if (adapter->flags & CXGB4_FW_OK) { 6303 err = t4_port_init(adapter, func, func, 0); 6304 if (err) 6305 goto out_free_dev; 6306 } else if (adapter->params.nports == 1) { 6307 /* If we don't have a connection to the firmware -- possibly 6308 * because of an error -- grab the raw VPD parameters so we 6309 * can set the proper MAC Address on the debug network 6310 * interface that we've created. 6311 */ 6312 u8 hw_addr[ETH_ALEN]; 6313 u8 *na = adapter->params.vpd.na; 6314 6315 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); 6316 if (!err) { 6317 for (i = 0; i < ETH_ALEN; i++) 6318 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 6319 hex2val(na[2 * i + 1])); 6320 t4_set_hw_addr(adapter, 0, hw_addr); 6321 } 6322 } 6323 6324 if (!(adapter->flags & CXGB4_FW_OK)) 6325 goto fw_attach_fail; 6326 6327 /* Configure queues and allocate tables now, they can be needed as 6328 * soon as the first register_netdev completes. 6329 */ 6330 err = cfg_queues(adapter); 6331 if (err) 6332 goto out_free_dev; 6333 6334 adapter->smt = t4_init_smt(); 6335 if (!adapter->smt) { 6336 /* We tolerate a lack of SMT, giving up some functionality */ 6337 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n"); 6338 } 6339 6340 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 6341 if (!adapter->l2t) { 6342 /* We tolerate a lack of L2T, giving up some functionality */ 6343 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); 6344 adapter->params.offload = 0; 6345 } 6346 6347 #if IS_ENABLED(CONFIG_IPV6) 6348 if (chip_ver <= CHELSIO_T5 && 6349 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { 6350 /* CLIP functionality is not present in hardware, 6351 * hence disable all offload features 6352 */ 6353 dev_warn(&pdev->dev, 6354 "CLIP not enabled in hardware, continuing\n"); 6355 adapter->params.offload = 0; 6356 } else { 6357 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 6358 adapter->clipt_end); 6359 if (!adapter->clipt) { 6360 /* We tolerate a lack of clip_table, giving up 6361 * some functionality 6362 */ 6363 dev_warn(&pdev->dev, 6364 "could not allocate Clip table, continuing\n"); 6365 adapter->params.offload = 0; 6366 } 6367 } 6368 #endif 6369 6370 for_each_port(adapter, i) { 6371 pi = adap2pinfo(adapter, i); 6372 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); 6373 if (!pi->sched_tbl) 6374 dev_warn(&pdev->dev, 6375 "could not activate scheduling on port %d\n", 6376 i); 6377 } 6378 6379 if (tid_init(&adapter->tids) < 0) { 6380 dev_warn(&pdev->dev, "could not allocate TID table, " 6381 "continuing\n"); 6382 adapter->params.offload = 0; 6383 } else { 6384 adapter->tc_u32 = cxgb4_init_tc_u32(adapter); 6385 if (!adapter->tc_u32) 6386 dev_warn(&pdev->dev, 6387 "could not offload tc u32, continuing\n"); 6388 6389 if (cxgb4_init_tc_flower(adapter)) 6390 dev_warn(&pdev->dev, 6391 "could not offload tc flower, continuing\n"); 6392 6393 if (cxgb4_init_tc_mqprio(adapter)) 6394 dev_warn(&pdev->dev, 6395 "could not offload tc mqprio, continuing\n"); 6396 6397 if (cxgb4_init_tc_matchall(adapter)) 6398 dev_warn(&pdev->dev, 6399 "could not offload tc matchall, continuing\n"); 6400 } 6401 6402 if (is_offload(adapter) || is_hashfilter(adapter)) { 6403 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { 6404 u32 hash_base, hash_reg; 6405 6406 if (chip_ver <= CHELSIO_T5) { 6407 hash_reg = LE_DB_TID_HASHBASE_A; 6408 hash_base = t4_read_reg(adapter, hash_reg); 6409 adapter->tids.hash_base = hash_base / 4; 6410 } else { 6411 hash_reg = T6_LE_DB_HASH_TID_BASE_A; 6412 hash_base = t4_read_reg(adapter, hash_reg); 6413 adapter->tids.hash_base = hash_base; 6414 } 6415 } 6416 } 6417 6418 /* See what interrupts we'll be using */ 6419 if (msi > 1 && enable_msix(adapter) == 0) 6420 adapter->flags |= CXGB4_USING_MSIX; 6421 else if (msi > 0 && pci_enable_msi(pdev) == 0) { 6422 adapter->flags |= CXGB4_USING_MSI; 6423 if (msi > 1) 6424 free_msix_info(adapter); 6425 } 6426 6427 /* check for PCI Express bandwidth capabiltites */ 6428 pcie_print_link_status(pdev); 6429 6430 cxgb4_init_mps_ref_entries(adapter); 6431 6432 err = init_rss(adapter); 6433 if (err) 6434 goto out_free_dev; 6435 6436 err = setup_non_data_intr(adapter); 6437 if (err) { 6438 dev_err(adapter->pdev_dev, 6439 "Non Data interrupt allocation failed, err: %d\n", err); 6440 goto out_free_dev; 6441 } 6442 6443 err = setup_fw_sge_queues(adapter); 6444 if (err) { 6445 dev_err(adapter->pdev_dev, 6446 "FW sge queue allocation failed, err %d", err); 6447 goto out_free_dev; 6448 } 6449 6450 fw_attach_fail: 6451 /* 6452 * The card is now ready to go. If any errors occur during device 6453 * registration we do not fail the whole card but rather proceed only 6454 * with the ports we manage to register successfully. However we must 6455 * register at least one net device. 6456 */ 6457 for_each_port(adapter, i) { 6458 pi = adap2pinfo(adapter, i); 6459 adapter->port[i]->dev_port = pi->lport; 6460 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); 6461 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); 6462 6463 netif_carrier_off(adapter->port[i]); 6464 6465 err = register_netdev(adapter->port[i]); 6466 if (err) 6467 break; 6468 adapter->chan_map[pi->tx_chan] = i; 6469 print_port_info(adapter->port[i]); 6470 } 6471 if (i == 0) { 6472 dev_err(&pdev->dev, "could not register any net devices\n"); 6473 goto out_free_dev; 6474 } 6475 if (err) { 6476 dev_warn(&pdev->dev, "only %d net devices registered\n", i); 6477 err = 0; 6478 } 6479 6480 if (cxgb4_debugfs_root) { 6481 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), 6482 cxgb4_debugfs_root); 6483 setup_debugfs(adapter); 6484 } 6485 6486 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ 6487 pdev->needs_freset = 1; 6488 6489 if (is_uld(adapter)) { 6490 mutex_lock(&uld_mutex); 6491 list_add_tail(&adapter->list_node, &adapter_list); 6492 mutex_unlock(&uld_mutex); 6493 } 6494 6495 if (!is_t4(adapter->params.chip)) 6496 cxgb4_ptp_init(adapter); 6497 6498 if (IS_REACHABLE(CONFIG_THERMAL) && 6499 !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK)) 6500 cxgb4_thermal_init(adapter); 6501 6502 print_adapter_info(adapter); 6503 return 0; 6504 6505 out_free_dev: 6506 t4_free_sge_resources(adapter); 6507 free_some_resources(adapter); 6508 if (adapter->flags & CXGB4_USING_MSIX) 6509 free_msix_info(adapter); 6510 if (adapter->num_uld || adapter->num_ofld_uld) 6511 t4_uld_mem_free(adapter); 6512 out_unmap_bar: 6513 if (!is_t4(adapter->params.chip)) 6514 iounmap(adapter->bar2); 6515 out_free_adapter: 6516 if (adapter->workq) 6517 destroy_workqueue(adapter->workq); 6518 6519 kfree(adapter->mbox_log); 6520 kfree(adapter); 6521 out_unmap_bar0: 6522 iounmap(regs); 6523 out_disable_device: 6524 pci_disable_pcie_error_reporting(pdev); 6525 pci_disable_device(pdev); 6526 out_release_regions: 6527 pci_release_regions(pdev); 6528 return err; 6529 } 6530 6531 static void remove_one(struct pci_dev *pdev) 6532 { 6533 struct adapter *adapter = pci_get_drvdata(pdev); 6534 struct hash_mac_addr *entry, *tmp; 6535 6536 if (!adapter) { 6537 pci_release_regions(pdev); 6538 return; 6539 } 6540 6541 /* If we allocated filters, free up state associated with any 6542 * valid filters ... 6543 */ 6544 clear_all_filters(adapter); 6545 6546 adapter->flags |= CXGB4_SHUTTING_DOWN; 6547 6548 if (adapter->pf == 4) { 6549 int i; 6550 6551 /* Tear down per-adapter Work Queue first since it can contain 6552 * references to our adapter data structure. 6553 */ 6554 destroy_workqueue(adapter->workq); 6555 6556 if (is_uld(adapter)) { 6557 detach_ulds(adapter); 6558 t4_uld_clean_up(adapter); 6559 } 6560 6561 adap_free_hma_mem(adapter); 6562 6563 disable_interrupts(adapter); 6564 6565 cxgb4_free_mps_ref_entries(adapter); 6566 6567 for_each_port(adapter, i) 6568 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 6569 unregister_netdev(adapter->port[i]); 6570 6571 debugfs_remove_recursive(adapter->debugfs_root); 6572 6573 if (!is_t4(adapter->params.chip)) 6574 cxgb4_ptp_stop(adapter); 6575 if (IS_REACHABLE(CONFIG_THERMAL)) 6576 cxgb4_thermal_remove(adapter); 6577 6578 if (adapter->flags & CXGB4_FULL_INIT_DONE) 6579 cxgb_down(adapter); 6580 6581 if (adapter->flags & CXGB4_USING_MSIX) 6582 free_msix_info(adapter); 6583 if (adapter->num_uld || adapter->num_ofld_uld) 6584 t4_uld_mem_free(adapter); 6585 free_some_resources(adapter); 6586 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist, 6587 list) { 6588 list_del(&entry->list); 6589 kfree(entry); 6590 } 6591 6592 #if IS_ENABLED(CONFIG_IPV6) 6593 t4_cleanup_clip_tbl(adapter); 6594 #endif 6595 if (!is_t4(adapter->params.chip)) 6596 iounmap(adapter->bar2); 6597 } 6598 #ifdef CONFIG_PCI_IOV 6599 else { 6600 cxgb4_iov_configure(adapter->pdev, 0); 6601 } 6602 #endif 6603 iounmap(adapter->regs); 6604 pci_disable_pcie_error_reporting(pdev); 6605 if ((adapter->flags & CXGB4_DEV_ENABLED)) { 6606 pci_disable_device(pdev); 6607 adapter->flags &= ~CXGB4_DEV_ENABLED; 6608 } 6609 pci_release_regions(pdev); 6610 kfree(adapter->mbox_log); 6611 synchronize_rcu(); 6612 kfree(adapter); 6613 } 6614 6615 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt 6616 * delivery. This is essentially a stripped down version of the PCI remove() 6617 * function where we do the minimal amount of work necessary to shutdown any 6618 * further activity. 6619 */ 6620 static void shutdown_one(struct pci_dev *pdev) 6621 { 6622 struct adapter *adapter = pci_get_drvdata(pdev); 6623 6624 /* As with remove_one() above (see extended comment), we only want do 6625 * do cleanup on PCI Devices which went all the way through init_one() 6626 * ... 6627 */ 6628 if (!adapter) { 6629 pci_release_regions(pdev); 6630 return; 6631 } 6632 6633 adapter->flags |= CXGB4_SHUTTING_DOWN; 6634 6635 if (adapter->pf == 4) { 6636 int i; 6637 6638 for_each_port(adapter, i) 6639 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 6640 cxgb_close(adapter->port[i]); 6641 6642 if (is_uld(adapter)) { 6643 detach_ulds(adapter); 6644 t4_uld_clean_up(adapter); 6645 } 6646 6647 disable_interrupts(adapter); 6648 disable_msi(adapter); 6649 6650 t4_sge_stop(adapter); 6651 if (adapter->flags & CXGB4_FW_OK) 6652 t4_fw_bye(adapter, adapter->mbox); 6653 } 6654 } 6655 6656 static struct pci_driver cxgb4_driver = { 6657 .name = KBUILD_MODNAME, 6658 .id_table = cxgb4_pci_tbl, 6659 .probe = init_one, 6660 .remove = remove_one, 6661 .shutdown = shutdown_one, 6662 #ifdef CONFIG_PCI_IOV 6663 .sriov_configure = cxgb4_iov_configure, 6664 #endif 6665 .err_handler = &cxgb4_eeh, 6666 }; 6667 6668 static int __init cxgb4_init_module(void) 6669 { 6670 int ret; 6671 6672 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); 6673 6674 ret = pci_register_driver(&cxgb4_driver); 6675 if (ret < 0) 6676 goto err_pci; 6677 6678 #if IS_ENABLED(CONFIG_IPV6) 6679 if (!inet6addr_registered) { 6680 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier); 6681 if (ret) 6682 pci_unregister_driver(&cxgb4_driver); 6683 else 6684 inet6addr_registered = true; 6685 } 6686 #endif 6687 6688 if (ret == 0) 6689 return ret; 6690 6691 err_pci: 6692 debugfs_remove(cxgb4_debugfs_root); 6693 6694 return ret; 6695 } 6696 6697 static void __exit cxgb4_cleanup_module(void) 6698 { 6699 #if IS_ENABLED(CONFIG_IPV6) 6700 if (inet6addr_registered) { 6701 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); 6702 inet6addr_registered = false; 6703 } 6704 #endif 6705 pci_unregister_driver(&cxgb4_driver); 6706 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ 6707 } 6708 6709 module_init(cxgb4_init_module); 6710 module_exit(cxgb4_cleanup_module); 6711