1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2021 Broadcom Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #include <linux/kernel.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/timekeeping.h> 16 #include <linux/ptp_classify.h> 17 #include "bnxt_hsi.h" 18 #include "bnxt.h" 19 #include "bnxt_hwrm.h" 20 #include "bnxt_ptp.h" 21 22 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time) 23 { 24 struct hwrm_func_ptp_cfg_input *req; 25 int rc; 26 27 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 28 if (rc) 29 return rc; 30 31 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME); 32 req->ptp_set_time = cpu_to_le64(time); 33 return hwrm_req_send(bp, req); 34 } 35 36 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) 37 { 38 unsigned int ptp_class; 39 struct ptp_header *hdr; 40 41 ptp_class = ptp_classify_raw(skb); 42 43 switch (ptp_class & PTP_CLASS_VMASK) { 44 case PTP_CLASS_V1: 45 case PTP_CLASS_V2: 46 hdr = ptp_parse_header(skb, ptp_class); 47 if (!hdr) 48 return -EINVAL; 49 50 *hdr_off = (u8 *)hdr - skb->data; 51 *seq_id = ntohs(hdr->sequence_id); 52 return 0; 53 default: 54 return -ERANGE; 55 } 56 } 57 58 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, 59 const struct timespec64 *ts) 60 { 61 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 62 ptp_info); 63 u64 ns = timespec64_to_ns(ts); 64 65 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC) 66 return bnxt_ptp_cfg_settime(ptp->bp, ns); 67 68 spin_lock_bh(&ptp->ptp_lock); 69 timecounter_init(&ptp->tc, &ptp->cc, ns); 70 spin_unlock_bh(&ptp->ptp_lock); 71 return 0; 72 } 73 74 /* Caller holds ptp_lock */ 75 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 76 u64 *ns) 77 { 78 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 79 u32 high_before, high_now, low; 80 81 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 82 return -EIO; 83 84 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 85 ptp_read_system_prets(sts); 86 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 87 ptp_read_system_postts(sts); 88 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 89 if (high_now != high_before) { 90 ptp_read_system_prets(sts); 91 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 92 ptp_read_system_postts(sts); 93 } 94 *ns = ((u64)high_now << 32) | low; 95 96 return 0; 97 } 98 99 static void bnxt_ptp_get_current_time(struct bnxt *bp) 100 { 101 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 102 103 if (!ptp) 104 return; 105 spin_lock_bh(&ptp->ptp_lock); 106 WRITE_ONCE(ptp->old_time, ptp->current_time); 107 bnxt_refclk_read(bp, NULL, &ptp->current_time); 108 spin_unlock_bh(&ptp->ptp_lock); 109 } 110 111 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts) 112 { 113 struct hwrm_port_ts_query_output *resp; 114 struct hwrm_port_ts_query_input *req; 115 int rc; 116 117 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY); 118 if (rc) 119 return rc; 120 121 req->flags = cpu_to_le32(flags); 122 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == 123 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { 124 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); 125 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid); 126 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off); 127 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT); 128 } 129 resp = hwrm_req_hold(bp, req); 130 131 rc = hwrm_req_send(bp, req); 132 if (!rc) 133 *ts = le64_to_cpu(resp->ptp_msg_ts); 134 hwrm_req_drop(bp, req); 135 return rc; 136 } 137 138 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, 139 struct timespec64 *ts, 140 struct ptp_system_timestamp *sts) 141 { 142 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 143 ptp_info); 144 u64 ns, cycles; 145 int rc; 146 147 spin_lock_bh(&ptp->ptp_lock); 148 rc = bnxt_refclk_read(ptp->bp, sts, &cycles); 149 if (rc) { 150 spin_unlock_bh(&ptp->ptp_lock); 151 return rc; 152 } 153 ns = timecounter_cyc2time(&ptp->tc, cycles); 154 spin_unlock_bh(&ptp->ptp_lock); 155 *ts = ns_to_timespec64(ns); 156 157 return 0; 158 } 159 160 /* Caller holds ptp_lock */ 161 void bnxt_ptp_update_current_time(struct bnxt *bp) 162 { 163 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 164 165 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time); 166 WRITE_ONCE(ptp->old_time, ptp->current_time); 167 } 168 169 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta) 170 { 171 struct hwrm_port_mac_cfg_input *req; 172 int rc; 173 174 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG); 175 if (rc) 176 return rc; 177 178 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE); 179 req->ptp_adj_phase = cpu_to_le64(delta); 180 181 rc = hwrm_req_send(ptp->bp, req); 182 if (rc) { 183 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc); 184 } else { 185 spin_lock_bh(&ptp->ptp_lock); 186 bnxt_ptp_update_current_time(ptp->bp); 187 spin_unlock_bh(&ptp->ptp_lock); 188 } 189 190 return rc; 191 } 192 193 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) 194 { 195 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 196 ptp_info); 197 198 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC) 199 return bnxt_ptp_adjphc(ptp, delta); 200 201 spin_lock_bh(&ptp->ptp_lock); 202 timecounter_adjtime(&ptp->tc, delta); 203 spin_unlock_bh(&ptp->ptp_lock); 204 return 0; 205 } 206 207 static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb) 208 { 209 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 210 ptp_info); 211 struct hwrm_port_mac_cfg_input *req; 212 struct bnxt *bp = ptp->bp; 213 int rc; 214 215 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 216 if (rc) 217 return rc; 218 219 req->ptp_freq_adj_ppb = cpu_to_le32(ppb); 220 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); 221 rc = hwrm_req_send(ptp->bp, req); 222 if (rc) 223 netdev_err(ptp->bp->dev, 224 "ptp adjfreq failed. rc = %d\n", rc); 225 return rc; 226 } 227 228 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) 229 { 230 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 231 struct ptp_clock_event event; 232 u64 ns, pps_ts; 233 234 pps_ts = EVENT_PPS_TS(data2, data1); 235 spin_lock_bh(&ptp->ptp_lock); 236 ns = timecounter_cyc2time(&ptp->tc, pps_ts); 237 spin_unlock_bh(&ptp->ptp_lock); 238 239 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { 240 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: 241 event.pps_times.ts_real = ns_to_timespec64(ns); 242 event.type = PTP_CLOCK_PPSUSR; 243 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 244 break; 245 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: 246 event.timestamp = ns; 247 event.type = PTP_CLOCK_EXTTS; 248 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 249 break; 250 } 251 252 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); 253 } 254 255 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) 256 { 257 struct hwrm_func_ptp_pin_cfg_input *req; 258 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 259 u8 state = usage != BNXT_PPS_PIN_NONE; 260 u8 *pin_state, *pin_usg; 261 u32 enables; 262 int rc; 263 264 if (!TSIO_PIN_VALID(pin)) { 265 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); 266 return -EOPNOTSUPP; 267 } 268 269 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG); 270 if (rc) 271 return rc; 272 273 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | 274 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); 275 req->enables = cpu_to_le32(enables); 276 277 pin_state = &req->pin0_state; 278 pin_usg = &req->pin0_usage; 279 280 *(pin_state + (pin * 2)) = state; 281 *(pin_usg + (pin * 2)) = usage; 282 283 rc = hwrm_req_send(ptp->bp, req); 284 if (rc) 285 return rc; 286 287 ptp->pps_info.pins[pin].usage = usage; 288 ptp->pps_info.pins[pin].state = state; 289 290 return 0; 291 } 292 293 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) 294 { 295 struct hwrm_func_ptp_cfg_input *req; 296 int rc; 297 298 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 299 if (rc) 300 return rc; 301 302 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); 303 req->ptp_pps_event = event; 304 return hwrm_req_send(bp, req); 305 } 306 307 void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp) 308 { 309 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 310 struct hwrm_port_mac_cfg_input *req; 311 312 if (!ptp || !ptp->tstamp_filters) 313 return; 314 315 if (hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG)) 316 goto out; 317 318 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters & 319 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 320 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) { 321 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 322 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE); 323 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n"); 324 } 325 326 req->flags = cpu_to_le32(ptp->tstamp_filters); 327 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); 328 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); 329 330 if (!hwrm_req_send(bp, req)) { 331 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters & 332 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE); 333 return; 334 } 335 ptp->tstamp_filters = 0; 336 out: 337 bp->ptp_all_rx_tstamp = 0; 338 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n"); 339 } 340 341 void bnxt_ptp_reapply_pps(struct bnxt *bp) 342 { 343 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 344 struct bnxt_pps *pps; 345 u32 pin = 0; 346 int rc; 347 348 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || 349 !(ptp->ptp_info.pin_config)) 350 return; 351 pps = &ptp->pps_info; 352 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { 353 if (pps->pins[pin].state) { 354 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); 355 if (!rc && pps->pins[pin].event) 356 rc = bnxt_ptp_cfg_event(bp, 357 pps->pins[pin].event); 358 if (rc) 359 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", 360 pin); 361 } 362 } 363 } 364 365 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns, 366 u64 *cycles_delta) 367 { 368 u64 cycles_now; 369 u64 nsec_now, nsec_delta; 370 int rc; 371 372 spin_lock_bh(&ptp->ptp_lock); 373 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now); 374 if (rc) { 375 spin_unlock_bh(&ptp->ptp_lock); 376 return rc; 377 } 378 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now); 379 spin_unlock_bh(&ptp->ptp_lock); 380 381 nsec_delta = target_ns - nsec_now; 382 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult); 383 return 0; 384 } 385 386 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, 387 struct ptp_clock_request *rq) 388 { 389 struct hwrm_func_ptp_cfg_input *req; 390 struct bnxt *bp = ptp->bp; 391 struct timespec64 ts; 392 u64 target_ns, delta; 393 u16 enables; 394 int rc; 395 396 ts.tv_sec = rq->perout.start.sec; 397 ts.tv_nsec = rq->perout.start.nsec; 398 target_ns = timespec64_to_ns(&ts); 399 400 rc = bnxt_get_target_cycles(ptp, target_ns, &delta); 401 if (rc) 402 return rc; 403 404 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 405 if (rc) 406 return rc; 407 408 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | 409 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | 410 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; 411 req->enables = cpu_to_le16(enables); 412 req->ptp_pps_event = 0; 413 req->ptp_freq_adj_dll_source = 0; 414 req->ptp_freq_adj_dll_phase = 0; 415 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); 416 req->ptp_freq_adj_ext_up = 0; 417 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta); 418 419 return hwrm_req_send(bp, req); 420 } 421 422 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, 423 struct ptp_clock_request *rq, int on) 424 { 425 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 426 ptp_info); 427 struct bnxt *bp = ptp->bp; 428 int pin_id; 429 int rc; 430 431 switch (rq->type) { 432 case PTP_CLK_REQ_EXTTS: 433 /* Configure an External PPS IN */ 434 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, 435 rq->extts.index); 436 if (!TSIO_PIN_VALID(pin_id)) 437 return -EOPNOTSUPP; 438 if (!on) 439 break; 440 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 441 if (rc) 442 return rc; 443 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); 444 if (!rc) 445 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; 446 return rc; 447 case PTP_CLK_REQ_PEROUT: 448 /* Configure a Periodic PPS OUT */ 449 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, 450 rq->perout.index); 451 if (!TSIO_PIN_VALID(pin_id)) 452 return -EOPNOTSUPP; 453 if (!on) 454 break; 455 456 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); 457 if (!rc) 458 rc = bnxt_ptp_perout_cfg(ptp, rq); 459 460 return rc; 461 case PTP_CLK_REQ_PPS: 462 /* Configure PHC PPS IN */ 463 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN); 464 if (rc) 465 return rc; 466 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); 467 if (!rc) 468 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL; 469 return rc; 470 default: 471 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); 472 return -EOPNOTSUPP; 473 } 474 475 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); 476 } 477 478 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) 479 { 480 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 481 u32 flags = 0; 482 int rc = 0; 483 484 switch (ptp->rx_filter) { 485 case HWTSTAMP_FILTER_ALL: 486 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE; 487 break; 488 case HWTSTAMP_FILTER_NONE: 489 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; 490 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 491 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE; 492 break; 493 case HWTSTAMP_FILTER_PTP_V2_EVENT: 494 case HWTSTAMP_FILTER_PTP_V2_SYNC: 495 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 496 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; 497 break; 498 } 499 500 if (ptp->tx_tstamp_en) 501 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; 502 else 503 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; 504 505 ptp->tstamp_filters = flags; 506 507 if (netif_running(bp->dev)) { 508 if (ptp->rx_filter == HWTSTAMP_FILTER_ALL) { 509 rc = bnxt_close_nic(bp, false, false); 510 if (!rc) 511 rc = bnxt_open_nic(bp, false, false); 512 } else { 513 bnxt_ptp_cfg_tstamp_filters(bp); 514 } 515 if (!rc && !ptp->tstamp_filters) 516 rc = -EIO; 517 } 518 519 return rc; 520 } 521 522 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 523 { 524 struct bnxt *bp = netdev_priv(dev); 525 struct hwtstamp_config stmpconf; 526 struct bnxt_ptp_cfg *ptp; 527 u16 old_rxctl; 528 int old_rx_filter, rc; 529 u8 old_tx_tstamp_en; 530 531 ptp = bp->ptp_cfg; 532 if (!ptp) 533 return -EOPNOTSUPP; 534 535 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) 536 return -EFAULT; 537 538 if (stmpconf.tx_type != HWTSTAMP_TX_ON && 539 stmpconf.tx_type != HWTSTAMP_TX_OFF) 540 return -ERANGE; 541 542 old_rx_filter = ptp->rx_filter; 543 old_rxctl = ptp->rxctl; 544 old_tx_tstamp_en = ptp->tx_tstamp_en; 545 switch (stmpconf.rx_filter) { 546 case HWTSTAMP_FILTER_NONE: 547 ptp->rxctl = 0; 548 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 549 break; 550 case HWTSTAMP_FILTER_ALL: 551 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) { 552 ptp->rx_filter = HWTSTAMP_FILTER_ALL; 553 break; 554 } 555 return -EOPNOTSUPP; 556 case HWTSTAMP_FILTER_PTP_V2_EVENT: 557 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 558 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 559 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 560 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 561 break; 562 case HWTSTAMP_FILTER_PTP_V2_SYNC: 563 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 564 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 565 ptp->rxctl = BNXT_PTP_MSG_SYNC; 566 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 567 break; 568 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 569 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 570 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 571 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; 572 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 573 break; 574 default: 575 return -ERANGE; 576 } 577 578 if (stmpconf.tx_type == HWTSTAMP_TX_ON) 579 ptp->tx_tstamp_en = 1; 580 else 581 ptp->tx_tstamp_en = 0; 582 583 rc = bnxt_hwrm_ptp_cfg(bp); 584 if (rc) 585 goto ts_set_err; 586 587 stmpconf.rx_filter = ptp->rx_filter; 588 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 589 -EFAULT : 0; 590 591 ts_set_err: 592 ptp->rx_filter = old_rx_filter; 593 ptp->rxctl = old_rxctl; 594 ptp->tx_tstamp_en = old_tx_tstamp_en; 595 return rc; 596 } 597 598 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 599 { 600 struct bnxt *bp = netdev_priv(dev); 601 struct hwtstamp_config stmpconf; 602 struct bnxt_ptp_cfg *ptp; 603 604 ptp = bp->ptp_cfg; 605 if (!ptp) 606 return -EOPNOTSUPP; 607 608 stmpconf.flags = 0; 609 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 610 611 stmpconf.rx_filter = ptp->rx_filter; 612 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 613 -EFAULT : 0; 614 } 615 616 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) 617 { 618 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; 619 u32 win_off; 620 int i; 621 622 for (i = 0; i < count; i++) { 623 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) 624 return -ERANGE; 625 } 626 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 627 writel(reg_base, bp->bar0 + win_off); 628 return 0; 629 } 630 631 static int bnxt_map_ptp_regs(struct bnxt *bp) 632 { 633 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 634 u32 *reg_arr; 635 int rc, i; 636 637 reg_arr = ptp->refclk_regs; 638 if (bp->flags & BNXT_FLAG_CHIP_P5) { 639 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); 640 if (rc) 641 return rc; 642 for (i = 0; i < 2; i++) 643 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + 644 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); 645 return 0; 646 } 647 return -ENODEV; 648 } 649 650 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 651 { 652 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 653 (BNXT_PTP_GRC_WIN - 1) * 4); 654 } 655 656 static u64 bnxt_cc_read(const struct cyclecounter *cc) 657 { 658 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); 659 u64 ns = 0; 660 661 bnxt_refclk_read(ptp->bp, NULL, &ns); 662 return ns; 663 } 664 665 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb) 666 { 667 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 668 struct skb_shared_hwtstamps timestamp; 669 u64 ts = 0, ns = 0; 670 int rc; 671 672 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts); 673 if (!rc) { 674 memset(×tamp, 0, sizeof(timestamp)); 675 spin_lock_bh(&ptp->ptp_lock); 676 ns = timecounter_cyc2time(&ptp->tc, ts); 677 spin_unlock_bh(&ptp->ptp_lock); 678 timestamp.hwtstamp = ns_to_ktime(ns); 679 skb_tstamp_tx(ptp->tx_skb, ×tamp); 680 } else { 681 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n", 682 rc); 683 } 684 685 dev_kfree_skb_any(ptp->tx_skb); 686 ptp->tx_skb = NULL; 687 atomic_inc(&ptp->tx_avail); 688 } 689 690 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) 691 { 692 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 693 ptp_info); 694 unsigned long now = jiffies; 695 struct bnxt *bp = ptp->bp; 696 697 if (ptp->tx_skb) 698 bnxt_stamp_tx_skb(bp, ptp->tx_skb); 699 700 if (!time_after_eq(now, ptp->next_period)) 701 return ptp->next_period - now; 702 703 bnxt_ptp_get_current_time(bp); 704 ptp->next_period = now + HZ; 705 if (time_after_eq(now, ptp->next_overflow_check)) { 706 spin_lock_bh(&ptp->ptp_lock); 707 timecounter_read(&ptp->tc); 708 spin_unlock_bh(&ptp->ptp_lock); 709 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; 710 } 711 return HZ; 712 } 713 714 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb) 715 { 716 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 717 718 if (ptp->tx_skb) { 719 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n"); 720 return -EBUSY; 721 } 722 ptp->tx_skb = skb; 723 ptp_schedule_worker(ptp->ptp_clock, 0); 724 return 0; 725 } 726 727 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) 728 { 729 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 730 u64 time; 731 732 if (!ptp) 733 return -ENODEV; 734 735 BNXT_READ_TIME64(ptp, time, ptp->old_time); 736 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts; 737 if (pkt_ts < (time & BNXT_LO_TIMER_MASK)) 738 *ts += BNXT_LO_TIMER_MASK + 1; 739 740 return 0; 741 } 742 743 static const struct ptp_clock_info bnxt_ptp_caps = { 744 .owner = THIS_MODULE, 745 .name = "bnxt clock", 746 .max_adj = BNXT_MAX_PHC_DRIFT, 747 .n_alarm = 0, 748 .n_ext_ts = 0, 749 .n_per_out = 0, 750 .n_pins = 0, 751 .pps = 0, 752 .adjfreq = bnxt_ptp_adjfreq, 753 .adjtime = bnxt_ptp_adjtime, 754 .do_aux_work = bnxt_ptp_ts_aux_work, 755 .gettimex64 = bnxt_ptp_gettimex, 756 .settime64 = bnxt_ptp_settime, 757 .enable = bnxt_ptp_enable, 758 }; 759 760 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, 761 enum ptp_pin_function func, unsigned int chan) 762 { 763 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 764 ptp_info); 765 /* Allow only PPS pin function configuration */ 766 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && 767 func != PTP_PF_PHYSYNC) 768 return 0; 769 else 770 return -EOPNOTSUPP; 771 } 772 773 static int bnxt_ptp_pps_init(struct bnxt *bp) 774 { 775 struct hwrm_func_ptp_pin_qcfg_output *resp; 776 struct hwrm_func_ptp_pin_qcfg_input *req; 777 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 778 struct ptp_clock_info *ptp_info; 779 struct bnxt_pps *pps_info; 780 u8 *pin_usg; 781 u32 i, rc; 782 783 /* Query current/default PIN CFG */ 784 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG); 785 if (rc) 786 return rc; 787 788 resp = hwrm_req_hold(bp, req); 789 rc = hwrm_req_send(bp, req); 790 if (rc || !resp->num_pins) { 791 hwrm_req_drop(bp, req); 792 return -EOPNOTSUPP; 793 } 794 795 ptp_info = &ptp->ptp_info; 796 pps_info = &ptp->pps_info; 797 pps_info->num_pins = resp->num_pins; 798 ptp_info->n_pins = pps_info->num_pins; 799 ptp_info->pin_config = kcalloc(ptp_info->n_pins, 800 sizeof(*ptp_info->pin_config), 801 GFP_KERNEL); 802 if (!ptp_info->pin_config) { 803 hwrm_req_drop(bp, req); 804 return -ENOMEM; 805 } 806 807 /* Report the TSIO capability to kernel */ 808 pin_usg = &resp->pin0_usage; 809 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { 810 snprintf(ptp_info->pin_config[i].name, 811 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); 812 ptp_info->pin_config[i].index = i; 813 ptp_info->pin_config[i].chan = i; 814 if (*pin_usg == BNXT_PPS_PIN_PPS_IN) 815 ptp_info->pin_config[i].func = PTP_PF_EXTTS; 816 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) 817 ptp_info->pin_config[i].func = PTP_PF_PEROUT; 818 else 819 ptp_info->pin_config[i].func = PTP_PF_NONE; 820 821 pps_info->pins[i].usage = *pin_usg; 822 } 823 hwrm_req_drop(bp, req); 824 825 /* Only 1 each of ext_ts and per_out pins is available in HW */ 826 ptp_info->n_ext_ts = 1; 827 ptp_info->n_per_out = 1; 828 ptp_info->pps = 1; 829 ptp_info->verify = bnxt_ptp_verify; 830 831 return 0; 832 } 833 834 static bool bnxt_pps_config_ok(struct bnxt *bp) 835 { 836 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 837 838 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; 839 } 840 841 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc) 842 { 843 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 844 845 if (!ptp->ptp_clock) { 846 memset(&ptp->cc, 0, sizeof(ptp->cc)); 847 ptp->cc.read = bnxt_cc_read; 848 ptp->cc.mask = CYCLECOUNTER_MASK(48); 849 ptp->cc.shift = 0; 850 ptp->cc.mult = 1; 851 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; 852 } 853 if (init_tc) 854 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); 855 } 856 857 /* Caller holds ptp_lock */ 858 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns) 859 { 860 timecounter_init(&ptp->tc, &ptp->cc, ns); 861 /* For RTC, cycle_last must be in sync with the timecounter value. */ 862 ptp->tc.cycle_last = ns & ptp->cc.mask; 863 } 864 865 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg) 866 { 867 struct timespec64 tsp; 868 u64 ns; 869 int rc; 870 871 if (!bp->ptp_cfg || !(bp->fw_cap & BNXT_FW_CAP_PTP_RTC)) 872 return -ENODEV; 873 874 if (!phc_cfg) { 875 ktime_get_real_ts64(&tsp); 876 ns = timespec64_to_ns(&tsp); 877 rc = bnxt_ptp_cfg_settime(bp, ns); 878 if (rc) 879 return rc; 880 } else { 881 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, &ns); 882 if (rc) 883 return rc; 884 } 885 spin_lock_bh(&bp->ptp_cfg->ptp_lock); 886 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns); 887 spin_unlock_bh(&bp->ptp_cfg->ptp_lock); 888 889 return 0; 890 } 891 892 static void bnxt_ptp_free(struct bnxt *bp) 893 { 894 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 895 896 if (ptp->ptp_clock) { 897 ptp_clock_unregister(ptp->ptp_clock); 898 ptp->ptp_clock = NULL; 899 kfree(ptp->ptp_info.pin_config); 900 ptp->ptp_info.pin_config = NULL; 901 } 902 } 903 904 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg) 905 { 906 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 907 int rc; 908 909 if (!ptp) 910 return 0; 911 912 rc = bnxt_map_ptp_regs(bp); 913 if (rc) 914 return rc; 915 916 if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) 917 return 0; 918 919 bnxt_ptp_free(bp); 920 921 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS); 922 spin_lock_init(&ptp->ptp_lock); 923 924 if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) { 925 bnxt_ptp_timecounter_init(bp, false); 926 rc = bnxt_ptp_init_rtc(bp, phc_cfg); 927 if (rc) 928 goto out; 929 } else { 930 bnxt_ptp_timecounter_init(bp, true); 931 } 932 933 ptp->ptp_info = bnxt_ptp_caps; 934 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { 935 if (bnxt_ptp_pps_init(bp)) 936 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 937 } 938 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 939 if (IS_ERR(ptp->ptp_clock)) { 940 int err = PTR_ERR(ptp->ptp_clock); 941 942 ptp->ptp_clock = NULL; 943 rc = err; 944 goto out; 945 } 946 if (bp->flags & BNXT_FLAG_CHIP_P5) { 947 spin_lock_bh(&ptp->ptp_lock); 948 bnxt_refclk_read(bp, NULL, &ptp->current_time); 949 WRITE_ONCE(ptp->old_time, ptp->current_time); 950 spin_unlock_bh(&ptp->ptp_lock); 951 ptp_schedule_worker(ptp->ptp_clock, 0); 952 } 953 return 0; 954 955 out: 956 bnxt_ptp_free(bp); 957 bnxt_unmap_ptp_regs(bp); 958 return rc; 959 } 960 961 void bnxt_ptp_clear(struct bnxt *bp) 962 { 963 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 964 965 if (!ptp) 966 return; 967 968 if (ptp->ptp_clock) 969 ptp_clock_unregister(ptp->ptp_clock); 970 971 ptp->ptp_clock = NULL; 972 kfree(ptp->ptp_info.pin_config); 973 ptp->ptp_info.pin_config = NULL; 974 975 if (ptp->tx_skb) { 976 dev_kfree_skb_any(ptp->tx_skb); 977 ptp->tx_skb = NULL; 978 } 979 bnxt_unmap_ptp_regs(bp); 980 } 981