1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2021 Broadcom Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #include <linux/kernel.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/timekeeping.h> 16 #include <linux/ptp_classify.h> 17 #include <linux/clocksource.h> 18 #include "bnxt_hsi.h" 19 #include "bnxt.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_ptp.h" 22 23 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time) 24 { 25 struct hwrm_func_ptp_cfg_input *req; 26 int rc; 27 28 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 29 if (rc) 30 return rc; 31 32 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME); 33 req->ptp_set_time = cpu_to_le64(time); 34 return hwrm_req_send(bp, req); 35 } 36 37 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) 38 { 39 unsigned int ptp_class; 40 struct ptp_header *hdr; 41 42 ptp_class = ptp_classify_raw(skb); 43 44 switch (ptp_class & PTP_CLASS_VMASK) { 45 case PTP_CLASS_V1: 46 case PTP_CLASS_V2: 47 hdr = ptp_parse_header(skb, ptp_class); 48 if (!hdr) 49 return -EINVAL; 50 51 *hdr_off = (u8 *)hdr - skb->data; 52 *seq_id = ntohs(hdr->sequence_id); 53 return 0; 54 default: 55 return -ERANGE; 56 } 57 } 58 59 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, 60 const struct timespec64 *ts) 61 { 62 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 63 ptp_info); 64 u64 ns = timespec64_to_ns(ts); 65 66 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC) 67 return bnxt_ptp_cfg_settime(ptp->bp, ns); 68 69 spin_lock_bh(&ptp->ptp_lock); 70 timecounter_init(&ptp->tc, &ptp->cc, ns); 71 spin_unlock_bh(&ptp->ptp_lock); 72 return 0; 73 } 74 75 /* Caller holds ptp_lock */ 76 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 77 u64 *ns) 78 { 79 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 80 u32 high_before, high_now, low; 81 82 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 83 return -EIO; 84 85 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 86 ptp_read_system_prets(sts); 87 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 88 ptp_read_system_postts(sts); 89 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 90 if (high_now != high_before) { 91 ptp_read_system_prets(sts); 92 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 93 ptp_read_system_postts(sts); 94 } 95 *ns = ((u64)high_now << 32) | low; 96 97 return 0; 98 } 99 100 static void bnxt_ptp_get_current_time(struct bnxt *bp) 101 { 102 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 103 104 if (!ptp) 105 return; 106 spin_lock_bh(&ptp->ptp_lock); 107 WRITE_ONCE(ptp->old_time, ptp->current_time); 108 bnxt_refclk_read(bp, NULL, &ptp->current_time); 109 spin_unlock_bh(&ptp->ptp_lock); 110 } 111 112 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts) 113 { 114 struct hwrm_port_ts_query_output *resp; 115 struct hwrm_port_ts_query_input *req; 116 int rc; 117 118 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY); 119 if (rc) 120 return rc; 121 122 req->flags = cpu_to_le32(flags); 123 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == 124 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { 125 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); 126 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid); 127 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off); 128 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT); 129 } 130 resp = hwrm_req_hold(bp, req); 131 132 rc = hwrm_req_send(bp, req); 133 if (!rc) 134 *ts = le64_to_cpu(resp->ptp_msg_ts); 135 hwrm_req_drop(bp, req); 136 return rc; 137 } 138 139 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, 140 struct timespec64 *ts, 141 struct ptp_system_timestamp *sts) 142 { 143 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 144 ptp_info); 145 u64 ns, cycles; 146 int rc; 147 148 spin_lock_bh(&ptp->ptp_lock); 149 rc = bnxt_refclk_read(ptp->bp, sts, &cycles); 150 if (rc) { 151 spin_unlock_bh(&ptp->ptp_lock); 152 return rc; 153 } 154 ns = timecounter_cyc2time(&ptp->tc, cycles); 155 spin_unlock_bh(&ptp->ptp_lock); 156 *ts = ns_to_timespec64(ns); 157 158 return 0; 159 } 160 161 /* Caller holds ptp_lock */ 162 void bnxt_ptp_update_current_time(struct bnxt *bp) 163 { 164 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 165 166 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time); 167 WRITE_ONCE(ptp->old_time, ptp->current_time); 168 } 169 170 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta) 171 { 172 struct hwrm_port_mac_cfg_input *req; 173 int rc; 174 175 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG); 176 if (rc) 177 return rc; 178 179 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE); 180 req->ptp_adj_phase = cpu_to_le64(delta); 181 182 rc = hwrm_req_send(ptp->bp, req); 183 if (rc) { 184 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc); 185 } else { 186 spin_lock_bh(&ptp->ptp_lock); 187 bnxt_ptp_update_current_time(ptp->bp); 188 spin_unlock_bh(&ptp->ptp_lock); 189 } 190 191 return rc; 192 } 193 194 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) 195 { 196 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 197 ptp_info); 198 199 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC) 200 return bnxt_ptp_adjphc(ptp, delta); 201 202 spin_lock_bh(&ptp->ptp_lock); 203 timecounter_adjtime(&ptp->tc, delta); 204 spin_unlock_bh(&ptp->ptp_lock); 205 return 0; 206 } 207 208 static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb) 209 { 210 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 211 ptp_info); 212 struct hwrm_port_mac_cfg_input *req; 213 struct bnxt *bp = ptp->bp; 214 int rc = 0; 215 216 if (!(ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)) { 217 int neg_adj = 0; 218 u32 diff; 219 u64 adj; 220 221 if (ppb < 0) { 222 neg_adj = 1; 223 ppb = -ppb; 224 } 225 adj = ptp->cmult; 226 adj *= ppb; 227 diff = div_u64(adj, 1000000000ULL); 228 229 spin_lock_bh(&ptp->ptp_lock); 230 timecounter_read(&ptp->tc); 231 ptp->cc.mult = neg_adj ? ptp->cmult - diff : ptp->cmult + diff; 232 spin_unlock_bh(&ptp->ptp_lock); 233 } else { 234 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 235 if (rc) 236 return rc; 237 238 req->ptp_freq_adj_ppb = cpu_to_le32(ppb); 239 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); 240 rc = hwrm_req_send(ptp->bp, req); 241 if (rc) 242 netdev_err(ptp->bp->dev, 243 "ptp adjfreq failed. rc = %d\n", rc); 244 } 245 return rc; 246 } 247 248 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) 249 { 250 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 251 struct ptp_clock_event event; 252 u64 ns, pps_ts; 253 254 pps_ts = EVENT_PPS_TS(data2, data1); 255 spin_lock_bh(&ptp->ptp_lock); 256 ns = timecounter_cyc2time(&ptp->tc, pps_ts); 257 spin_unlock_bh(&ptp->ptp_lock); 258 259 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { 260 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: 261 event.pps_times.ts_real = ns_to_timespec64(ns); 262 event.type = PTP_CLOCK_PPSUSR; 263 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 264 break; 265 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: 266 event.timestamp = ns; 267 event.type = PTP_CLOCK_EXTTS; 268 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 269 break; 270 } 271 272 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); 273 } 274 275 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) 276 { 277 struct hwrm_func_ptp_pin_cfg_input *req; 278 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 279 u8 state = usage != BNXT_PPS_PIN_NONE; 280 u8 *pin_state, *pin_usg; 281 u32 enables; 282 int rc; 283 284 if (!TSIO_PIN_VALID(pin)) { 285 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); 286 return -EOPNOTSUPP; 287 } 288 289 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG); 290 if (rc) 291 return rc; 292 293 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | 294 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); 295 req->enables = cpu_to_le32(enables); 296 297 pin_state = &req->pin0_state; 298 pin_usg = &req->pin0_usage; 299 300 *(pin_state + (pin * 2)) = state; 301 *(pin_usg + (pin * 2)) = usage; 302 303 rc = hwrm_req_send(ptp->bp, req); 304 if (rc) 305 return rc; 306 307 ptp->pps_info.pins[pin].usage = usage; 308 ptp->pps_info.pins[pin].state = state; 309 310 return 0; 311 } 312 313 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) 314 { 315 struct hwrm_func_ptp_cfg_input *req; 316 int rc; 317 318 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 319 if (rc) 320 return rc; 321 322 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); 323 req->ptp_pps_event = event; 324 return hwrm_req_send(bp, req); 325 } 326 327 void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp) 328 { 329 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 330 struct hwrm_port_mac_cfg_input *req; 331 332 if (!ptp || !ptp->tstamp_filters) 333 return; 334 335 if (hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG)) 336 goto out; 337 338 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters & 339 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 340 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) { 341 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 342 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE); 343 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n"); 344 } 345 346 req->flags = cpu_to_le32(ptp->tstamp_filters); 347 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); 348 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); 349 350 if (!hwrm_req_send(bp, req)) { 351 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters & 352 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE); 353 return; 354 } 355 ptp->tstamp_filters = 0; 356 out: 357 bp->ptp_all_rx_tstamp = 0; 358 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n"); 359 } 360 361 void bnxt_ptp_reapply_pps(struct bnxt *bp) 362 { 363 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 364 struct bnxt_pps *pps; 365 u32 pin = 0; 366 int rc; 367 368 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || 369 !(ptp->ptp_info.pin_config)) 370 return; 371 pps = &ptp->pps_info; 372 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { 373 if (pps->pins[pin].state) { 374 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); 375 if (!rc && pps->pins[pin].event) 376 rc = bnxt_ptp_cfg_event(bp, 377 pps->pins[pin].event); 378 if (rc) 379 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", 380 pin); 381 } 382 } 383 } 384 385 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns, 386 u64 *cycles_delta) 387 { 388 u64 cycles_now; 389 u64 nsec_now, nsec_delta; 390 int rc; 391 392 spin_lock_bh(&ptp->ptp_lock); 393 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now); 394 if (rc) { 395 spin_unlock_bh(&ptp->ptp_lock); 396 return rc; 397 } 398 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now); 399 spin_unlock_bh(&ptp->ptp_lock); 400 401 nsec_delta = target_ns - nsec_now; 402 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult); 403 return 0; 404 } 405 406 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, 407 struct ptp_clock_request *rq) 408 { 409 struct hwrm_func_ptp_cfg_input *req; 410 struct bnxt *bp = ptp->bp; 411 struct timespec64 ts; 412 u64 target_ns, delta; 413 u16 enables; 414 int rc; 415 416 ts.tv_sec = rq->perout.start.sec; 417 ts.tv_nsec = rq->perout.start.nsec; 418 target_ns = timespec64_to_ns(&ts); 419 420 rc = bnxt_get_target_cycles(ptp, target_ns, &delta); 421 if (rc) 422 return rc; 423 424 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 425 if (rc) 426 return rc; 427 428 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | 429 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | 430 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; 431 req->enables = cpu_to_le16(enables); 432 req->ptp_pps_event = 0; 433 req->ptp_freq_adj_dll_source = 0; 434 req->ptp_freq_adj_dll_phase = 0; 435 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); 436 req->ptp_freq_adj_ext_up = 0; 437 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta); 438 439 return hwrm_req_send(bp, req); 440 } 441 442 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, 443 struct ptp_clock_request *rq, int on) 444 { 445 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 446 ptp_info); 447 struct bnxt *bp = ptp->bp; 448 int pin_id; 449 int rc; 450 451 switch (rq->type) { 452 case PTP_CLK_REQ_EXTTS: 453 /* Configure an External PPS IN */ 454 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, 455 rq->extts.index); 456 if (!TSIO_PIN_VALID(pin_id)) 457 return -EOPNOTSUPP; 458 if (!on) 459 break; 460 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 461 if (rc) 462 return rc; 463 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); 464 if (!rc) 465 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; 466 return rc; 467 case PTP_CLK_REQ_PEROUT: 468 /* Configure a Periodic PPS OUT */ 469 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, 470 rq->perout.index); 471 if (!TSIO_PIN_VALID(pin_id)) 472 return -EOPNOTSUPP; 473 if (!on) 474 break; 475 476 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); 477 if (!rc) 478 rc = bnxt_ptp_perout_cfg(ptp, rq); 479 480 return rc; 481 case PTP_CLK_REQ_PPS: 482 /* Configure PHC PPS IN */ 483 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN); 484 if (rc) 485 return rc; 486 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); 487 if (!rc) 488 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL; 489 return rc; 490 default: 491 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); 492 return -EOPNOTSUPP; 493 } 494 495 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); 496 } 497 498 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) 499 { 500 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 501 u32 flags = 0; 502 int rc = 0; 503 504 switch (ptp->rx_filter) { 505 case HWTSTAMP_FILTER_ALL: 506 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE; 507 break; 508 case HWTSTAMP_FILTER_NONE: 509 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; 510 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 511 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE; 512 break; 513 case HWTSTAMP_FILTER_PTP_V2_EVENT: 514 case HWTSTAMP_FILTER_PTP_V2_SYNC: 515 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 516 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; 517 break; 518 } 519 520 if (ptp->tx_tstamp_en) 521 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; 522 else 523 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; 524 525 ptp->tstamp_filters = flags; 526 527 if (netif_running(bp->dev)) { 528 if (ptp->rx_filter == HWTSTAMP_FILTER_ALL) { 529 rc = bnxt_close_nic(bp, false, false); 530 if (!rc) 531 rc = bnxt_open_nic(bp, false, false); 532 } else { 533 bnxt_ptp_cfg_tstamp_filters(bp); 534 } 535 if (!rc && !ptp->tstamp_filters) 536 rc = -EIO; 537 } 538 539 return rc; 540 } 541 542 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 543 { 544 struct bnxt *bp = netdev_priv(dev); 545 struct hwtstamp_config stmpconf; 546 struct bnxt_ptp_cfg *ptp; 547 u16 old_rxctl; 548 int old_rx_filter, rc; 549 u8 old_tx_tstamp_en; 550 551 ptp = bp->ptp_cfg; 552 if (!ptp) 553 return -EOPNOTSUPP; 554 555 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) 556 return -EFAULT; 557 558 if (stmpconf.tx_type != HWTSTAMP_TX_ON && 559 stmpconf.tx_type != HWTSTAMP_TX_OFF) 560 return -ERANGE; 561 562 old_rx_filter = ptp->rx_filter; 563 old_rxctl = ptp->rxctl; 564 old_tx_tstamp_en = ptp->tx_tstamp_en; 565 switch (stmpconf.rx_filter) { 566 case HWTSTAMP_FILTER_NONE: 567 ptp->rxctl = 0; 568 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 569 break; 570 case HWTSTAMP_FILTER_ALL: 571 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) { 572 ptp->rx_filter = HWTSTAMP_FILTER_ALL; 573 break; 574 } 575 return -EOPNOTSUPP; 576 case HWTSTAMP_FILTER_PTP_V2_EVENT: 577 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 578 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 579 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 580 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 581 break; 582 case HWTSTAMP_FILTER_PTP_V2_SYNC: 583 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 584 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 585 ptp->rxctl = BNXT_PTP_MSG_SYNC; 586 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 587 break; 588 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 589 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 590 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 591 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; 592 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 593 break; 594 default: 595 return -ERANGE; 596 } 597 598 if (stmpconf.tx_type == HWTSTAMP_TX_ON) 599 ptp->tx_tstamp_en = 1; 600 else 601 ptp->tx_tstamp_en = 0; 602 603 rc = bnxt_hwrm_ptp_cfg(bp); 604 if (rc) 605 goto ts_set_err; 606 607 stmpconf.rx_filter = ptp->rx_filter; 608 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 609 -EFAULT : 0; 610 611 ts_set_err: 612 ptp->rx_filter = old_rx_filter; 613 ptp->rxctl = old_rxctl; 614 ptp->tx_tstamp_en = old_tx_tstamp_en; 615 return rc; 616 } 617 618 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 619 { 620 struct bnxt *bp = netdev_priv(dev); 621 struct hwtstamp_config stmpconf; 622 struct bnxt_ptp_cfg *ptp; 623 624 ptp = bp->ptp_cfg; 625 if (!ptp) 626 return -EOPNOTSUPP; 627 628 stmpconf.flags = 0; 629 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 630 631 stmpconf.rx_filter = ptp->rx_filter; 632 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 633 -EFAULT : 0; 634 } 635 636 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) 637 { 638 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; 639 u32 win_off; 640 int i; 641 642 for (i = 0; i < count; i++) { 643 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) 644 return -ERANGE; 645 } 646 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 647 writel(reg_base, bp->bar0 + win_off); 648 return 0; 649 } 650 651 static int bnxt_map_ptp_regs(struct bnxt *bp) 652 { 653 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 654 u32 *reg_arr; 655 int rc, i; 656 657 reg_arr = ptp->refclk_regs; 658 if (bp->flags & BNXT_FLAG_CHIP_P5) { 659 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); 660 if (rc) 661 return rc; 662 for (i = 0; i < 2; i++) 663 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + 664 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); 665 return 0; 666 } 667 return -ENODEV; 668 } 669 670 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 671 { 672 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 673 (BNXT_PTP_GRC_WIN - 1) * 4); 674 } 675 676 static u64 bnxt_cc_read(const struct cyclecounter *cc) 677 { 678 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); 679 u64 ns = 0; 680 681 bnxt_refclk_read(ptp->bp, NULL, &ns); 682 return ns; 683 } 684 685 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb) 686 { 687 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 688 struct skb_shared_hwtstamps timestamp; 689 u64 ts = 0, ns = 0; 690 int rc; 691 692 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts); 693 if (!rc) { 694 memset(×tamp, 0, sizeof(timestamp)); 695 spin_lock_bh(&ptp->ptp_lock); 696 ns = timecounter_cyc2time(&ptp->tc, ts); 697 spin_unlock_bh(&ptp->ptp_lock); 698 timestamp.hwtstamp = ns_to_ktime(ns); 699 skb_tstamp_tx(ptp->tx_skb, ×tamp); 700 } else { 701 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n", 702 rc); 703 } 704 705 dev_kfree_skb_any(ptp->tx_skb); 706 ptp->tx_skb = NULL; 707 atomic_inc(&ptp->tx_avail); 708 } 709 710 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) 711 { 712 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 713 ptp_info); 714 unsigned long now = jiffies; 715 struct bnxt *bp = ptp->bp; 716 717 if (ptp->tx_skb) 718 bnxt_stamp_tx_skb(bp, ptp->tx_skb); 719 720 if (!time_after_eq(now, ptp->next_period)) 721 return ptp->next_period - now; 722 723 bnxt_ptp_get_current_time(bp); 724 ptp->next_period = now + HZ; 725 if (time_after_eq(now, ptp->next_overflow_check)) { 726 spin_lock_bh(&ptp->ptp_lock); 727 timecounter_read(&ptp->tc); 728 spin_unlock_bh(&ptp->ptp_lock); 729 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; 730 } 731 return HZ; 732 } 733 734 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb) 735 { 736 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 737 738 if (ptp->tx_skb) { 739 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n"); 740 return -EBUSY; 741 } 742 ptp->tx_skb = skb; 743 ptp_schedule_worker(ptp->ptp_clock, 0); 744 return 0; 745 } 746 747 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) 748 { 749 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 750 u64 time; 751 752 if (!ptp) 753 return -ENODEV; 754 755 BNXT_READ_TIME64(ptp, time, ptp->old_time); 756 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts; 757 if (pkt_ts < (time & BNXT_LO_TIMER_MASK)) 758 *ts += BNXT_LO_TIMER_MASK + 1; 759 760 return 0; 761 } 762 763 static const struct ptp_clock_info bnxt_ptp_caps = { 764 .owner = THIS_MODULE, 765 .name = "bnxt clock", 766 .max_adj = BNXT_MAX_PHC_DRIFT, 767 .n_alarm = 0, 768 .n_ext_ts = 0, 769 .n_per_out = 0, 770 .n_pins = 0, 771 .pps = 0, 772 .adjfreq = bnxt_ptp_adjfreq, 773 .adjtime = bnxt_ptp_adjtime, 774 .do_aux_work = bnxt_ptp_ts_aux_work, 775 .gettimex64 = bnxt_ptp_gettimex, 776 .settime64 = bnxt_ptp_settime, 777 .enable = bnxt_ptp_enable, 778 }; 779 780 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, 781 enum ptp_pin_function func, unsigned int chan) 782 { 783 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 784 ptp_info); 785 /* Allow only PPS pin function configuration */ 786 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && 787 func != PTP_PF_PHYSYNC) 788 return 0; 789 else 790 return -EOPNOTSUPP; 791 } 792 793 static int bnxt_ptp_pps_init(struct bnxt *bp) 794 { 795 struct hwrm_func_ptp_pin_qcfg_output *resp; 796 struct hwrm_func_ptp_pin_qcfg_input *req; 797 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 798 struct ptp_clock_info *ptp_info; 799 struct bnxt_pps *pps_info; 800 u8 *pin_usg; 801 u32 i, rc; 802 803 /* Query current/default PIN CFG */ 804 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG); 805 if (rc) 806 return rc; 807 808 resp = hwrm_req_hold(bp, req); 809 rc = hwrm_req_send(bp, req); 810 if (rc || !resp->num_pins) { 811 hwrm_req_drop(bp, req); 812 return -EOPNOTSUPP; 813 } 814 815 ptp_info = &ptp->ptp_info; 816 pps_info = &ptp->pps_info; 817 pps_info->num_pins = resp->num_pins; 818 ptp_info->n_pins = pps_info->num_pins; 819 ptp_info->pin_config = kcalloc(ptp_info->n_pins, 820 sizeof(*ptp_info->pin_config), 821 GFP_KERNEL); 822 if (!ptp_info->pin_config) { 823 hwrm_req_drop(bp, req); 824 return -ENOMEM; 825 } 826 827 /* Report the TSIO capability to kernel */ 828 pin_usg = &resp->pin0_usage; 829 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { 830 snprintf(ptp_info->pin_config[i].name, 831 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); 832 ptp_info->pin_config[i].index = i; 833 ptp_info->pin_config[i].chan = i; 834 if (*pin_usg == BNXT_PPS_PIN_PPS_IN) 835 ptp_info->pin_config[i].func = PTP_PF_EXTTS; 836 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) 837 ptp_info->pin_config[i].func = PTP_PF_PEROUT; 838 else 839 ptp_info->pin_config[i].func = PTP_PF_NONE; 840 841 pps_info->pins[i].usage = *pin_usg; 842 } 843 hwrm_req_drop(bp, req); 844 845 /* Only 1 each of ext_ts and per_out pins is available in HW */ 846 ptp_info->n_ext_ts = 1; 847 ptp_info->n_per_out = 1; 848 ptp_info->pps = 1; 849 ptp_info->verify = bnxt_ptp_verify; 850 851 return 0; 852 } 853 854 static bool bnxt_pps_config_ok(struct bnxt *bp) 855 { 856 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 857 858 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; 859 } 860 861 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc) 862 { 863 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 864 865 if (!ptp->ptp_clock) { 866 memset(&ptp->cc, 0, sizeof(ptp->cc)); 867 ptp->cc.read = bnxt_cc_read; 868 ptp->cc.mask = CYCLECOUNTER_MASK(48); 869 ptp->cc.shift = BNXT_CYCLES_SHIFT; 870 ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift); 871 ptp->cmult = ptp->cc.mult; 872 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; 873 } 874 if (init_tc) 875 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); 876 } 877 878 /* Caller holds ptp_lock */ 879 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns) 880 { 881 timecounter_init(&ptp->tc, &ptp->cc, ns); 882 /* For RTC, cycle_last must be in sync with the timecounter value. */ 883 ptp->tc.cycle_last = ns & ptp->cc.mask; 884 } 885 886 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg) 887 { 888 struct timespec64 tsp; 889 u64 ns; 890 int rc; 891 892 if (!bp->ptp_cfg || !(bp->fw_cap & BNXT_FW_CAP_PTP_RTC)) 893 return -ENODEV; 894 895 if (!phc_cfg) { 896 ktime_get_real_ts64(&tsp); 897 ns = timespec64_to_ns(&tsp); 898 rc = bnxt_ptp_cfg_settime(bp, ns); 899 if (rc) 900 return rc; 901 } else { 902 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, &ns); 903 if (rc) 904 return rc; 905 } 906 spin_lock_bh(&bp->ptp_cfg->ptp_lock); 907 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns); 908 spin_unlock_bh(&bp->ptp_cfg->ptp_lock); 909 910 return 0; 911 } 912 913 static void bnxt_ptp_free(struct bnxt *bp) 914 { 915 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 916 917 if (ptp->ptp_clock) { 918 ptp_clock_unregister(ptp->ptp_clock); 919 ptp->ptp_clock = NULL; 920 kfree(ptp->ptp_info.pin_config); 921 ptp->ptp_info.pin_config = NULL; 922 } 923 } 924 925 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg) 926 { 927 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 928 int rc; 929 930 if (!ptp) 931 return 0; 932 933 rc = bnxt_map_ptp_regs(bp); 934 if (rc) 935 return rc; 936 937 if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) 938 return 0; 939 940 bnxt_ptp_free(bp); 941 942 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS); 943 spin_lock_init(&ptp->ptp_lock); 944 945 if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) { 946 bnxt_ptp_timecounter_init(bp, false); 947 rc = bnxt_ptp_init_rtc(bp, phc_cfg); 948 if (rc) 949 goto out; 950 } else { 951 bnxt_ptp_timecounter_init(bp, true); 952 } 953 954 ptp->ptp_info = bnxt_ptp_caps; 955 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { 956 if (bnxt_ptp_pps_init(bp)) 957 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 958 } 959 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 960 if (IS_ERR(ptp->ptp_clock)) { 961 int err = PTR_ERR(ptp->ptp_clock); 962 963 ptp->ptp_clock = NULL; 964 rc = err; 965 goto out; 966 } 967 if (bp->flags & BNXT_FLAG_CHIP_P5) { 968 spin_lock_bh(&ptp->ptp_lock); 969 bnxt_refclk_read(bp, NULL, &ptp->current_time); 970 WRITE_ONCE(ptp->old_time, ptp->current_time); 971 spin_unlock_bh(&ptp->ptp_lock); 972 ptp_schedule_worker(ptp->ptp_clock, 0); 973 } 974 return 0; 975 976 out: 977 bnxt_ptp_free(bp); 978 bnxt_unmap_ptp_regs(bp); 979 return rc; 980 } 981 982 void bnxt_ptp_clear(struct bnxt *bp) 983 { 984 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 985 986 if (!ptp) 987 return; 988 989 if (ptp->ptp_clock) 990 ptp_clock_unregister(ptp->ptp_clock); 991 992 ptp->ptp_clock = NULL; 993 kfree(ptp->ptp_info.pin_config); 994 ptp->ptp_info.pin_config = NULL; 995 996 if (ptp->tx_skb) { 997 dev_kfree_skb_any(ptp->tx_skb); 998 ptp->tx_skb = NULL; 999 } 1000 bnxt_unmap_ptp_regs(bp); 1001 } 1002