1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2021 Broadcom Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #include <linux/kernel.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/timekeeping.h> 16 #include <linux/ptp_classify.h> 17 #include "bnxt_hsi.h" 18 #include "bnxt.h" 19 #include "bnxt_hwrm.h" 20 #include "bnxt_ptp.h" 21 22 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time) 23 { 24 struct hwrm_func_ptp_cfg_input *req; 25 int rc; 26 27 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 28 if (rc) 29 return rc; 30 31 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME); 32 req->ptp_set_time = cpu_to_le64(time); 33 return hwrm_req_send(bp, req); 34 } 35 36 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) 37 { 38 unsigned int ptp_class; 39 struct ptp_header *hdr; 40 41 ptp_class = ptp_classify_raw(skb); 42 43 switch (ptp_class & PTP_CLASS_VMASK) { 44 case PTP_CLASS_V1: 45 case PTP_CLASS_V2: 46 hdr = ptp_parse_header(skb, ptp_class); 47 if (!hdr) 48 return -EINVAL; 49 50 *hdr_off = (u8 *)hdr - skb->data; 51 *seq_id = ntohs(hdr->sequence_id); 52 return 0; 53 default: 54 return -ERANGE; 55 } 56 } 57 58 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, 59 const struct timespec64 *ts) 60 { 61 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 62 ptp_info); 63 u64 ns = timespec64_to_ns(ts); 64 65 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC) 66 return bnxt_ptp_cfg_settime(ptp->bp, ns); 67 68 spin_lock_bh(&ptp->ptp_lock); 69 timecounter_init(&ptp->tc, &ptp->cc, ns); 70 spin_unlock_bh(&ptp->ptp_lock); 71 return 0; 72 } 73 74 /* Caller holds ptp_lock */ 75 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 76 u64 *ns) 77 { 78 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 79 80 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 81 return -EIO; 82 83 ptp_read_system_prets(sts); 84 *ns = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 85 ptp_read_system_postts(sts); 86 *ns |= (u64)readl(bp->bar0 + ptp->refclk_mapped_regs[1]) << 32; 87 return 0; 88 } 89 90 static void bnxt_ptp_get_current_time(struct bnxt *bp) 91 { 92 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 93 94 if (!ptp) 95 return; 96 spin_lock_bh(&ptp->ptp_lock); 97 WRITE_ONCE(ptp->old_time, ptp->current_time); 98 bnxt_refclk_read(bp, NULL, &ptp->current_time); 99 spin_unlock_bh(&ptp->ptp_lock); 100 } 101 102 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts) 103 { 104 struct hwrm_port_ts_query_output *resp; 105 struct hwrm_port_ts_query_input *req; 106 int rc; 107 108 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY); 109 if (rc) 110 return rc; 111 112 req->flags = cpu_to_le32(flags); 113 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == 114 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { 115 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); 116 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid); 117 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off); 118 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT); 119 } 120 resp = hwrm_req_hold(bp, req); 121 122 rc = hwrm_req_send(bp, req); 123 if (!rc) 124 *ts = le64_to_cpu(resp->ptp_msg_ts); 125 hwrm_req_drop(bp, req); 126 return rc; 127 } 128 129 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, 130 struct timespec64 *ts, 131 struct ptp_system_timestamp *sts) 132 { 133 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 134 ptp_info); 135 u64 ns, cycles; 136 int rc; 137 138 spin_lock_bh(&ptp->ptp_lock); 139 rc = bnxt_refclk_read(ptp->bp, sts, &cycles); 140 if (rc) { 141 spin_unlock_bh(&ptp->ptp_lock); 142 return rc; 143 } 144 ns = timecounter_cyc2time(&ptp->tc, cycles); 145 spin_unlock_bh(&ptp->ptp_lock); 146 *ts = ns_to_timespec64(ns); 147 148 return 0; 149 } 150 151 /* Caller holds ptp_lock */ 152 void bnxt_ptp_update_current_time(struct bnxt *bp) 153 { 154 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 155 156 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time); 157 WRITE_ONCE(ptp->old_time, ptp->current_time); 158 } 159 160 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta) 161 { 162 struct hwrm_port_mac_cfg_input *req; 163 int rc; 164 165 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG); 166 if (rc) 167 return rc; 168 169 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE); 170 req->ptp_adj_phase = cpu_to_le64(delta); 171 172 rc = hwrm_req_send(ptp->bp, req); 173 if (rc) { 174 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc); 175 } else { 176 spin_lock_bh(&ptp->ptp_lock); 177 bnxt_ptp_update_current_time(ptp->bp); 178 spin_unlock_bh(&ptp->ptp_lock); 179 } 180 181 return rc; 182 } 183 184 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) 185 { 186 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 187 ptp_info); 188 189 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC) 190 return bnxt_ptp_adjphc(ptp, delta); 191 192 spin_lock_bh(&ptp->ptp_lock); 193 timecounter_adjtime(&ptp->tc, delta); 194 spin_unlock_bh(&ptp->ptp_lock); 195 return 0; 196 } 197 198 static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb) 199 { 200 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 201 ptp_info); 202 struct hwrm_port_mac_cfg_input *req; 203 struct bnxt *bp = ptp->bp; 204 int rc; 205 206 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 207 if (rc) 208 return rc; 209 210 req->ptp_freq_adj_ppb = cpu_to_le32(ppb); 211 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); 212 rc = hwrm_req_send(ptp->bp, req); 213 if (rc) 214 netdev_err(ptp->bp->dev, 215 "ptp adjfreq failed. rc = %d\n", rc); 216 return rc; 217 } 218 219 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) 220 { 221 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 222 struct ptp_clock_event event; 223 u64 ns, pps_ts; 224 225 pps_ts = EVENT_PPS_TS(data2, data1); 226 spin_lock_bh(&ptp->ptp_lock); 227 ns = timecounter_cyc2time(&ptp->tc, pps_ts); 228 spin_unlock_bh(&ptp->ptp_lock); 229 230 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { 231 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: 232 event.pps_times.ts_real = ns_to_timespec64(ns); 233 event.type = PTP_CLOCK_PPSUSR; 234 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 235 break; 236 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: 237 event.timestamp = ns; 238 event.type = PTP_CLOCK_EXTTS; 239 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 240 break; 241 } 242 243 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); 244 } 245 246 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) 247 { 248 struct hwrm_func_ptp_pin_cfg_input *req; 249 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 250 u8 state = usage != BNXT_PPS_PIN_NONE; 251 u8 *pin_state, *pin_usg; 252 u32 enables; 253 int rc; 254 255 if (!TSIO_PIN_VALID(pin)) { 256 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); 257 return -EOPNOTSUPP; 258 } 259 260 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG); 261 if (rc) 262 return rc; 263 264 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | 265 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); 266 req->enables = cpu_to_le32(enables); 267 268 pin_state = &req->pin0_state; 269 pin_usg = &req->pin0_usage; 270 271 *(pin_state + (pin * 2)) = state; 272 *(pin_usg + (pin * 2)) = usage; 273 274 rc = hwrm_req_send(ptp->bp, req); 275 if (rc) 276 return rc; 277 278 ptp->pps_info.pins[pin].usage = usage; 279 ptp->pps_info.pins[pin].state = state; 280 281 return 0; 282 } 283 284 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) 285 { 286 struct hwrm_func_ptp_cfg_input *req; 287 int rc; 288 289 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 290 if (rc) 291 return rc; 292 293 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); 294 req->ptp_pps_event = event; 295 return hwrm_req_send(bp, req); 296 } 297 298 void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp) 299 { 300 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 301 struct hwrm_port_mac_cfg_input *req; 302 303 if (!ptp || !ptp->tstamp_filters) 304 return; 305 306 if (hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG)) 307 goto out; 308 309 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters & 310 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 311 PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE))) { 312 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 313 PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE); 314 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n"); 315 } 316 317 req->flags = cpu_to_le32(ptp->tstamp_filters); 318 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); 319 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); 320 321 if (!hwrm_req_send(bp, req)) { 322 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters & 323 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE); 324 return; 325 } 326 ptp->tstamp_filters = 0; 327 out: 328 bp->ptp_all_rx_tstamp = 0; 329 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n"); 330 } 331 332 void bnxt_ptp_reapply_pps(struct bnxt *bp) 333 { 334 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 335 struct bnxt_pps *pps; 336 u32 pin = 0; 337 int rc; 338 339 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || 340 !(ptp->ptp_info.pin_config)) 341 return; 342 pps = &ptp->pps_info; 343 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { 344 if (pps->pins[pin].state) { 345 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); 346 if (!rc && pps->pins[pin].event) 347 rc = bnxt_ptp_cfg_event(bp, 348 pps->pins[pin].event); 349 if (rc) 350 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", 351 pin); 352 } 353 } 354 } 355 356 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns, 357 u64 *cycles_delta) 358 { 359 u64 cycles_now; 360 u64 nsec_now, nsec_delta; 361 int rc; 362 363 spin_lock_bh(&ptp->ptp_lock); 364 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now); 365 if (rc) { 366 spin_unlock_bh(&ptp->ptp_lock); 367 return rc; 368 } 369 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now); 370 spin_unlock_bh(&ptp->ptp_lock); 371 372 nsec_delta = target_ns - nsec_now; 373 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult); 374 return 0; 375 } 376 377 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, 378 struct ptp_clock_request *rq) 379 { 380 struct hwrm_func_ptp_cfg_input *req; 381 struct bnxt *bp = ptp->bp; 382 struct timespec64 ts; 383 u64 target_ns, delta; 384 u16 enables; 385 int rc; 386 387 ts.tv_sec = rq->perout.start.sec; 388 ts.tv_nsec = rq->perout.start.nsec; 389 target_ns = timespec64_to_ns(&ts); 390 391 rc = bnxt_get_target_cycles(ptp, target_ns, &delta); 392 if (rc) 393 return rc; 394 395 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 396 if (rc) 397 return rc; 398 399 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | 400 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | 401 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; 402 req->enables = cpu_to_le16(enables); 403 req->ptp_pps_event = 0; 404 req->ptp_freq_adj_dll_source = 0; 405 req->ptp_freq_adj_dll_phase = 0; 406 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); 407 req->ptp_freq_adj_ext_up = 0; 408 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta); 409 410 return hwrm_req_send(bp, req); 411 } 412 413 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, 414 struct ptp_clock_request *rq, int on) 415 { 416 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 417 ptp_info); 418 struct bnxt *bp = ptp->bp; 419 int pin_id; 420 int rc; 421 422 switch (rq->type) { 423 case PTP_CLK_REQ_EXTTS: 424 /* Configure an External PPS IN */ 425 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, 426 rq->extts.index); 427 if (!TSIO_PIN_VALID(pin_id)) 428 return -EOPNOTSUPP; 429 if (!on) 430 break; 431 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 432 if (rc) 433 return rc; 434 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); 435 if (!rc) 436 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; 437 return rc; 438 case PTP_CLK_REQ_PEROUT: 439 /* Configure a Periodic PPS OUT */ 440 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, 441 rq->perout.index); 442 if (!TSIO_PIN_VALID(pin_id)) 443 return -EOPNOTSUPP; 444 if (!on) 445 break; 446 447 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); 448 if (!rc) 449 rc = bnxt_ptp_perout_cfg(ptp, rq); 450 451 return rc; 452 case PTP_CLK_REQ_PPS: 453 /* Configure PHC PPS IN */ 454 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN); 455 if (rc) 456 return rc; 457 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); 458 if (!rc) 459 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL; 460 return rc; 461 default: 462 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); 463 return -EOPNOTSUPP; 464 } 465 466 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); 467 } 468 469 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) 470 { 471 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 472 u32 flags = 0; 473 int rc = 0; 474 475 switch (ptp->rx_filter) { 476 case HWTSTAMP_FILTER_ALL: 477 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE; 478 break; 479 case HWTSTAMP_FILTER_NONE: 480 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; 481 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 482 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE; 483 break; 484 case HWTSTAMP_FILTER_PTP_V2_EVENT: 485 case HWTSTAMP_FILTER_PTP_V2_SYNC: 486 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 487 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; 488 break; 489 } 490 491 if (ptp->tx_tstamp_en) 492 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; 493 else 494 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; 495 496 ptp->tstamp_filters = flags; 497 498 if (netif_running(bp->dev)) { 499 rc = bnxt_close_nic(bp, false, false); 500 if (!rc) 501 rc = bnxt_open_nic(bp, false, false); 502 if (!rc && !ptp->tstamp_filters) 503 rc = -EIO; 504 } 505 506 return rc; 507 } 508 509 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 510 { 511 struct bnxt *bp = netdev_priv(dev); 512 struct hwtstamp_config stmpconf; 513 struct bnxt_ptp_cfg *ptp; 514 u16 old_rxctl; 515 int old_rx_filter, rc; 516 u8 old_tx_tstamp_en; 517 518 ptp = bp->ptp_cfg; 519 if (!ptp) 520 return -EOPNOTSUPP; 521 522 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) 523 return -EFAULT; 524 525 if (stmpconf.tx_type != HWTSTAMP_TX_ON && 526 stmpconf.tx_type != HWTSTAMP_TX_OFF) 527 return -ERANGE; 528 529 old_rx_filter = ptp->rx_filter; 530 old_rxctl = ptp->rxctl; 531 old_tx_tstamp_en = ptp->tx_tstamp_en; 532 switch (stmpconf.rx_filter) { 533 case HWTSTAMP_FILTER_NONE: 534 ptp->rxctl = 0; 535 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 536 break; 537 case HWTSTAMP_FILTER_ALL: 538 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) { 539 ptp->rx_filter = HWTSTAMP_FILTER_ALL; 540 break; 541 } 542 return -EOPNOTSUPP; 543 case HWTSTAMP_FILTER_PTP_V2_EVENT: 544 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 545 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 546 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 547 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 548 break; 549 case HWTSTAMP_FILTER_PTP_V2_SYNC: 550 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 551 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 552 ptp->rxctl = BNXT_PTP_MSG_SYNC; 553 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 554 break; 555 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 556 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 557 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 558 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; 559 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 560 break; 561 default: 562 return -ERANGE; 563 } 564 565 if (stmpconf.tx_type == HWTSTAMP_TX_ON) 566 ptp->tx_tstamp_en = 1; 567 else 568 ptp->tx_tstamp_en = 0; 569 570 rc = bnxt_hwrm_ptp_cfg(bp); 571 if (rc) 572 goto ts_set_err; 573 574 stmpconf.rx_filter = ptp->rx_filter; 575 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 576 -EFAULT : 0; 577 578 ts_set_err: 579 ptp->rx_filter = old_rx_filter; 580 ptp->rxctl = old_rxctl; 581 ptp->tx_tstamp_en = old_tx_tstamp_en; 582 return rc; 583 } 584 585 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 586 { 587 struct bnxt *bp = netdev_priv(dev); 588 struct hwtstamp_config stmpconf; 589 struct bnxt_ptp_cfg *ptp; 590 591 ptp = bp->ptp_cfg; 592 if (!ptp) 593 return -EOPNOTSUPP; 594 595 stmpconf.flags = 0; 596 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 597 598 stmpconf.rx_filter = ptp->rx_filter; 599 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 600 -EFAULT : 0; 601 } 602 603 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) 604 { 605 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; 606 u32 win_off; 607 int i; 608 609 for (i = 0; i < count; i++) { 610 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) 611 return -ERANGE; 612 } 613 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 614 writel(reg_base, bp->bar0 + win_off); 615 return 0; 616 } 617 618 static int bnxt_map_ptp_regs(struct bnxt *bp) 619 { 620 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 621 u32 *reg_arr; 622 int rc, i; 623 624 reg_arr = ptp->refclk_regs; 625 if (bp->flags & BNXT_FLAG_CHIP_P5) { 626 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); 627 if (rc) 628 return rc; 629 for (i = 0; i < 2; i++) 630 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + 631 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); 632 return 0; 633 } 634 return -ENODEV; 635 } 636 637 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 638 { 639 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 640 (BNXT_PTP_GRC_WIN - 1) * 4); 641 } 642 643 static u64 bnxt_cc_read(const struct cyclecounter *cc) 644 { 645 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); 646 u64 ns = 0; 647 648 bnxt_refclk_read(ptp->bp, NULL, &ns); 649 return ns; 650 } 651 652 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb) 653 { 654 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 655 struct skb_shared_hwtstamps timestamp; 656 u64 ts = 0, ns = 0; 657 int rc; 658 659 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts); 660 if (!rc) { 661 memset(×tamp, 0, sizeof(timestamp)); 662 spin_lock_bh(&ptp->ptp_lock); 663 ns = timecounter_cyc2time(&ptp->tc, ts); 664 spin_unlock_bh(&ptp->ptp_lock); 665 timestamp.hwtstamp = ns_to_ktime(ns); 666 skb_tstamp_tx(ptp->tx_skb, ×tamp); 667 } else { 668 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n", 669 rc); 670 } 671 672 dev_kfree_skb_any(ptp->tx_skb); 673 ptp->tx_skb = NULL; 674 atomic_inc(&ptp->tx_avail); 675 } 676 677 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) 678 { 679 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 680 ptp_info); 681 unsigned long now = jiffies; 682 struct bnxt *bp = ptp->bp; 683 684 if (ptp->tx_skb) 685 bnxt_stamp_tx_skb(bp, ptp->tx_skb); 686 687 if (!time_after_eq(now, ptp->next_period)) 688 return ptp->next_period - now; 689 690 bnxt_ptp_get_current_time(bp); 691 ptp->next_period = now + HZ; 692 if (time_after_eq(now, ptp->next_overflow_check)) { 693 spin_lock_bh(&ptp->ptp_lock); 694 timecounter_read(&ptp->tc); 695 spin_unlock_bh(&ptp->ptp_lock); 696 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; 697 } 698 return HZ; 699 } 700 701 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb) 702 { 703 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 704 705 if (ptp->tx_skb) { 706 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n"); 707 return -EBUSY; 708 } 709 ptp->tx_skb = skb; 710 ptp_schedule_worker(ptp->ptp_clock, 0); 711 return 0; 712 } 713 714 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) 715 { 716 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 717 u64 time; 718 719 if (!ptp) 720 return -ENODEV; 721 722 BNXT_READ_TIME64(ptp, time, ptp->old_time); 723 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts; 724 if (pkt_ts < (time & BNXT_LO_TIMER_MASK)) 725 *ts += BNXT_LO_TIMER_MASK + 1; 726 727 return 0; 728 } 729 730 static const struct ptp_clock_info bnxt_ptp_caps = { 731 .owner = THIS_MODULE, 732 .name = "bnxt clock", 733 .max_adj = BNXT_MAX_PHC_DRIFT, 734 .n_alarm = 0, 735 .n_ext_ts = 0, 736 .n_per_out = 0, 737 .n_pins = 0, 738 .pps = 0, 739 .adjfreq = bnxt_ptp_adjfreq, 740 .adjtime = bnxt_ptp_adjtime, 741 .do_aux_work = bnxt_ptp_ts_aux_work, 742 .gettimex64 = bnxt_ptp_gettimex, 743 .settime64 = bnxt_ptp_settime, 744 .enable = bnxt_ptp_enable, 745 }; 746 747 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, 748 enum ptp_pin_function func, unsigned int chan) 749 { 750 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 751 ptp_info); 752 /* Allow only PPS pin function configuration */ 753 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && 754 func != PTP_PF_PHYSYNC) 755 return 0; 756 else 757 return -EOPNOTSUPP; 758 } 759 760 static int bnxt_ptp_pps_init(struct bnxt *bp) 761 { 762 struct hwrm_func_ptp_pin_qcfg_output *resp; 763 struct hwrm_func_ptp_pin_qcfg_input *req; 764 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 765 struct ptp_clock_info *ptp_info; 766 struct bnxt_pps *pps_info; 767 u8 *pin_usg; 768 u32 i, rc; 769 770 /* Query current/default PIN CFG */ 771 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG); 772 if (rc) 773 return rc; 774 775 resp = hwrm_req_hold(bp, req); 776 rc = hwrm_req_send(bp, req); 777 if (rc || !resp->num_pins) { 778 hwrm_req_drop(bp, req); 779 return -EOPNOTSUPP; 780 } 781 782 ptp_info = &ptp->ptp_info; 783 pps_info = &ptp->pps_info; 784 pps_info->num_pins = resp->num_pins; 785 ptp_info->n_pins = pps_info->num_pins; 786 ptp_info->pin_config = kcalloc(ptp_info->n_pins, 787 sizeof(*ptp_info->pin_config), 788 GFP_KERNEL); 789 if (!ptp_info->pin_config) { 790 hwrm_req_drop(bp, req); 791 return -ENOMEM; 792 } 793 794 /* Report the TSIO capability to kernel */ 795 pin_usg = &resp->pin0_usage; 796 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { 797 snprintf(ptp_info->pin_config[i].name, 798 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); 799 ptp_info->pin_config[i].index = i; 800 ptp_info->pin_config[i].chan = i; 801 if (*pin_usg == BNXT_PPS_PIN_PPS_IN) 802 ptp_info->pin_config[i].func = PTP_PF_EXTTS; 803 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) 804 ptp_info->pin_config[i].func = PTP_PF_PEROUT; 805 else 806 ptp_info->pin_config[i].func = PTP_PF_NONE; 807 808 pps_info->pins[i].usage = *pin_usg; 809 } 810 hwrm_req_drop(bp, req); 811 812 /* Only 1 each of ext_ts and per_out pins is available in HW */ 813 ptp_info->n_ext_ts = 1; 814 ptp_info->n_per_out = 1; 815 ptp_info->pps = 1; 816 ptp_info->verify = bnxt_ptp_verify; 817 818 return 0; 819 } 820 821 static bool bnxt_pps_config_ok(struct bnxt *bp) 822 { 823 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 824 825 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; 826 } 827 828 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc) 829 { 830 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 831 832 if (!ptp->ptp_clock) { 833 memset(&ptp->cc, 0, sizeof(ptp->cc)); 834 ptp->cc.read = bnxt_cc_read; 835 ptp->cc.mask = CYCLECOUNTER_MASK(48); 836 ptp->cc.shift = 0; 837 ptp->cc.mult = 1; 838 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; 839 } 840 if (init_tc) 841 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); 842 } 843 844 /* Caller holds ptp_lock */ 845 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns) 846 { 847 timecounter_init(&ptp->tc, &ptp->cc, ns); 848 /* For RTC, cycle_last must be in sync with the timecounter value. */ 849 ptp->tc.cycle_last = ns & ptp->cc.mask; 850 } 851 852 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg) 853 { 854 struct timespec64 tsp; 855 u64 ns; 856 int rc; 857 858 if (!bp->ptp_cfg || !(bp->fw_cap & BNXT_FW_CAP_PTP_RTC)) 859 return -ENODEV; 860 861 if (!phc_cfg) { 862 ktime_get_real_ts64(&tsp); 863 ns = timespec64_to_ns(&tsp); 864 rc = bnxt_ptp_cfg_settime(bp, ns); 865 if (rc) 866 return rc; 867 } else { 868 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, &ns); 869 if (rc) 870 return rc; 871 } 872 spin_lock_bh(&bp->ptp_cfg->ptp_lock); 873 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns); 874 spin_unlock_bh(&bp->ptp_cfg->ptp_lock); 875 876 return 0; 877 } 878 879 static void bnxt_ptp_free(struct bnxt *bp) 880 { 881 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 882 883 if (ptp->ptp_clock) { 884 ptp_clock_unregister(ptp->ptp_clock); 885 ptp->ptp_clock = NULL; 886 kfree(ptp->ptp_info.pin_config); 887 ptp->ptp_info.pin_config = NULL; 888 } 889 } 890 891 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg) 892 { 893 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 894 int rc; 895 896 if (!ptp) 897 return 0; 898 899 rc = bnxt_map_ptp_regs(bp); 900 if (rc) 901 return rc; 902 903 if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) 904 return 0; 905 906 bnxt_ptp_free(bp); 907 908 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS); 909 spin_lock_init(&ptp->ptp_lock); 910 911 if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) { 912 bnxt_ptp_timecounter_init(bp, false); 913 rc = bnxt_ptp_init_rtc(bp, phc_cfg); 914 if (rc) 915 goto out; 916 } else { 917 bnxt_ptp_timecounter_init(bp, true); 918 } 919 920 ptp->ptp_info = bnxt_ptp_caps; 921 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { 922 if (bnxt_ptp_pps_init(bp)) 923 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 924 } 925 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 926 if (IS_ERR(ptp->ptp_clock)) { 927 int err = PTR_ERR(ptp->ptp_clock); 928 929 ptp->ptp_clock = NULL; 930 rc = err; 931 goto out; 932 } 933 if (bp->flags & BNXT_FLAG_CHIP_P5) { 934 spin_lock_bh(&ptp->ptp_lock); 935 bnxt_refclk_read(bp, NULL, &ptp->current_time); 936 WRITE_ONCE(ptp->old_time, ptp->current_time); 937 spin_unlock_bh(&ptp->ptp_lock); 938 ptp_schedule_worker(ptp->ptp_clock, 0); 939 } 940 return 0; 941 942 out: 943 bnxt_ptp_free(bp); 944 bnxt_unmap_ptp_regs(bp); 945 return rc; 946 } 947 948 void bnxt_ptp_clear(struct bnxt *bp) 949 { 950 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 951 952 if (!ptp) 953 return; 954 955 if (ptp->ptp_clock) 956 ptp_clock_unregister(ptp->ptp_clock); 957 958 ptp->ptp_clock = NULL; 959 kfree(ptp->ptp_info.pin_config); 960 ptp->ptp_info.pin_config = NULL; 961 962 if (ptp->tx_skb) { 963 dev_kfree_skb_any(ptp->tx_skb); 964 ptp->tx_skb = NULL; 965 } 966 bnxt_unmap_ptp_regs(bp); 967 } 968