1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2021 Broadcom Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #include <linux/kernel.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/timekeeping.h> 16 #include <linux/ptp_classify.h> 17 #include "bnxt_hsi.h" 18 #include "bnxt.h" 19 #include "bnxt_hwrm.h" 20 #include "bnxt_ptp.h" 21 22 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) 23 { 24 unsigned int ptp_class; 25 struct ptp_header *hdr; 26 27 ptp_class = ptp_classify_raw(skb); 28 29 switch (ptp_class & PTP_CLASS_VMASK) { 30 case PTP_CLASS_V1: 31 case PTP_CLASS_V2: 32 hdr = ptp_parse_header(skb, ptp_class); 33 if (!hdr) 34 return -EINVAL; 35 36 *hdr_off = (u8 *)hdr - skb->data; 37 *seq_id = ntohs(hdr->sequence_id); 38 return 0; 39 default: 40 return -ERANGE; 41 } 42 } 43 44 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, 45 const struct timespec64 *ts) 46 { 47 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 48 ptp_info); 49 u64 ns = timespec64_to_ns(ts); 50 51 spin_lock_bh(&ptp->ptp_lock); 52 timecounter_init(&ptp->tc, &ptp->cc, ns); 53 spin_unlock_bh(&ptp->ptp_lock); 54 return 0; 55 } 56 57 /* Caller holds ptp_lock */ 58 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 59 u64 *ns) 60 { 61 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 62 63 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 64 return -EIO; 65 66 ptp_read_system_prets(sts); 67 *ns = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 68 ptp_read_system_postts(sts); 69 *ns |= (u64)readl(bp->bar0 + ptp->refclk_mapped_regs[1]) << 32; 70 return 0; 71 } 72 73 static void bnxt_ptp_get_current_time(struct bnxt *bp) 74 { 75 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 76 77 if (!ptp) 78 return; 79 spin_lock_bh(&ptp->ptp_lock); 80 WRITE_ONCE(ptp->old_time, ptp->current_time); 81 bnxt_refclk_read(bp, NULL, &ptp->current_time); 82 spin_unlock_bh(&ptp->ptp_lock); 83 } 84 85 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts) 86 { 87 struct hwrm_port_ts_query_output *resp; 88 struct hwrm_port_ts_query_input *req; 89 int rc; 90 91 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY); 92 if (rc) 93 return rc; 94 95 req->flags = cpu_to_le32(flags); 96 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == 97 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { 98 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); 99 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid); 100 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off); 101 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT); 102 } 103 resp = hwrm_req_hold(bp, req); 104 105 rc = hwrm_req_send(bp, req); 106 if (!rc) 107 *ts = le64_to_cpu(resp->ptp_msg_ts); 108 hwrm_req_drop(bp, req); 109 return rc; 110 } 111 112 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, 113 struct timespec64 *ts, 114 struct ptp_system_timestamp *sts) 115 { 116 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 117 ptp_info); 118 u64 ns, cycles; 119 int rc; 120 121 spin_lock_bh(&ptp->ptp_lock); 122 rc = bnxt_refclk_read(ptp->bp, sts, &cycles); 123 if (rc) { 124 spin_unlock_bh(&ptp->ptp_lock); 125 return rc; 126 } 127 ns = timecounter_cyc2time(&ptp->tc, cycles); 128 spin_unlock_bh(&ptp->ptp_lock); 129 *ts = ns_to_timespec64(ns); 130 131 return 0; 132 } 133 134 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) 135 { 136 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 137 ptp_info); 138 139 spin_lock_bh(&ptp->ptp_lock); 140 timecounter_adjtime(&ptp->tc, delta); 141 spin_unlock_bh(&ptp->ptp_lock); 142 return 0; 143 } 144 145 static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb) 146 { 147 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 148 ptp_info); 149 struct hwrm_port_mac_cfg_input *req; 150 struct bnxt *bp = ptp->bp; 151 int rc; 152 153 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 154 if (rc) 155 return rc; 156 157 req->ptp_freq_adj_ppb = cpu_to_le32(ppb); 158 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); 159 rc = hwrm_req_send(ptp->bp, req); 160 if (rc) 161 netdev_err(ptp->bp->dev, 162 "ptp adjfreq failed. rc = %d\n", rc); 163 return rc; 164 } 165 166 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) 167 { 168 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 169 struct ptp_clock_event event; 170 u64 ns, pps_ts; 171 172 pps_ts = EVENT_PPS_TS(data2, data1); 173 spin_lock_bh(&ptp->ptp_lock); 174 ns = timecounter_cyc2time(&ptp->tc, pps_ts); 175 spin_unlock_bh(&ptp->ptp_lock); 176 177 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { 178 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: 179 event.pps_times.ts_real = ns_to_timespec64(ns); 180 event.type = PTP_CLOCK_PPSUSR; 181 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 182 break; 183 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: 184 event.timestamp = ns; 185 event.type = PTP_CLOCK_EXTTS; 186 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 187 break; 188 } 189 190 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); 191 } 192 193 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) 194 { 195 struct hwrm_func_ptp_pin_cfg_input *req; 196 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 197 u8 state = usage != BNXT_PPS_PIN_NONE; 198 u8 *pin_state, *pin_usg; 199 u32 enables; 200 int rc; 201 202 if (!TSIO_PIN_VALID(pin)) { 203 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); 204 return -EOPNOTSUPP; 205 } 206 207 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG); 208 if (rc) 209 return rc; 210 211 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | 212 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); 213 req->enables = cpu_to_le32(enables); 214 215 pin_state = &req->pin0_state; 216 pin_usg = &req->pin0_usage; 217 218 *(pin_state + (pin * 2)) = state; 219 *(pin_usg + (pin * 2)) = usage; 220 221 rc = hwrm_req_send(ptp->bp, req); 222 if (rc) 223 return rc; 224 225 ptp->pps_info.pins[pin].usage = usage; 226 ptp->pps_info.pins[pin].state = state; 227 228 return 0; 229 } 230 231 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) 232 { 233 struct hwrm_func_ptp_cfg_input *req; 234 int rc; 235 236 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 237 if (rc) 238 return rc; 239 240 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); 241 req->ptp_pps_event = event; 242 return hwrm_req_send(bp, req); 243 } 244 245 void bnxt_ptp_reapply_pps(struct bnxt *bp) 246 { 247 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 248 struct bnxt_pps *pps; 249 u32 pin = 0; 250 int rc; 251 252 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || 253 !(ptp->ptp_info.pin_config)) 254 return; 255 pps = &ptp->pps_info; 256 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { 257 if (pps->pins[pin].state) { 258 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); 259 if (!rc && pps->pins[pin].event) 260 rc = bnxt_ptp_cfg_event(bp, 261 pps->pins[pin].event); 262 if (rc) 263 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", 264 pin); 265 } 266 } 267 } 268 269 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns, 270 u64 *cycles_delta) 271 { 272 u64 cycles_now; 273 u64 nsec_now, nsec_delta; 274 int rc; 275 276 spin_lock_bh(&ptp->ptp_lock); 277 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now); 278 if (rc) { 279 spin_unlock_bh(&ptp->ptp_lock); 280 return rc; 281 } 282 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now); 283 spin_unlock_bh(&ptp->ptp_lock); 284 285 nsec_delta = target_ns - nsec_now; 286 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult); 287 return 0; 288 } 289 290 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, 291 struct ptp_clock_request *rq) 292 { 293 struct hwrm_func_ptp_cfg_input *req; 294 struct bnxt *bp = ptp->bp; 295 struct timespec64 ts; 296 u64 target_ns, delta; 297 u16 enables; 298 int rc; 299 300 ts.tv_sec = rq->perout.start.sec; 301 ts.tv_nsec = rq->perout.start.nsec; 302 target_ns = timespec64_to_ns(&ts); 303 304 rc = bnxt_get_target_cycles(ptp, target_ns, &delta); 305 if (rc) 306 return rc; 307 308 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 309 if (rc) 310 return rc; 311 312 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | 313 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | 314 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; 315 req->enables = cpu_to_le16(enables); 316 req->ptp_pps_event = 0; 317 req->ptp_freq_adj_dll_source = 0; 318 req->ptp_freq_adj_dll_phase = 0; 319 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); 320 req->ptp_freq_adj_ext_up = 0; 321 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta); 322 323 return hwrm_req_send(bp, req); 324 } 325 326 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, 327 struct ptp_clock_request *rq, int on) 328 { 329 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 330 ptp_info); 331 struct bnxt *bp = ptp->bp; 332 u8 pin_id; 333 int rc; 334 335 switch (rq->type) { 336 case PTP_CLK_REQ_EXTTS: 337 /* Configure an External PPS IN */ 338 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, 339 rq->extts.index); 340 if (!on) 341 break; 342 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 343 if (rc) 344 return rc; 345 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); 346 if (!rc) 347 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; 348 return rc; 349 case PTP_CLK_REQ_PEROUT: 350 /* Configure a Periodic PPS OUT */ 351 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, 352 rq->perout.index); 353 if (!on) 354 break; 355 356 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); 357 if (!rc) 358 rc = bnxt_ptp_perout_cfg(ptp, rq); 359 360 return rc; 361 case PTP_CLK_REQ_PPS: 362 /* Configure PHC PPS IN */ 363 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN); 364 if (rc) 365 return rc; 366 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); 367 if (!rc) 368 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL; 369 return rc; 370 default: 371 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); 372 return -EOPNOTSUPP; 373 } 374 375 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); 376 } 377 378 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) 379 { 380 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 381 struct hwrm_port_mac_cfg_input *req; 382 u32 flags = 0; 383 int rc; 384 385 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 386 if (rc) 387 return rc; 388 389 if (ptp->rx_filter) 390 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; 391 else 392 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; 393 if (ptp->tx_tstamp_en) 394 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; 395 else 396 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; 397 req->flags = cpu_to_le32(flags); 398 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); 399 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); 400 401 return hwrm_req_send(bp, req); 402 } 403 404 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 405 { 406 struct bnxt *bp = netdev_priv(dev); 407 struct hwtstamp_config stmpconf; 408 struct bnxt_ptp_cfg *ptp; 409 u16 old_rxctl; 410 int old_rx_filter, rc; 411 u8 old_tx_tstamp_en; 412 413 ptp = bp->ptp_cfg; 414 if (!ptp) 415 return -EOPNOTSUPP; 416 417 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) 418 return -EFAULT; 419 420 if (stmpconf.tx_type != HWTSTAMP_TX_ON && 421 stmpconf.tx_type != HWTSTAMP_TX_OFF) 422 return -ERANGE; 423 424 old_rx_filter = ptp->rx_filter; 425 old_rxctl = ptp->rxctl; 426 old_tx_tstamp_en = ptp->tx_tstamp_en; 427 switch (stmpconf.rx_filter) { 428 case HWTSTAMP_FILTER_NONE: 429 ptp->rxctl = 0; 430 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 431 break; 432 case HWTSTAMP_FILTER_PTP_V2_EVENT: 433 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 434 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 435 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 436 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 437 break; 438 case HWTSTAMP_FILTER_PTP_V2_SYNC: 439 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 440 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 441 ptp->rxctl = BNXT_PTP_MSG_SYNC; 442 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 443 break; 444 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 445 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 446 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 447 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; 448 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 449 break; 450 default: 451 return -ERANGE; 452 } 453 454 if (stmpconf.tx_type == HWTSTAMP_TX_ON) 455 ptp->tx_tstamp_en = 1; 456 else 457 ptp->tx_tstamp_en = 0; 458 459 rc = bnxt_hwrm_ptp_cfg(bp); 460 if (rc) 461 goto ts_set_err; 462 463 stmpconf.rx_filter = ptp->rx_filter; 464 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 465 -EFAULT : 0; 466 467 ts_set_err: 468 ptp->rx_filter = old_rx_filter; 469 ptp->rxctl = old_rxctl; 470 ptp->tx_tstamp_en = old_tx_tstamp_en; 471 return rc; 472 } 473 474 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 475 { 476 struct bnxt *bp = netdev_priv(dev); 477 struct hwtstamp_config stmpconf; 478 struct bnxt_ptp_cfg *ptp; 479 480 ptp = bp->ptp_cfg; 481 if (!ptp) 482 return -EOPNOTSUPP; 483 484 stmpconf.flags = 0; 485 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 486 487 stmpconf.rx_filter = ptp->rx_filter; 488 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 489 -EFAULT : 0; 490 } 491 492 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) 493 { 494 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; 495 u32 win_off; 496 int i; 497 498 for (i = 0; i < count; i++) { 499 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) 500 return -ERANGE; 501 } 502 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 503 writel(reg_base, bp->bar0 + win_off); 504 return 0; 505 } 506 507 static int bnxt_map_ptp_regs(struct bnxt *bp) 508 { 509 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 510 u32 *reg_arr; 511 int rc, i; 512 513 reg_arr = ptp->refclk_regs; 514 if (bp->flags & BNXT_FLAG_CHIP_P5) { 515 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); 516 if (rc) 517 return rc; 518 for (i = 0; i < 2; i++) 519 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + 520 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); 521 return 0; 522 } 523 return -ENODEV; 524 } 525 526 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 527 { 528 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 529 (BNXT_PTP_GRC_WIN - 1) * 4); 530 } 531 532 static u64 bnxt_cc_read(const struct cyclecounter *cc) 533 { 534 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); 535 u64 ns = 0; 536 537 bnxt_refclk_read(ptp->bp, NULL, &ns); 538 return ns; 539 } 540 541 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb) 542 { 543 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 544 struct skb_shared_hwtstamps timestamp; 545 u64 ts = 0, ns = 0; 546 int rc; 547 548 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts); 549 if (!rc) { 550 memset(×tamp, 0, sizeof(timestamp)); 551 spin_lock_bh(&ptp->ptp_lock); 552 ns = timecounter_cyc2time(&ptp->tc, ts); 553 spin_unlock_bh(&ptp->ptp_lock); 554 timestamp.hwtstamp = ns_to_ktime(ns); 555 skb_tstamp_tx(ptp->tx_skb, ×tamp); 556 } else { 557 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n", 558 rc); 559 } 560 561 dev_kfree_skb_any(ptp->tx_skb); 562 ptp->tx_skb = NULL; 563 atomic_inc(&ptp->tx_avail); 564 } 565 566 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) 567 { 568 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 569 ptp_info); 570 unsigned long now = jiffies; 571 struct bnxt *bp = ptp->bp; 572 573 if (ptp->tx_skb) 574 bnxt_stamp_tx_skb(bp, ptp->tx_skb); 575 576 if (!time_after_eq(now, ptp->next_period)) 577 return ptp->next_period - now; 578 579 bnxt_ptp_get_current_time(bp); 580 ptp->next_period = now + HZ; 581 if (time_after_eq(now, ptp->next_overflow_check)) { 582 spin_lock_bh(&ptp->ptp_lock); 583 timecounter_read(&ptp->tc); 584 spin_unlock_bh(&ptp->ptp_lock); 585 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; 586 } 587 return HZ; 588 } 589 590 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb) 591 { 592 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 593 594 if (ptp->tx_skb) { 595 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n"); 596 return -EBUSY; 597 } 598 ptp->tx_skb = skb; 599 ptp_schedule_worker(ptp->ptp_clock, 0); 600 return 0; 601 } 602 603 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) 604 { 605 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 606 u64 time; 607 608 if (!ptp) 609 return -ENODEV; 610 611 BNXT_READ_TIME64(ptp, time, ptp->old_time); 612 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts; 613 if (pkt_ts < (time & BNXT_LO_TIMER_MASK)) 614 *ts += BNXT_LO_TIMER_MASK + 1; 615 616 return 0; 617 } 618 619 static const struct ptp_clock_info bnxt_ptp_caps = { 620 .owner = THIS_MODULE, 621 .name = "bnxt clock", 622 .max_adj = BNXT_MAX_PHC_DRIFT, 623 .n_alarm = 0, 624 .n_ext_ts = 0, 625 .n_per_out = 0, 626 .n_pins = 0, 627 .pps = 0, 628 .adjfreq = bnxt_ptp_adjfreq, 629 .adjtime = bnxt_ptp_adjtime, 630 .do_aux_work = bnxt_ptp_ts_aux_work, 631 .gettimex64 = bnxt_ptp_gettimex, 632 .settime64 = bnxt_ptp_settime, 633 .enable = bnxt_ptp_enable, 634 }; 635 636 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, 637 enum ptp_pin_function func, unsigned int chan) 638 { 639 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 640 ptp_info); 641 /* Allow only PPS pin function configuration */ 642 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && 643 func != PTP_PF_PHYSYNC) 644 return 0; 645 else 646 return -EOPNOTSUPP; 647 } 648 649 static int bnxt_ptp_pps_init(struct bnxt *bp) 650 { 651 struct hwrm_func_ptp_pin_qcfg_output *resp; 652 struct hwrm_func_ptp_pin_qcfg_input *req; 653 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 654 struct ptp_clock_info *ptp_info; 655 struct bnxt_pps *pps_info; 656 u8 *pin_usg; 657 u32 i, rc; 658 659 /* Query current/default PIN CFG */ 660 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG); 661 if (rc) 662 return rc; 663 664 resp = hwrm_req_hold(bp, req); 665 rc = hwrm_req_send(bp, req); 666 if (rc || !resp->num_pins) { 667 hwrm_req_drop(bp, req); 668 return -EOPNOTSUPP; 669 } 670 671 ptp_info = &ptp->ptp_info; 672 pps_info = &ptp->pps_info; 673 pps_info->num_pins = resp->num_pins; 674 ptp_info->n_pins = pps_info->num_pins; 675 ptp_info->pin_config = kcalloc(ptp_info->n_pins, 676 sizeof(*ptp_info->pin_config), 677 GFP_KERNEL); 678 if (!ptp_info->pin_config) { 679 hwrm_req_drop(bp, req); 680 return -ENOMEM; 681 } 682 683 /* Report the TSIO capability to kernel */ 684 pin_usg = &resp->pin0_usage; 685 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { 686 snprintf(ptp_info->pin_config[i].name, 687 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); 688 ptp_info->pin_config[i].index = i; 689 ptp_info->pin_config[i].chan = i; 690 if (*pin_usg == BNXT_PPS_PIN_PPS_IN) 691 ptp_info->pin_config[i].func = PTP_PF_EXTTS; 692 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) 693 ptp_info->pin_config[i].func = PTP_PF_PEROUT; 694 else 695 ptp_info->pin_config[i].func = PTP_PF_NONE; 696 697 pps_info->pins[i].usage = *pin_usg; 698 } 699 hwrm_req_drop(bp, req); 700 701 /* Only 1 each of ext_ts and per_out pins is available in HW */ 702 ptp_info->n_ext_ts = 1; 703 ptp_info->n_per_out = 1; 704 ptp_info->pps = 1; 705 ptp_info->verify = bnxt_ptp_verify; 706 707 return 0; 708 } 709 710 static bool bnxt_pps_config_ok(struct bnxt *bp) 711 { 712 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 713 714 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; 715 } 716 717 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc) 718 { 719 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 720 721 if (!ptp->ptp_clock) { 722 memset(&ptp->cc, 0, sizeof(ptp->cc)); 723 ptp->cc.read = bnxt_cc_read; 724 ptp->cc.mask = CYCLECOUNTER_MASK(48); 725 ptp->cc.shift = 0; 726 ptp->cc.mult = 1; 727 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; 728 } 729 if (init_tc) 730 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); 731 } 732 733 static void bnxt_ptp_free(struct bnxt *bp) 734 { 735 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 736 737 if (ptp->ptp_clock) { 738 ptp_clock_unregister(ptp->ptp_clock); 739 ptp->ptp_clock = NULL; 740 kfree(ptp->ptp_info.pin_config); 741 ptp->ptp_info.pin_config = NULL; 742 } 743 } 744 745 int bnxt_ptp_init(struct bnxt *bp) 746 { 747 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 748 int rc; 749 750 if (!ptp) 751 return 0; 752 753 rc = bnxt_map_ptp_regs(bp); 754 if (rc) 755 return rc; 756 757 if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) 758 return 0; 759 760 bnxt_ptp_free(bp); 761 762 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS); 763 spin_lock_init(&ptp->ptp_lock); 764 765 bnxt_ptp_timecounter_init(bp, true); 766 767 ptp->ptp_info = bnxt_ptp_caps; 768 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { 769 if (bnxt_ptp_pps_init(bp)) 770 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 771 } 772 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 773 if (IS_ERR(ptp->ptp_clock)) { 774 int err = PTR_ERR(ptp->ptp_clock); 775 776 ptp->ptp_clock = NULL; 777 bnxt_unmap_ptp_regs(bp); 778 return err; 779 } 780 if (bp->flags & BNXT_FLAG_CHIP_P5) { 781 spin_lock_bh(&ptp->ptp_lock); 782 bnxt_refclk_read(bp, NULL, &ptp->current_time); 783 WRITE_ONCE(ptp->old_time, ptp->current_time); 784 spin_unlock_bh(&ptp->ptp_lock); 785 ptp_schedule_worker(ptp->ptp_clock, 0); 786 } 787 return 0; 788 } 789 790 void bnxt_ptp_clear(struct bnxt *bp) 791 { 792 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 793 794 if (!ptp) 795 return; 796 797 if (ptp->ptp_clock) 798 ptp_clock_unregister(ptp->ptp_clock); 799 800 ptp->ptp_clock = NULL; 801 kfree(ptp->ptp_info.pin_config); 802 ptp->ptp_info.pin_config = NULL; 803 804 if (ptp->tx_skb) { 805 dev_kfree_skb_any(ptp->tx_skb); 806 ptp->tx_skb = NULL; 807 } 808 bnxt_unmap_ptp_regs(bp); 809 } 810